CN101064091A - Total caching OLED display screen arrange control circuit - Google Patents
Total caching OLED display screen arrange control circuit Download PDFInfo
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Abstract
This invention relates to one total buffer OLED display screen control circuit, which comprises input data as series input signal and output data as series output signal device and also buffer from series device input data, wherein it also comprises selector to input all data and output data from buffer; the series device has lock signal and zero signal as simultaneous signal to input series energy signals and buffer; the selector has selection terminal to select weight right input signals; the series device, buffer and selector adopt integral whole clock.
Description
Technical field
The present invention relates to a kind of OLED (organic electroluminescence device) display screen arrange control circuit, particularly a kind of total caching OLED display screen arrange control circuit.Wherein suitably increase image buffer storage,, and can directly accept gradation data with the scan efficiency of raising demonstration and the luminance loss in the reduction scanning.
Background technology
Along with the develop rapidly of VLSI (large scale integrated circuit) and new display spare, the pay attention to day by day that people use in the demonstration field OLED (organic electroluminescence device), supporting with it OLED display device chip for driving is also with regard to corresponding appearance.For feature richness, superior performance, the requirement of using display driver chip easily is strong day by day.
It is the serial transmission mode that the video data slave controller of tradition OLED flat-panel monitor is sent to the common method that adopts of display panel, as shown in Figure 1.
The tradition arrange control circuit comprises serializer (11) and (12) two parts of buffer, wherein serializer (11) is the multidigit of group more than register, shared identical clock end (the serial clock cp of a plurality of registers, 21), the input data of first group of register are serial input signals cdin (22), first group output data is connected to second group input, second group output is connected to the 3rd group input, by that analogy, the data of last group export serial output signal cdout (23) to, each output of organizing register is a high position by first group, last group constitutes serial data sdata (24) for the low level mode, when serial clock cp (21) rising edge, each register in the serializer (11) will be imported data and lock to output data; Buffer (12) is the latch of a multidigit band zero clearing control end, the shared identical end that latchs of a plurality of latchs, lock signal latch (25) and clear terminal (reset signal clrn, 26), as reset signal clrn (26) when low level is effective, column data cdata (27) output all is low level, to close the demonstration of display screen, invalid and lock signal latch (25) when high level is effective as reset signal clrn (26), serial data sdata (24) is latching to column data cdata (27), to drive the demonstration of display screen.Signal cdin (22) and cdout (23) have same bit-width in the traditional circuit; Data sdata (24) and cdata (27) also have same bit-width.
Use serial approach scanning to generate high gray level image, the general employing pressed weights (step-by-step) scan mode, as shown in Figure 2, Fig. 2 represents the sweep waveform segment of 32 grades of gray scales, the data of " 1.8 " expression first row weights 8 correspondences among the figure, the data of " 2.1 " expression second row weights 1 correspondence etc., weights scan by the order of " 1-2-4-8-16 ".
At time point A, at first the data " 1.1 " of first first weights of row are sent on the panel by cp (21) and cdin (22), transmitting all required time of data of weights is called a delivery time, and after a delivery time, " 1.1 " are transmitted and finished;
At time point B, " 1.1 " are transmitted and are finished, effectively latch (25) signal is to produce the high level pulse of a clock width, so that data are locked in the buffer, between latch (25) high period, be the correctness that guarantees to lock, should keep cp (21) is high level, reset signal clrn (26) invalid (high level) is to carry out the demonstration of " 1.1 " data simultaneously, because weights have only 1, show that the shared time is the shortest, the demonstration time of weights 1 correspondence is called a demonstration time, in order to reach high gray scale requirement, one shows that delivery time of time ratio is much smaller;
At time point C, begin the transmission of next weights data " 1.2 ", the demonstration of " 1.1 " at this moment finishes, and effectively reset signal clrn (26) is to close demonstration;
At time point D, " 1.2 " are transmitted and are finished, and produce a latch (25) high level pulse, and invalid clrn (26) is to show " 1.2 " data simultaneously;
At time point E, the transmission of beginning " 1.4 " data;
At time point F, the demonstration of " 1.2 " finishes, and effectively clrn (26) is to close the demonstration of " 1.2 ";
At time point G, " 1.4 " are transmitted and are finished, and produce a latch (25) high level pulse, and invalid clrn (26) is to show " 1.4 " data simultaneously;
At time point H, the transmission of beginning " 1.8 " data;
At time point I, the demonstration of " 1.4 " finishes, and effectively clrn (26) is to close the demonstration of " 1.4 ";
At time point J, " 1.8 " are transmitted and are finished, and produce a latch (25) high level pulse, and invalid clrn (26) is to show " 1.8 " data simultaneously;
At time point K, the transmission of beginning " 1.16 " data;
At time point L, " 1.16 " are transmitted and are finished, and the demonstration of " 1.8 " at this moment is not over yet, and should keep cp (21) is high level;
At time point M, " 1.8 " show end, produce a latch (25) high level pulse to show " 1.16 ";
At time point N, the transmission of beginning next line weights " 2.1 ";
At time point O, " 2.1 " are transmitted and are finished, but " 1.16 " are showing that still keeping cp (21) is high level;
At time point P, " 1.16 " show end, produce the demonstration of a latch (25) high level pulse with the beginning next line.
Even if so far the scanning of first row is finished, show that from weights 1 beginning to finish (time point C is to P) to weights 16 demonstrations is a line period, constantly repeat this cycle to carry out the scanning of next line, finally finish the scanning of whole 32 grades of gray level images.
The note demonstration time is Ts, and the demonstration time of weights n correspondence is Ts (n), and Ts (n)=n * Ts (1) is arranged, effectively the T.T. ∑ Ts=(2 that shows
N-1) * and Ts (1), wherein N is the weights number;
The note delivery time is Tt, and the delivery time of weights n correspondence is Tt (n), and Tt (n)=Tt (1) is arranged, effectively the T.T. ∑ Tt=N * Tt (1) that transmits;
Remember that the single weights real time is Tw, the real time of weights n correspondence is Tw (n), and it is the maximal value of corresponding demonstration time and delivery time, and Tw (n)=max (Ts (n), Tt (n)) is arranged;
Note is Tc the line period time, it be add up real time of all weights and, Tc=∑ Tw is arranged;
Note Fsc shows the time at the free time in the line period, and Fsc=Tc-∑ Ts is arranged; Note Rsc is a demonstration time idleness, and Rsc=Fsc/Tc * 100% is arranged;
Note Ftc is the effective delivery time in the line period, and Ftc=∑ Tt=N * Tt (1) is arranged; Note Rtc is the delivery time utilization factor, and Rtc=Ftc/Tc * 100% is arranged.
Obviously, Tc is the smaller the better, and the more little delegation's required time that then scans of Tc reduces, and can improve frame frequency, improves gray shade scale or increase picture size; Fsc and Rsc are the smaller the better, and the big more time total amount that then is used for actual displayed reduces, and the brightness of display screen loss increases, and the screen body is dark partially; Ftc and Rtc are the bigger the better, and the more little time ratio that then is used for actual transmission reduces, because it is constant to transmit total amount, needs more time to finish transmission.Rsc is used to weigh the luminance loss, and Rtc is used for weighing the scanning conveying function.
Under the situation of cp (21) clock frequency and display image size constancy, Tt is constant, and note R is the ratio of a demonstration time and a delivery time, i.e. R=Ts (1)/Tt (1).If R is more little, then many more Ts are less than Tt, and many Tw value is Tt more, and then Tc is more little, but Fsc is big more, therefore can improve gray scale and frame frequency, but loss display screen overall brightness; If R is big more, then on the contrary, brightness of display screen loss reduces, but that gray scale and frame frequency are carried is not high.This is a pair of contradiction of traditional implementation.
In 32 grades of gray scale scanning methods shown in Figure 2, be basic time unit with Ts (1), Ts (1)=1 then, actual being transmitted as 4 times adds and waits for that latch (25) needs a clock, so Tt (1)=5, R=1/5, Ts (n)=n, Tt (n)=5, Tw (n)=if n is 5 otherwise for n less than 5, Tc=5+5+5+8+16=39, Fsc=39-31=8, Ftc=4*5=20, Rsc=22.51%, Rtc=51.28%.
Therefore, adopt control circuit method illustrated in figures 1 and 2, the luminance loss surpasses 1/5th, transmits utilization factor and has only fifty percent substantially.
Summary of the invention
The object of the present invention is to provide a kind of total caching OLED display screen arrange control circuit, can effectively reduce even eliminate the luminance loss who causes in the scanning process, improve display frame frequency, and can directly receive the gray level image data, obviously simplify the scan control complexity, effectively reduce the clock frequency of the data transmission of scan control circuit.
For achieving the above object, design of the present invention is:
Referring to Fig. 1, the tradition arrange control circuit comprises serializer (11) and (12) two parts of buffer, wherein serializer (11) is the multidigit of group more than register, shared identical clock end (the serial clock cp of a plurality of registers, 21), the input data of first group of register are serial input signals cdin (22), first group output data is connected to second group input, second group output is connected to the 3rd group input, by that analogy, the data of last group export serial output signal cdout (23) to, each output of organizing register is a high position by first group, last group constitutes serial data sdata (24) for the low level mode, and when serial clock cp (21) rising edge, each register in the serializer (11) will be imported data and lock to output data; Buffer (12) is the latch of a multidigit band zero clearing control end, the shared identical end that latchs of a plurality of latchs (is locked signal latch, 25) and clear terminal (reset signal clrn, 26), as reset signal clrn (26) when low level is effective, column data cdata (27) output all is low level, to close the demonstration of display screen, invalid and lock signal latch (25) when high level is effective as reset signal clrn (26), serial data sdata (24) is latching to column data cdata (27), to drive the demonstration of display screen.Signal cdin (22) and cdout (23) have same bit-width in the traditional circuit; Data sdata (24) and cdata (27) also have same bit-width.Circuit of the present invention comprises serializer (31), (33) three parts of buffer (32) and selector switch, wherein serializer (31) is the register that the multidigit of group more than band enables, the register figure place is the bit wide of the gradation data of acceptance, shared identical clock end (the global clock clk of a plurality of registers, 41) and Enable Pin (serial enables cdena, 48), the input data of first group of register are serial input signals cdin (22), first group output data is connected to second group input, second group output is connected to the 3rd group input, by that analogy, the data of last group export serial output signal cdout (23) to, each output of organizing register constitutes serial gradation data sdata (44), enable cdena (48) when high level is effective at global clock clk (41) rising edge and serial, each register in the serializer (31) will be imported data and lock to output data; Buffer (32) is that a multidigit band enables the register with zero clearing, shared identical clock end (the global clock clk of a plurality of registers, 41), Enable Pin (is locked signal latch, 25) and clear terminal (reset signal clrn, 26), when global clock clk (41) rising edge, if reset signal clrn (26) low level is effective, then latch data ldata (49) output all is low level, to close the demonstration of display screen, reset signal clrn (26) is invalid and to lock signal latch (25) high level effective else if, then data sdata (44) is locked to latch data ldata (49), select the column data output demonstration of specific weight values to be input to selector switch; Selector switch (33) is that a multidigit N selects a selector switch, the bit wide of gradation data is N, a plurality of N select the shared identical selecting side of a selector switch (to select signal sel, 40), when selecting signal sel (40) input selector (33) for one, selector switch (33) all exports all mutually deserved weights among the gradation data ldata (49) to column data cdata (27), to drive the demonstration of display screen; Signal cdin (22) and cdout (23) have same bit-width in the circuit of the present invention; Data sdata (44) and ldata (45) also have same bit-width.Circuit of the present invention is compared with traditional circuit, serializer (31) increase enables control end, buffer (32) changes clock synchronization mode into, and increased memory capacity, increased selector switch (33) circuit, change serial clock signal cp (21) into global clock signal clk (41), lock signal latch (25) and change the synchronous working mode into, increase control signal cdena (48) and sel (40).
According to above-mentioned inventive concept, the present invention adopts following technical proposals:
A kind of total caching OLED display screen arrange control circuit, comprise that the input data are that serial input signals cdin (22) and output data are the serializer (31) of serial output signal cdout (23), and, it is characterized in that from the buffer (32) of serializer (31) input serial data sdata (44):
(1) also includes the selector switch (33) of importing all data ldata (49) and output column data cdata (27) from buffer (32);
(2) described serializer (31) has the Enable Pin input string to exercise energy signal cdena (48);
(3) described buffer (32) input lock signal latch (25) and reset signal clrn (26) is a synchronizing signal;
(4) described selector switch (33) has the selecting side input to select weights input signal sel (40);
(5) described serializer (31), buffer (32) and selector switch (33) adopt unified global clock clk (41).
Above-mentioned serializer (31) is the register that the multidigit of group more than band enables, the register figure place is the bit wide of the gradation data of acceptance, the shared identical clock end of a plurality of registers, be global clock clk (41) and shared identical Enable Pin, serial enables cdena (48), the input data of first group of register are serial input signals cdin (22), first group output data is connected to second group input, second group output is connected to the 3rd group input, by that analogy, the data of last group export serial output signal cdout (23) to, each output of organizing register constitutes serial data sdata (44), enable cdena (48) when high level is effective at global clock clk (41) rising edge and serial, each register in the serializer (31) will be imported data and lock to output data.
Above-mentioned buffer (32) is that a multidigit band enables the register with zero clearing, the shared identical clock end of a plurality of registers, be global clock clk (41), and signal latch (25) and clear terminal input reset signal clrn (26) are locked in the input of common identical Enable Pin, when global clock clk (41) rising edge, if reset signal clrn (26) low level is effective, then latch data ldata (49) exports whole low levels, to close the demonstration of display screen, reset signal clrn (26) is invalid and to lock signal latch (25) high level effective else if, then data sdata (44) is locked to latch data ldata (49), select the column data output demonstration of specific weight values to be input to selector switch.
Above-mentioned selector switch (33) is that a multidigit N selects a selector switch, the bit wide of gradation data is N, a plurality of N select the shared identical selecting side input select signal sel (40) of a selector switch, when selecting signal sel (40) input selector (33) for one, selector switch (33) exports the total data of all mutually deserved weights among all data ldata (49) to column data cdata (27), to drive the demonstration of display screen.
Above-mentioned serial input signals cdin (22) and serial output signal cdout (23) have same bit-width; Serial data sdata (44) and all data ldata (49) also have same bit-width.
The present invention compared with prior art, have following conspicuous outstanding substantive distinguishing features and remarkable advantage: on the basis of display screen arrange data conventional serial transmission circuit, adopt the total caching structure, promptly by increasing latch and increasing selector switch, and the use method of synchronization, can reduce effectively, even the luminance loss who causes in the elimination scanning process, improve display frame frequency, and can directly receive the gray level image data, obviously simplify the scan control complexity, effectively reduce the clock frequency of the data transmission of scan control circuit.Under 256 grades of gray scales, compare under the condition of R=1/33 with traditional structure, adopt the present invention, the luminance loss only is 0.39%, transmits utilization factor up to 100%, reduces 98.87% than traditional structure luminance loss, basic elimination luminance loss, and the transmission utilization factor reaches capacity.The total caching structure has only increased a selector control signal, and circuit is simple, is fit to the OLED chip design.
Description of drawings
Fig. 1 is traditional OLED arrange control circuit figure.
Fig. 2 is 32 grades of gray scale scanning oscillograms of traditional arrange control circuit.
Fig. 3 is the arrange control circuit figure that the present invention adopts.
Fig. 4 adopts 32 grades of gray scale scanning oscillograms of the present invention.
Fig. 5 is the serializer detailed circuit diagram that adopts 256 grades of gray scales of 32 row of the present invention.
Fig. 6 is the buffer detailed circuit diagram that adopts 256 grades of gray scales of 32 row of the present invention.
Fig. 7 is the selector switch detailed circuit diagram that adopts 256 grades of gray scales of 32 row of the present invention.
Fig. 8 is the top-level module detailed circuit diagram that adopts 256 grades of gray scales of 256 row of the present invention.
Embodiment
Also details are as follows in conjunction with the accompanying drawings for a preferred embodiment of the present invention:
This total caching OLED display screen arrange control circuit is based on traditional OLED arrange control circuit shown in Figure 1, change latch among Fig. 1 (25) and clrn (26) into synchronizing signal, cp (21) changes the global clock signal into, rename clk (41) as, increase a serial enable signal cdena (48), allow serial to lock cdin (22) when this signal high level is effective, simultaneously selector switch (32), and increase a selection signal sel (40), as shown in Figure 3.
Referring to Fig. 3, serializer (31) is the register that the multidigit of group more than band enables, the register figure place is the bit wide of the gradation data of acceptance, shared identical clock end (the global clock clk of a plurality of registers, 41) and Enable Pin (serial enables cdena, 48), the input data of first group of register are serial input signals cdin (22), first group output data is connected to second group input, second group output is connected to the 3rd group input, by that analogy, the data of last group export serial output signal cdout (23) to, each output of organizing register constitutes serial gradation data sdata (44), enables cdena (48) when high level is effective at global clock clk (41) rising edge and serial, and each register in the serializer (11) will be imported data and lock to output data; Buffer (32) is that a multidigit band enables the register with zero clearing, shared identical clock end (the global clock clk of a plurality of registers, 41), Enable Pin (is locked signal latch, 25) and clear terminal (reset signal clrn, 26), when global clock clk (41) rising edge, if reset signal clrn (26) low level is effective, then buffer data ldata (49) output all is low level, to close the demonstration of display screen, reset signal clrn (26) is invalid and to lock signal latch (25) high level effective else if, then data sdata (44) is locked to buffer data ldata (49), select the column data output demonstration of specific weight values to be input to selector switch; Selector switch (33) is that a multidigit N selects a selector switch, the bit wide of gradation data is N, a plurality of N select the shared identical selecting side of a selector switch (to select signal sel, 40), when selecting signal sel (40) input selector (33) for one, selector switch (33) all exports all mutually deserved weights among the gradation data ldata (49) to column data cdata (27), to drive the demonstration of display screen; Signal cdin (22) and cdout (23) have same bit-width in the circuit of the present invention; Data sdata (44) and ldata (49) also have same bit-width.
Be that example illustrates scanning process with 32 grades of gray scales equally, as shown in Figure 4, weights scan by the order of " 1-2-4-8-16 ".
At time point A, under global clock clk (41) effect, by serial input cdin (22) with all images data serial of first row in serializer, the view data of first row transmits and finishes, if the demonstration of previous row does not finish as yet, then must invalid serial enable cdena (48) signal (low level), wait end to be shown, continue to transmit otherwise the serial of remaining valid enables cdena (48) signal (high level) to close transmission; Finish if show, image is blanking, then effective latch (25) signal is to produce the high level pulse of a clock width, and invalid zero clearing clrn (26) signal (high level), to be cached to serial data sdata (44) among the ldata (49) and to begin the demonstration of first row " 1 " image, simultaneously effective serial enables cdena (48) signal (high level) continuation second row " 2 " view data and transmits;
At time point B, the demonstration of beginning first row " 1.1 " image, the weights selection signal sel (40) that produce at scan control circuit are binary number 000, and count corresponding time span, selector switch (33) is selected weights from gray level image data ldata (49) be that 1 data are delivered to column data cdata (27), shows with the driving OLED panel;
At time point C, the demonstration of beginning first row " 1.2 " image, the weights selection signal sel (40) that produce at scan control circuit are binary number 001, and count corresponding time span, selector switch (33) is selected weights from gray level image data ldata (49) be that 2 data are delivered to column data cdata (27), shows with the driving OLED panel;
At time point D, the demonstration of beginning first row " 1.4 " image, the weights selection signal sel (40) that produce at scan control circuit are binary number 010, and count corresponding time span, selector switch (33) is selected weights from gray level image data ldata (49) be that 4 data are delivered to column data cdata (27), shows with the driving OLED panel;
At time point E, the demonstration of beginning first row " 1.8 " image, the weights selection signal sel (40) that produce at scan control circuit are binary number 011, and count corresponding time span, selector switch (33) is selected weights from gray level image data ldata (49) be that 8 data are delivered to column data cdata (27), shows with the driving OLED panel;
At time point F, the demonstration of beginning first row " 1.16 " image, the weights selection signal sel (40) that produce at scan control circuit are binary number 100, and count corresponding time span, selector switch (33) is selected weights from gray level image data ldata (49) be that 16 data are delivered to column data cdata (27), shows with the driving OLED panel;
At time point G, first row " 1 " view data shows and to close to an end, effective zero clearing clrn (26) signal (low level), and with the buffer zero clearing, image shows will begin blanking when next rising edge clock;
At time point H, the first row image shows end;
At time point I, the second row view data transmission finishes, and finishes if the lastrow image shows as yet, then must invalid serial enable cdena (48) to close transmission, continues to transmit otherwise effective serial enables cdena (48); If showing, finishes first row, effectively latch (25) signal is to produce the high level pulse of a clock width, and invalid zero clearing clrn (26) signal (high level), serial data sdata (44) be cached among the ldata (49) and prepare to begin the demonstration of second row " 2 " image, effectively serial enables cdena (48) to continue the transmission of the third line " 3 " view data simultaneously;
At time point J, the demonstration of the beginning second row image, select under the control of signal sel (40) at the weights that scan control circuit produces, selector switch (33) beginning is according to the weights scanning sequency of " 1-2-4-8-16 ", and corresponding time span, from the view data ldata (49) of latch (32) storage, select and deliver to column data cdata (27), show with the driving OLED panel.
Weights order by " 1-2-4-8-16 ", from the demonstration of weights 1, to lock latch (32) to picture blanking and new data and finish, this stage is a line period (from time point C to L), constantly repeat this cycle and carry out the scanning of next line, can finish the scanning of entire image.
Because total caching makes to show when not finishing when transmitting end, can carry out the transmission of next weights in advance, reduces the free time of transmitting; Simultaneously, because total caching the whole buffer memorys of the gradation data of delegation's image, when a weights data presentation finishes, can directly carry out the demonstration of the data of next weights, begin the demonstration of next weights so needn't wait for transmission to finish immediately, reduce the free time that shows.
Management to buffer is by latch (25) and these two signals of clrn (26), management for selector switch is by (40) signals of sel, should guarantee during the sweep circuit design that latch (25) signal and clrn (26) signal are ineffective simultaneously, sel (40) signal can scan according to random order.
Data transmit and depend on cdena (48) signal, as long as cdena (48) effectively can begin the transmission of next line, when transmission is finished as if clrn (26) then invalid clrn (26) and effective latch (25) signal have appearred effectively, otherwise invalid cdena (48) also waits for next clock effectively latch (25) and cdena (48) again after clrn (26) effectively, and invalid clrn (26); And demonstration depends on latch (25) signal, as long as latch (25) effectively then clrn (26) be high simultaneously, begin to select the weights data in proper order, and the demonstration time is counted by weights by sel (40), after the demonstration of entitlement Value Data is finished, clrn (26) is effective, BKP, and next again clock is if clrn (26) is invalid, cdena (48) is invalid, effective latch (25) then if cdena (48) is effective, waits for that then the next clock of cdena (48) after invalid is effective again; Latch (25) and clrn (26) can not simultaneously effectively should keep clrn (26) to be low level at waiting time.
Because the demonstration time of low weights is less than the delivery time, if adopt " 1-2-4-8-16 " weights order, then the demonstration of weights 1 and weights 2 is all finished and is once transmitted and may also not finish, and therefore has to insert show the stand-by period, and this can cause the luminance loss.
When effective demonstration time of adjacent weights during less than corresponding delivery time, must insert the invalid time during scanning and finish to wait for transmitting, will increase total sweep time like this.
The weights sequence adopts " 1-2-4-8-16 " in proper order.
In scan method shown in Figure 4, Ts (1)=1, Tc=32, Fsc=32-31=1, Ftc=32, Rsc=1/32=3.13%, Rtc=32/32=100% compares with method shown in Figure 2, transmission utilization ratio reaches 100%, frame frequency has improved 95.01%, and the luminance loss has reduced by 86.10%, and the luminance loss eliminates substantially.
Under 256 grades high gray scale situations, 256 grades of gray scales have 8 weights, are 1 chronomere with Ts (1), show that then temporal summation is ∑ Ts=255.The scanning sequency of " 1-2-4-8-16-32-64-128 " is adopted in weights scanning.
If get R=1/33, Ftc=8 * 33=264 then, Ts=255 is close with ∑, at this moment pays attention to improving transmitting utilization factor.
In classic method, can calculate Tc=33+33+33+33+33+33+64+128=390, then luminance loss Rsc=34.62% transmits utilization factor Rtc=67.69%.
Use the method for circuit of the present invention, (delivery time is 256 can to calculate Tc=256; The demonstration time is 255; The invalid demonstration time is 256-255=1), then luminance loss Rsc=0.39% can ignore, and transmits utilization factor Rtc=100%, compares with tradition, and the luminance loss reduces 98.87%, and the luminance loss eliminates substantially, reaches 100% and transmit utilization factor.
Can see that after the employing total caching structure, can reduce the luminance loss greatly, even can eliminate fully, meanwhile, display performance also has appreciable raising in arrange control circuit.
The transmission utilization ratio Rtc of circuit of the present invention and luminance loss Rsc can be calculated by following formula:
At first define the columns that M represents the display panel that drives, the figure place of N presentation video gradation data, the data bit width that seals in of serializer is W, for circuit succinct, general M * the N that selects can be divided exactly by W, at this moment (M * N)/a W unit interval is exactly the needed delivery time of gradation data that serializer seals in a full line image
When (M * N)/W 〉=2
N-1 o'clock, Rtc=100%, Rsc=[M * N-(2
N-1) * W]/(M * N) * 100%;
When (M * N)/W＜2
N-1 o'clock, and Rtc=(M * N)/[(2
N-1) * W] * 100%, Rsc=0%.
From above formula as can be seen, when circuit design, in order to reach the highest transfer efficiency and minimum luminance loss, should design as far as possible and make (M * N)/W and 2
N-1 is approaching.
A specific embodiment of the present invention such as Fig. 5, Fig. 6 and shown in Figure 7, this is one the 32 look OLED serial arrange control circuit of itemizing, and entire circuit is by 3 modules, and totally 96 elements constitute, from U1 to U96, wherein, U1 to U32 constitutes serializer (31), and detailed circuit is seen Fig. 5, U33 to U64 constitutes buffer (32), detailed circuit is seen Fig. 6, and U65 to U96 constitutes selector switch (33), and detailed circuit is seen Fig. 7.
Element REG8#ENA is one 8 bit strip enable register, and CLK is a clock, and ENA is that clock enables D[7:0] be input data, Q[7:0] be the register output data, when CLK rising edge and ENA were effective, the IN data latching was to the OUT port.
Element REG8 is the register that one 8 bit synchronization zero clearing band enables, and function and REG8#ENA are similar, increase a synchronous reset signal CLRN, when the CLK rising edge, if CLRN effective (low level), then OUT zero clearing, ENA is effective else if, then with D[7:0] be latching to Q[7:0].
Element 8MUX1 is one 1 eight and selects a selector switch, as SEL[2:0] when being 0, select A0 to export Y to, as SEL[2:0] when being 1, select A1 to export Y to, as SEL[2:0] when being 2, select A2 to export Y to, as SEL[2:0] when being 3, select A3 to export Y to, as SEL[2:0] when being 4, select A4 to export Y to, as SEL[2:0] when being 5, select A5 to export Y to, as SEL[2:0] when being 6, select A6 to export Y to, as SEL[2:0] when being 7, select A7 to export Y to.
Among Fig. 5, constitute a serializer (31) by 32 REG8#ENA, when clk (41) rises and cdena (48) effectively the time, cdin[7:0] (22) be locked into sdata[7:0], simultaneously the low level of sdata every 8 to high bit serial, be sdata[7:0] be locked to sdata[15:8], sdata[15:8] be locked to sdata[23:16], sdata[23:16] be locked to sdata[31:24], by that analogy, and signal sdata[255:248] export cdout[7:0 to] (23) so that row control signal tandem connects, signal sdata[255:0] (24) export buffer (32) to.
Among Fig. 6, element U33 to U64 is buffer (32), when clk (41) rising edge, if clrn (26) is a low level, ldata[31:0 then] (27) output low level, if it is effective that clrn (26) is high level and latch (25), then with sdata[255:0] (45) lock to ldata[255:0] (27).
Among Fig. 7, element U65 to U96 is selector switch (33), as sel[2:0] when (40) are n, then according to ldata[n+i * 8]=cdata[i] (i=0,1,2,3,4,5 ... 31) rule will select a ldata (45) signal to export to cdata (27) with 31 at every interval.
Another specific embodiment of the present invention as shown in Figure 8, it is made of eight identical submodule SU1 to SU8 cascades expansions, submodule 32Driver is the 32 look OLED serial arrange control circuits of describing in first kind of concrete enforcement of itemizing.The clock clk of eight submodule SU1 to SU8 links together and constitutes the clock signal clk of entire circuit, the Enable Pin cdena of eight submodule SU1 to SU8 links together and constitutes the serial enable signal cdena of entire circuit, the clear terminal clrn of eight submodule SU1 to SU8 links together and constitutes the reset signal clrn of entire circuit, the end latch that latchs of eight submodule SU1 to SU8 links together and constitutes the latch signal latch of entire circuit, the weights of eight submodule SU1 to SU8 are selected sel[2:0] weights that constitute entire circuit that link together select signal sel[2:0], the serializer output data cdout[7:0 of SU1] import data cdin[7:0 with the serializer of SU2] link to each other, the serializer output data cdout[7:0 of SU2] import data cdin[7:0 with the serializer of SU3] link to each other, the serializer output data cdout[7:0 of SU3] import data cdin[7:0 with the serializer of SU4] link to each other, the serializer output data cdout[7:0 of SU4] import data cdin[7:0 with the serializer of SU5] link to each other, the serializer output data cdout[7:0 of SU5] import data cdin[7:0 with the serializer of SU6] link to each other, the serializer output data cdout[7:0 of SU6] import data cdin[7:0 with the serializer of SU7] link to each other, the serializer output data cdout[7:0 of SU7] import data cdin[7:0 with the serializer of SU8] link to each other, data width during serial is 8, the serializer input cdin[7:0 of SU1] be the serial input cdin[7:0 of the serializer of entire circuit], the serializer output cdout[7:0 of SU8] be the serial output cdout[7:0 of the serializer of entire circuit], all U1 to U32 have constituted the serializer of entire circuit in eight submodules, all U33 to U64 have constituted the buffer of entire circuit in eight submodules, and all U65 to U96 have constituted the selector switch of entire circuit in eight submodules.
Claims (5)
1. total caching OLED display screen arrange control circuit, comprise that the input data are that serial input signals cdin (22) and output data are the serializer (31) of serial output signal cdout (23), and, it is characterized in that from the buffer (32) of serializer (31) input serial data sdata (44):
(1) also includes the selector switch (33) of importing all data 1data (49) and output column data cdata (27) from buffer (32);
(2) described serializer (31) has the Enable Pin input string to exercise energy signal cdena (48);
(3) described buffer (32) input lock signal 1atch (25) and reset signal clrn (26) is a synchronizing signal;
(4) described selector switch (33) has the selecting side input to select weights input signal sel (40);
(5) described serializer (31), buffer (32) and selector switch (33) adopt unified global clock clk (41).
2. total caching OLED display screen arrange control circuit according to claim 1, it is characterized in that described serializer (31) is the register that the multidigit of group more than band enables, the register figure place is the bit wide of the gradation data of acceptance, the shared identical clock end of a plurality of registers, be global clock clk (41) and shared identical Enable Pin, serial enables cdena (48), the input data of first group of register are serial input signals cdin (22), first group output data is connected to second group input, second group output is connected to the 3rd group input, by that analogy, the data of last group export serial output signal cdout (23) to, each output of organizing register constitutes serial data sdata (44), enable cdena (48) when high level is effective at global clock clk (41) rising edge and serial, each register in the serializer (31) will be imported data and lock to output data.
3. total caching OLED display screen arrange control circuit according to claim 1, it is characterized in that described buffer (32) is that a multidigit band enables the register with zero clearing, the shared identical clock end of a plurality of registers, be global clock clk (41), and signal 1atch (25) and clear terminal input reset signal clrn (26) are locked in shared identical Enable Pin input, when global clock clk (41) rising edge, if reset signal clrn (26) low level is effective, then latch data 1data (49) exports whole low levels, to close the demonstration of display screen, reset signal clrn (26) is invalid and to lock signal 1atch (25) high level effective else if, then data sdata (44) is locked to latch data 1data (49), select the column data output demonstration of specific weight values to be input to selector switch.
4. total caching OLED display screen arrange control circuit according to claim 1, it is characterized in that described selector switch (33) is that a multidigit N selects a selector switch, the bit wide of gradation data is N, a plurality of N select the shared identical selecting side input select signal sel (40) of a selector switch, when selecting signal sel (40) input selector (33) for one, selector switch (33) all exports all mutually deserved weights among all data 1data (49) to column data cdata (27), to drive the demonstration of display screen.
5. total caching OLED display screen arrange control circuit according to claim 1 is characterized in that described serial input signals cdin (22) and serial output signal cdout (23) have same bit-width; Serial data sdata (44) and all data 1data (49) also have same bit-width.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101520980B (en) * | 2009-04-07 | 2010-10-27 | 中国科学院长春光学精密机械与物理研究所 | LED display screen mixed weight-value time-slice scanner |
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| CN101520980B (en) * | 2009-04-07 | 2010-10-27 | 中国科学院长春光学精密机械与物理研究所 | LED display screen mixed weight-value time-slice scanner |
| CN101520981B (en) * | 2009-04-07 | 2011-01-19 | 中国科学院长春光学精密机械与物理研究所 | LED display-screen multi-set parallel weight-value time-slice scanner |
| CN102264176A (en) * | 2010-05-31 | 2011-11-30 | 聚积科技股份有限公司 | Driving device and driving system of LED (light emitting diode) |
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| CN113450704A (en) * | 2020-10-13 | 2021-09-28 | 重庆康佳光电技术研究院有限公司 | LED driving method, driving unit, display device and readable storage medium |
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