CN1940645A - Apparatus and method for transmission data, apparatus and method for driving image display device using the same - Google Patents
Apparatus and method for transmission data, apparatus and method for driving image display device using the same Download PDFInfo
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- CN1940645A CN1940645A CNA2006100834901A CN200610083490A CN1940645A CN 1940645 A CN1940645 A CN 1940645A CN A2006100834901 A CNA2006100834901 A CN A2006100834901A CN 200610083490 A CN200610083490 A CN 200610083490A CN 1940645 A CN1940645 A CN 1940645A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3685—Details of drivers for data electrodes
- G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
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- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
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- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/027—Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
- G09G2330/06—Handling electromagnetic interferences [EMI], covering emitted as well as received electromagnetic radiation
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Abstract
An apparatus and method for data transmission and an apparatus and method for driving an image display device using the same are disclosed, in which transition of data is minimized during data transmission to minimize electromagnetic interference. The apparatus for data transmission includes a data modulator modulating low bits excluding the most significant bit (MSB) in response to the MSB of input data, and a data restorer restoring the modulated data transmitted from the data modulator to their original data in response to the MSB. Since the low data bit excluding the MSB data are inverted in response to the MSB data of the input data, the number of times of data transition can be reduced to reach half, thereby minimizing electromagnetic interference.
Description
The application requires in the right of priority of the Korean Patent Application No. P05-91416 of submission on September 29th, 2005, at this in conjunction with its full content as a reference.
Technical field
The present invention relates to a kind of apparatus and method that are used for data transmission, more specifically, relate to a kind of apparatus and method that are used for the apparatus and method of data transmission and utilize this apparatus and method driving image display device, wherein the conversion of data value is dropped to minimum with minimum electromagnetic interference during data transmission.
Background technology
The developing direction of information display industry is multiple flat-panel display device, and it is compared with cathode-ray tube (CRT) has the weight and volume that reduces.The example of these flat-panel monitors comprises LCD (LCD), field-emitter display (FED), plasma display panel (PDP) and active display (LED).
Especially, LCD comes display image by the light transmission according to vision signal control liquid crystal cells.Active array type LCD is provided with and is formed on the on-off element in each liquid crystal cells and is suitable for showing mobile image.Thin film transistor (TFT) (TFT) is main with the on-off element that acts on active array type LCD.
Fig. 1 has illustrated the prior-art devices that is used to drive LCD.
With reference to figure 1, the prior-art devices that drives LCD comprises image-display units 2, it comprises the liquid crystal cells that is formed in each zone that is limited by article one to the n bar grid line GL1 to GLn and article one to the m bar data line DL1 to DLm, analog video signal is offered the data driver 4 of data line DL1 to DLm, scanning impulse is offered the gate driver 6 of grid line GL1 to GLn, and time schedule controller 8, its adjustment (align) from the source RGB data of outside input to provide it to data driver 4, produce data controlling signal DCS with control data driver 4, and the grid-control system of generation signal GCS is with control gate driver 6.
Image-display units 2 comprises transistor (TFT) array substrate, color filter array substrate, wadding and liquid crystal.Transistor (TFT) array substrate and color filter array substrate face with each other and are bonded to one another.Wadding keeps two box gaps between the substrate equably.Liquid crystal is filled in the liquid crystal region that is limited by wadding.
Image-display units 2 comprises the liquid crystal cells that is formed on the TFT in the zone that is limited by grid line GL1 to GLn and data line DL1 to DLm and is connected to TFT.The TFT response will offer liquid crystal cells from the analog video signal of data line DL1 to DLm from the scanning impulse of grid line GL1 to GLn.Liquid crystal cells is made of the pixel capacitors that faces with each other and have the public electrode of liquid crystal therebetween and be connected to TFT.Therefore, liquid crystal cells is equivalent to liquid crystal capacitance Clc.This liquid crystal cells comprises memory capacitance Cst, and its maintenance is filled in the analog video signal among the liquid crystal capacitance Clc, till next analog video signal is filled in wherein.
Gate driver 6 comprises that response is producing scanning impulse from the grid enabling pulse (GSP) among the grid-control system signal GCS of time schedule controller and grid shift clock (GSC) order, i.e. grid high impulse, shift register.Gate driver 6 offers the grid line GL of image-display units 2 in proper order with the grid high impulse, is connected to the TFT of grid line GL with connection.
Data driver 4 responses will be converted to analog video signal by the data RGB that time schedule controller 8 is adjusted by the data controlling signal DCS that time schedule controller 8 provides, and provide this analog video signal corresponding to a horizontal alignment data line DL1 to DLm of each horizontal cycle, wherein scanning impulse is offered grid line GL1 to GLn at this horizontal cycle.In other words, data driver 4 selects to have the gamma voltage of predetermined level according to the gray-scale value of data RGB, and the gamma voltage that will select offers data line DL1 to DLm.At this moment, data driver 4 response polarity control signals (POL) and counter-rotating offers the polarity of the analog video signal of data line DL.
Fig. 2 has illustrated time schedule controller shown in Figure 1 and the data transmission bus between the data driver.
With reference to Fig. 2 relevant with Fig. 1, time schedule controller 8 comprises control-signals generator 22 and adjustment source data RGB that produces control signal DCS and GCS and the data adjuster 24 that adjusted date is offered data driver 4.
Control-signals generator 22 is utilized major clock MCLK, data enable signal DE and level and vertical synchronizing signal Hsync and the Vsync generation grid-control system signal GCS (GSC, GSP and GOE) and the data controlling signal DCS (SSC, SSP, SOE and POL) of outside input.
Grid-control system signal GCS is provided for gate driver 6 by each transmission line that is included in the grid-control system signal bus (not shown).Data controlling signal DCS is provided for data driver 4 by each transmission line that is included in the data controlling signal bus 12.
Data adjuster 24 is adjusted the outside RGB source data of importing so that it is suitable for bus transmission model, and makes adjusted RGB data and source shift clock (SSC) signal Synchronization so that this data in synchronization is offered data driver 4.For example, data adjuster 24 offers data driver 4 by red, green and blue data bus 14,16 and 18 with adjusted RGB data, and is as shown in table 1.If the RGB source data is 6 data bit, then each data bus 14,16 and 18 is made of six data lines.As a result, data line adds up to 18.
[table 1]
| The position gray level | D5 | D4 | D3 | D2 | D1 | D0 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| 1 | 0 | 0 | 0 | 0 | 0 | 1 |
| 2 | 0 | 0 | 0 | 0 | 1 | 0 |
| 3 | 0 | 0 | 0 | 0 | 1 | 1 |
| | | | | | | |
| 63 | 1 | 1 | 1 | 1 | 1 | 1 |
In table 1, D0～D5 represents one of R, G and B data value.
For example, if current pixel data has bit value " 0 ", next pixel data has bit value " 1 ", then changes in all positions to take place, thereby causes high electromagnetic interference (EMI).Especially, if the resolution of image-display units and size increase, then electromagnetic interference problem becomes more serious.
Summary of the invention
Therefore, the present invention relates to a kind of apparatus and method that are used for the apparatus and method of data transmission and utilize this apparatus and method driving image display device, it has been avoided basically because the restriction of correlation technique and one or more problems that shortcoming causes.
An advantage of the invention is that providing a kind of is used for the apparatus and method of data transmission and utilizes these apparatus and method to drive the apparatus and method of image display device, wherein the conversion of data is minimized with minimum electromagnetic interference during data transmission.
Other advantage of the present invention and feature state in the following description that with part part becomes apparent for those skilled in the art according to following test, maybe can understand from enforcement of the present invention.Purpose of the present invention and other advantages can realize by the structure that particularly points out in described instructions and claims and appended accompanying drawing and obtain.
In order to realize these and other advantages and according to purpose of the present invention, as concrete and general description at this, a kind of device that is used for data transmission comprises data modulator, the low level of highest significant position (MSB) modulation except that this MSB of its response input data, with the data restorer, its response MSB will return to its raw data from the modulated data of data modulator transmission.
Data modulator comprises that described input data are input to many Data In-Lines wherein, counter-rotating is input to a plurality of first phase inverters of the low level of each bar Data In-Line, with a plurality of first selectors, its response MSB selects from the low level of each bar Data In-Line and passes through one of low level of each first phase inverter counter-rotating, and a low level will selecting outputs to many data lines.
The data restorer comprises that counter-rotating is transferred to a plurality of second phase inverters of the low level of each bar data line, with a plurality of second selectors, its response MSB selects from the low level of each bar data line and passes through one of low level of each second phase inverter counter-rotating, and a low level will selecting returns to raw data.
Data modulator utilization input shadow data response MSB modulation low level.
Data modulator comprises that described input data are input to many Data In-Lines wherein, provide many shadow data transmission lines of shadow data, a plurality of first logic gates that the low level that is input to each bar Data In-Line and shadow data are carried out logical operation, with a plurality of first selectors, its response MSB selects from the low level of each bar Data In-Line and passes through one of low level of each first logic gate operation, and a low level will selecting outputs to many data lines.
The data restorer comprises a plurality of second logic gates that the low level that is transferred to each bar data line and shadow data are carried out logical operation, with a plurality of second selectors, its response MSB selects from the low level of each bar data line and passes through one of low level of each second logic gate operation, and a low level will selecting returns to raw data.
Described first and second logic gates are XOR gate.
According to a further aspect in the invention, a kind of device that is used to drive image display device comprises image-display units, it comprises the pixel unit that is formed in each zone that is limited by many grid lines and many data lines, the time schedule controller of the low level of MSB modulation except that this MSB of response external input data, under the control of time schedule controller, scanning impulse is offered the gate driver of grid line, and data driver, its response MSB will return to raw data from the modulated data of time schedule controller transmission, and under the control of time schedule controller restore data be converted to analog video signal and provide it to data line.
According to a further aspect in the invention, a kind of method that is used for data transmission comprise response input data the MSB modulation except that this MSB low level and respond MSB modulated data returned to its raw data.
According to another aspect of the invention, in the method that drives image display device, this display device comprises the pixel unit that is formed in each zone that is limited by many grid lines and many data lines, this method comprises the low level of MSB modulation except that this MSB of response external input data, MSB returns to raw data with modulated data with response, scanning impulse is offered grid line, restore data is converted to analog video signal with synchronous with scanning impulse with inciting somebody to action, and this analog video signal is offered data line.
Should be appreciated that aforementioned general description of the present invention and following detailed description all are exemplary and indicative, and plan provides further explanation of the present invention.
Description of drawings
Included appended accompanying drawing provides further understanding of the present invention, and is included in wherein, constitutes the application's a part, these description of drawings embodiments of the present invention and be used from instructions one and explain principle of the present invention.In the accompanying drawings:
Fig. 1 has illustrated the correlation technique device that is used to drive LCD;
Fig. 2 has illustrated time schedule controller shown in Figure 1 and the data transmission between the data driver;
Fig. 3 has illustrated according to first embodiment of the invention and has been used for the device of data transmission and utilizes this device to drive the device of image display device;
Fig. 4 has illustrated time schedule controller shown in Figure 3 and the data transmission between the data driver;
Fig. 5 has illustrated data modulator shown in Figure 4;
Fig. 6 has illustrated the block diagram of data driver shown in Figure 3;
Fig. 7 has illustrated data restorer shown in Figure 6;
Fig. 8 has illustrated according to second embodiment of the invention and has been used for the device of data transmission and the device that drives image display device with this device;
Fig. 9 has illustrated time schedule controller shown in Figure 8 and the data transmission between the data driver;
Figure 10 has illustrated data modulator shown in Figure 9;
Figure 11 has illustrated the block diagram of data driver shown in Figure 8; And
Figure 12 has illustrated data restorer shown in Figure 11.
Embodiment
To describe embodiments of the invention in detail now, these examples illustrate in appended accompanying drawing.In the case of any possible, identical Reference numeral is represented same or analogous parts in whole accompanying drawing.
Fig. 3 has illustrated according to first embodiment of the invention and has been used for the device of data transmission and utilizes this device to drive the device of image display device.
With reference to figure 3, the device that is used for the device of data transmission and utilizes this device to drive image display device according to first embodiment of the invention comprises image-display units 102, it is included in the liquid crystal cells that forms to each zone that m bar data line DL1 to DLm limits by first to n bar grid line GL1 to GLn and first, time schedule controller 108, it adjusts the source data RGB of outside input and the low bit except that MSB of reversing in response to MSB (highest significant position) data of the data RGB that adjusts, under the control of time schedule controller 108, scanning impulse is offered the gate driver 106 of grid line GL1 to GLn, and data driver 104, it will return to its raw data from the data of time schedule controller 108 transmission in response to the MSB data, and under the control of time schedule controller 108 data recovered will be converted to analog video signal to provide it to data line DL1 to DLm.
Image-display units 102 comprises transistor (TFT) array substrate, color filter array substrate, wadding and liquid crystal.Transistor (TFT) array substrate and color filter array substrate face with each other and are bonded to one another.Wadding keeps two box gaps between the substrate equably.Liquid crystal is filled in the liquid crystal region that is produced by wadding.
Image-display units 102 comprises the liquid crystal cells that is formed on the TFT in the zone that is limited by grid line GL1 to GLn and data line DL1 to DLm and is connected to TFT.This TFT response will offer liquid crystal cells from the analog video signal of data line DL1 to DLm from the scanning impulse of grid line GL1 to GLn.This liquid crystal cells is made of the pixel electrode that faces with each other and have the public electrode of liquid crystal therebetween and be connected to TFT.Therefore, liquid crystal cells is equivalent to liquid crystal capacitance Clc.This liquid crystal cells comprises memory capacitance Cst, and its maintenance is filled in the analog video signal among the liquid crystal capacitance Clc, till next analog video signal is filled in wherein.
Equally, time schedule controller 108 utilizes major clock MCLK, data enable signal DE, level and the vertical synchronizing signal Hsync of outside input and Vsync to produce data controlling signal DCS and grid-control system signal GCS, so that each self-driven sequential of control data driver 104 and gate driver 106.
The data controlling signal DCS that data driver 104 response is provided by time schedule controller 108 will be being converted to analog video signal from the modulated data R ' G ' B ' of time schedule controller 108 transmission, and provide this analog video signal corresponding to a horizontal alignment data line DL of each horizontal cycle, wherein scanning impulse is provided for grid line GL.In other words, data driver 104 selects to have the gamma voltage of predetermined level according to the gray-scale value of modulated data R ' G ' B ', and the gamma voltage that will select offers data line DL1 to DLm.The polarity of the analog video signal of data line DL is provided in response to the polarity control signal that is provided by time schedule controller 108 (POL) counter-rotating data driver 104.
Fig. 4 has illustrated time schedule controller shown in Figure 3 and the data transmission bus between the data driver.
With reference to Fig. 4 relevant with Fig. 3, time schedule controller 108 comprises the control-signals generator 122 that produces control signal DCS and GCS, data adjuster 124 and the data modulator 126 of adjusting source data RGB, this data modulator 126 with the low bit of counter-rotating except that these MSB data, and provides it to data driver 104 in response to the MSB data of adjusted data RGB.
Control-signals generator 122 is utilized from major clock MCLK, data enable signal DE, level and the vertical synchronizing signal Hsync of outside input and Vsync and is produced grid-control system signal GCS (GSC, GSP and GOE) and data controlling signal DCS (SSC, SSP, SOE and POL).
Grid-control system signal GCS is provided for gate driver 106 by each transmission line that is included in the grid-control system signal bus (not shown).Data controlling signal DCS is provided for data driver 104 by each transmission line that is included in the data controlling signal bus 112.
For this reason, as shown in Figure 5, data modulator 126 comprises first to the 5th phase inverter 1301 to 1305, it is connected to first to the 5th data bit D0 to the D4 incoming line except that the 6th data bit D5 transmission line, and first to the 5th multiplexer 1321 to 1325, it responds the 6th data bit and selects from the data bit of first to the 5th data bit incoming line with by one of data bit of phase inverter 1301 to 1305 counter-rotatings, and the data bit of selecting is transferred to data driver 104 by each data line.
At first, each R, G and the B data of adjusting from data adjuster 124 are provided for first to the 6th data bit incoming line.
Each phase inverter 1301 to 1305 is electrically connected to first to the 5th data bit incoming line with first to the 5th data bit of reversing, and the data that will reverse offer each multiplexer 1321 to 1325.
Each multiplexer 1321 to 1325 comprises the first input end that is electrically connected to first to the 5th data bit incoming line, is electrically connected to second input end of output terminal of each phase inverter 1301 to 1305 and the control end that is electrically connected to the 6th data bit incoming line.The 6th data bit D5 that offers the 6th data bit incoming line controls each multiplexer 1321 to 1325, and is provided for data driver 104 simultaneously.
Each multiplexer 1321 to 1325 selects to offer the data bit of one of first and second input ends in response to the 6th data bit D5 that offers the 6th data bit incoming line, and the data bit of output selection.In other words, as shown in table 2, if the 6th data bit D5 is " 0 ", then each multiplexer 1321 to 1325 is transferred to data driver 104 by the data bit D0 to D4 that data line will offer first input end.On the contrary, if the 6th data bit D5 is " 1 ", then each multiplexer 1321 to 1325 is transferred to data driver 104 by the invert data bits D0 to D4 that data line will offer second input end.
[table 2]
| The position gray level | D5 | D4 | D3 | D2 | D1 | D0 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| 1 | 0 | 0 | 0 | 0 | 0 | 1 |
| 2 | 0 | 0 | 0 | 0 | 1 | 0 |
| | | | | | | |
| 29 | 0 | 1 | 1 | 1 | 0 | 1 |
| 30 | 0 | 1 | 1 | 1 | 1 | 0 |
| 31 | 0 | 1 | 1 | 1 | 1 | 1 |
| 32 | 1 | 1 | 1 | 1 | 1 | 1 |
| 33 | 1 | 1 | 1 | 1 | 1 | 0 |
| 34 | 1 | 1 | 1 | 1 | 0 | 1 |
| | | | | | | |
| 61 | 1 | 0 | 0 | 0 | 1 | 0 |
| 62 | 1 | 0 | 0 | 0 | 0 | 1 |
| 63 | 1 | 0 | 0 | 0 | 0 | 0 |
Therefore, as shown in table 2, data modulator 126 responds the 6th data bit D5 and first to the 5th data bit D0 to D4 that reverses, and the data bit that will reverse is transferred to data driver 104.As a result, the number of times of data-switching might be reduced half during data transmission.For example, if first to the 6th adjusted data bit D0 to D5 is " 000000 "～" 011111 ", then the 6th data bit D5 is " 0 ".Therefore, data modulator 126 will from first to the 6th data bit incoming line provide and the data transmission selected by each multiplexer 1321 to 1325 to data driver 104.On the contrary, if first to the 6th adjusted data bit D0 to D5 is " 100000 "～" 111111 ", then the 6th data bit D5 is " 1 ".Therefore, data modulator 126 will arrive data driver 104 by each phase inverter 1301 to 1305 counter-rotating and the data transmission of selecting by each multiplexer 1321 to 1325.
Fig. 6 has illustrated the block diagram of data driver shown in Figure 3.
With reference to Fig. 6 relevant with Fig. 5, data driver 104 comprises that order produces the shift register 150 of sampled signal, to return to the data restorer 160 of its raw data RGB by the data R ' G ' B ' of data modulator 126 modulation, response sampled signal and latching from the latch 170 of data restorer 160 data recovered RGB, select the digital analog converter (DAC) 180 of one of a plurality of gamma voltage GMA with the generation analog video signal in response to latched data RGB, and the output unit 190 of buffering analog video signal to provide it to data line.
Source enabling pulse (SSP) and source shift clock (SSC) order that shift register 150 is used in the data controlling signal of time schedule controller 108 produce sampled signal and provide it to latch 170.
Fig. 7 has illustrated data restorer shown in Figure 6.
With reference to Fig. 7 relevant with Fig. 6, data restorer 160 comprises first to the 5th phase inverter 1621 to 1625, it is connected to first to the 5th modulating data position D0 ' except that the 6th data bit D5 ' transmission line to D4 ' transmission line, and first to the 5th multiplexer 1641 to 1645, it responds the 6th data bit D5 ' and selects from the data bit of modulated first to the 5th data bit transmission line with by one of data bit of phase inverter 1621 to 1625 counter-rotatings, and the data bit of selecting is offered latch 170.
At first, offer data restorer 160 by R, the G of data modulator 126 modulation and each in the B data by first to the 6th data bit transmission line.
Each phase inverter 1621 to 1625 is electrically connected to first to the 5th data bit transmission line, offers each multiplexer 1641 to 1645 with first to the 5th data bit D0 ' that reverses to D4 ' and the data that will reverse.
Each multiplexer 1641 to 1645 comprises the first input end that is electrically connected to first to the 5th data bit transmission line, be electrically connected to each phase inverter 1621 to 1625 output terminal second input end and be electrically connected to the control end of the 6th data bit transmission line.The 6th data bit D5 ' that offers the 6th data bit transmission line controls each multiplexer 1641 to 1645, and is provided for latch 170 simultaneously.
Each multiplexer 1641 to 1645 response MSB promptly offers the 6th data bit D5 ' of the 6th data bit transmission line, and selects to offer the data bit of one of first and second input ends and the data bit of output selection.In other words, if the 6th data bit D5 ' is " 0 ", then each multiplexer 1641 to 1645 data bit D0 ' that will offer first input end is transferred to latch 170 to D4 '.On the contrary, if the 6th data bit D5 ' is " 1 ", then each multiplexer 1641 to 1645 invert data bits D0 to D4 that will offer the two or two input end is transferred to latch 170.
Therefore, data restorer 160 response the 6th data bit D5 ' and reverse first to the 5th modulated data position D0 ' to D4 ' recovering its raw data R6B, and data recovered RGB offers latch 170.For example, if first to the 6th data bit D0 ' is " 000000 "～" 011111 " to D5 ', then the 6th data bit D5 is " 0 ".Therefore, data restorer 160 will from first to the 6th data bit transmission line provide and the data transmission selected by each multiplexer 1641 to 1645 to latch 170.On the contrary, if first to the 6th data bit DO ' is " 100000 "～" 111111 " to D5 ', then the 6th data bit D5 is " 1 ".Therefore, data restorer 160 will arrive latch 170 by each phase inverter 1621 to 1625 counter-rotating and the data transmission of selecting by each multiplexer 1641 to 1645.
Be used for the device of data transmission according to first embodiment of the invention and utilizing this device to drive the device of image display device, low bit except that the MSB data of input data responds these MSB data and is inverted, so that the number of times of data-switching is reduced to half, thus minimum electromagnetic interference.
Fig. 8 has illustrated according to second embodiment of the invention and has been used for the device of data transmission and utilizes this device to drive the device of image display device.
With reference to figure 8, the device that is used for the device of data transmission and utilizes this device to drive image display device according to second embodiment of the invention comprises image-display units 102, it comprises and being formed on by first to n bar grid line GL1 to GLn and first the liquid crystal cells to each zone that m bar data line DL1 to DLm limits, time schedule controller 208, it adjusts the source RGB data of outside input and the low bit of MSB data-modulated except that the MSB data that data RGB is adjusted in response, under the control of time schedule controller 208, scanning impulse is offered the gate driver 106 of grid line GL1 to GLn, with data driver 204, its response MSB data will return to its raw data from the data of time schedule controller 208 transmission, and under the control of time schedule controller 208 data recovered will be converted to analog video signal to provide it to data line DL1 to DLm.
Above-mentionedly be used for the device of data transmission and utilize device that this device drives image display device except time schedule controller 208 and data driver 204, have the structure identical with the device of first embodiment of the invention according to second embodiment of the invention.Therefore, with time schedule controller 208 and the data driver 204 described according to second embodiment of the invention.
Fig. 9 has illustrated time schedule controller shown in Figure 8 and the data transmission bus between the data driver.
With reference to Fig. 9 relevant with Fig. 8, time schedule controller 208 comprises the control-signals generator 222 that produces control signal DCS and GCS, the data adjuster 224 of adjustment source RGB data, with data modulator 226, the MSB data of this data modulator 226 response adjusted data RGB and modulate low bit except that the MSB data, and provide it to data driver 204.
Control-signals generator 222 utilizes major clock MCLK, data enable signal DE, level and the vertical synchronizing signal Hsync of outside input and Vsync to produce grid-control system signal GCS (GSC, GSP and GOE) and data controlling signal DCS (SSC, SSP, SOE and POL).
Grid-control system signal GCS is supplied to gate driver 106 by each transmission line that is included in the grid-control system signal bus (not shown).Data controlling signal DCS is supplied to data driver 204 by each transmission line that is included in the data controlling signal bus 112.
In addition, data modulator 226 will comprise that by red, green and blue data bus 114,116 and 118 the MSB data D5 of adjusted data RGB and modulated data position D0 ' offer data driver 204 to the red, green and blue data R ' G ' B ' of D4 '.At this moment, each red, green and blue data bus 114,116 and 118 is made of six data lines.As a result, data line adds up to 18.
For this reason, as shown in figure 10, data modulator 226 comprises first to the 5th different valve XOR 2301 to 2305, it is connected to shadow data transmission line 119 and first to the 5th data bit incoming line except that the 6th data bit incoming line, and first to the 5th multiplexer 2321 to 2325, it responds the 6th data bit D5 and selects from the data bit of first to the 5th data bit incoming line with by one of data bit of each XOR gate 2301 to 2305 modulation, and the data bit of selecting is transferred to data driver 204 by each data line.
At first, from each R that data adjuster 224 is adjusted, G and B data are provided for first to the 6th data bit incoming line.
Each XOR gate 2301 to 2305 is electrically connected to first to the 5th data bit incoming line and shadow data transmission line 119 so that first to the 5th data bit and shadow data Mb are carried out xor operation, and resulting data are offered each multiplexer 2321 to 2325.For example, if the first data bit D0 is different from the first shadow data position of shadow data Mb, then first XOR gate 2301 offers first multiplexer 2321 with data bit " 1 ".On the contrary, if not this situation, then first XOR gate 2301 offers first multiplexer 2321 with data bit " 0 ".
Each multiplexer 2321 to 2325 comprises the first input end that is electrically connected to first to the 5th data bit incoming line, be electrically connected to each XOR gate 2301 to 2305 output terminal second input end and be electrically connected to the control end of the 6th data bit transmission line.The 6th data bit D5 that offers the 6th data bit incoming line controls each multiplexer 2321 to 2325, and is provided for data driver 204 simultaneously.
Each multiplexer 2321 to 2325 responds MSB, promptly offers the 6th data bit D5 of the 6th data bit incoming line, selects to offer the data bit of one of first and second input ends, and the data bit of output selection.In other words, as shown in table 2, if the 6th data bit D5 is " 0 ", then each multiplexer 2321 to 2325 is transferred to data driver 204 by the data bit D0 to D4 that data line will offer first input end.On the contrary, if the 6th data bit D5 is " 1 ", then each multiplexer 2321 to 2325 data bit D0 to D4 that will offer the xor operation of second input end is transferred to data driver 204.
As mentioned above, data modulator 226 response the 6th data bit D5 carries out the xor operation of the shadow data Mb and first to the 5th data bit D0 to D4, and the data transmission that will carry out xor operation is to data driver 204.As a result, might during data transmission, reduce the number of times of data-switching more significantly.For example, if first to the 6th adjusted data bit D0 to D5 is " 000000 "～" 011111 ", then the 6th data bit D5 is " 0 ".Therefore, data modulator 226 will from first to the 6th data bit incoming line provide and the data transmission selected by each multiplexer 2321 to 2325 to data driver 204.On the contrary, if first to the 6th adjusted data bit D0 to D5 is " 100000 "～" 111111 ", then the 6th data bit D5 is " 1 ".Therefore, data modulator 226 will arrive data driver 204 by the shadow data Mb of each multiplexer 2321 to 2325 selection and the xor operation data transmission of first to the 5th data bit D0 to D5.
Figure 11 has illustrated the block diagram of data driver shown in Figure 8.
With reference to Figure 11 relevant with Fig. 8, data driver 204 comprises that order produces the shift register 150 of sampled signal, to return to the data restorer 260 of its raw data RGB by the data R ' G ' B ' of data modulator 126 modulation, the response sampled signal latchs from the latch 170 of data restorer 260 data recovered RGB, response latch data RGB selects one of a plurality of gamma voltage GMA to produce the digital analog converter (DAC) 180 of analog video signal, and gentle punch die is intended the output unit 190 of vision signal to provide it to data line.
For this reason, as shown in figure 12, data restorer 260 comprises first to the 5th XOR gate 2621 to 2625, it is connected to shadow data transmission line and first to the 5th modulated data position D0 ' except that the 6th data bit D5 ' transmission line to D4 ' transmission line, with first to the 5th multiplexer 2641 to 2645, it responds the 6th data bit D5 ' and selects from the data bit of first to the 5th data bit transmission line with from one of data bit of each XOR gate 2621 to 2625, and the data bit of selecting is transferred to latch 170.
At first, offer data restorer 260 by R, the G of data modulator 226 modulation and each in the B data by first to the 6th data bit transmission line.
Each XOR gate 2621 to 2625 is electrically connected to first to the 5th data bit D0 to the D4 transmission line and shadow data transmission line 119 carrying out the xor operation of first to the 5th modulated data position D0 ' to D4 ' and shadow data Mb, and resulting data are offered each multiplexer 2641 to 2645.For example, if the first data bit D0 ' is different from the first shadow data position of shadow data Mb, then first XOR gate 2621 offers first multiplexer 2641 with data bit " 1 ".On the contrary, if not this situation, then first XOR gate 2621 offers first multiplexer 2641 with data bit " 0 ".
Each multiplexer 2641 to 2645 comprises the first input end that is electrically connected to first to the 5th data bit D0 to the D4 transmission line, be electrically connected to each XOR gate 2621 to 2625 output terminal second input end and be electrically connected to the control end of the 6th data bit transmission line.The 6th data bit D5 that offers the 6th data bit transmission line controls each multiplexer 2641 to 2645, and is provided for latch 170 simultaneously.
Each multiplexer 2641 to 2645 responds MSB, promptly offers the 6th data bit D5 ' of the 6th data bit transmission line, selects to offer the data bit of one of first and second input ends, and the data bit of output selection.In other words, as shown in table 2, if the 6th data bit D5 ' is " 0 ", then each multiplexer 2641 to 2645 data bit D0 to D4 that will offer first input end is transferred to latch 170.On the contrary, if the 6th data bit D5 ' is " 1 ", then each multiplexer 2641 to 2645 xor operation data bit D0 to D4 that will offer second input end is transferred to latch 170.
As mentioned above, data restorer 260 response the 6th data bit D5 ' carries out shadow data Mb and first to the 5th data bit D0 ' xor operation to D4 ', and the data transmission that will carry out xor operation is to latch 170.As a result, might during data transmission, reduce the number of times of data-switching more significantly.For example, if first to the 6th adjusted data bit D0 ' is " 000000 "～" 011111 " to D5 ', then the 6th data bit D5 ' is " 0 ".Therefore, data restorer 260 will from first to the 5th data bit D0 ' to D4 ' transmission line provide and the data transmission selected by each multiplexer 2641 to 2645 to latch 170.On the contrary, if first to the 6th adjusted data bit D0 ' is " 100000 "～" 111111 " to D5 ', then the 6th data bit D5 ' is " 1 ".Therefore, the data restorer 260 shadow data Mb that will select by each multiplexer 2641 to 2645 and first to the 5th data bit D0 ' to the xor operation data transmission of D5 ' to latch 170.
Be used for the device of data transmission according to second embodiment of the invention and utilizing this device to drive the device of image display device, low bit except that the MSB data responds the MSB data of importing data with shadow data, through xor operation, so that the number of times of data-switching can reduce during data transmission more significantly, thus minimum electromagnetic interference.
It is above-mentioned that first and second embodiments are used for the device of data transmission and utilize device that this device drives image display device except being used to have the LCD plate of liquid crystal cells, the plasma display panel that can also be used to have the light-emitting display device of luminescence unit or have discharge cell according to the present invention.
As mentioned above, be used for the apparatus and method of data transmission and utilize these apparatus and method to drive the apparatus and method of image display device above-mentioned according to the preferred embodiment of the present invention, the MSB data of the low bit response input data except that the MSB data are inverted, so that the number of times of data-switching can be reduced to half, thus minimum electromagnetic interference.
In addition, the low bit except that the MSB data responds the MSB data of input data with shadow data, through xor operation, so that the number of times of data-switching can reduce during data transmission more significantly, and minimum electromagnetic interference thus.
It will be apparent to those skilled in the art that multiple modification and change and to obtain in the present invention, as long as without departing from the spirit and scope of the present invention.Thereby the present invention covers these modification and variation, as long as they are in the scope of claims and equivalent thereof.
Claims (35)
1, a kind of device that is used for data transmission comprises:
Data modulator, its response have the low level of highest significant position modulation except that this Must Significant Bit of the input data of original value; With
The data restorer, it responds described highest significant position and will return to its original value from the modulated data of data modulator transmission.
2, device according to claim 1 is characterized in that, described data modulator comprises:
Described input data are input to many Data In-Lines wherein;
Counter-rotating is input to a plurality of first phase inverters of the low level of each bar Data In-Line; With
A plurality of first selectors, it responds described highest significant position and selects from one of the low level of each bar Data In-Line and the low level by each described first phase inverter counter-rotating, and a low level will selecting outputs to many data lines.
3, device according to claim 2 is characterized in that, described data restorer comprises:
Counter-rotating is transferred to a plurality of second phase inverters of the low level of each many data line; With
A plurality of second selectors, it responds described highest significant position and selects from one of the low level of each bar data line and the low level by each described second phase inverter counter-rotating, and a low level will selecting returns to raw data.
4, device according to claim 1 is characterized in that, described data modulator utilization input shadow data responds described highest significant position and modulates described low level.
5, device according to claim 4 is characterized in that, described data modulator comprises:
Described input data are input to many Data In-Lines wherein;
Provide many shadow data transmission lines of shadow data;
A plurality of first logic gates that the described low level that is input to each bar Data In-Line and shadow data are carried out logical operation; With
A plurality of first selectors, it responds described highest significant position and selects from one of the low level of each bar Data In-Line and the low level by each first logic gate operation, and a low level will selecting outputs to many data lines.
6, device according to claim 5 is characterized in that, described first logic gate is an XOR gate.
7, device according to claim 5 is characterized in that, described data restorer comprises:
A plurality of second logic gates that the low level that is transferred to each bar data line and shadow data are carried out logical operation; With
A plurality of second selectors, it responds described highest significant position and selects from one of the low level of each bar data line and the low level by each second logic gate operation, and a low level will selecting returns to raw data.
8, device according to claim 7 is characterized in that, described second logic gate is an XOR gate.
9, a kind of device that is used to drive image display device comprises:
Image-display units, it comprises the pixel unit that is formed in each zone that is limited by many grid lines and many data lines;
The highest significant position of response external input data and modulate time schedule controller except that the low level this highest significant position;
Under the control of described time schedule controller, scanning impulse is offered the gate driver of described grid line; With
Data driver, it responds described highest significant position and will return to raw data from the modulated data of time schedule controller transmission, and under the control of time schedule controller restore data be converted to analog video signal and provide it to described data line.
10, device according to claim 9 is characterized in that, described time schedule controller comprises:
Generation is used to control the control-signals generator of the control signal of described gate driver and data driver;
Adjust described input data so that it is suitable for driving the data adjuster of described image-display units; With
Data modulator, the highest significant position of its response adjusted data and modulate except that the low level this highest significant position and with modulated data and be transferred to described data driver.
11, device according to claim 10 is characterized in that, described data modulator comprises:
Described input data are input to many Data In-Lines wherein;
Counter-rotating is input to a plurality of first phase inverters of the low level of each bar Data In-Line; With
A plurality of first selectors, it responds described highest significant position and selects from one of the low level of each bar Data In-Line and the low level by each first phase inverter counter-rotating, and a low level will selecting outputs to many data lines.
12, device according to claim 11 is characterized in that, described data driver comprises:
Order produces the shift register of sampled signal;
Respond described highest significant position and will return to the data restorer of its raw data by the modulating data of described data modulator transmission;
Respond described sampled signal and latch the latch of restore data; With
To be converted to analog video signal by the data that latch provides to provide it to the digital analog converter of data line.
13, device according to claim 12 is characterized in that, described data restorer comprises:
Counter-rotating is transferred to a plurality of second phase inverters of the low level of each bar data line; With
A plurality of first selectors, it responds described highest significant position and selects from one of the low level of each bar data line and the low level by each second phase inverter counter-rotating, and a low level will selecting returns to raw data.
14, device according to claim 10 is characterized in that, described data modulator utilization input shadow data responds described highest significant position and modulates described low level.
15, device according to claim 14 is characterized in that, described data modulator comprises:
Described input data are input to many Data In-Lines wherein;
Provide many shadow data transmission lines of shadow data;
A plurality of first logic gates that the low level that is input to each bar Data In-Line and shadow data are carried out logical operation; With
A plurality of second selectors, it responds described highest significant position and selects from one of the low level of each bar Data In-Line and the low level by each first logic gate operation, and a low level will selecting outputs to many data lines.
16, device according to claim 15 is characterized in that, described first logic gate is an XOR gate.
17, device according to claim 15 is characterized in that, described data driver comprises:
Order produces the shift register of sampled signal;
Respond described highest significant position and will return to the data restorer of its raw data by the modulating data of data modulator transmission;
Respond described sampled signal and latch the latch of restore data; With
To be converted to analog video signal by the data that latch provides to provide it to the digital analog converter of described data line.
18, device according to claim 17 is characterized in that, described data restorer comprises:
A plurality of second logic gates that the low level that is transferred to each bar data line and shadow data are carried out logical operation; With
A plurality of second selectors, it responds described highest significant position and selects from one of the low level of each bar data line and the low level by each second logic gate operation, and a low level will selecting returns to raw data.
19, device according to claim 18 is characterized in that, described second logic gate is an XOR gate.
20, a kind of method that is used for data transmission comprises:
A) response is imported the highest significant position of data and is modulated except that the low level this highest significant position; With
B) respond described highest significant position and modulated data is returned to its raw data.
21, method according to claim 20 is characterized in that, described step a) comprises:
Counter-rotating is input to the low level of many Data In-Lines; With
Respond described highest significant position and select, and a low level will selecting outputs to many data lines from one of the low level of each bar Data In-Line and low level of counter-rotating.
22, method according to claim 21 is characterized in that, described step b) comprises:
Counter-rotating is transferred to the low level of each bar data line; With
Respond described highest significant position and select, and a low level will selecting returns to raw data from one of the low level of each bar data line and low level of counter-rotating.
23, method according to claim 20 is characterized in that, described step a) comprises utilizes the input shadow data to respond described highest significant position and modulate described low level.
24, method according to claim 23 is characterized in that, described step a) comprises:
A1) low level and the described shadow data that is input to each bar Data In-Line carried out logical operation; With
A2) response described highest significant position and selecting from one of the low level of each bar Data In-Line and low level of having operated, and a low level will selecting outputs to many data lines.
25, method according to claim 24 is characterized in that, described step b) comprises:
B1) low level and the described shadow data that is transferred to each bar data line carried out logical operation; With
B2) the described highest significant position of response and selecting from one of the low level of each bar data line and the low level by each second logic gate operation, and a low level will selecting returns to raw data.
26, method according to claim 25 is characterized in that, described logical operation is xor operation.
27, a kind of method that is used to drive image display device, this display device comprises the pixel unit that is formed in each zone that is limited by many grid lines and many data lines, this method comprises:
A) response external is imported the highest significant position of data and is modulated except that the low level this highest significant position;
B) respond described highest significant position and modulated data is returned to raw data;
C) scanning impulse is offered described grid line; With
D) restore data is converted to analog video signal with synchronous with scanning impulse, and this analog video signal is offered described data line.
28, method according to claim 27 is characterized in that, described step a) comprises:
Counter-rotating is input to the low level of many Data In-Lines; With
Respond described highest significant position and select, and a low level will selecting outputs to many data lines from one of the low level of each bar Data In-Line and low level of counter-rotating.
29, method according to claim 28 is characterized in that, described step b) comprises:
Counter-rotating is input to the low level of each bar data line; With
Respond described highest significant position and select, and a low level will selecting returns to raw data from one of the low level of each bar data line and low level of counter-rotating.
30, method according to claim 27 is characterized in that, described step d) comprises:
Order produces sampled signal;
Respond described sampled signal and latch restore data; With
Latched data is converted to analog video signal to output it to described data line.
31, method according to claim 27 is characterized in that, described step a) comprises to be utilized shadow data to respond described highest significant position and modulate described low level.
32, method according to claim 31 is characterized in that, described step a) comprises:
Low level and the shadow data that is input to each bar Data In-Line carried out logical operation; With
Respond described highest significant position and select, and a low level will selecting outputs to many data lines from one of the low level of each bar Data In-Line and low level of having operated.
33, method according to claim 32 is characterized in that, described step b) comprises:
Low level and the shadow data that is transferred to each bar data line carried out logical operation; With
Respond described highest significant position and select, and a low level will selecting returns to raw data from one of the low level of each bar data line and low level of having operated.
34, method according to claim 33 is characterized in that, described logical operation is xor operation.
35, method according to claim 31 is characterized in that, described step d) comprises:
Order produces sampled signal;
Respond described sampled signal and latch restore data; With
Latched data is converted to analog video signal it is outputed to described data line.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020050091416A KR101157950B1 (en) | 2005-09-29 | 2005-09-29 | Apparatus and method for driving image display device using the same |
| KR1020050091416 | 2005-09-29 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1940645A true CN1940645A (en) | 2007-04-04 |
| CN100507648C CN100507648C (en) | 2009-07-01 |
Family
ID=37893695
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2006100834901A Expired - Fee Related CN100507648C (en) | 2005-09-29 | 2006-05-30 | Apparatus and method for transmission data, apparatus and method for driving image display device using the same |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US7920115B2 (en) |
| JP (1) | JP4933146B2 (en) |
| KR (1) | KR101157950B1 (en) |
| CN (1) | CN100507648C (en) |
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| CN101645258B (en) * | 2008-08-04 | 2013-03-20 | 乐金显示有限公司 | Method for minimizing data transition and circuit for minimizing data transition |
| CN106205452A (en) * | 2015-05-29 | 2016-12-07 | 乐金显示有限公司 | Timing controller and display device |
| CN108269551A (en) * | 2016-12-30 | 2018-07-10 | 乐金显示有限公司 | DIU display interface unit and its data transmission method |
| WO2019080589A1 (en) * | 2017-10-26 | 2019-05-02 | 京东方科技集团股份有限公司 | Source driving sub-circuit and driving method thereof, source driving circuit, and display device |
| US11120767B2 (en) | 2018-04-20 | 2021-09-14 | Ordos Yuansheng Optoelectronics Co., Ltd. | Source driving circuit and method for driving the same, and display apparatus |
| TWI827261B (en) * | 2022-09-15 | 2023-12-21 | 大陸商常州欣盛半導體技術股份有限公司 | Automatic tuning of clock skew within a display system |
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| KR101235696B1 (en) * | 2012-09-28 | 2013-02-21 | 주식회사 아나패스 | Method for data transmission and method for data recovery |
| KR101815895B1 (en) * | 2015-05-29 | 2018-01-09 | 엘지디스플레이 주식회사 | Data driver, display device, and data driving method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101645258B (en) * | 2008-08-04 | 2013-03-20 | 乐金显示有限公司 | Method for minimizing data transition and circuit for minimizing data transition |
| CN106205452A (en) * | 2015-05-29 | 2016-12-07 | 乐金显示有限公司 | Timing controller and display device |
| US10229626B2 (en) | 2015-05-29 | 2019-03-12 | Lg Display Co., Ltd. | Timing controller generating pseudo control data included in control packet and N-bit image data included in RGB packet |
| CN108269551A (en) * | 2016-12-30 | 2018-07-10 | 乐金显示有限公司 | DIU display interface unit and its data transmission method |
| CN108269551B (en) * | 2016-12-30 | 2020-10-23 | 乐金显示有限公司 | Display interface device and data transmission method thereof |
| WO2019080589A1 (en) * | 2017-10-26 | 2019-05-02 | 京东方科技集团股份有限公司 | Source driving sub-circuit and driving method thereof, source driving circuit, and display device |
| US11011247B2 (en) | 2017-10-26 | 2021-05-18 | Ordos Yuansheng Optoelectronics Co., Ltd. | Source driving sub-circuit and driving method thereof, source driving circuit, and display device |
| US11120767B2 (en) | 2018-04-20 | 2021-09-14 | Ordos Yuansheng Optoelectronics Co., Ltd. | Source driving circuit and method for driving the same, and display apparatus |
| TWI827261B (en) * | 2022-09-15 | 2023-12-21 | 大陸商常州欣盛半導體技術股份有限公司 | Automatic tuning of clock skew within a display system |
Also Published As
| Publication number | Publication date |
|---|---|
| KR101157950B1 (en) | 2012-06-25 |
| KR20070036417A (en) | 2007-04-03 |
| US7920115B2 (en) | 2011-04-05 |
| JP2007094365A (en) | 2007-04-12 |
| JP4933146B2 (en) | 2012-05-16 |
| US20070070750A1 (en) | 2007-03-29 |
| CN100507648C (en) | 2009-07-01 |
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