CN101047131A - Method for manufacturing insulated-gate type field effect transistor - Google Patents
Method for manufacturing insulated-gate type field effect transistor Download PDFInfo
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- CN101047131A CN101047131A CN 200710088459 CN200710088459A CN101047131A CN 101047131 A CN101047131 A CN 101047131A CN 200710088459 CN200710088459 CN 200710088459 CN 200710088459 A CN200710088459 A CN 200710088459A CN 101047131 A CN101047131 A CN 101047131A
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Abstract
The invention discloses a method for manufacturing an insulating gate field effect transistor . A poly-silicon layer is deposited on a surface of a substrate after forming a gate insulating film in an element hole of a field insulating film 12, and thereon a silicon oxide layer is formed by a thermal oxidation process. After patterning the silicon oxide layer in accordance with a gate electrode pattern, the poly-silicon layer is patterned by dry-etching using a remaining resist layer as a mask. After removing the resist layer, a gate electrode layer 16 a is formed by decreasing a width of the poly-silicon layer by isotropic etching using the silicon oxide layer 18 A as a mask. N<+>-type source and drain regions 22 and 24 and n<->-type source and drain regions 26 and 28 are formed by doping impurity ions via the gate insulating film 14 through the silicon oxide layer 18 A. The silicon oxide layer 18 A may be made of a layer of tungsten silicide.
Description
Technical field
The present invention relates to a kind of manufacture method with the insulated-gate type field effect transistor that extends drain electrode structure etc.
Background technology
Common known a kind of insulated-gate type field effect transistor with lightly doped drain (LDD) structure.It is similar substantially to the LDD structure to extend drain electrode structure, but extending drain electrode structure can avoid owing to increase the mis-behave that the dead resistance of impurity concentration causes, in other words, it carries out ion doping by comparing with lower energy with the drain region with source area, can suppress short-channel effect.Incidentally, the amount of the dopant in LDD district is up to about 5 * 10
13Cm
-2, and the dopant dose of extension drain region is about 1 * 10
14Cm
-2To 1 * 10
15Cm
-2, and the dopant dose of source area and drain region is not less than 1 * 10
15Cm
-2General it is said, since the thickness of gate electrode (wiring) becomes about 0.25 μ m, the LDD structure has been extended drain electrode structure and has replaced because by LDD partly in the mis-behave that causes of dead resistance can not be out in the cold.
The manufacture method of the insulated-gate type field effect transistor with LDD structure of known a kind of routine shown in Figure 17 to 19.This method for example discloses in TOHKEMY communique No.H06-275635.
In technology shown in Figure 17, on a first type surface of p N-type semiconductor N substrate 1, form have the field insulating membrane 2 of component hole 2a after, the gate insulating film of being made by silica etc. 3 is formed on the semiconductor surface of component hole 2a.On dielectric film 3 after the deposit spathic silicon layer, carry out etch process by utilizing resist layer 5 as mask, form the gate electrode layer of forming by the remainder of polysilicon layer 4.At this moment, the gate insulating film 3 under gate electrode layer 4 is retained, and other parts of gate insulating film 3 are then removed by etching.
In technology shown in Figure 180, under the situation by resist layer 5 covering grid electrode layers 4, by the lateral erosion carving technology, each lateral edges of gate electrode layer 4 is stepped back the distance of about Δ d=0.15 μ m from the lateral edges of resist layer.As a result, for example, the width of gate electrode layer 4 (grid width) is reduced to 0.8 μ m to 0.5 μ m.
In technology shown in Figure 19, remove after the resist layer 5, by adopting the mask Doping Phosphorus ion of forming by the lamination and the field insulating membrane 2 of gate electrode layer 4 and gate insulating film 3, in p type district, form n respectively in the source side and the drain side of gate electrode layer 4
-Type source area 8 and n
-Type drain region 9.Drain region 9 is commonly called the LDD district.
Above-mentioned conventional transistorized productive rate is low, and promptly resist layer 5 is etched twice in the technology shown in Figure 17 and 18, make and the side etch quantity of their wayward gate electrode layers 4, and lateral erosion amount at quarter alters a great deal.Therefore, grid width alters a great deal.In addition, in the ion doping technology in Figure 17, the semiconductor surface that exposes is carried out ion doping technology in component hole 2a; Therefore, because so-called channel phenomenon and the ion doping change in depth is very big.Thus, n
+The change in depth in type district is also very big.
In addition, the LDD among the source electrode in Figure 17 and drain electrode formation technology and Figure 19 forms arts demand two ion doping technologies altogether; Therefore, the quantity of technology is many, and forms arts demand low energy ion implantation equipment at the LDD of Figure 19.
Summary of the invention
The purpose of this invention is to provide the method that a kind of productive rate manufacturing of becoming reconciled with a spot of technology has the insulated-gate type field effect transistor that extends drain electrode structure or lightly doped drain (LDD) structure.
According to an aspect of the present invention, provide a kind of first method of making insulated-gate type field effect transistor, it step that comprises is: semiconductor substrate is provided, and at least a portion of a first type surface of this semiconductor substrate has first conductivity type; Form isolated area, be used to demarcate corresponding to the element setting area of this part of a first type surface of semiconductor substrate; In the element setting area, on semiconductor surface, form gate insulating film; On gate insulating film, form conductive material layer; Above gate insulating film, form layer of hard mask material via conductive material layer; On layer of hard mask material, form resist layer by photoetching process according to the gate electrode pattern of expecting; Utilize resist layer to carry out etch process for layer of hard mask material, to form the hard mask of forming by the part of the layer of hard mask material that keeps according to gate electrode pattern as mask; Utilize resist layer to carry out etch process for conductive material layer, to form a part that keeps conductive material layer according to gate electrode pattern as mask; Remove resist layer; Utilize hard mask to carry out isotropic etching,, thereby form the gate electrode layer that the remainder of the conductive material layer that is reduced by its width is formed with the width of the remainder that reduces conductive material layer as mask; With by utilizing gate insulating film, the lamination and the isolated area of gate electrode film and hard mask are carried out the foreign ion doping process as mask, side at gate electrode layer forms source area and the drain region with second conductivity type relative with first conductivity type respectively with opposite side, wherein by via mask with foreign ion be doped to wherein hard mask not with each first of overlapping source area of gate electrode layer and drain region, the wherein hard mask under mask not with each first of overlapping source area of gate electrode layer and drain region in the ion doping degree of depth be shallower than the ion doping degree of depth in each the second portion of the source area that do not have masked covering and drain region.
According to first method of the present invention, by utilizing the etch process of resist layer as mask, formed hard mask by the composition layer of hard mask material, and by utilizing the anisotropic etching process of resist, kept the part of conductive material layer by the patterning conductive material layer thereafter as mask.Then, after removing resist layer, reduce the width of the remainder of conductive layer, formed gate electrode layer by the isotropic etching that utilizes hard mask.Therefore, can accurately carry out isotropic etching by utilizing hard mask, and can accurately form narrow gate electrode layer.
In addition, when by utilizing gate insulating film, the lamination of gate electrode film and hard mask and isolated area are carried out the foreign ion doping process when forming source area and drain region as mask, by via mask with foreign ion be doped to wherein hard mask not with each first of overlapping source area of gate electrode layer and drain region, the wherein hard mask under mask not with each first of overlapping source area of gate electrode layer and drain region in the ion doping degree of depth be shallower than the ion doping degree of depth in each the second portion of the source area that do not have masked covering and drain region.Therefore, can carry out the formation of source area and drain region and the formation of extension drain electrode structure or LDD structure simultaneously by a foreign ion doping process, and can shorten whole technology.
In first method of above-mentioned manufacturing insulated-gate type field effect transistor, be used for this etch process by utilizing isotropic etching, hard mask can form to have the width narrower than the width of resist layer.
According to a further aspect in the invention, provide a kind of second method of making insulated-gate type field effect transistor, it step that comprises is: semiconductor substrate is provided, and at least a portion of a first type surface of this semiconductor substrate has first conductivity type; Form isolated area, be used to demarcate corresponding to the element setting area of this part of a first type surface of semiconductor substrate; In the element setting area, on semiconductor surface, form gate insulating film; On gate insulating film, form conductive material layer; Above gate insulating film, form layer of hard mask material via conductive material layer; On layer of hard mask material, form resist layer by photoetching process according to the gate electrode pattern of expecting; Utilize resist layer to carry out anisotropic etching process for layer of hard mask material and conductive material layer as mask, forming the hard mask of forming by the part of the layer of hard mask material that keeps according to gate electrode pattern, and form a part simultaneously according to gate electrode pattern reservation conductive material layer; Remove resist layer; Utilize hard mask to carry out isotropic etching,, thereby form the gate electrode layer that the remainder of the conductive material layer that is reduced by its width is formed with the width of the remainder that reduces conductive material layer as mask; With by utilizing gate insulating film, the lamination and the isolated area of gate electrode film and hard mask are carried out the foreign ion doping process as mask, form source area and drain region respectively with second conductivity type relative with first conductivity type in the both sides of gate electrode layer, wherein by via mask with foreign ion be doped to wherein hard mask not with each first of overlapping source area of gate electrode layer and drain region, the wherein hard mask under mask not with each first of overlapping source area of gate electrode layer and drain region in the ion doping degree of depth be shallower than the ion doping degree of depth in each the second portion of the source area that do not have masked covering and drain region.
According to second method of the present invention,,, formed hard mask and kept the part of conductive material layer according to gate electrode pattern by composition layer of hard mask material and conductive material layer by utilizing the anisotropic etching process of resist layer as mask.Then, after removing resist layer, reduce the width of the remainder of conductive layer, formed gate electrode layer by the isotropic etching that utilizes hard mask.Therefore, can accurately carry out isotropic etching by utilizing hard mask, and can accurately form narrow gate electrode layer.In addition, similar to first method, the formation of source area and drain region and the formation of extension drain electrode structure or LDD structure can be carried out simultaneously by a foreign ion doping process, and whole technology can be shortened.
According to the present invention, because can accurately form narrow gate electrode, thus can realize transistorized microminiaturization, and can improve productive rate.In addition, can carry out the formation of source area and drain region and the formation of extension drain electrode structure or LDD structure simultaneously by a foreign ion doping process, and can shorten whole technology.In addition, do not need the low energy ion implantation equipment.
According to the present invention, can provide a kind of productive rate manufacturing of becoming reconciled to have the method for the insulated-gate type field effect transistor that extends drain electrode structure or lightly doped drain (LDD) structure with a spot of technology.
Description of drawings
Fig. 1 is the profile of substrate of polysilicon deposition technology of method that shows the manufacturing insulated-gate type field effect transistor of first embodiment of the invention.
Fig. 2 is the profile of the substrate of the polysilicon oxidation technology after the technology of displayed map 1.
Fig. 3 is the profile that the technology resist layer afterwards of displayed map 2 forms the substrate of technology and isotropic etching.
Fig. 4 is the profile of the substrate of the dry method etch technology after the technology of displayed map 3.
Fig. 5 is the profile that the technology resist afterwards of displayed map 4 is removed the substrate of technology.
Fig. 6 is the profile of the substrate of the isotropic etching after the technology of displayed map 5.
Fig. 7 is the profile of the substrate of the ion doping technology after the technology of displayed map 6.
Fig. 8 is the profile of the substrate of the isotropic etching after the technology of displayed map 7.
Fig. 9 is the profile that the technology interlayer dielectric afterwards of displayed map 8 forms the substrate of technology and wiring formation technology.
Figure 10 is the profile of substrate of polysilicon deposition technology that shows the method for manufacturing insulated-gate type field effect transistor second embodiment of the invention.
Figure 11 is the profile that shows the substrate of the WSi depositing operation after the technology of Figure 10.
Figure 12 shows that the technology resist layer afterwards of Figure 11 forms the profile of the substrate of technology and isotropic etching.
Figure 13 is the profile that shows the substrate of the dry method etch technology after the technology of Figure 12.
Figure 14 is the profile that the technology resist afterwards of demonstration Figure 13 is removed the substrate of technology.
Figure 15 is the profile that shows the substrate of the isotropic etching after the technology of Figure 14.
Figure 16 is the profile that shows the substrate of the ion doping technology after the technology of Figure 15.
Figure 17 is the profile of demonstration according to the substrate of the first ion doping technology of the manufacture method of the insulated-gate type field effect transistor with LDD structure of prior art.
Figure 18 is the profile that shows the substrate of the isotropic etching after the technology of Figure 17.
Figure 19 is the profile that the technology resist afterwards of demonstration Figure 18 is removed the substrate of the technology and the second ion doping technology.
Embodiment
Fig. 1 is the profile of semiconductor substrate 10 of polysilicon deposition technology of method that shows the manufacturing insulated-gate type field effect transistor of first embodiment of the invention.
For example, the semiconductor substrate of being made by silicon 10 has p type conductivity type on the whole or has p type well region.By known selective oxidation technology, the field insulating membrane of being made by silica 12 is formed on the interarea of substrate 10.Field insulating membrane 12 description component hole 12a are as the element setting area corresponding to the part of the substrate 10 with p type conductivity type or p type well region.Field insulating membrane 12 can be by will be such as the insulating material of silica by forming in the lip-deep groove that utilizes the chemical vapor deposition (CVD) method to be filled in to be formed at substrate 10.In addition, though field insulating membrane 12 is used as isolated area, but for example by known shallow trench isolation from (STI) method or by utilizing the part of SOI substrate (by the substrate that forms of deposition silicon layer on insulation board) and pre-oxidation silicon layer, can form isolated area.
On the surface of the p N-type semiconductor N in the component hole 12a of field insulating membrane 12, form the gate insulating film of making by silica 14 by thermal oxidation technology.On field insulating membrane 12, form polysilicon layer 16 with covering gate dielectric film 14 by the CVD method.When deposition or after deposition, conductivity type is defined doping impurity to polysilicon layer 16.This is in order to make the resistance of polysilicon layer 16 enough low, thereby utilizes polysilicon layer 16 as electrode or wiring.The thickness of polysilicon layer 16 can be 2000 to 6000 , is preferably 2500 to 4500 , and more preferably is 3500 .
Fig. 2 is the profile of the substrate 10 of the polysilicon oxidation technology after the technology of displayed map 1.
On the surface of polysilicon layer 16, for example formed silicon oxide layer 18 by thermal oxidation technology.The thickness of silicon oxide layer 18 can be about 100 to 500 .
Fig. 3 is the profile that the technology resist layer afterwards of displayed map 2 forms the substrate 10 of technology and isotropic etching.
On silicon oxide layer 18, by the gate electrode pattern formation resist layer 20 of photoetching process according to expectation.Then, utilize resist layer 20, carry out isotropic etching, to keep a part of 18A of silicon oxide layer 18 according to gate electrode pattern for silicon oxide layer 18 as mask.Each side of the reserve part 18A of silicon oxide layer 18 has been stepped back the distance of about Δ D=0.015 to 0.075 μ m from the side of resist layer 20, makes that the width of silicon oxide layer 18A is narrower than the width of resist layer 20.Silicon oxide layer 18A will be used as the hard mask of etch process described later shown in Figure 6, thereby silicon oxide layer 18A will be called as " hard mask " in the back.
Fig. 4 is the profile of the substrate 10 of the dry method etch technology after the technology of displayed map 3.
Utilize resist layer 20 to carry out anisotropic etching process for polysilicon layer 16, to keep a part of 16A of polysilicon layer 16 according to gate electrode pattern as mask.The thickness of field insulating membrane 12 and gate insulating film 14 is by the attenuation slightly of this etch process.
Fig. 5 is the profile that the technology resist afterwards of displayed map 4 is removed the substrate 10 of technology.
Remove resist layer 20 by cineration technics etc.As a result, hard mask 18A is retained on the polysilicon layer 16A.
Fig. 6 is the profile of the substrate 10 of the isotropic etching after the technology of displayed map 5.
Utilize hard mask 18A to carry out isotropic etching, with the both sides of etching polysilicon layer 16A for polysilicon layer 16A.Promptly, each side of polysilicon layer 16A is stepped back the distance of about Δ L=0.05 to 0.15 μ m from the side of hard mask 18A, so that the width of polysilicon layer 16A is narrower than the width of hard mask layer 18A, thereby form the gate electrode layer 16a that forms by the reserve part of polysilicon layer 16A.
Fig. 7 is the profile of the substrate 10 of the ion doping technology after the technology of displayed map 6.
Utilize lamination and the field insulating membrane 12 of gate insulating film 14, gate electrode layer 16a and hard mask 16A,, formed N simultaneously by the foreign ion doping process
+ Type source area 22 and drain region 24 and N
- Type source area 26 and drain region 28.In this situation, by foreign ion being doped to the not first overlapping with gate electrode layer 16a of wherein hard mask 18A via mask, make under mask wherein hard mask 18A not with each first of overlapping source area 22 of gate electrode layer 16a and drain region 24 in the ion doping degree of depth be shallower than the ion doping degree of depth in the second portion that does not have masked covering, thereby make N
-N is compared in type source area 26 and drain region 28
+ Type source area 22 and drain region 24 are more shallow and have a lower impurity concentration.By accelerating voltage and 4 * 10 with 35kev
15Cm
-2Dopant dose come Doping Phosphorus, can carry out foreign ion and mix.
In the ion doping technology of Fig. 7, carry out ion doping via gate insulating film 14; Therefore, limit tunneling effect (channeling effect) phenomenon, and reduced the variation of the degree of depth of source area and drain region.In addition, by turning to N
+The formation technology of type source area 22 and drain region 24 has formed N
- Type source area 26 and drain region 28; Therefore, do not need the low energy ion implantation equipment.
Fig. 8 is the profile of the substrate 10 of the isotropic etching after the technology of displayed map 7.
Removed the exposed portions of gate insulating film 14 and hard mask 18A by isotropic etching.As a result, exposed the upper surface of gate electrode layer 16a, and exposed N
+ Type source area 22 and drain region 24 and N
- Type source area 26 and drain region 28.
Fig. 9 is the profile that the technology interlayer dielectric afterwards of displayed map 8 forms the substrate 10 of technology and wiring formation technology.
By CVD method and coating process one of or combination, on the upper surface of substrate 10, form the interlayer insulating film of making by silica etc. 30.Thereafter, by carrying out photoetching and dry method etch technology for dielectric film 30, formed corresponding respectively to the connecting hole 30s and the 30d of source area 22 and drain region 24.Then, by the coating and composition by the wiring material layer that Al or Al alloy etc. makes, above the upper surface of substrate 10, formed source wiring layer 32 and drain electrode wiring layer 34. Wiring layer 32 and 34 is connected to source area 22 and drain region 24 via connecting hole 30s and 30d respectively.
First embodiment of the invention, hard mask 18A is carved by lateral erosion in isotropic etching shown in Figure 3, and polysilicon layer 16A is carved by lateral erosion in isotropic etching shown in Figure 6; Therefore, can accurately form narrow gate electrode layer 16a, transistorized microminiaturization becomes possibility, and will improve and make productive rate.In addition, the ion doping technology shown in Figure 7 has formed N simultaneously
+ Type source area 22 and drain region 24 and N
- Type source area 26 and drain region 28; Therefore, reduced manufacturing cost by shortening manufacturing process.
Next, will second execution mode of the present invention be described with reference to Figure 10 to 16.In the accompanying drawings, in the similar part of first execution mode reference number identical and symbol mark with first execution mode, and the explanation that will omit similar components.
Figure 10 is the profile of substrate 10 of polysilicon deposition technology that shows the method for manufacturing insulated-gate type field effect transistor second embodiment of the invention.
On the field insulating membrane 12 on the surface that covers semiconductor substrate 10, by CVD method deposit spathic silicon layer 16, with covering gate dielectric film 14.Polysilicon layer 16 has the thickness (preferably 800 to 2500 dusts, and more preferably be 1500 dusts) of 500 to 5000 dusts.
Figure 11 is the profile that shows the substrate 10 of the WSi depositing operation after the technology of Figure 10.
On polysilicon layer 16, deposit tungsten silicide (being called " WSi " thereafter) layer 19 by sputter etc.This WSi layer 19 has the thickness (preferably 1000 to 3000 dusts, and more preferably be 2000 dusts) of 500 to 5000 dusts.
Figure 12 shows that the technology resist layer afterwards of Figure 11 forms the profile of the substrate 10 of technology and isotropic etching.
By the gate electrode pattern of photoetching process, on WSi layer 19, formed resist layer 20 according to expectation.
Figure 13 is the profile that shows the substrate 10 of the dry method etch technology after the technology of Figure 12.
Utilize resist layer 20 to carry out anisotropic etching for WSi layer 19 and polysilicon layer 16, to keep a part of 19A of WiSi layer 19 and a part of 16A of polysilicon layer 16 according to gate electrode pattern as mask.By this etch process, the thickness attenuation slightly of field insulating membrane 12 and gate insulating film 14.
Figure 14 is the profile that the technology resist afterwards of demonstration Figure 13 is removed the substrate 10 of technology.
Removed resist layer 20 by cineration technics etc.As a result, exposed the upper surface of WSi layer 19A.WSi layer 19A will be used as hard mask in etch process described later shown in Figure 15, and WSi layer 19A will after be called as " hard mask ".
Figure 15 is the profile that shows the substrate 10 of the isotropic etching after the technology of Figure 14.
Utilize hard mask 19A to carry out isotropic etching, with the both sides of etching polysilicon layer 16A for polysilicon layer 16A.That is, each side of polysilicon layer 16A is all stepped back predetermined distance, delta L from the side of hard mask 19A, so that the width of polysilicon layer 16A is narrower than the width of hard mask layer 19A, thereby forms the gate electrode layer 16a that is made up of the remainder of polysilicon layer 16A.
Figure 16 is the profile that shows the substrate 10 of the ion doping technology after the technology of Figure 15.
Utilize lamination and the field insulating membrane 12 of gate insulating film 14, gate electrode layer 16a and hard mask 19A,, formed N simultaneously by the foreign ion doping process
+ Type source area 22 and drain region 24 and N
- Type source area 26 and drain region 28.In this situation, by foreign ion being doped to the not first overlapping with gate electrode layer 16a of wherein hard mask 19A via mask, make under mask wherein hard mask 19A not with each first of overlapping source area 22 of gate electrode layer 16a and drain region 24 in the ion doping degree of depth be shallower than the ion doping degree of depth in the second portion that does not have masked covering, thereby make N
-N is compared in type source area 26 and drain region 28
+ Type source area 22 and drain region 24 are more shallow and have a lower impurity concentration.By accelerating voltage and 3 * 10 with 100kev
15Cm
-2Dopant dose come Doping Phosphorus, can carry out foreign ion and mix.
In the ion doping technology of Figure 16, carry out ion doping via gate insulating film 14; Therefore, limit the tunneling effect phenomenon, and reduced the variation of the degree of depth of source area and drain region.In addition, by turning to N
+The formation technology of type source area 22 and drain region 24 has formed N
- Type source area 26 and drain region 28; Therefore, do not need the low energy ion implantation equipment.
After ion doping technology shown in Figure 16, as described in reference to figure 8, remove the expose portion of gate insulating film 14, and source of exposure polar region 22 and 26 and drain region 24 and 28.As with reference to figure 9 as described in, successively carry out the formation of interlayer insulating film and the formation of source electrode and drain electrode wiring thereafter.In this situation, on gate electrode layer (polysilicon layer) 16a, kept hard mask (WSi layer) 19A so-called to form " multi-crystal silicification thing grid ".
Second embodiment of the invention, polysilicon layer 16A is carved by lateral erosion in isotropic etching shown in Figure 15, therefore, can accurately form narrow gate electrode layer 16a, and transistorized microminiaturization becomes possibility, and will improve and make productive rate.In addition, the ion doping technology shown in Figure 16 has formed N simultaneously
+Type source area 22 and drain region 24 and N
- Type source area 26 and drain region 28; Therefore, by shortening manufacturing process, reduced manufacturing cost.In addition, WSi layer 19 and polysilicon layer 16 in technology shown in Figure 13 by composition together; Therefore, compare with first execution mode of the present invention, the quantity of etch process can be reduced one.And, reduced manufacturing cost by shortening manufacturing process.
The present invention is described in conjunction with preferred implementation.The present invention is not limited only to above-mentioned execution mode.Be apparent that those skilled in the art can carry out various modifications, improvement and combination.For example, following modification is possible.
The material of hard mask is not limited to the silica or the tungsten silicide that are formed by thermal oxidation, but also can use the silica that forms by the CVD method, or such as silicon nitride, silicon oxynitride, aluminium oxide, TiOx, TiN, the material of refractory metal, molybdenum silicide, titanium silicide etc. such as Mo, W and Ti.
The material of gate electrode is not limited to polysilicon, but also can use the refractory metal that is selected from such as Mo, W and Ti, these one of the material of material group of metal silicide, or the lamination of one of material and polysilicon.
Though above-mentioned execution mode is mainly explained for N raceway groove insulated-gate type field effect transistor, by the counter-rotating conduction type, can make P raceway groove insulated-gate type field effect transistor.
Though removed hard mask 18A in the first embodiment in technology shown in Figure 8, hard mask 18A also can be retained the part as interlayer dielectric 30.In addition, when hard mask 18A was formed by electric conducting material, hard mask 18A also can be retained the part as gate electrode, as shown in Figure 7.In addition, hard mask 19A can be formed by insulating material.In this situation, hard mask 19A can be removed after technology shown in Figure 16, maybe can be retained.
Though shallow-source electrode district and drain region are formed N in the above-described embodiment
-Type, but this shallow-source electrode district and drain region can be N
+Type, or can be revised arbitrarily, as long as they can form the extension drain electrode structure.
This application is based on Japanese patent application 2006-084493 that submits on March 27th, 2006 and the Japanese patent application 2006-213208 that submits on August 4th, 2006, and its whole contents is incorporated in this as a reference.
Claims (3)
1, a kind of method of making insulated-gate type field effect transistor comprises the steps:
Semiconductor substrate is provided, and at least a portion of a first type surface of described semiconductor substrate has first conductivity type;
Form isolated area, be used to demarcate corresponding to the element setting area of the described part of a first type surface of described semiconductor substrate;
In described element setting area, on semiconductor surface, form gate insulating film;
On described gate insulating film, form conductive material layer;
Above described gate insulating film, form layer of hard mask material via described conductive material layer;
By the gate electrode pattern of photoetching process, on described layer of hard mask material, form resist layer according to expectation;
Utilize described resist layer to carry out etch process for described layer of hard mask material, to form the hard mask of forming by the part of the layer of hard mask material that keeps according to described gate electrode pattern as mask;
Utilize described resist layer to carry out etch process for described conductive material layer, to keep the part of described conductive material layer according to described gate electrode pattern as mask;
Remove described resist layer;
Utilize described hard mask to carry out isotropic etching,, thereby form the gate electrode layer that the remainder of the conductive material layer that is reduced by its width is formed with the width of the remainder that reduces described conductive material layer as mask; With
By utilizing described gate insulating film, the lamination and the described isolated area of gate electrode film and hard mask are carried out the foreign ion doping process as mask, on a side of described gate electrode layer and opposite side, form source area and drain region respectively with second conductivity type relative with described first conductivity type, wherein by via described mask with described foreign ion be doped to wherein said hard mask not with each first of overlapping source area of described gate electrode layer and drain region, the wherein said hard mask under described mask not with each first of overlapping source area of described gate electrode layer and drain region in the ion doping degree of depth be shallower than not the ion doping degree of depth in each the second portion of the source area that covered by described mask and drain region.
2, according to the method for the manufacturing insulated-gate type field effect transistor of claim 1, wherein by utilizing isotropic etching as described etch process, described hard mask can form to have the width narrower than the width of described resist layer.
3, a kind of method of making insulated-gate type field effect transistor, it comprises the steps:
Semiconductor substrate is provided, and at least a portion of a first type surface of described semiconductor substrate has first conductivity type;
Form isolated area, be used to demarcate corresponding to the element setting area of the described part of a first type surface of described semiconductor substrate;
In described element setting area, on semiconductor surface, form gate insulating film;
On described gate insulating film, form conductive material layer;
Above described gate insulating film, form layer of hard mask material via described conductive material layer;
On described layer of hard mask material, form resist layer according to the gate electrode pattern of expecting by photoetching process;
Utilize described resist layer to carry out anisotropic etching process for described layer of hard mask material and described conductive material layer as mask, forming the hard mask of being made up of the part of the described layer of hard mask material that keeps according to described gate electrode pattern, and the while keeps the part of described conductive material layer according to described gate electrode pattern;
Remove described resist layer;
Utilize described hard mask to carry out isotropic etching,, thereby form the gate electrode layer that the remainder of the conductive material layer that is reduced by its width is formed with the width of the remainder that reduces described conductive material layer as mask; With
By utilizing described gate insulating film, the lamination and the described isolated area of gate electrode film and hard mask are carried out the foreign ion doping process as mask, on a side of described gate electrode layer and opposite side, form source area and drain region respectively with second conductivity type relative with described first conductivity type, wherein by via described mask with described foreign ion be doped to wherein said hard mask not with each first of overlapping source area of described gate electrode layer and drain region, the wherein said hard mask under described mask not with each first of overlapping source area of described gate electrode layer and drain region in the ion doping degree of depth be shallower than not the ion doping degree of depth in each the second portion of the source area that covered by described mask and drain region.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2006084493 | 2006-03-27 | ||
| JP084493/06 | 2006-03-27 | ||
| JP213208/06 | 2006-08-04 |
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|---|---|
| CN101047131A true CN101047131A (en) | 2007-10-03 |
| CN100533692C CN100533692C (en) | 2009-08-26 |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102347236A (en) * | 2010-07-29 | 2012-02-08 | 中芯国际集成电路制造(上海)有限公司 | Methods for manufacturing doped well and transistor comprising doped well |
| CN102479714A (en) * | 2010-11-29 | 2012-05-30 | 无锡华润上华半导体有限公司 | Preparation method of metal oxide semiconductor field-effect transistor |
| CN110506324A (en) * | 2017-04-19 | 2019-11-26 | 三菱电机株式会社 | Semiconductor device and its manufacturing method |
| CN110610860A (en) * | 2018-06-14 | 2019-12-24 | 美格纳半导体有限公司 | Semiconductor device and method for manufacturing semiconductor device |
-
2007
- 2007-03-27 CN CNB2007100884591A patent/CN100533692C/en not_active Expired - Fee Related
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102347236A (en) * | 2010-07-29 | 2012-02-08 | 中芯国际集成电路制造(上海)有限公司 | Methods for manufacturing doped well and transistor comprising doped well |
| CN102347236B (en) * | 2010-07-29 | 2013-09-04 | 中芯国际集成电路制造(上海)有限公司 | Methods for manufacturing doped well and transistor comprising doped well |
| CN102479714A (en) * | 2010-11-29 | 2012-05-30 | 无锡华润上华半导体有限公司 | Preparation method of metal oxide semiconductor field-effect transistor |
| CN110506324A (en) * | 2017-04-19 | 2019-11-26 | 三菱电机株式会社 | Semiconductor device and its manufacturing method |
| CN110610860A (en) * | 2018-06-14 | 2019-12-24 | 美格纳半导体有限公司 | Semiconductor device and method for manufacturing semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN100533692C (en) | 2009-08-26 |
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