CN102347236A - Methods for manufacturing doped well and transistor comprising doped well - Google Patents
Methods for manufacturing doped well and transistor comprising doped well Download PDFInfo
- Publication number
- CN102347236A CN102347236A CN2010102454725A CN201010245472A CN102347236A CN 102347236 A CN102347236 A CN 102347236A CN 2010102454725 A CN2010102454725 A CN 2010102454725A CN 201010245472 A CN201010245472 A CN 201010245472A CN 102347236 A CN102347236 A CN 102347236A
- Authority
- CN
- China
- Prior art keywords
- pattern
- photoresist layer
- layer
- cross
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
The invention relates to a method for manufacturing a doped well. The method comprises the following steps of: providing a substrate and forming a photoresist layer with a first pattern on the substrate; coating crosslinking material layers on the photoresist layer with the first pattern and the substrate; baking the substrate, so that the crosslinking material layers generate crosslinking reaction and a crosslinking layer is formed on a part, contacted with the photoresist layer with the first pattern, of the crosslinking material layer; removing the part, which does not generate the crosslinking reaction, from the crosslinking material layer so as to retain the crosslinking layer; forming a photoresist layer with a second pattern on the crosslinking layer; and performing ion injection by using the photoresist layer with the second pattern and the photoresist layer with the first pattern as masks to form the doped well in the substrate. By the method for manufacturing the doped well, the process period is shortened effectively, process steps are reduced, the burden on tools is reduced and the production efficiency is improved.
Description
Technical field
The present invention relates to semiconductor fabrication process, particularly a kind of transistorized method of making dopant well and comprising this dopant well.
Background technology
Transistor, especially " metal-semiconductor-oxide " field-effect transistor (MOSFET) are one of integrated circuit most common components.Leakage current is an important indicator of weighing transistor performance.The low more transistor that means of leakage current is strong more to the control ability of electric current.
Adopting shallow doping techniques (LDD) is to make one of modal technology in field at transistor at present.This technology is to adopt the dopant ion identical with source/drain electrode to inject the zone between source/drain electrode and the conducting channel, and the doping content of formation forms so-called shallow doped source/drain electrode structure less than the doping content of source/drain electrode.The effect of this structure is the channel length that increases between source electrode and the drain doping region territory, suppresses short-channel effect, thereby reduces transistor leakage current between source electrode and the drain electrode under off state.
Figure 1A-1C is the sectional view that prior art forms each step in the transistorized flow process.At first, shown in Figure 1A, on substrate 100, forming the photoresist layer 101 with first pattern, is that mask carries out the ion injection with the photoresist layer 101 with first pattern, forms shallow doped region 102A and 102B.Remove photoresist layer 101 then with first pattern.Substrate 100 can be P type or N type substrate, and the dopant ion of shallow doped region 102A and 102B has the conduction type opposite with substrate 100.Then; Shown in Figure 1B; On substrate 100, form photoresist layer 103 with second pattern; Photoresist layer 103 with second pattern cover do not carry out on the substrate zone that ion injects directly over, and the photoresist layer 103 with second pattern is wider than and is not carried out the zone that ion injects on the substrate.With the photoresist layer 103 with second pattern is that mask carries out the ion injection, forms source electrode 104A and drain electrode 104B.The dopant ion of source electrode 104A and drain electrode 104B has the identical conduction type of dopant ion with shallow doped region 102A and 102B.Remove photoresist layer 103 then, accomplish the making of shallow doped source/drain electrode structure with second pattern.Wherein, shallow doped source structure comprises source electrode 104A and shallow doped region 102A, and shallow doped-drain structure comprises drain electrode 104B and shallow doped region 102B.
In addition, in order to accomplish transistorized making, also to directly over the zone (being 101 region covered of photoresist layer that former cause has first pattern) of not carrying out the ion injection on the substrate 100, form grid structure 105, shown in Fig. 1 C.
Adopt shallow doping techniques can shorten the distance between source electrode 104A and the drain electrode 104B, suppress short-channel effect.The above-mentioned two injection techniques of available technology adopting form dopant well (promptly; Shallow doped source/drain electrode structure); Dopant ion is distribution gradient in substrate 100; The distribution of the doping content on consequent substrate 100 surfaces also has gradient, and is lower near the doping content of grid structure 101 1 sides, higher away from the doping content of grid structure 101 1 sides.
In addition, along with the continuous development of semiconductor technology, the integrated degree of semiconductor device is also increasingly high, and is therefore, also increasingly high for the requirement of the critical size of semiconductor device.When the critical size of semiconductor device is controlled, in order to optimize junction depth and the reason that reduces electric leakage, to the contact area between the semiconductor device also requirement to some extent.For example in the process of the photodiode dopant well of existing construction drawing image-position sensor; Dopant well is made ion degree of depth distribution gradient; To increase the contact area between semiconductor device and substrate, i.e. PN junction area, and then make that junction capacitance increases, resistance increases; Improve and resist the ability of wearing, and reduce the generation of leakage current.
Fig. 2 A-2B is the sectional view of each step in the flow process of the prior art dopant well that forms degree of depth distribution gradient.Shown in Fig. 2 A, on substrate 200, form photoresist layer 201 with first pattern.Then, be that mask carries out the ion injection with photoresist layer 201 with first pattern, form first dopant well 202, remove first photoresist layer 201.Shown in Figure 1B, on substrate 200, form photoresist layer 203 with second pattern.Then, be that mask carries out the ion injection with photoresist layer 203 with second pattern, form second dopant well 204, remove photoresist layer 203 with second pattern.Above-mentioned pair of injection technology all adopts identical ion, forms the dopant well of degree of depth distribution gradient, increased the PN junction area.
The dopant well of degree of depth distribution gradient has extensive use in semiconductor technology, its range of application is not limited to above-mentioned two types.Yet the dopant well that existing technology forms degree of depth distribution gradient all adopts two injection technologies, promptly forms and injects photoresist-injection-formation first time photoresist-second time.Two injection technologies need be carried out twice injection, and most of situation needs the removal photoresist twice, and therefore, processing step is more, needs long process cycle, and has increased the burden of instrument, is unfavorable for the raising of production efficiency.
Therefore, need a kind of manufacture method of new dopant well,, reduce processing step, reduce the burden of instrument, and enhance productivity to shorten process cycle.
Summary of the invention
In the summary of the invention part, introduced the notion of a series of reduced forms, this will further explain in the embodiment part.Summary of the invention part of the present invention does not also mean that key feature and the essential features that will attempt to limit technical scheme required for protection, does not more mean that the protection range of attempting to confirm technical scheme required for protection.
The invention provides a kind of method of making dopant well, comprising: substrate is provided, on substrate, forms photoresist layer with first pattern; On said photoresist layer with first pattern and said substrate, apply the cross-linked material layer; Said substrate is cured,, and form cross-linked layer in the part that contacts with said photoresist layer of said cross-linked material layer with first pattern so that make said cross-linked material layer generation cross-linking reaction; Remove the part that cross-linking reaction does not take place in the said cross-linked material layer, to stay said cross-linked layer; On said cross-linked layer, form photoresist layer with second pattern; With said photoresist layer and said photoresist layer with first pattern with second pattern is that mask carries out the ion injection, in said substrate, forms said dopant well.
Preferably, said thickness with photoresist layer of first pattern is 300-600nm.
Preferably, said photoresist layer and said gross thickness with photoresist layer of second pattern with first pattern is 1500-1900nm.
Preferably, forming said material with photoresist layer of first pattern is the photoresist that can produce the light acid molecule, and the material of said cross-linked material layer is that chemical shrinkage-assisted analysis enhancing etching is used material.
It is preferably, said that to cure used stoving temperature be 60-120 ℃.
It is preferably, said that to cure the used time of curing be 60-90 second.
Preferably, said second pattern is different with said first pattern.
Preferably, said dopant well is the dopant well of degree of depth distribution gradient.
Preferably, in the horizontal, the width of said second pattern is less than the width of said first pattern, and said dopant well is shallow doped source/drain electrode structure.
The present invention also provides a kind of making transistorized method, comprising: adopt said method to make said dopant well as shallow doped source/drain electrode structure; Remove said the have photoresist layer of first pattern, said cross-linked layer and said photoresist layer with second pattern; On said substrate, form grid structure, to form said transistor with said photoresist layer The corresponding area with second pattern.
According to the manufacture method of dopant well of the present invention, can shorten process cycle effectively, reduce processing step, reduce the burden of instrument, and enhance productivity.
Description of drawings
Attached drawings of the present invention is used to understand the present invention at this as a part of the present invention.Embodiments of the invention and description thereof have been shown in the accompanying drawing, have been used for explaining principle of the present invention.In the accompanying drawings,
Figure 1A-1C is the sectional view that prior art forms each step in the transistorized flow process;
Fig. 2 A-2B is the sectional view of each step in the flow process of the prior art dopant well that forms degree of depth distribution gradient;
Fig. 3 A-3G is for form the sectional view of each step in the transistorized flow process according to the method for the invention;
Fig. 4 A-4F is the sectional view of each step in the flow process of the dopant well that forms degree of depth distribution gradient according to the method for the invention;
Fig. 5 is for form the flow chart of the dopant well of degree of depth distribution gradient according to the method for the invention.
Embodiment
In the description hereinafter, a large amount of concrete details have been provided so that more thorough understanding of the invention is provided.Yet, it will be apparent to one skilled in the art that the present invention can need not one or more these details and be able to enforcement.In other example,, describe for technical characterictics more well known in the art for fear of obscuring with the present invention.
In order thoroughly to understand the present invention, will in following description, detailed steps be proposed, so that explanation the present invention is the dopant well that how to form degree of depth distribution gradient.Obviously, execution of the present invention is not limited to the specific details that the technical staff had the knack of of semiconductor applications.Preferred embodiment of the present invention is described in detail as follows, yet except these were described in detail, the present invention can also have other execution modes.
Embodiment one
Fig. 3 A-3G is for form the sectional view of each step in the transistorized flow process according to the method for the invention.
Shown in Fig. 3 A, substrate 300 is provided, substrate 300 can be monocrystalline silicon, polysilicon or amorphous silicon; Substrate 300 also can be silicon, germanium, GaAs or silicon Germanium compound; Substrate 300 can also have epitaxial loayer or epitaxial loayer silicon-on; Substrate 300 can also be other semi-conducting material, enumerates no longer one by one here.Substrate 300 can be P type or N type substrate.On substrate 300, form the photoresist layer 301 with first pattern, the thickness with photoresist layer 301 of first pattern can be 300-600nm.In the horizontal, the width of first pattern is D1, wherein said laterally for subsequent technique in the transverse cross-section parallel of the grid that forms, and with the surperficial parallel direction of substrate 300, i.e. direction X shown in Fig. 3 A.The formation method of photoresist layer 301 with first pattern is for forming earlier photoresist layer on substrate 300, form through technology such as exposure, development then.
Shown in Fig. 3 B, on photoresist layer with first pattern 301 and substrate 300, apply cross-linked material layer 302.The material that formation has the photoresist layer 301 of first pattern is the photoresist that can produce the light acid molecule, for example, and i-line type photoresist, ArF type photoresist or KrF type photoresist.The material of cross-linked material layer 302 can be the chemical shrinkage-assisted analysis that provides of AZ electronic material company strengthen etching with material (Resolution Enhancement Lithography Assisted By Chemical Shrink, RELACS).
Shown in Fig. 3 C; Cure the substrate that is coated with cross-linked material layer 302 300 that forms through above-mentioned steps; So that make cross-linked material layer 302 that cross-linking reaction take place, and form cross-linked layer 303 in the part that contacts with the photoresist layer with first pattern 301 of cross-linked material layer 302.Wherein, the temperature of curing is 60-120 ℃, and the time of curing is 60-90 second.In the process of curing; Cross-linking reaction takes place with cross-linked material layer 302 at boundary (being the part that contacts with the photoresist layer with first pattern 301 of cross-linked material layer 302) in the photoresist layer 301 with first pattern, forms the water-fast cross-linked layer 303 of one deck on the surface of the photoresist layer with first pattern 301.Via the development step of water-soluble developer solution, remove the part that cross-linking reaction does not take place in the cross-linked material layer 302, then to stay cross-linked layer 303.
According to the embodiment of the present invention, the material of cross-linked material layer is RELACS.RELACS mainly is made up of water miscible macromolecule and crosslinking agent.Contain the light acid molecule in the photoresist, after technologies such as overexposure, development,, make the light acid molecule lowering of concentration at edge because the developer solution of alkalescence can produce neutralization with the light acid molecule at photoresist layer edge.In baking step; Remain in the light acid molecule in the photoresist and produce diffusion motion because be heated; In the process of diffusion, can produce new light acid molecule simultaneously; These light acid molecules can diffuse in the RELACS layer, and what the cross-linking reaction of catalysis RELACS, concrete course of reaction can be looked is the chemical reaction that three molecules are participated in:
P+C+H
+→PC+H
+，
Wherein, P represents the macromolecule in the RELACS reagent, and C represents the corsslinking molecular among the RELACS, H
+Be photoresist residual light acid molecule after formation has the lithography layer of pattern, PC then represents the product after macromolecule and corsslinking molecular produce cross-linking reaction.
Shown in Fig. 3 D, on cross-linked layer 303, form the position that the photoresist layer 304 with second pattern defines shallow doped region in advance.Second pattern is different with first pattern.In the present embodiment, forming two-layer photoresist layer is in order to define transistorized shallow doped source/drain structure, therefore, further to require in the horizontal the width (D of second pattern
2) less than the width (D of first pattern
1), with on substrate with D
1-D
2(2d) corresponding zone forms shallow doped region.The formation method of photoresist layer 304 with second pattern is for forming earlier photoresist layer on substrate 300 and cross-linked layer 303, form through technology such as exposure, development then.Photoresist layer 301 with first pattern is 1500-1900nm with the gross thickness with photoresist layer 304 of second pattern.The particular location of second pattern can specifically be confirmed according to the width and the depth distribution situation of the shallow doped region that will form with concrete width.Photoresist layer 304 with second pattern further blocks ions is injected in the substrate 300, so that do not mix in the zone that has on the photoresist layer 304 pairing substrates 300 of second pattern.
This execution mode will form shallow doped source/drain electrode structure, to increase the distance between the source/drain electrode that will form subsequently through shallow doped region, suppresses short-channel effect.Therefore, the photoresist layer 304 with second pattern be positioned at photoresist layer 301 with first pattern directly over, and in the horizontal, the width of second pattern is than the little 2d of width of first pattern, wherein, width d is corresponding to the width of shallow doped region.
Shown in Fig. 3 E, be that mask carries out the ion injection with photoresist layer 304 with second pattern and photoresist layer 301 with first pattern, in substrate 300, form source electrode 306A and drain electrode 306B, and shallow doped region 305A and 305B.Source electrode 306A and drain electrode 306B, and the dopant ion of shallow doped region 305A and 305B has the conduction type opposite with substrate 300.When substrate 300 was the P type, said dopant ion was N type, for example arsenic ion, phosphonium ion etc.; When substrate 300 was the N type, said dopant ion was the P type, for example indium ion, boron ion, boron fluoride ion etc.
Shown in Fig. 3 F, technologies such as employing ashing are removed the photoresist layer 301 that has photoresist layer 304, the cross-linked layer 303 of second pattern and have first pattern.
In addition, in order to accomplish transistorized making, directly over the zone (photoresist layer 304 The corresponding area that promptly have second pattern) of not carrying out the ion injection on the substrate 300, form grid structure 307, shown in Fig. 3 G.
Embodiment two
Fig. 4 A-4F is the sectional view of each step in the flow process of the dopant well that forms degree of depth distribution gradient according to the method for the invention.
Shown in Fig. 4 A, substrate 400 is provided, substrate 400 can be monocrystalline silicon, polysilicon or amorphous silicon; Substrate 400 also can be silicon, germanium, GaAs or silicon Germanium compound; Substrate 400 can also have epitaxial loayer or epitaxial loayer silicon-on; Substrate 400 can also be other semi-conducting material, enumerates no longer one by one here.On substrate 400, form the photoresist layer 401 with first pattern, the thickness with photoresist layer 401 of first pattern can be 800-3000nm.
Shown in Fig. 4 B, on photoresist layer with first pattern 401 and substrate 400, apply cross-linked material layer 402.The material that formation has the photoresist layer 401 of first pattern is the photoresist that can produce the light acid molecule, for example, and i-line type photoresist, ArF type photoresist or KrF type photoresist.The material of cross-linked material layer 402 can be the RELACS that AZ electronic material company provides.
Shown in Fig. 4 C; Cure the substrate that is coated with cross-linked material layer 402 400 that forms through above-mentioned steps; So that make cross-linked material layer 402 that cross-linking reaction take place, and form cross-linked layer 403 in the part that contacts with the photoresist layer with first pattern 401 of cross-linked material layer 402.Wherein, the temperature of curing is 60-120 ℃, and the time of curing is 60-90 second.In the process of curing; Cross-linking reaction takes place with cross-linked material layer 402 at boundary (being the part that contacts with the photoresist layer with first pattern 401 of cross-linked material layer 402) in the photoresist layer 401 with first pattern, forms the water-fast cross-linked layer 403 of one deck on the surface of the photoresist layer with first pattern 401.Via the development step of water-soluble developer solution, remove the part that cross-linking reaction does not take place in the cross-linked material layer 402, then to stay cross-linked layer 403.
Shown in Fig. 4 D, on cross-linked layer 403, form photoresist layer 404 with second pattern, define the position that forms shallow doped region in advance.In order to make the degree of depth distribution gradient of dopant well, common first pattern is different with second pattern.Realizing with this: does not mix in the zone on the substrate 400 that is covered by two-layer photoresist layer; Zone on the substrate 400 that only covers by one deck photoresist layer, the ion concentration of injection is lower, the degree of depth is more shallow; Zone on the substrate 400 that is not covered by any photoresist layer, the ion concentration of injection is higher, the degree of depth is darker.Thickness with photoresist layer 404 of second pattern can be 800-3000nm.The position of second pattern and width can specifically be confirmed according to the width and the depth distribution situation of the shallow doped region that will form.
The formation method of photoresist layer 401 and the photoresist layer with second pattern 404 with first pattern is identical with the method shown in Fig. 3 A-3G, promptly forms photoresist layer earlier, makes photoresist layer have pattern through technologies such as exposure, developments then.
Shown in Fig. 4 E, be that mask carries out the ion injection with photoresist layer 404 with second pattern and photoresist layer 401 with first pattern, in substrate 400, form the dopant well 405 of degree of depth distribution gradient.Dopant well 405 can be N type or P type.When dopant well 405 was the N type, dopant ion was N type, for example arsenic ion, phosphonium ion etc.; When dopant well 405 was the P type, dopant ion was the P type, for example indium ion, boron ion, boron fluoride ion etc.
Shown in Fig. 4 F, technologies such as employing ashing are removed the photoresist layer 401 that has photoresist layer 404, the cross-linked layer 403 of second pattern and have first pattern, accomplish whole doping process.
According to above-mentioned execution mode of the present invention, after formation has photoresist layer, the cross-linked layer of first pattern and has the photoresist layer of second pattern, adopt and once inject the dopant well that forms degree of depth distribution gradient.Therefore, compare, can shorten process cycle effectively, reduce processing step, reduce the burden of instrument, and enhance productivity with twice injection of prior art, twice removal photoresist pattern.The invention is not restricted to above-mentioned two kinds of execution modes, method of the present invention can be used to form the dopant well of various types of degree of depth distribution gradient.
Fig. 5 is for form the flow chart of the dopant well of degree of depth distribution gradient according to the method for the invention.In step 501, substrate is provided, on substrate, form photoresist layer with first pattern.In step 502, on photoresist layer with first pattern and substrate, apply the cross-linked material layer.In step 503, substrate is cured, so that make cross-linked material layer generation cross-linking reaction, and form cross-linked layer in the part that the photoresist layer with having first pattern of cross-linked material layer contacts.In step 504, remove the part that cross-linking reaction does not take place in the cross-linked material layer, to stay cross-linked layer.In step 505, on cross-linked layer, form photoresist layer with second pattern, define the position that forms shallow doped region in advance.In step 506, be that mask carries out the ion injection with photoresist layer with second pattern and photoresist layer with first pattern, form the dopant well of degree of depth distribution gradient.In step 507, technologies such as employing ashing are removed the photoresist layer that has photoresist layer, the cross-linked layer of second pattern and have first pattern, accomplish whole doping process.
The semiconductor device that has according to the dopant well of aforesaid embodiment manufacturing can be applicable in the multiple integrated circuit (IC).According to IC of the present invention for example is memory circuitry, like random-access memory (ram), dynamic ram (DRAM), synchronous dram (SDRAM), static RAM (SRAM) (SRAM) or read-only memory (ROM) or the like.According to IC of the present invention can also be logical device, like programmable logic array (PLA), application-specific integrated circuit (ASIC) (ASIC), combination type DRAM logical integrated circuit (buried type dynamic random access memory), radio-frequency devices or other circuit devcies arbitrarily.IC chip according to the present invention can be used for for example consumer electronic products; In various electronic products such as personal computer, portable computer, game machine, cellular phone, personal digital assistant, video camera, digital camera, mobile phone, especially in the radio frequency products.
The present invention is illustrated through the foregoing description, but should be understood that, the foregoing description just is used for for example and illustrative purposes, but not is intended to the present invention is limited in the described scope of embodiments.It will be appreciated by persons skilled in the art that in addition the present invention is not limited to the foregoing description, can also make more kinds of variants and modifications according to instruction of the present invention, these variants and modifications all drop in the present invention's scope required for protection.Protection scope of the present invention is defined by appended claims book and equivalent scope thereof.
Claims (10)
1. method of making dopant well comprises:
Substrate is provided, on said substrate, forms photoresist layer with first pattern;
On said photoresist layer with first pattern and said substrate, apply the cross-linked material layer;
Said substrate is cured,, and form cross-linked layer in the part that contacts with said photoresist layer of said cross-linked material layer with first pattern so that make said cross-linked material layer generation cross-linking reaction;
Remove the part that cross-linking reaction does not take place in the said cross-linked material layer, to stay said cross-linked layer;
On said cross-linked layer, form photoresist layer with second pattern;
With said photoresist layer and said photoresist layer with first pattern with second pattern is that mask carries out the ion injection, in said substrate, forms said dopant well.
2. the method for claim 1 is characterized in that, said thickness with photoresist layer of first pattern is 300-600nm.
3. the method for claim 1 is characterized in that, said photoresist layer and said gross thickness with photoresist layer of second pattern with first pattern is 1500-1900nm.
4. the method for claim 1 is characterized in that, forming said material with photoresist layer of first pattern is the photoresist that can produce the light acid molecule, and the material of said cross-linked material layer is that chemical shrinkage-assisted analysis enhancing etching is used material.
5. method as claimed in claim 4 is characterized in that, said to cure used stoving temperature be 60-120 ℃.
6. method as claimed in claim 5 is characterized in that, said to cure the used time of curing be 60-90 second.
7. like each described method among the claim 1-6, it is characterized in that said second pattern is different with said first pattern.
8. method as claimed in claim 7 is characterized in that, said dopant well is the dopant well of degree of depth distribution gradient.
9. method as claimed in claim 7 is characterized in that, in the horizontal, the width of said second pattern is less than the width of said first pattern, and said dopant well is shallow doped source/drain electrode structure.
10. make transistorized method for one kind, comprising:
Adopt the method for claim 1 to make said dopant well as shallow doped source/drain electrode structure;
Remove said the have photoresist layer of first pattern, said cross-linked layer and said photoresist layer with second pattern;
On said substrate, form grid structure, to form said transistor with said photoresist layer The corresponding area with second pattern.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201010245472 CN102347236B (en) | 2010-07-29 | 2010-07-29 | Methods for manufacturing doped well and transistor comprising doped well |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201010245472 CN102347236B (en) | 2010-07-29 | 2010-07-29 | Methods for manufacturing doped well and transistor comprising doped well |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102347236A true CN102347236A (en) | 2012-02-08 |
| CN102347236B CN102347236B (en) | 2013-09-04 |
Family
ID=45545788
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201010245472 Active CN102347236B (en) | 2010-07-29 | 2010-07-29 | Methods for manufacturing doped well and transistor comprising doped well |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102347236B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP4266384A1 (en) * | 2022-04-20 | 2023-10-25 | GLOBALFOUNDRIES Singapore Pte. Ltd. | Photodiodes with serpentine shaped electrical junction |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06250379A (en) * | 1993-02-26 | 1994-09-09 | Oki Electric Ind Co Ltd | Pattern forming method and formation of photomask for phase shift method |
| CN1799006A (en) * | 2003-06-11 | 2006-07-05 | Az电子材料（日本）株式会社 | Micropattern formation material and method of micropattern formation |
| CN101047131A (en) * | 2006-03-27 | 2007-10-03 | 雅马哈株式会社 | Method for manufacturing insulated-gate type field effect transistor |
| CN101145544A (en) * | 2006-09-13 | 2008-03-19 | 东部高科股份有限公司 | Method for forming semiconductor device |
| CN101571674A (en) * | 2009-06-09 | 2009-11-04 | 上海集成电路研发中心有限公司 | Double exposure method |
-
2010
- 2010-07-29 CN CN 201010245472 patent/CN102347236B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06250379A (en) * | 1993-02-26 | 1994-09-09 | Oki Electric Ind Co Ltd | Pattern forming method and formation of photomask for phase shift method |
| CN1799006A (en) * | 2003-06-11 | 2006-07-05 | Az电子材料（日本）株式会社 | Micropattern formation material and method of micropattern formation |
| CN101047131A (en) * | 2006-03-27 | 2007-10-03 | 雅马哈株式会社 | Method for manufacturing insulated-gate type field effect transistor |
| CN101145544A (en) * | 2006-09-13 | 2008-03-19 | 东部高科股份有限公司 | Method for forming semiconductor device |
| CN101571674A (en) * | 2009-06-09 | 2009-11-04 | 上海集成电路研发中心有限公司 | Double exposure method |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP4266384A1 (en) * | 2022-04-20 | 2023-10-25 | GLOBALFOUNDRIES Singapore Pte. Ltd. | Photodiodes with serpentine shaped electrical junction |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102347236B (en) | 2013-09-04 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8133790B2 (en) | Semiconductor device and method for fabricating the same | |
| CN104103519A (en) | Method for manufacturing semiconductor power device | |
| CN103730417A (en) | Semiconductor device and manufacturing method thereof | |
| US10991724B2 (en) | CMOS transistor and method for fabricating the same, display panel and display device | |
| KR960026463A (en) | Manufacturing method of MOS field effect transistor (MOSFET) | |
| CN102347236B (en) | Methods for manufacturing doped well and transistor comprising doped well | |
| JP2005150267A5 (en) | ||
| CN106856190B (en) | Method for forming semiconductor structure | |
| CN106328505B (en) | The forming method of semiconductor structure | |
| CN203826346U (en) | Mask and ion implantation device | |
| US20150108586A1 (en) | Transistor device with improved source/drain junction architecture and methods of making such a device | |
| CN103000501A (en) | NMOS (N-channel metal oxide semiconductor) transistor forming method | |
| CN103247528A (en) | Manufacturing method for metal-oxide-semiconductor field effect transistor (MOSFET) | |
| KR100840662B1 (en) | Manufacturing Method of Semiconductor Device | |
| CN109273360A (en) | The production method of semiconductor device | |
| US20080283915A1 (en) | High voltage semiconductor device and method of manufacturing the same | |
| CN103346125B (en) | Improve the method for the electrical parameter homogeneity of GP cmos device | |
| TW200511402A (en) | Method of forming gate electrode in flash memory device | |
| US10879361B2 (en) | Method for manufacturing semiconductor structure | |
| CN102610528B (en) | Method for reducing grid induction drain leakage of semiconductor device and method for manufacturing metal oxide semiconductor (MOS) device | |
| CN104282622A (en) | Manufacturing method of contact holes of integrated circuit | |
| CN103280432A (en) | Manufacturing method of integration power device with small size | |
| CN104269379A (en) | Array substrate, manufacturing method thereof and display device | |
| CN102790085B (en) | Semiconductor device and manufacture method thereof | |
| CN101783324B (en) | CMOS (complementary metal-oxide-semiconductor) transistor and manufacturing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| ASS | Succession or assignment of patent right |
Owner name: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING Effective date: 20130109 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20130109 Address after: 201203 Shanghai City, Pudong New Area Zhangjiang Road No. 18 Applicant after: Semiconductor Manufacturing International (Shanghai) Corporation Applicant after: Semiconductor Manufacturing International (Beijing) Corporation Address before: 201203 Shanghai City, Pudong New Area Zhangjiang Road No. 18 Applicant before: Semiconductor Manufacturing International (Shanghai) Corporation |
|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |