CN116093151B - Bipolar transistor structure and manufacturing method thereof - Google Patents
Bipolar transistor structure and manufacturing method thereof Download PDFInfo
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
- H01L29/735—Lateral transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/6625—Lateral transistors
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Abstract
The application provides a bipolar transistor structure and a manufacturing method thereof, wherein the bipolar transistor structure comprises a P-type substrate, a deep N well, an N-type epitaxial layer, an electrode leading-out end injection region, a grid structure and an electrode leading-out end, wherein the electrode leading-out end injection region comprises a first base leading-out end injection region, a first collector leading-out end injection region, an emitter leading-out end injection region, a second collector leading-out end injection region and a second base leading-out end injection region which are sequentially arranged at intervals, the first grid structure spans across the first collector leading-out end injection region and the emitter leading-out end injection region, and the second grid structure spans across the emitter leading-out end injection region and the second collector leading-out end injection region. According to the bipolar transistor, the grid electrode is added between the emitter region and the collector region to regulate and control the potential of the transverse PNP base region, so that the parallel MOS transistor formed by the bipolar transistor, the emitter region and the collector region is formed, and positive feedback can be formed by periodically applying the voltage of the grid electrode terminal, so that the PNP transistor stably works under high current and cannot generate breakdown phenomenon.
Description
Technical Field
The application belongs to the field of semiconductor manufacturing, and relates to a bipolar transistor structure and a manufacturing method thereof.
Background
With the rapid development of industries such as new energy automobiles, smart grids, mobile communication and the like, high-voltage switching circuits with large current are increasingly emphasized, and current electronic switching elements include bipolar transistors (Bipolar Junction Transistor, 103BJT for short), insulated Gate Bipolar Transistors (IGBT) and field effect transistors (MOSFET), and compared with other two switching elements, the BJT has wide application due to good impact resistance, low failure rate and lower cost. In order to obtain a large current gain, the BJT needs to have the following characteristics: (1) the doping concentration of the emission region is higher (the multi-sub number is large); (2) The doping concentration of the base region is lower (compositeSmall current) and thin width (small composite current); and (3) the area of the collector region is larger, and the doping concentration is low. In the common emitter output characteristic state, following V CE With the continued increase of the collector reverse bias voltage, the width of the barrier region (space charge region) of the collector junction is increased, the size of the base region is decreased, the concentration gradient of the base region, that is, the concentration gradient of the electrons from the emitter is increased, so that the current is increased, when the collector reverse bias voltage reaches a limit, the collector junction current is increased sharply, and the collector junction breaks down, so, referring to fig. 1, a schematic internal structure of a bipolar junction transistor is shown, wherein B represents the base, C represents the collector and E represents the emitter, and the bipolar transistor includes the base region 101, the collector region 102 and the emitter region 103, which are limited by the width and the doping concentration of the base region 101, and the bipolar transistor is easy to break down at a high current, that is, the breakdown voltage is lower under the condition of floating the base, and is easy to damage the open circuit.
Therefore, how to provide a bipolar transistor structure and a manufacturing method thereof, so as to realize that the PNP transistor can stably work without collector breakdown under the large current generated by applying the reverse bias voltage of the collector junction, and prevent circuit damage, is an important technical problem to be solved urgently by those skilled in the art.
It should be noted that the foregoing description of the background art is only for the purpose of providing a clear and complete description of the technical solution of the present application and is presented for the convenience of understanding by those skilled in the art. The above-described solutions are not considered to be known to the person skilled in the art simply because they are set forth in the background of the application section.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present application is to provide a bipolar transistor structure for solving the problem that the bipolar transistor is susceptible to collector breakdown under high current due to the limitation of the body width and the doping concentration in the prior art.
To achieve the above and other related objects, the present application provides a bipolar transistor structure comprising:
a P-type substrate;
the deep N well is positioned in the P-type substrate;
the N-type epitaxial layer is positioned above the P-type substrate;
the electrode leading-out end injection region is positioned in the N-type epitaxial layer and comprises a first base leading-out end injection region, a first collector leading-out end injection region, an emitter leading-out end injection region, a second collector leading-out end injection region and a second base leading-out end injection region which are sequentially arranged at intervals in the horizontal direction;
the first grid structure and the second grid structure are positioned above the N-type epitaxial layer, the first grid structure spans between the first collector lead-out end injection region and the emitter lead-out end injection region, and the second grid structure spans between the emitter lead-out end injection region and the second collector lead-out end injection region;
the electrode lead-out end comprises a base electrode lead-out end, a collector electrode lead-out end, an emitter electrode lead-out end and a grid electrode lead-out end, wherein the base electrode lead-out end is electrically connected with the first base electrode lead-out end injection region and the second base electrode lead-out end injection region, the collector electrode lead-out end is electrically connected with the first collector electrode lead-out end injection region and the second collector electrode lead-out end injection region, the emitter electrode lead-out end is electrically connected with the emitter electrode lead-out end injection region, and the grid electrode lead-out end is electrically connected with the first grid electrode structure and the second grid electrode structure.
Optionally, the semiconductor device further comprises an N-type buried layer and a P-type buried layer, wherein the N-type buried layer is located in the deep N well, and the P-type buried layer is located in the P-type substrate and is adjacent to the deep N well.
Optionally, the doping concentration range of the N-type buried layer is 8e17cm -3 ～2e18cm -3 The doping concentration range of the P-type buried layer is 8e17cm -3 ～2e18cm -3 。
Optionally, a first isolation structure is further included, and the first isolation structure is located in the N-type epitaxial layer.
Optionally, the first isolation structure comprises a deep trench isolation structure.
Optionally, the semiconductor device further comprises a second isolation structure, the second isolation structure is located on the upper surface layer of the N-type epitaxial layer, electric isolation is achieved between the first base extraction end injection region and the first collector extraction end injection region through the second isolation structure, and electric isolation is achieved between the second base extraction end injection region and the second collector extraction end injection region through the second isolation structure.
Optionally, the second isolation structure includes at least one of LOCOS isolation and STI isolation.
Optionally, the doping concentration of the P-type substrate is in the range of 1e15cm -3 ～3e15cm -3 The doping concentration range of the N-type epitaxial layer is 1e18cm -3 ～5e18cm -3 The doping concentration range of the deep N well is 8e16cm -3 ～2e17cm -3 The doping concentration range of the base extraction end injection region is 8e19cm -3 ～2e20cm -3 The doping concentration range of the collector terminal injection region is 8e19cm -3 ～2e20cm -3 The doping concentration range of the emitter extraction end injection region is 8e19cm -3 ～2e20cm -3 。
Optionally, the first gate structure includes a first gate dielectric layer, the second gate structure includes a second gate dielectric layer, the thickness of the first gate dielectric layer is greater than 3nm, and the thickness of the second gate dielectric layer is greater than 3nm.
The application also discloses a manufacturing method of the bipolar transistor structure, which comprises the following steps:
providing a P-type substrate;
forming a deep N well in the P-type substrate;
forming an N-type epitaxial layer above the P-type substrate;
forming an electrode lead-out end injection region in the N-type epitaxial layer, wherein the electrode lead-out end injection region comprises a first base electrode lead-out end injection region, a first collector electrode lead-out end injection region, an emitter electrode lead-out end injection region, a second collector electrode lead-out end injection region and a second base electrode lead-out end injection region which are sequentially arranged at intervals in the horizontal direction;
forming a first gate structure and a second gate structure above the N-type epitaxial layer, wherein the first gate structure spans between the first collector lead-out end injection region and the emitter lead-out end injection region, and the second gate structure spans between the emitter lead-out end injection region and the second collector lead-out end injection region;
the electrode lead-out end is formed and comprises a base electrode lead-out end, a collector electrode lead-out end, an emitter electrode lead-out end and a grid electrode lead-out end, wherein the base electrode lead-out end is electrically connected with the first base electrode lead-out end injection region and the second base electrode lead-out end injection region, the collector electrode lead-out end is electrically connected with the first collector electrode lead-out end injection region and the second collector electrode lead-out end injection region, the emitter electrode lead-out end is electrically connected with the emitter electrode lead-out end injection region, and the grid electrode lead-out end is electrically connected with the first grid electrode structure and the second grid electrode structure.
As described above, the bipolar transistor structure of the application is used for regulating and controlling the potential of the lateral PNP base region by adding the grid electrode between the emitter region and the collector region to form the parallel MOS transistor formed by the lateral PNP base region, the emitter region and the collector region, and positive feedback can be formed by periodically applying the voltage of the grid electrode terminal, so that the PNP transistor can stably work under high current, the phenomenon that the PNP transistor is damaged and even a switching circuit is damaged can not occur due to breakdown phenomenon, and the bipolar transistor structure of the application reduces the occurrence of substrate leakage under the high current working condition and improves the performance stability of the device during working by isolating the base region to form a local floating body structure.
Drawings
Fig. 1 shows a schematic structure of a bipolar transistor.
Fig. 2 is a schematic cross-sectional view of a bipolar transistor structure according to the present application.
Fig. 3 shows an equivalent circuit diagram of the bipolar transistor structure of the present application.
Fig. 4 is a schematic diagram showing the movement of electron-hole pairs in the space charge region of the collector junction in the bipolar transistor structure according to the present application when impact ionization occurs.
Fig. 5 is a diagram showing the effect of the bipolar transistor structure of the present application.
Description of element numbers: 101 base region, 102 collector region, 103 emitter region, 1P-type substrate, 2 deep N well, 3N epitaxial layer, 4 first base extraction end injection region, 5 first collector extraction end injection region, 6 emitter extraction end injection region, 7 second collector extraction end injection region, 8 second base extraction end injection region, 9 first gate structure, 10 second gate structure, 11N buried layer, 12P-type buried layer, 13 first isolation structure, 14 second isolation structure, 15 passivation layer.
Detailed Description
Other advantages and effects of the present application will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present application with reference to specific examples. The application may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present application.
Please refer to fig. 2 to fig. 5. It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present application by way of illustration, and only the components related to the present application are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
Example 1
The present embodiment provides a bipolar transistor structure, please refer to fig. 2, which is a schematic cross-sectional view of the bipolar transistor structure, wherein B represents a base electrode, C represents a collector electrode, E represents an emitter electrode, G represents a gate electrode in fig. 2, the bipolar transistor structure includes a P-type substrate 1, a deep N-well 2, an N-type epitaxial layer 3, an electrode lead-out injection region, a first gate structure 9, a second gate structure 10, and an electrode lead-out, wherein the deep N-well 2 is located in the P-type substrate 1, the N-type epitaxial layer 3 is located above the P-type substrate 1, the electrode lead-out injection region is located in the N-type epitaxial layer 3, and the first gate structure 9 and the second gate structure 10 are located above the N-type epitaxial layer 3.
Specifically, the electrode lead-out end injection region comprises a first base electrode lead-out end injection region 4, a first collector electrode lead-out end injection region 5, an emitter electrode lead-out end injection region 6, a second collector electrode lead-out end injection region 7 and a second base electrode lead-out end injection region 8 which are sequentially arranged at intervals in the horizontal direction; the first gate structure 9 spans between the first collector terminal implant region 5 and the emitter terminal implant region 6, and the second gate structure 10 spans between the emitter terminal implant region 6 and the second collector terminal implant region 7.
Specifically, the electrode lead-out terminal includes a base lead-out terminal, a collector electrode lead-out terminal, an emitter electrode lead-out terminal and a gate lead-out terminal, the base lead-out terminal is electrically connected with the first base lead-out terminal injection region 4 and the second base lead-out terminal injection region 8, the collector lead-out terminal is electrically connected with the first collector lead-out terminal injection region 5 and the second collector lead-out terminal injection region 7, the emitter lead-out terminal is electrically connected with the emitter lead-out terminal injection region 6, and the gate lead-out terminal is electrically connected with the first gate structure 9 and the second gate structure 10.
As an example, the semiconductor device further includes an N-type buried layer 11 and a P-type buried layer 12, wherein the N-type buried layer 11 is located in the deep N-well 2, and the P-type buried layer 12 is located in the P-type substrate 1 and is adjacent to the deep N-well 2.
Specifically, the collector of the transistor in the bipolar integrated circuit must be led out from the bottom layer to the connection point, which increases the collector series resistance and can adversely affect the circuit performance. In order to reduce the series resistance of the collector, a buried layer is firstly diffused below the collector when the transistor is manufactured, so that carriers firstly move to the buried layer region and are collected by the collector, a current low-resistance channel is provided for the collector, the collection efficiency is improved, the parasitic resistance of the collector is small, and the series resistance of the collector is reduced. The forming of the N-type buried layer 11 includes the steps of: and on the basis of the pre-judging region for manufacturing the collector of the P-type substrate 1, forming a high doping region by diffusion below the region where the collector is to be formed, and epitaxially growing an N-type epitaxial layer 3 on the high doping region in the later period to embed an N-type buried layer 11 below.
As an example, the doping concentration of the N-type buried layer 11 is 8e17cm -3 ～2e18cm -3 The doping concentration range of the P-type buried layer 12 is 8e17cm -3 ～2e18cm -3 。
As an example, a first isolation structure 13 is further included, the first isolation structure 13 is located in the N-type epitaxial layer 3, and the first isolation structure 13 includes a deep trench isolation structure. The purpose of the first isolation structure 13 is to electrically isolate adjacent bipolar transistor structures, and the deep trench isolation structure can completely isolate adjacent bipolar transistors, so as to prevent leakage, low breakdown voltage, latch-up effect and the like caused by incomplete isolation.
As an example, the semiconductor device further comprises a second isolation structure 14, the second isolation structure 14 is located on the upper surface layer of the N-type epitaxial layer 3, the first base terminal injection region 4 and the first collector terminal injection region 5 are electrically isolated by the second isolation structure 14, and the second base terminal injection region 8 and the second collector terminal injection region 7 are electrically isolated by the second isolation structure 14. The second isolation structure 14 includes at least one of LOCOS isolation and STI isolation, and the purpose of the second isolation structure 14 is to electrically isolate the adjacent base terminal injection region from the collector terminal injection region or the first isolation structure 13, where the second isolation structure 14 is LOCOS isolation in this embodiment, and the LOCOS isolation is simpler and less costly to manufacture than other isolation technologies. In addition, a second isolation structure 14 is also arranged between the first base extraction end injection region 4 and the first isolation structure 13 and between the second base extraction end injection region 8 and the first isolation structure 13, so that a better electrical isolation effect can be achieved. The method for forming the second isolation structure 14 includes growing a passivation layer 15 on the surface of the N-type epitaxial layer 3, etching a growth window of the isolation structure to form the second isolation structure 14, etching a window of the electrode lead-out terminal to lead out an electrode after forming the second isolation structure 14, and remaining passivation layer 15 remains as a protection layer of the device.
As an example, the doping concentration of the P-type substrate 1 is in the range of 1e15cm -3 ～3e15cm -3 The doping concentration range of the N-type epitaxial layer 3 is 1e18cm -3 ～5e18cm -3 The doping concentration range of the deep N well 2 is 8e16cm -3 ～2e17cm -3 The doping concentration range of the base extraction end injection region is 8e19cm -3 ～2e20cm -3 The doping concentration range of the collector terminal injection region is 8e19cm -3 ～2e20cm -3 The doping concentration range of the emitter lead-out end injection region 6 is 8e19cm -3 ～2e20cm -3 . In this embodiment, the doping concentration of the P-type substrate 1 is 1e15cm -3 The doping concentration of the deep N well 2 is 1e17cm -3 The doping concentrations of the first base lead-out end injection region 4, the second base lead-out end injection region 8, the first collector lead-out end injection region 5, the second collector lead-out end injection region 7 and the emitter lead-out end injection region 6 are all 1e20cm -3 。
As an example, the doping ions of the P-type substrate 1 and the P-type buried layer 12 include at least one of B, ga and In, the doping ions of the deep N-well 2, the N-type buried layer 11 and the N-type epitaxial layer 3 include at least one of P, as and Sb, in this embodiment, the doping ions of the P-type substrate 1 and the P-type buried layer 12 are B, the doping ions of the deep N-well 2, the N-type buried layer 11 and the N-type epitaxial layer 3 are As, and In other embodiments, the doping ion types In the above structures may be reasonably selected according to actual requirements, and may be one or more ion combinations.
As an example, the first gate structure 9 includes a first gate dielectric layer, the second gate structure 10 includes a second gate dielectric layer, the thickness of the first gate dielectric layer is greater than 3nm, the thickness of the second gate dielectric layer is greater than 3nm, and the materials of the first gate dielectric layer and the second gate dielectric layer include at least one of silicon dioxide and a high-k dielectric material (e.g., hafnium dioxide). In this embodiment, the materials of the first gate dielectric layer and the second gate dielectric layer are silicon dioxide, and the materials and thickness of the gate dielectric layers are selected according to specific processes in actual production.
Specifically, referring to fig. 3, an equivalent circuit diagram of the bipolar transistor structure of the present embodiment is shown, which is equivalent to connecting the lateral PNP transistor and the floating body P-type MOS transistor in parallel. When working with low current, the emitter junction (B-E junction) is forward biased, i.e. V for PNP tube E ＝V SS ，V B ＝V SS -0.7, collector junction (B-C junction) reverse biased, V as collector voltage continues to increase, i.e. for PNP tube C Gradually decrease, resulting in V CE The absolute value of (a) is gradually increased, at the moment, positive voltage is applied to the G end, and collision ionization is generated in the space charge region of the collecting junction, wherein V E For emitter potential, V C For collector potential, V B For base potential, V CE V is the voltage between the collector and the emitter SS Is the supply voltage.
Referring to fig. 4, an electron-hole motion diagram of a space charge region is shown, where a reverse bias PN junction is applied, where a strong electric field is present in the space charge region, when the reverse bias is high enough and the electric field is strong enough in the space charge region, carriers in a semiconductor are heated by the electric field to generate hot carriers, and a part of the carriers can obtain high enough energy, and the carriers can transfer energy to electrons on a clamp band through collision to ionize the electrons, so as to generate electron-hole pairs, and the generated electron-hole pairs are heated by the electric field and generate new electron-hole pairs, so that the reverse current is greatly increased along with the reverse voltage, and the carriers continuously drift along the direction of the electric field under the action of the strong electric field, so that great kinetic energy can be obtained, thereby becoming hot carriers. Holes in electron-hole pairs generated by impact ionization are rapidly collected by the C end, electrons drift and accumulate towards the B end, and as electrons are far away from the B end, the local potential of a base region is reduced, so that PNP tube current is increased, the increased current of the PNP tube further increases the holes at the C end in turn, therefore, positive feedback can be formed by periodically applying G end voltage, and the current of a collector junction is rapidly increased when the reverse bias voltage of the collector junction continuously increases to the limit due to the continuous voltage application, so that the collector junction breaks down, and even the bipolar transistor is damaged. In addition, the isolation structure formed by the P-type buried layer 4, the deep N well 2 and the N-type buried layer 3 shown in fig. 2 can isolate the base region to form a local floating body structure, so that the occurrence of substrate leakage under the high-current working condition is reduced, and the performance stability of the device in working is improved.
Referring to fig. 5, a graph of the actual effect of the bipolar transistor according to the present embodiment is shown, in which a solid line is a curve of current variation along with voltage of a conventional PNP transistor, and the current of the PNP transistor gradually increases along with the increase of the collector-emitter voltage and reaches a saturated state soon, that is, the current of the PNP transistor tends to be stable and does not increase along with the increase of the voltage when reaching a certain value, if the collector junction of the PNP transistor is continuously applied with voltage, a breakdown phenomenon may occur, in which a dotted line is a curve of current variation along with voltage in the operation process of the PNP transistor according to the present embodiment, that is, by periodically applying the voltage at the G end, the current of the PNP transistor can be obviously increased, and meanwhile, the breakdown phenomenon of the PNP transistor caused by the continuous voltage application does not occur, so that the high current operation capability of the PNP transistor is improved, and the risk of failure is reduced.
According to the bipolar transistor structure, the grid electrode is added between the emitter region and the collector region to regulate and control the potential of the transverse PNP base region, the parallel MOS transistor formed by the lateral PNP base region, the emitter region and the collector region is formed, positive feedback can be formed by periodically applying the voltage of the grid electrode end, the PNP transistor can stably work under high current, the PNP transistor is not damaged due to breakdown phenomenon, and even a switching circuit is damaged.
Example two
Referring to fig. 2, a schematic cross-sectional view of a bipolar transistor structure obtained by the method of the present embodiment is shown, and includes the following steps:
providing a P-type substrate 1;
forming a deep N well 2 in the P-type substrate 1;
forming an N-type epitaxial layer 3 above the P-type substrate 1;
forming an electrode lead-out end injection region in the N-type epitaxial layer 3, wherein the electrode lead-out end injection region comprises a first base electrode lead-out end injection region 4, a first collector electrode lead-out end injection region 5, an emitter electrode lead-out end injection region 6, a second collector electrode lead-out end injection region 7 and a second base electrode lead-out end injection region 8 which are sequentially arranged at intervals in the horizontal direction;
forming a first gate structure 9 and a second gate structure 10 above the N-type epitaxial layer 3, wherein the first gate structure 9 spans between the first collector terminal implant region 5 and the emitter terminal implant region 6, and the second gate structure 10 spans between the emitter terminal implant region 6 and the second collector terminal implant region 7;
the electrode lead-out end is formed and comprises a base lead-out end, a collector electrode lead-out end, an emitter electrode lead-out end and a grid electrode lead-out end, wherein the base lead-out end is electrically connected with the first base lead-out end injection region 4 and the second base lead-out end injection region 8, the collector lead-out end is electrically connected with the first collector lead-out end injection region 5 and the second collector lead-out end injection region 7, the emitter lead-out end is electrically connected with the emitter lead-out end injection region 6, and the grid electrode lead-out end is electrically connected with the first grid electrode structure 9 and the second grid electrode structure 10.
As an example, the method further includes forming an N-type buried layer 11 and a P-type buried layer 12, wherein the N-type buried layer 11 is located in the deep N-well 2, the P-type buried layer 12 is located in the P-type substrate 1, and the P-type buried layer 12 is adjacent to the deep N-well 2. The method for forming the N-type buried layer 11 and the P-type buried layer 12 comprises the following steps: and growing a layer of silicon dioxide serving as a hard mask layer on the P-type substrate 1, performing photoetching to form a buried layer region, and respectively injecting N-type impurities and P-type impurities to form the N-type buried layer 11 and the P-type buried layer 12.
As an example, a first isolation structure 13 is formed in the N-type epitaxial layer 3, and the first isolation structure 13 and the P-type buried layer form a stacked structure to play a role in isolation.
As an example, a second isolation structure 14 is further formed on the upper surface layer of the N-type epitaxial layer 3, the second isolation structure 14 is located between the first base terminal implantation region 4 and the first collector terminal implantation region 5, and the second isolation structure 14 is further located between the second base terminal implantation region 8 and the second collector terminal implantation region 7.
As an example, the methods of forming the first base terminal implant region 4, the first collector terminal implant region 5, the second collector terminal implant region 7, and the emitter terminal implant region 6 include, but are not limited to, ion implantation.
The bipolar transistor structure manufactured by the manufacturing method of the bipolar transistor structure of the embodiment can form positive feedback by periodically applying the voltage of the gate terminal, so that the PNP tube can stably work under high current and cannot break down to cause damage to the PNP tube or even damage to a switch circuit.
In summary, according to the bipolar transistor structure and the manufacturing method thereof, the grid electrode is added between the emitter region and the collector region to regulate and control the potential of the lateral PNP base region, so that the parallel MOS transistor formed by the lateral PNP base region, the emitter region and the collector region is formed, positive feedback can be formed by periodically applying the voltage of the grid electrode end, the PNP transistor can stably work under high current, the phenomenon that the PNP transistor is damaged and even a switching circuit is damaged can be avoided, and the bipolar transistor structure of the application reduces the occurrence of substrate leakage under the high current working condition by isolating the base region to form a local floating body structure, so that the performance stability of the device in working is improved; the bipolar transistor structure manufactured by the manufacturing method can form positive feedback by periodically applying the voltage of the gate terminal, so that the PNP tube can stably work under high current, and the phenomenon that the PNP tube is damaged and even a switch circuit is damaged due to the breakdown phenomenon can not occur. Therefore, the application effectively overcomes various defects in the prior art and has high industrial utilization value.
The above embodiments are merely illustrative of the principles of the present application and its effectiveness, and are not intended to limit the application. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the application. Accordingly, it is intended that all equivalent modifications and variations of the application be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.
Claims (9)
1. A bipolar transistor structure comprising:
a P-type substrate;
the deep N well is positioned in the P-type substrate;
the N-type epitaxial layer is positioned above the P-type substrate;
the electrode leading-out end injection region is positioned in the N-type epitaxial layer and comprises a first base leading-out end injection region, a first collector leading-out end injection region, an emitter leading-out end injection region, a second collector leading-out end injection region and a second base leading-out end injection region which are sequentially arranged at intervals in the horizontal direction;
the first grid structure and the second grid structure are positioned above the N-type epitaxial layer, the first grid structure spans between the first collector lead-out end injection region and the emitter lead-out end injection region, and the second grid structure spans between the emitter lead-out end injection region and the second collector lead-out end injection region;
the electrode lead-out end comprises a base lead-out end, a collector electrode lead-out end, an emitter electrode lead-out end and a grid electrode lead-out end, wherein the base lead-out end is electrically connected with the first base lead-out end injection region and the second base lead-out end injection region, the collector lead-out end is electrically connected with the first collector lead-out end injection region and the second collector lead-out end injection region, the emitter lead-out end is electrically connected with the emitter lead-out end injection region, the grid electrode lead-out end is electrically connected with the first grid electrode structure and the second grid electrode structure, and the grid electrode lead-out end is used for periodically applying voltage to form positive feedback so as to improve the heavy current working capacity of the bipolar transistor;
the N-type buried layer is positioned in the deep N well, and the P-type buried layer is positioned in the P-type substrate and is adjacent to the deep N well.
2. The bipolar transistor structure of claim 1, wherein: the doping concentration range of the N-type buried layer is 8e17cm -3 ~2e18 cm -3 The doping concentration range of the P-type buried layer is 8e17cm -3 ~2e18 cm -3 。
3. The bipolar transistor structure of claim 1, wherein: the semiconductor device further comprises a first isolation structure, wherein the first isolation structure is located in the N-type epitaxial layer.
4. A bipolar transistor structure according to claim 3, wherein: the first isolation structure includes a deep trench isolation structure.
5. The bipolar transistor structure of claim 1, wherein: the semiconductor device further comprises a second isolation structure, the second isolation structure is located on the upper surface layer of the N-type epitaxial layer, electric isolation is achieved between the first base extraction end injection region and the first collector extraction end injection region through the second isolation structure, and electric isolation is achieved between the second base extraction end injection region and the second collector extraction end injection region through the second isolation structure.
6. The bipolar transistor structure of claim 5, wherein: the second isolation structure includes at least one of LOCOS isolation and STI isolation.
7. The bipolar transistor structure of claim 1, wherein: the doping concentration range of the P-type substrate is 1e15cm -3 ~3e15 cm -3 The doping concentration range of the N-type epitaxial layer is 1e18cm -3 ~5e18 cm -3 The doping concentration range of the deep N well is 8e16cm -3 ~2e17 cm -3 The doping concentration range of the first base extraction end injection region is 8e19cm -3 ~2e20 cm -3 The doping concentration range of the second base extraction end injection region is 8e19cm -3 ~2e20 cm -3 The doping concentration range of the first collector lead-out end injection region is 8e19cm -3 ~2e20 cm -3 The doping concentration range of the second collector lead-out end injection region is 8e19cm -3 ~2e20 cm -3 The doping concentration range of the emitter lead-out end injection region is 8e19cm -3 ~2e20 cm -3 。
8. The bipolar transistor structure of claim 1, wherein: the first gate structure comprises a first gate dielectric layer, the second gate structure comprises a second gate dielectric layer, the thickness of the first gate dielectric layer is larger than 3nm, and the thickness of the second gate dielectric layer is larger than 3nm.
9. A method for fabricating a bipolar transistor structure, comprising the steps of:
providing a P-type substrate;
forming a deep N well in the P-type substrate;
forming an N-type epitaxial layer above the P-type substrate;
forming an electrode lead-out end injection region in the N-type epitaxial layer, wherein the electrode lead-out end injection region comprises a first base electrode lead-out end injection region, a first collector electrode lead-out end injection region, an emitter electrode lead-out end injection region, a second collector electrode lead-out end injection region and a second base electrode lead-out end injection region which are sequentially arranged at intervals in the horizontal direction;
forming a first gate structure and a second gate structure above the N-type epitaxial layer, wherein the first gate structure spans between the first collector lead-out end injection region and the emitter lead-out end injection region, and the second gate structure spans between the emitter lead-out end injection region and the second collector lead-out end injection region;
forming an electrode lead-out end, wherein the electrode lead-out end comprises a base electrode lead-out end, a collector electrode lead-out end, an emitter electrode lead-out end and a grid electrode lead-out end, the base electrode lead-out end is electrically connected with the first base electrode lead-out end injection region and the second base electrode lead-out end injection region, the collector electrode lead-out end is electrically connected with the first collector electrode lead-out end injection region and the second collector electrode lead-out end injection region, the emitter electrode lead-out end is electrically connected with the emitter electrode lead-out end injection region, the grid electrode lead-out end is electrically connected with the first grid electrode structure and the second grid electrode structure, and the grid electrode lead-out end is used for periodically applying voltage to form positive feedback so as to improve the heavy current working capacity of the bipolar transistor;
the method further comprises the step of forming an N-type buried layer and a P-type buried layer, wherein the N-type buried layer is located in the deep N well, the P-type buried layer is located in the P-type substrate, and the P-type buried layer is adjacent to the deep N well.
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| CN1050469A (en) * | 1987-01-30 | 1991-04-03 | 得克萨斯仪器公司 | Ambipolar and CMOS (Complementary Metal Oxide Semiconductor) transistor |
| CN101887911A (en) * | 2009-05-12 | 2010-11-17 | 联发科技股份有限公司 | Lateral bipolar junction transistor and manufacture method thereof |
| CN103151351A (en) * | 2013-03-29 | 2013-06-12 | 西安电子科技大学 | Self substrate trigger ESD (Electro-Static Discharge) protecting device using dynamic substrate resistance technology, and application |
| CN105408741A (en) * | 2013-06-20 | 2016-03-16 | 埃克隆德创新公司 | An integrated sensor device for charge detection |
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| US20050275027A1 (en) * | 2003-09-09 | 2005-12-15 | Micrel, Incorporated | ESD protection for integrated circuits |
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| CN1050469A (en) * | 1987-01-30 | 1991-04-03 | 得克萨斯仪器公司 | Ambipolar and CMOS (Complementary Metal Oxide Semiconductor) transistor |
| CN101887911A (en) * | 2009-05-12 | 2010-11-17 | 联发科技股份有限公司 | Lateral bipolar junction transistor and manufacture method thereof |
| CN103151351A (en) * | 2013-03-29 | 2013-06-12 | 西安电子科技大学 | Self substrate trigger ESD (Electro-Static Discharge) protecting device using dynamic substrate resistance technology, and application |
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