CN100582296C - 在平滑衬底上形成高-k介电层 - Google Patents

在平滑衬底上形成高-k介电层 Download PDF

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CN100582296C
CN100582296C CN200580017642A CN200580017642A CN100582296C CN 100582296 C CN100582296 C CN 100582296C CN 200580017642 A CN200580017642 A CN 200580017642A CN 200580017642 A CN200580017642 A CN 200580017642A CN 100582296 C CN100582296 C CN 100582296C
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贾斯廷·布拉斯克
杰克·卡瓦列罗斯
马克·多齐
马修·梅茨
苏曼·达塔
乌代·沙阿
吉尔伯特·杜威
罗伯特·赵
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Abstract

在平滑的硅衬底上形成缓冲层和高-k金属氧化物介电层。衬底平滑可以减小高-k金属氧化物栅电介质的柱状生长。在沉积之前可以使用羟基末端使衬底表面饱和。

Description

在平滑衬底上形成高-K介电层
技术领域
本发明涉及半导体器件的制造方法，具体地，涉及包括高-K栅介电层的半导体器件的制造方法。
技术背景
具有非常薄的基于二氧化硅的栅电介质的MOS场效应晶体管会出现不可接受的栅漏电流。用某些高介电常数(k)的介电材料代替二氧化硅形成栅电介质，能够减小栅漏电流。高介电常数为大于10。然而，这样的电介质可能与多晶硅不兼容——多晶硅是制造器件栅电极的优选材料。
当栅电介质包括高-k膜时，可以在沟道和高-k膜之间形成二氧化硅或氮氧化硅薄层，从而在高-k膜上保持可接受的电子迁移率。当在电学上非常薄的栅电介质由这样一个缓冲层组成时，该缓冲层必须非常薄，例如小于大约10埃厚。当这种超薄的高-k膜包括氧化物时，会出现氧空位和过大的杂质量。氧空位使得高-k膜和栅电极之间产生不期望的相互作用。当栅电极包括多晶硅时，这种相互作用会改变电极的功函数或导致器件穿过电介质短路。
因此，需要一种用于制造包括高-k电介质的半导体器件的改善工艺。
附图说明
图1是根据本发明的一个实施例的处理晶片的示意性描述；以及
图2A-2D表示在执行本发明的实施例时所形成的结构的横截面。
具体实施方式
参见图1，衬底100可以包括体硅或绝缘体上硅晶片。或者，衬底100可以包括其他材料——所述其他材料可以与也可以不与硅结合——例如：锗、锑化铟、碲化铅、砷化铟、磷化铟、砷化镓、或锑化镓。虽然这里描述了几种形成衬底的材料的例子，但是任何可以作为制造半导体器件的基础的材料都落入本发明的精神和范围。
在衬底的表面上形成缓冲层和高-k栅介电层之前，清洗衬底100。晶片可以暴露于水/H2O2/NH4OH溶液，然后暴露于水/H2O2/HCl溶液。水/H2O2/NH4OH溶液可以除去颗粒和有机污染物，水/H2O2/HCl溶液可以除去金属污染物。
参见图1，槽140可以含有浸没晶片100的液体。管道150可以连接到臭氧源，可将臭氧泵入槽140内的液体中。兆声波搅拌器(megasonic agitator)160可以向槽140中的液体、最终向晶片100提供兆声波能量。液体可以是H2O2。
通过利用兆声波能量和臭氧进行处理，可以得到晶片100非常均匀或平滑的表面。以下未限制本发明的范围，声波能量通过提供能量克服任意表面势能，可以驱动羟基表面饱和反应，否则该表面势能将抑制末端替代(termini substitution)。
兆声波搅拌器160可以在650到1050kHz下、最优选在750kHz下工作，能耗在1到5W/cm2之间，优选范围为2W/cm2左右。来自管道150的臭氧溶解在槽140中的液体中。
在清洗衬底100之后，晶片100的硅表面上的羟基末端饱和。例如，在本发明的一个实施例中，硅表面上的任何羟基基团会与金属氯化物反应。在本发明的一个实施例中，该反应可以在真空中发生。在另一实施例中，该反应可以在槽140中发生。用于使羟基饱和的金属可以是铪、锆、镧、铝、或任何其他用于形成高-k金属氧化物电介质的金属。
在本发明的一个实施例中，例如通过喷射或浸渍在晶片表面施加金属氯化物。金属氯化物取代连接到晶片100的羟基末端的氢原子，连接到羟基末端的氧原子。然后，羟基取代氯原子，使具有羟基的硅表面饱和。
在本发明的某些实施例中，在随后缓冲层和/或高-k金属氧化物介电层的原子层沉积期间，比自然产生的氢和桥氧基团混合物更高浓度的羟基基团减少了柱状生长。对于改善的高介电常数膜生长，晶片100的表面可以小于或等于原子力显微镜(atomic force microscopy)测得的约3埃的均方根(RMS)表面偏差。
一旦表面足够平滑，就可以在衬底100上形成缓冲层110和高-k栅介电层105，如图2A和2B所示。在本发明的一个实施例中，在缓冲层上形成高-k栅介电层105之前，在衬底100上形成缓冲层110。在另一个实施例中，直接在衬底100上形成高-k栅介电层105，接着在衬底100和高-k栅介电层105之间形成缓冲层110，从而分隔开衬底100和高-k栅介电层105。
图2A-2D示出了在缓冲层110上形成高-k栅介电层105之前，在衬底100上形成缓冲层110的实施例。缓冲层110可以由任何能够确保后续沉积的高-k膜上的可接受电子迁移率的材料形成。该材料包括，例如氧化硅(例如，二氧化硅)和氮氧化硅。
在优选实施例中，缓冲层110包括使用传统的热氧化和/或氮化步骤生成的非常薄的二氧化硅或氮氧化硅层。或者，可以使用原子层沉积工艺沉积缓冲层110。缓冲层110的厚度优选小于大约15埃，更优选地介于大约2埃和大约10埃之间。
在本发明的一个实施例中，缓冲层110的厚度可以为大约2到大约4埃。这对应于大约1个单层的厚度。可以在20到30℃下、利用去离子水中4到9％的未加稳定的H2O2溶液生长单层缓冲层110。
可以在35到45℃下、利用去离子水中4到9％的未加稳定的H2O2溶液生长大约5到7埃厚的双层。惊喜地发现在某些实施例中，与使用单层生长相比使用双层生长所得到的晶体管的饱和电流较高。
另一实施例中，可以在35到65℃下、利用去离子水中25到45％的未加稳定的H2O2溶液生长大约8到10埃厚的三层。
在形成缓冲层110之后，在其表面上沉积高-k栅介电层105，形成图2B的结构。可用于制造高-k栅电介质的材料包括：氧化铪、氧化镧、铝镧氧化物、氧化锆、锆硅氧化物、氧化钛、氧化钽、氧化钇和氧化铝。特别优选的是氧化铪、氧化锆、氧化钛、和氧化铝。虽然这里描述了几种可用于形成介电层105的材料的例子，但是该层可以由其它能够减小栅漏电流的材料形成。
可以使用传统原子层化学气相沉积(CVD)工艺在缓冲层110上形成高-k栅介电层105。在该工艺中，以选定流速向CVD反应器中供应金属氧化物前体(例如金属氯化物)和蒸气，然后该CVD反应器在选定温度和压力下工作，从而在缓冲层110和介电层105之间产生原子平滑的界面。CVD反应器应该工作足够长的时间，以形成具有期望厚度的层。在优选实施例中，介电层105是超薄的层，即该层厚度小于大约20埃，更优选厚度介于大约5埃到大约20埃之间。
然后再氧化高-k栅介电层105。在优选实施例中，可以使用等离子体辅助氧化工艺来再氧化高-k栅介电层105。在该工艺中，通过将高-k栅介电层105的表面暴露于由等离子体源产生的离子化氧物质(ionized oxygen species)，来氧化该表面。例如，通过向反应器中供应氧、一氧化二氮、或氧和一氧化二氮的混合物，然后轰击反应器内的等离子体，可以产生该离子化氧物质。或者，可以远程轰击等离子体，然后将得到的离子化氧物质供应至反应器中。也可以通过使用载气，例如氩或氦，远程轰击等离子体，把得到的离子化成分提供至反应器中，然后向反应器中提供氧、一氧化二氮、或氧和一氧化二氮的混合物——等离子体源的下游，来形成离子化氧物质。
当使用等离子体辅助氧化工艺再氧化介电层105时，反应器应当在适当的条件(例如压力、射频和功率)下工作足够长的时间，以显著增大介电层表面处的氧和金属的比率，从而减小存在于该层中的氧空位。在该实施例中，优选在较低温度下，例如在低于大约500℃的温度下进行该再氧化步骤。
作为使用等离子体辅助氧化工艺再氧化高-k栅介电层105的一种选择，可以使用热氧化工艺(在适当的氧化环境中进行)。例如，在低于大约600℃下发生并持续不到大约60秒的快速热氧化步骤，足以使氧和金属的比率增大到可接受的程度。400℃、30秒的快速热氧化处理表现出令人满意的结果。通过在较低温度下再氧化高-k栅介电层105较短的时间，高-k栅介电层可以保持它的无定形状态，并且可以减小扩散进入硅界面的氧量。继而可以限制在该界面处生长的额外氧化物的量——保证缓冲层110的厚度基本保持不变。
作为使用等离子体辅助氧化工艺或热氧化工艺的一种选择，可以使用化学氧化、蒸气氧化、臭氧清洗、或过氧化清洗工艺来再氧化高-k栅介电层105。也可使用这些工艺的各种组合，例如特定的湿/干氧化步骤。用于氧化高-k栅介电层105的工艺不限于以上列出的工艺。本发明的方法考虑使用在任何适当氧化环境中发生的任何适当氧化步骤，或任意可接受的使高-k栅介电层105中的氧与金属的比率增大的化学处理。
在氧化高-k栅介电层105之后，可以在其上形成栅电极。在优选实施例中，可以通过初始在高-k栅介电层105上沉积多晶硅层120形成栅电极一产生图2C的结构。可以使用传统方法沉积多晶硅层120，优选厚度介于大约500埃到大约4000埃之间。在使用传统技术蚀刻层120、105和110以形成图2D的结构之后，可以应用通常用来完成栅电极的其它步骤(例如，在蚀刻过的多晶硅结构130的上部形成硅化物(未示出))。这些步骤对于本领域技术人员来说是公知的，这里不再具体描述。虽然栅电极优选包括多晶硅，但是可以选择由各种可与上述高-k栅介电层一起使用的金属制成。
虽然上面的描述详细说明了在本发明的方法中可以使用的特定步骤和材料，但是本领域技术人员应该意识到可以做出许多变形和替换。因此，所有变形、修改、替换和附加都应视为落入由所附权利要求限定的本发明的精神和范围内。

Claims (18)

1.一种方法，包括：
在衬底上形成高-k栅介电层，该衬底具有使用原子力显微镜测得的小于约3埃的均方根表面偏差，
该方法还包括将所述衬底暴露在具有溶解的臭氧和声波能量的槽中。
2.根据权利要求1所述的方法，其中所述高-k栅介电层使用原子层化学气相沉积工艺形成。
3.根据权利要求1所述的方法，包括在形成所述高-k栅介电层之前，增加所述衬底上的表面羟基末端。
4.根据权利要求3所述的方法，包括使现有末端与金属氯化物反应。
5.根据权利要求4所述的方法，包括通过用羟基末端代替氯原子，来增加表面羟基末端。
6.根据权利要求1所述的方法，包括在所述衬底上方和所述介电层下方形成大约一个单层厚的缓冲层。
7.根据权利要求1所述的方法，包括在所述衬底上方和所述介电层下方形成大约两个单层厚的缓冲层。
8.根据权利要求1所述的方法，包括在所述衬底上方和所述介电层下方形成大约三个单层厚的缓冲层。
9.根据权利要求1所述的方法，包括将所述衬底暴露在过氧化氢的槽中。
10.根据权利要求9所述的方法，包括将所述衬底暴露在兆声波能量中。
11.根据权利要求1所述的方法，包括在大约35到大约45℃之间的温度下、利用过氧化氢在所述衬底上生长双层缓冲材料层。
12.一种通过权利要求1所述的方法制造的半导体结构
13.根据权利要求12所述的结构，包括所述高-k栅介电层和所述衬底之间的缓冲层。
14.根据权利要求13所述的结构，其中所述缓冲层大约为一个单层厚。
15.根据权利要求13所述的结构，其中所述缓冲层大约为两个单层厚。
16.根据权利要求13所述的结构，其中所述缓冲层大约为三个单层厚。
17.根据权利要求12所述的结构，其中所述高-k栅介电层为金属氧化物。
18.根据权利要求12所述的结构，其中所述衬底具有饱和羟基。
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Families Citing this family (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7068544B2 (en) * 2001-08-30 2006-06-27 Micron Technology, Inc. Flash memory with low tunnel barrier interpoly insulators
US6921702B2 (en) * 2002-07-30 2005-07-26 Micron Technology Inc. Atomic layer deposited nanolaminates of HfO2/ZrO2 films as gate dielectrics
US7601649B2 (en) * 2004-08-02 2009-10-13 Micron Technology, Inc. Zirconium-doped tantalum oxide films
US7361608B2 (en) * 2004-09-30 2008-04-22 Tokyo Electron Limited Method and system for forming a feature in a high-k layer
TWI237867B (en) * 2004-10-29 2005-08-11 Taiwan Semiconductor Mfg Method of improving to deposit dielectric
US7235501B2 (en) 2004-12-13 2007-06-26 Micron Technology, Inc. Lanthanum hafnium oxide dielectrics
US7374964B2 (en) * 2005-02-10 2008-05-20 Micron Technology, Inc. Atomic layer deposition of CeO2/Al2O3 films as gate dielectrics
US7687409B2 (en) 2005-03-29 2010-03-30 Micron Technology, Inc. Atomic layer deposited titanium silicon oxide films
US7365027B2 (en) * 2005-03-29 2008-04-29 Micron Technology, Inc. ALD of amorphous lanthanide doped TiOx films
US7972441B2 (en) 2005-04-05 2011-07-05 Applied Materials, Inc. Thermal oxidation of silicon using ozone
US7662729B2 (en) 2005-04-28 2010-02-16 Micron Technology, Inc. Atomic layer deposition of a ruthenium layer to a lanthanide oxide dielectric layer
US7927948B2 (en) 2005-07-20 2011-04-19 Micron Technology, Inc. Devices with nanocrystals and methods of formation
US7393736B2 (en) * 2005-08-29 2008-07-01 Micron Technology, Inc. Atomic layer deposition of Zrx Hfy Sn1-x-y O2 films as high k gate dielectrics
US20070049023A1 (en) * 2005-08-29 2007-03-01 Micron Technology, Inc. Zirconium-doped gadolinium oxide films
US8071476B2 (en) * 2005-08-31 2011-12-06 Micron Technology, Inc. Cobalt titanium oxide dielectric films
US7410910B2 (en) * 2005-08-31 2008-08-12 Micron Technology, Inc. Lanthanum aluminum oxynitride dielectric films
US20070161214A1 (en) * 2006-01-06 2007-07-12 International Business Machines Corporation High k gate stack on III-V compound semiconductors
US7972974B2 (en) * 2006-01-10 2011-07-05 Micron Technology, Inc. Gallium lanthanide oxide films
JP2008034563A (ja) * 2006-07-27 2008-02-14 National Institute Of Advanced Industrial & Technology Ｍｉｓ型半導体装置
US7932150B2 (en) * 2008-05-21 2011-04-26 Kabushiki Kaisha Toshiba Lateral oxidation with high-K dielectric liner
US20100102393A1 (en) * 2008-10-29 2010-04-29 Chartered Semiconductor Manufacturing, Ltd. Metal gate transistors
KR101634748B1 (ko) 2009-12-08 2016-07-11 삼성전자주식회사 트랜지스터의 제조방법 및 그를 이용한 집적 회로의 형성방법
US8334161B2 (en) * 2010-07-02 2012-12-18 Sunpower Corporation Method of fabricating a solar cell with a tunnel dielectric layer
CN103137461B (zh) * 2011-12-02 2015-10-14 中芯国际集成电路制造(上海)有限公司 高k栅介质层的形成方法及形成装置、晶体管的形成方法
CN103928307B (zh) * 2013-01-10 2016-08-31 中芯国际集成电路制造(上海)有限公司 晶体管的形成方法、高k栅介质层的形成方法
US20210104401A1 (en) * 2019-10-04 2021-04-08 Applied Materials, Inc. Novel method for gate interface engineering
WO2021086788A1 (en) 2019-11-01 2021-05-06 Applied Materials, Inc. Cap oxidation for finfet formation

Family Cites Families (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5646976A (en) * 1994-08-01 1997-07-08 Osmic, Inc. Optical element of multilayered thin film for X-rays and neutrons
JP3923103B2 (ja) * 1995-08-29 2007-05-30 忠弘 大見 半導体製造システム及びクリーンルーム
US6090442A (en) 1997-04-14 2000-07-18 University Technology Corporation Method of growing films on substrates at room temperatures using catalyzed binary reaction sequence chemistry
US6479195B1 (en) * 2000-09-15 2002-11-12 Intel Corporation Mask absorber for extreme ultraviolet lithography
JP4367599B2 (ja) * 2000-12-19 2009-11-18 日本電気株式会社 高誘電率薄膜の成膜方法
US6486682B1 (en) * 2001-05-18 2002-11-26 Advanced Micro Devices, Inc. Determination of dielectric constants of thin dielectric materials in a MOS (metal oxide semiconductor) stack
US6806145B2 (en) 2001-08-31 2004-10-19 Asm International, N.V. Low temperature method of forming a gate stack with a high k layer deposited over an interfacial oxide layer
US6643353B2 (en) * 2002-01-10 2003-11-04 Osmic, Inc. Protective layer for multilayers exposed to x-rays
US6504214B1 (en) * 2002-01-11 2003-01-07 Advanced Micro Devices, Inc. MOSFET device having high-K dielectric layer
US6452229B1 (en) * 2002-02-21 2002-09-17 Advanced Micro Devices, Inc. Ultra-thin fully depleted SOI device with T-shaped gate and method of fabrication
US6627556B1 (en) 2002-04-24 2003-09-30 Lsi Logic Corporation Method of chemically altering a silicon surface and associated electrical devices
US20030232501A1 (en) 2002-06-14 2003-12-18 Kher Shreyas S. Surface pre-treatment for enhancement of nucleation of high dielectric constant materials
US7102367B2 (en) * 2002-07-23 2006-09-05 Fujitsu Limited Probe card and testing method of semiconductor chip, capacitor and manufacturing method thereof
JP2004087733A (ja) * 2002-08-26 2004-03-18 Fujitsu Ltd 半導体装置の製造方法
JP2004087960A (ja) * 2002-08-28 2004-03-18 Fujitsu Ltd 半導体装置の製造方法
US6723581B1 (en) * 2002-10-21 2004-04-20 Agere Systems Inc. Semiconductor device having a high-K gate dielectric and method of manufacture thereof
US6706581B1 (en) * 2002-10-29 2004-03-16 Taiwan Semiconductor Manufacturing Company Dual gate dielectric scheme: SiON for high performance devices and high k for low power devices
US6787440B2 (en) 2002-12-10 2004-09-07 Intel Corporation Method for making a semiconductor device having an ultra-thin high-k gate dielectric
US7049242B2 (en) * 2003-01-06 2006-05-23 Texas Instruments Incorporated Post high voltage gate dielectric pattern plasma surface treatment
US7018925B2 (en) * 2003-01-06 2006-03-28 Texas Instruments Incorporated Post high voltage gate oxide pattern high-vacuum outgas surface treatment
US6696327B1 (en) 2003-03-18 2004-02-24 Intel Corporation Method for making a semiconductor device having a high-k gate dielectric
US20040198069A1 (en) * 2003-04-04 2004-10-07 Applied Materials, Inc. Method for hafnium nitride deposition
US7238628B2 (en) * 2003-05-23 2007-07-03 Symmorphix, Inc. Energy conversion and storage films and devices by physical vapor deposition of titanium and titanium oxides and sub-oxides
US7220635B2 (en) * 2003-12-19 2007-05-22 Intel Corporation Method for making a semiconductor device with a metal gate electrode that is formed on an annealed high-k gate dielectric layer
US7012027B2 (en) * 2004-01-27 2006-03-14 Taiwan Semiconductor Manufacturing Company, Ltd. Zirconium oxide and hafnium oxide etching using halogen containing chemicals

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