CN100525110C

CN100525110C - Storage detecting circuit realized adopting simulation method

Info

Publication number: CN100525110C
Application number: CNB2005101112950A
Authority: CN
Inventors: 朱红卫; 刘天伟; 温建新; 童红亮
Original assignee: Shanghai Hua Hong NEC Electronics Co Ltd
Current assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority date: 2005-12-08
Filing date: 2005-12-08
Publication date: 2009-08-05
Anticipated expiration: 2025-12-08
Also published as: CN1980065A

Abstract

The level detection circuit can detect lock state of phase locking ring circuit (PLRC). Using the level detection circuit combined with logic module can determine locking time of PLRC. The level detection circuit includes lowpass filter, pedestal generator, two comparators, and latch unit. Lowpass filter is in use for filtering out burrs of nonlinear variational signal from PLRC, and picking up DC and low frequency components. The pedestal generator generates offset voltage signal needed by the two comparators, and generates comparison signal needed by the input ends of the two comparators. Comparing between nonlinear variational signal passed through the lowpass filter and two voltage signals generated by the pedestal generator, the comparators return logic 0 or 1. Latch unit latches or jumps logic signals of two comparators.

Description

A kind of level sensitive circuit that adopts analogy method to realize

Technical field

The present invention relates to a kind of circuit that detects phase lock loop lock on time, relate in particular to a kind of level sensitive circuit that adopts analogy method to realize.

Background technology

Phase-locked loop has become a requisite module in the modern very lagre scale integrated circuit (VLSIC) as the important component part of clock circuit, all adopts integrated phase lock to produce high-frequency clock in the sheet in nearly all digital integrated circuit.Phase-locked loop is a negative feedback automatic control system, its loop operating state can be divided two stages of doing: follow the tracks of, lock, the loop frequency required time simple defining that is stabilized in design of just having started working is locking time, usually, phase-locked loop circuit can clearly be judged its locking time in the design and simulation process, but in the circuit practical work process, owing in the microsecond magnitude, be difficult to locking time judge.This just needs corresponding circuit structure to detect judgement, and the design of current phase-locked loop circuit seldom has corresponding designing technique to realize.

Summary of the invention

Technical problem to be solved by this invention provides a kind of level sensitive circuit that adopts analogy method to realize, it can detect the phase-locked loop circuit lock condition, can utilize this circuit in conjunction with certain logic function module, just can realize the phase-locked loop circuit judgement of locking time.

In order to solve above technical problem, the invention provides a kind of level sensitive circuit that adopts analogy method to realize, it comprises low pass filter, pedestal generator, two comparators, latch and output driver element, described low pass filter is with the burr filtering from the nonlinear change signal of phase-locked loop circuit, extract the direct current and the low frequency component of signal, described pedestal generator produces described two needed biasing voltage signals of comparator and two needed comparison signals of comparator input terminal, described comparator is to be compared by two voltage signals that described pedestal generator produced together through the nonlinear change signal behind the described low pass filter, and return logical zero or 1, described latch is that the logical signal with two comparators latchs or saltus step, and described output driver element is that the result with latch strengthens driving.

Because the present invention uses dual comparator that nonlinear change band burr signal is detected and utilizes latch that testing result is latched or saltus step, can realize detecting the monitoring of phase-locked loop circuit lock condition, if and, just can realize to the phase-locked loop circuit judgement of locking time in conjunction with certain logic function module.

Description of drawings

Below in conjunction with the drawings and specific embodiments the present invention is further elaborated.

Fig. 1 is a circuit diagram of the present invention;

Fig. 2 has circuit phase-locked loop simulated effect figure of the present invention.

Embodiment

As shown in Figure 1, it is a level sensitive circuit schematic diagram of the present invention.It comprises low pass filter (LPF) 1,2, two comparators of pedestal generator (BGR) (COM) 3,4 and latch (LATH) 5, output driver element (BUF) 6.At first, low pass filter 1 will extract the direct current and the low frequency component of signal from the burr filtering of the nonlinear change signal (can be the phase frequency detector output signal of phase-locked loop circuit) of phase-locked loop circuit; Pedestal generator 2 mainly contains two functions, and the one, produce comparator 3,4 needed biasing voltage signals, the 2nd, produce the needed comparison signal of two comparators, 3,4 inputs respectively; Comparator the 3, the 4th will be compared by two voltage signals that described pedestal generator produced together through the nonlinear change signal behind the described low pass filter, and returned logical zero or 1; Latch 5 latchs the logical signal of two comparators 3,4 or saltus step then.

Output driver element 6 is that the result with latch 5 strengthens driving, to satisfy the driving force of design.

As shown in Figure 2, it is that this patent uses the CL250 of NEC Electronics Co., Ltd. of Huahong technology, be applied to the simulated effect figure in the phase-locked loop HQCOMPLDHR00V1 circuit, wherein ordinate is respectively input voltage (V_in) and latch voltage (V_lock), and abscissa is time (T).

Can significantly see from figure, after circuit was started working, the loop experience was from tracing into the stabilization process gradually of locking, and control voltage signal (the nonlinear change signal of phase-locked loop circuit just) changes since 0, the rising of irregular band burr slowly is stabilized on a certain fixed value to the end.Whether change this control signal into level signal that non-linear from high to low band burr changes by the present invention, just can detect control signal by this patent and stablize, its result is shown in the LOCK signal.When control signal during in nonlinear change, loop is locking not, so the LOCK signal is " low ", when control signal was stablized at last, the saltus step of LOCK signal was " height ".

Claims

1, a kind of level sensitive circuit that adopts analogy method to realize, it is characterized in that, it comprises low pass filter, pedestal generator, two comparators, latch and output driver element, described low pass filter is with the burr filtering from the nonlinear change signal of phase-locked loop circuit, extract the direct current and the low frequency component of signal, described pedestal generator produces described two needed biasing voltage signals of comparator and two needed comparison signals of comparator input terminal, described comparator is to be compared by two voltage signals that described pedestal generator produced together through the nonlinear change signal behind the described low pass filter, and return logical zero or 1, described latch is that the logical signal with two comparators latchs or saltus step, and described output driver element is that the result with described latch strengthens driving.