CN101841322A - Method for detecting clock signal and device thereof - Google Patents
Method for detecting clock signal and device thereof Download PDFInfo
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- CN101841322A CN101841322A CN200910080390A CN200910080390A CN101841322A CN 101841322 A CN101841322 A CN 101841322A CN 200910080390 A CN200910080390 A CN 200910080390A CN 200910080390 A CN200910080390 A CN 200910080390A CN 101841322 A CN101841322 A CN 101841322A
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Abstract
The embodiment of the invention provides a method for detecting a clock signal and a device thereof. The method comprises the steps of: first, receiving a reference clock signal and a feedback clock signal; and then, detecting whether the reference clock signal is normal according to the feedback clock signal within the preset detection period, and outputting an indication signal showing whether the clock signal is normal, wherein a method for acquiring the feedback clock signal particularly comprises the steps of: detecting the phase difference between the reference clock signal and the feedback clock signal, and obtaining a phase difference signal; transforming the phase difference signal into a first clock signal; and taking the first clock signal as the feedback clock signal of the next detection period. By adopting the technical scheme, a clock device can be judged to be good or not by the output of a self detection clock source, so that the invention can eliminate the clock detection blind spot in a complicated system; and meanwhile, the detection of a clock is not needed to be judged by a logic device, so that logic detection resource can be omitted.
Description
Technical field
The present invention relates to network communication field, relate in particular to a kind of method and device that detects clock signal.
Background technology
At present, on network communication equipment, all must do detection with the raising fault detect rate, and then improve the reliability of system for important clock signal.General detection method be with the signal in clock source through after the clock driver spare, send wherein one the road to logical device; Detect having or not of other clock signal by this logical device by master clock then.Be illustrated in figure 1 as the structural representation of clock driver spare in the prior art, among the figure: the signal that time-base generator produces is after the processing of oversampling clock processing unit and voltage controlled oscillator VCO, sending wherein, one road CLK2 handles in logical device, detect other by this logical device by master clock and send having or not of next clock signal clk 2 to, above-mentioned clock processing unit generally comprises parts such as phase discriminator PD, current pump CP and loop filter LF.
But, no matter there is the how many kinds of clock need do detection on the veneer, always have a clock can't be detected under certain scene according to top this detection clock method, for example the needed master clock of logical device just can't be detected, and this is the weakest link in the present clock detection; In addition, owing to need logical device to do clock detection, so also consumed corresponding logical resource; Because clock signal need be avoided bringing interference to periphery as far as possible, so just give and utilize CAD also to have increased trouble to the wiring between the logical device for the CLK2 of clock source output simultaneously.
Summary of the invention
The embodiment of the invention provides a kind of method and device that detects clock signal, can export the quality of judging clock devices by the detection of self, thereby the clock detection blind spot in the elimination complication system, and saved logic detection resource, improved level of integrated system.
The embodiment of the invention provides a kind of method that detects clock signal, comprising:
Receive reference clock signal and feedback clock signal;
In cycle, whether according to described feedback clock signal, it is normal to detect described reference clock signal in preset detection, and normally whether clock signal index signal;
Wherein, the acquisition methods of described feedback clock signal specifically comprises:
Detect the phase difference of described reference clock signal and feedback clock signal, obtain phase signal;
Described phase signal is converted into first clock signal, with the feedback clock signal of described first clock signal as next sense cycle.
The embodiment of the invention also provides a kind of device that detects clock signal, comprising:
Signal receiving unit is used to receive reference clock signal and feedback clock signal;
Whether normal detecting signal unit was used in preset detection in the cycle, and whether according to described feedback clock signal, it is normal to detect described reference clock signal, and clock signal index signal;
Phase difference detection unit is used to detect the phase difference of described feedback clock signal and described reference clock signal, obtains phase signal;
The feedback clock signal acquiring unit is used for described phase signal is converted into first clock signal, with the feedback clock signal of described first clock signal as next sense cycle.
By the above-mentioned technical scheme that provides as can be seen, at first receive reference clock signal and feedback clock signal; In cycle, whether according to described feedback clock signal, it is normal to detect described reference clock signal in preset detection, and normally whether clock signal index signal; Wherein, the method that described feedback clock signal is obtained specifically comprises: detect the phase difference of described reference clock signal and feedback clock signal, obtain phase signal; Described phase signal is converted into first clock signal, with the feedback clock signal of described first clock signal as next sense cycle.Enforcement by technique scheme just can realize that self detects the quality that the judgement clock devices is exported in the clock source, thereby has eliminated the clock detection blind spot in the complication system; Simultaneously owing to no longer needing logical device to do clock detection, so saved logic detection resource.
Description of drawings
Fig. 1 is the structural representation of clock driver spare in the prior art;
The schematic flow sheet of the embodiment of the invention 1 method that provides is provided Fig. 2;
Fig. 3 is the structural representation of 2 generators of the embodiment of the invention;
Fig. 4 is the structural representation of the embodiment of the invention 2 clock signal automatic detection device in the specific implementation process.
Embodiment
The embodiment of the invention provides a kind of method and device that detects clock signal, clock devices for single-ended clock signal of output or differential clock signal, can by on this clock devices except that the clock signal output pin of reality, a newly-increased again clock signal detects the pin of output automatically, and distinguishes having or not of clock signal by the high-low level on the identification pin.Thereby can export the quality of judging clock devices by the detection of self, eliminate the clock detection blind spot in the complication system, and saved the logical resource that the clock detection function takies, improve level of integrated system.
Embodiment 1: the embodiment of the invention 1 provides a kind of method that detects clock signal, and the schematic flow sheet of present embodiment 1 method that provides is provided, and described method comprises:
Step 21: receive reference clock signal and feedback clock signal.
Here, reference clock signal can obtain in several ways, for instance, can be behind the clock signal of clock source, with the clock signal of this output directly as with reference to clock signal; Obtain reference clock signal REFIN after also the clock signal of this output can being passed through M frequency division or M frequency multiplication.The value of above-mentioned frequency division or frequency parameter M can be set according to the user demand of reality, also can be decided by the intrinsic design of device.
Above-mentioned feedback clock signal can obtain by following mode: detect the phase difference of described reference clock signal and feedback clock signal, obtain phase signal; Again described phase signal is transformed first clock signal, with the feedback clock signal of this first clock signal as next sense cycle.
In addition, in the specific implementation process, the process that phase signal is converted into first clock signal can comprise: the described phase signal of current draw obtains voltage signal; This voltage signal forms the voltage control signal of voltage controlled oscillator VCO after low pass filter filtering; VCO by piezoelectric effect, is converted into the second clock signal with this voltage control signal more then; This second clock signal can be used as first clock signal, with feedback clock signal as next sense cycle, also can will obtain first clock signal behind this second clock signal frequency split, with the feedback clock signal of this first clock signal as next sense cycle.
Above-mentioned feedback clock signal obtains when system's operate as normal, be understandable that, just power in system, promptly when system's initialization, this feedback clock signal is a spacing wave, such as in first sense cycle, can be understood as does not have feedback clock signal at this moment, and just this feedback clock signal is a spacing wave; Then this spacing wave is carried out the phase difference detection operation as initial feedback clock signal and reference clock signal, obtain phase signal; Again this phase signal is converted into the second clock signal; With this second clock signal as first clock signal, and with the feedback clock signal of this first clock signal as next sense cycle (second sense cycle), perhaps above-mentioned second clock signal is carried out behind the frequency division as first clock signal, and with the feedback clock signal of this first clock signal as next sense cycle (second sense cycle); Then, the feedback clock signal of this second sense cycle and reference clock signal carry out the detection of phase difference, and carry out follow-up processing, can obtain the feedback clock signal of the 3rd sense cycle again, so circulation, thus form the reponse system of a closed loop.
Step 22: in the cycle, whether according to feedback clock signal, it is normal to detect reference clock signal in preset detection, and normally whether clock signal index signal.
In this step in 22, the preset detection cycle, be meant according to actual needs continuous K cycle of reference clock signal as a sense cycle, the value of K is decided according to the actual needs, but K is more than or equal to 1.
In cycle, whether normally above-mentioned resulting reference clock signal and feedback clock signal are carried out clock signal detection in preset detection in the clock detection parts, and the whether normal index signal of clock signal.Specifically, in a sense cycle, for example, continuous two cycles of reference clock signal as a sense cycle, with the rising edge of this feedback clock signal this reference clock signal is carried out sample detecting.If detect above-mentioned reference clock signal saltus step is arranged, with regard to the normal index signal of clock signal, such as the output high level, the clock signal of expression clock source output is normal; If it is lasting constant to detect above-mentioned reference clock signal, with regard to the index signal of clock signal fault, such as output low level, the clocking fault of expression clock source output.By the high-low level of identification output, just can learn whether reference clock signal is normal like this, learn just whether the clock signal of clock source output is normal.Be understandable that, also can come the clock signal of telltable clock source output normal, come the clock signal of telltable clock source output to break down with the output high level with output low level.
By the enforcement of above technical scheme, just can export the quality of judging clock devices, thereby eliminate the clock detection blind spot in the complication system by the detection of self; Simultaneously owing to no longer needing logic processing device to do clock detection, so saved the logical resource that the clock detection function takies.
In addition, above-mentioned resulting second clock signal can also be carried out Fractional-N frequency or N frequency multiplication, the clock signal of externally being exported again; The value of this frequency division or frequency parameter N can be set according to the user demand of reality.
Embodiment 2: the embodiment of the invention 2 provides a kind of device that detects clock signal, be illustrated in figure 3 as the structural representation of 2 generators of present embodiment, described device comprises signal receiving unit, detecting signal unit, phase difference detection unit and feedback clock signal acquiring unit, wherein:
Signal receiving unit is used to receive reference clock signal and feedback clock signal.
Detecting signal unit was used in preset detection in the cycle, and whether according to feedback clock signal, it is normal to detect reference clock signal, and clock signal normal index signal whether.Specifically, be exactly in preset detection in the cycle, such as continuous two cycles of reference clock signal as a sense cycle, with the rising edge of this feedback clock signal this reference clock signal is carried out sample detecting; If detect above-mentioned reference clock signal saltus step is arranged, with regard to the normal index signal of clock signal, for example export high level, the clock signal of expression clock source output is normal; If it is lasting constant to detect above-mentioned reference clock signal, with regard to the index signal of clock signal fault, for example output low level is represented the clocking fault that export in the clock source.Just can learn whether fault of reference clock signal by the high-low level of identification signal detecting unit output like this, learn just whether the clock signal of exporting in the clock source is normal.Be understandable that, also can come the clock signal of telltable clock source output normal, come the clock signal of telltable clock source output to break down with the output high level with output low level.
Phase difference detection unit is used to detect the phase difference of feedback clock signal and reference clock signal, obtains phase signal.
The feedback clock signal acquiring unit is used for the resulting phase signal of phase difference detection unit is converted into first clock signal, with the feedback clock signal of this first clock signal as next sense cycle.
In addition, also can comprise frequency unit in the device of the above detection clock signal, this frequency unit is used for the clock signal of receive clock source output, and with the clock signal frequency division that export in this clock source, obtains reference clock signal; Perhaps comprise the frequency multiplication unit, be used for the clock signal of receive clock source output, and, obtain reference clock signal the clock signal frequency multiplication that export in this clock source.
In addition, can comprise current draw module, filter and voltage controlled oscillator in the above-described feedback clock signal acquiring unit, wherein:
Described current draw module is used for the resulting phase signal of described phase difference detection unit is carried out current draw, obtains voltage signal;
Described filter is used for described voltage signal is carried out filtering, obtains voltage control signal;
Described voltage controlled oscillator is used for by piezoelectric effect, and described voltage control signal is converted into described second clock signal, and with described second clock signal as first clock signal, with the feedback clock signal of this first clock signal as next sense cycle.
In addition, also can further comprise frequency division module in this feedback clock signal acquiring unit, behind the second clock signal frequency split that this frequency division module is used for voltage controlled oscillator is exported, obtain described first clock signal, with the feedback clock signal of this first clock signal as next sense cycle.
The foregoing description 2 described devices can integratedly be arranged in clock source or the clock driver spare.This device is integrated when being arranged in clock source or the clock driver spare, can make things convenient for CAD placement-and-routing, reduced interference to peripheral signal, improved the signal quality in the plate.
For instance, be illustrated in figure 4 as the structural representation of clock signal detection device in the embodiment of the invention 2 specific implementation processes, comprise time-base generator among the figure, the frequency plot detection module, current pump CP, loop filter LF and voltage controlled oscillator VCO, wherein: the frequency plot detection module is integrated with detecting signal unit and the phase difference detection unit among the embodiment 2, can obtain reference clock signal REFIN after the clock signal process frequency division of time-base generator output or the frequency multiplication, when equaling 1, the M among Fig. 4 represents, the clock signal that expression produces time-base generator is neither carried out frequency division and is not also carried out frequency multiplication, directly conduct is with reference to clock signal REFIN, when M is during greater than 1 integer, the clock signal that expression produces time-base generator is carried out behind the frequency division as with reference to clock signal REFIN, when M is during less than 1 mark, the clock signal that expression produces time-base generator is carried out after the frequency multiplication as with reference to clock signal REFIN, for example, when M is two/for the moment, the clock signal that expression produces time-base generator is carried out after two frequencys multiplication as with reference to clock signal REFIN.
Then, in the frequency plot detection module, detect the phase difference of this reference clock signal and initial feedback clock signal, obtain phase signal; Again described phase signal is converted into first clock signal, the detailed process of conversion is: after earlier phase signal being carried out current draw through current pump CP, obtain voltage signal; Loop filter LF carries out filtering to this voltage signal then, obtains voltage control signal; This voltage control signal control voltage controlled oscillator VCO produces the second clock signal; With this second clock signal as first clock signal, then can be with the feedback clock signal CLK2 of this first clock signal as next sense cycle, the value of the N among Fig. 4 is 1 o'clock, promptly represents the second clock signal directly as first clock signal; Or this second clock signal carried out frequency division, obtain first clock signal, and then with the feedback clock signal CLK2 of this first clock signal as next sense cycle, the N among Fig. 4 is the integer greater than 1, promptly represent the second clock signal is carried out frequency division, obtain first clock signal.
Then, whether in the cycle, it is normal to detect reference clock signal according to feedback clock signal in the frequency plot detection module in preset detection, and whether clock signal indicates normally; Be exactly in preset detection in the cycle specifically, for example in continuous two cycles of reference clock signal, rising edge with feedback clock signal carries out sample detecting to this reference clock signal, if detect above-mentioned reference clock signal saltus step is arranged, just will export the CLKDET pin and place high level, the clock signal of expression clock source output is normal; If it is lasting constant to detect above-mentioned reference clock signal, just will export the CLKDET pin and place low level, the clocking fault of expression clock source output, the comparative result output among Fig. 4 just is meant the high-low level of CLKDET pin output.Be understandable that, the CLKDET pin is placed low level, the clock signal that is used to refer to the output of clock source is normal, and the CLKDET pin is placed high level, is used to refer to the clocking fault of clock source output.
Among Fig. 4: above-mentioned resultant feedback clock signal CLK2 also can continue to carry out follow-up phase difference detection with reference clock signal in the frequency plot detection module, and continue the feedback clock signal CLK2 that follow-up operation obtains next sense cycle, so circulation, thus a feedback closed loop formed.
It should be noted that, among the said apparatus embodiment, each included unit is just divided according to function logic, but be not limited to above-mentioned division, as long as can realize function corresponding, for example in actual applications, above-mentioned detecting signal unit and phase difference detection unit integrate; In addition, the concrete title of each functional unit also just for the ease of mutual differentiation, is not limited to protection scope of the present invention.
In addition, one of ordinary skill in the art will appreciate that all or part of step that realizes among the said method embodiment is to instruct relevant hardware to finish by program, corresponding program can be stored in a kind of computer-readable recording medium, the above-mentioned storage medium of mentioning can be a read-only memory, disk or CD etc.
In sum, the embodiment of the invention can be exported the quality of judging clock devices by the detection of self, thereby has eliminated the clock detection blind spot in the complication system; Simultaneously owing to no longer needing logic processing device to do clock detection, so saved the logical resource that the clock detection function takies; Integrated being arranged in clock source or the clock driver of clock signal detection device in can the present invention so also made things convenient for CAD placement-and-routing, reduced and crosstalked, and improved the signal quality in the plate.
The above; only be the preferable embodiment of the present invention; but protection scope of the present invention is not limited thereto; anyly be familiar with those skilled in the art in the technical scope that the embodiment of the invention discloses; the variation that can expect easily or replacement all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection range of claim.
Claims (11)
1. a method that detects clock signal is characterized in that,
Receive reference clock signal and feedback clock signal;
In cycle, whether according to described feedback clock signal, it is normal to detect described reference clock signal in preset detection, and normally whether clock signal index signal;
Wherein, the acquisition methods of described feedback clock signal specifically comprises:
Detect the phase difference of described reference clock signal and feedback clock signal, obtain phase signal;
Described phase signal is converted into first clock signal, with the feedback clock signal of described first clock signal as next sense cycle.
2. the method for claim 1 is characterized in that, described feedback clock signal is a spacing wave when initial.
3. the method for claim 1 is characterized in that, before described reception reference clock signal and feedback clock signal, further comprises:
The clock signal of receive clock source output;
With the clock signal of described clock source output as described reference clock signal, perhaps with after the clock signal frequency division of described clock source output or the frequency multiplication as described reference clock signal.
4. method as claimed in claim 3 is characterized in that, described in preset detection in the cycle, whether according to described feedback clock signal, it is normal to detect described reference clock signal, and whether clock signal normal index signal, specifically comprises:
In preset detection in the cycle, this reference clock signal is carried out sample detecting with the rising edge of described feedback clock signal;
If detect described reference clock signal saltus step is arranged, then the normal index signal of clock signal; If it is lasting constant to detect described reference clock signal, then the index signal of clock signal fault.
5. the method for claim 1 is characterized in that, described described phase signal is converted into first clock signal, specifically comprises:
The described phase signal of current draw obtains voltage signal;
Described voltage signal is carried out filtering, obtain voltage control signal;
By piezoelectric effect, described voltage control signal is converted into the second clock signal;
Described second clock signal as described first clock signal, or will be obtained described first clock signal behind the described second clock signal frequency split.
6. method as claimed in claim 5 is characterized in that, described method also comprises:
With described second clock signal frequency split or frequency multiplication, the clock signal of externally being exported.
7. a device that detects clock signal is characterized in that, comprising:
Signal receiving unit is used to receive reference clock signal and feedback clock signal;
Whether normal detecting signal unit was used in preset detection in the cycle, and whether according to described feedback clock signal, it is normal to detect described reference clock signal, and clock signal index signal;
Phase difference detection unit is used to detect the phase difference of described feedback clock signal and described reference clock signal, obtains phase signal;
The feedback clock signal acquiring unit is used for described phase signal is converted into first clock signal, with the feedback clock signal of described first clock signal as next sense cycle.
8. device as claimed in claim 7 is characterized in that, described device further comprises:
Frequency unit is used for the clock signal of receive clock source output, and with the clock signal frequency division that export in described clock source, obtains described reference clock signal;
Perhaps, comprising:
The frequency multiplication unit is used for the clock signal of receive clock source output, and with the clock signal frequency multiplication that export in described clock source, obtains described reference clock signal.
9. device as claimed in claim 7 is characterized in that, described feedback clock signal acquiring unit comprises:
The current draw module is used for the resulting phase signal of described phase difference detection unit is carried out current draw, obtains voltage signal;
Filter is used for described voltage signal is carried out filtering, obtains voltage control signal;
Voltage controlled oscillator is used for by piezoelectric effect, and described voltage control signal is converted into the second clock signal, and with described second clock signal as described first clock signal, with the feedback clock signal of described first clock signal as next sense cycle.
10. device as claimed in claim 7 is characterized in that, described feedback clock signal acquiring unit comprises:
The current draw module is used for the resulting phase signal of described phase difference detection unit is carried out current draw, obtains voltage signal;
Filter is used for described voltage signal is carried out filtering, obtains voltage control signal;
Voltage controlled oscillator is used for by piezoelectric effect, and described voltage control signal is converted into the second clock signal;
Frequency division module is used for described second clock signal frequency split is obtained described first clock signal, with the feedback clock signal of described first clock signal as next sense cycle.
11., it is characterized in that described device is integrated to be arranged in clock source or the clock driver spare as each described device of claim 7 to 10.
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| CN200910080390A CN101841322A (en) | 2009-03-20 | 2009-03-20 | Method for detecting clock signal and device thereof |
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| CN200910080390A CN101841322A (en) | 2009-03-20 | 2009-03-20 | Method for detecting clock signal and device thereof |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103558753A (en) * | 2013-10-30 | 2014-02-05 | 福建星网锐捷网络有限公司 | High-resolution clock detection method and device |
| CN107005098A (en) * | 2017-03-15 | 2017-08-01 | 香港应用科技研究院有限公司 | Wireless power transmitter |
| CN107229009A (en) * | 2016-03-25 | 2017-10-03 | 精工爱普生株式会社 | Circuit arrangement, measuring physical, electronic equipment and moving body |
| CN108931696A (en) * | 2017-05-25 | 2018-12-04 | 许继集团有限公司 | A kind of the B code clock method for detecting abnormality and protective relaying device of intelligent substation |
| CN108958092A (en) * | 2017-05-23 | 2018-12-07 | 青岛海尔洗衣机有限公司 | Clock method for detecting abnormality and device, computer readable storage medium, equipment |
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2009
- 2009-03-20 CN CN200910080390A patent/CN101841322A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103558753A (en) * | 2013-10-30 | 2014-02-05 | 福建星网锐捷网络有限公司 | High-resolution clock detection method and device |
| CN103558753B (en) * | 2013-10-30 | 2016-07-06 | 福建星网锐捷网络有限公司 | A kind of high-resolution clock detection method and device |
| CN107229009A (en) * | 2016-03-25 | 2017-10-03 | 精工爱普生株式会社 | Circuit arrangement, measuring physical, electronic equipment and moving body |
| CN107005098A (en) * | 2017-03-15 | 2017-08-01 | 香港应用科技研究院有限公司 | Wireless power transmitter |
| CN108958092A (en) * | 2017-05-23 | 2018-12-07 | 青岛海尔洗衣机有限公司 | Clock method for detecting abnormality and device, computer readable storage medium, equipment |
| CN108958092B (en) * | 2017-05-23 | 2022-11-04 | 佛山市顺德海尔电器有限公司 | Singlechip clock anomaly detection method and device, computer readable storage medium and equipment |
| CN108931696A (en) * | 2017-05-25 | 2018-12-04 | 许继集团有限公司 | A kind of the B code clock method for detecting abnormality and protective relaying device of intelligent substation |
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Application publication date: 20100922 |