CN100444371C - 功率半导体封装 - Google Patents
功率半导体封装 Download PDFInfo
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- CN100444371C CN100444371C CNB2005800299898A CN200580029989A CN100444371C CN 100444371 C CN100444371 C CN 100444371C CN B2005800299898 A CNB2005800299898 A CN B2005800299898A CN 200580029989 A CN200580029989 A CN 200580029989A CN 100444371 C CN100444371 C CN 100444371C
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Abstract
一种功率半导体封装,包括:具有至少两个功率电极的半导体晶片,以及电气地并且机械地连接到各个功率电极的导电夹。
Description
相关申请
本申请基于2004年9月13日提交的名称为“FINE CONNECT PACKAGINGFOR NEXT GENERATION HIGH-PERFORMANCE POWER DEVICES”的美国临时申请No.60/609,597并且要求其优先权,其公开内容作为引用结合于此。
技术领域
本发明涉及功率半导体封装,以及制造功率半导体封装的工艺。
背景技术
最新一代功率半导体晶片(die)尺寸很小但是功率容量更高。因此,功率半导体封装必须能够与新一代功率半导体设备进行很小的但是低电阻的连接,并且仍然为终端用户提供可用的接出引脚和外部连接性能。
发明内容
根据本发明的功率半导体封装包括:至少具有第一功率电极和第二功率电极的功率半导体晶片,电气地并且机械地连接到所述第一功率电极的第一导电夹,以及电气地并且机械地连接到所述第二功率电极的第二导电夹。
根据本发明一个方面,钝化体封装半导体晶片,优选地至少封装第一和第二导电夹的部分。钝化体是能够保护半导体晶片的绝缘聚合物的薄膜而不需要通过例如塑模(mold)复合物或者任何其他类型封装材料制成的封装。形成钝化体的适当材料是聚硅氧烷基聚合物。
根据本发明另一个方面,半导体晶片的各个电极包括电连接并且机械连接到各个夹子的对应耙指(finger)的多个间隔的功率耙指。
根据本发明的半导体封装最适合用于基于III-氮化物(III-nitridebased)的半导体设备,例如基于InAlGaN的合金(例如GaN,A1GaN)的功率半导体设备,因为这些设备具有很小的物理尺寸但是很高的功率容量,需要低电阻连接。然而,本发明概念同样可以应用到使用传统技术不能连接到外部元件的小型的硅基设备。
本发明的其他特征和优点通过下面的参考附图的详细描述可以更加明白。
附图说明
图1示意显示了本发明一个优选实施例中使用的半导体晶片的顶视平面图;
图2示意显示了根据本发明优选实施例的功率半导体封装的底视平面图;
图3示意显示了图2中的封装从箭头3-3方向看去的侧视平面图;
图4示意显示了图2中的封装从箭头4-4方向看去的侧视平面图;
图5示意显示了图2中的封装沿着直线5-5从箭头方向看去的截面图;
图6示意显示了图2中的封装沿着直线6-6从箭头方向看去的截面图。
具体实施方式
参考图1,在根据本发明的封装中使用的功率半导体晶片10至少包括:半导体衬底(body)9、第一功率电极(源极或者漏极)12、以及第二功率电极(源极或者漏极)14。优选的,功率电极12、14均置于半导体衬底9的相同表面上,并且分别包括多个间隔(spaced)的功率耙指16、18,所述功率耙指被排列为交叉梳状(interdigitated)图案,并且通过公共电源馈线(power feed)20、22互相连接。
在优选实施例中,功率半导体晶片10是双向功率设备,至少包括:第一控制电极(第一栅极)24、第二控制电极(第二栅极)26、第一电流检测电极28、以及第二电流检测电极30。美国专利申请序列号11/056,062公开了双向功率半导体设备的一个示例。根据本发明的封装中的半导体晶片10优选的是通过InAlGaN合金(例如GaN,AlGaN)形成的基于III-氮化物的功率设备。例如,半导体晶片10可以为基于III-氮化物的肖特基设备,或者高电子迁移率晶体管(HEMT),高电子迁移率晶体管(HEMT)例如为金属绝缘半导体异质结场效应晶体管(MISHFET)或者金属氧化物半导体异质结场效应晶体管(MOSHFET)或者任何其他基于III-氮化物的异质结场效应晶体管(HFET)。
根据本发明的封装的半导体晶片10的一个示例为大约1.8mmx3.6mm的尺寸,并且优选的为具有电流检测功能的双向开关设备。为了通过这种半导体晶片实现良好性能,这种半导体晶片的电极应当连接到更大(moresubstantial)的物体。否则,将会累积大量的扩展电阻。并且,由于晶片的尺寸小,用户不能通过传统的表面安装技术而直接连接电极的节距(pitch)。因此,封装必须将电极重新分布为终端用户的传统生产环境中可以处理的尺寸和布局。例如,在功率半导体设备中,具有0.8mm或者更小尺寸的针脚的功率电极很难直接连接到电路板的导电垫(pad),即使接受大幅度的性能损失。而且,在长度仅为3.6mm(或者更小)的晶片中,即使针脚降低至大约0.8mm,合理地也不会超过四个功率电极。根据本发明的封装概念适合于具有针脚为大约0.8mm或者更小的功率电极的功率半导体设备。
根据本发明的封装提供了与晶片的连接,并且通过使用精细几何结构的夹子接合而实现了重新分布。优选实施例中的夹子由相对较薄(0.100mm或者更低数量级)的铜体制成,所述铜体被电镀以保护铜并且提供良好的与焊料相容的表层(finish)。
下面参考图2,根据本发明优选实施例的功率半导体封装30包括半导体晶片10,以及至少包括电气地且机械地连接到第一功率电极的第一导电夹,以及电气地并且机械地连接到第二功率电极的第二导电夹34。各个导电夹优选的包括多个间隔的耙指。因此,第一导电夹包括电气地并且机械地连接到功率耙指16的耙指33,并且第二导电夹34包括电气地并且机械地连接到耙指18的耙指35。耙指33与第一公共连接器31形成整体,并且耙指35与第二公共连接器37形成整体。公共连接器31、37用作外部功率引线(lead)。根据优选实施例的设备可以进一步包括电气地并且机械地连接到各个剩余电极的导电夹。因此,根据本发明的功率半导体封装进一步包括:电气地并且机械地连接到第一控制电极24的第一控制夹36、电气地并且机械地连接到第二控制电极26的第二控制夹38、电气地并且机械地连接到第一电流检测电极28的第一电流检测夹40、以及电气地并且机械地连接到第二电流检测电极30的第二电流检测夹42。
参考图3至图6,根据本发明一个方面,半导体封装30由钝化体44保护,钝化体44至少覆盖半导体晶片10。优选的,夹子32、34、36、38、40、42除了外部连接到电路板的导电垫的部分之外也可以被钝化体44覆盖。钝化体44由能够保护半导体晶片10的材料制成。因此,根据本发明的封装不需要通过例如塑模复合物或者任何其他封装材料制成的封装。
应当注意,夹子32、34、36、38、40、42用作封装30的外部连接器或者引线。因此,各个夹子32、34、36、38、40、42包括配置成用于外部连接到例如基底上的导电垫的部分。如图2至图6所示,各个夹子32、34、36、38、40、42的配置成用于外部连接的部分可以被扩大,可能需要扩展到半导体晶片10的外边界之外。因此,如图2至图6所示,夹子32、34、36、38、40、42从半导体晶片10的外边缘向外具有凸缘。因此,优选为共面的连接表面(配置成用于外部连接的表面)46可以被加宽。由此,原本不能表面安装的微小半导体晶片能够很容易安装到例如电路板的导电垫上。应当注意,连接表面46优选的与半导体晶片10间隔,这样在需要时可以进行安装后焊剂残留物的清除和/或对连接表面46与基底的导电垫的连接进行检验。
在优选实施例中,各个夹子32、34、36、38、40、42通过适当的导电粘合剂48例如焊剂、导电环氧树脂等等而电气地并且机械地连接到半导体晶片10的各个电极。可替换的,可以使用冷焊接以获得所需的电气地和机械地连接。
优选实施例的夹子32、34、36、38、40、42为引线框架的一部份,可以使用适当的方法或者方法的组合而制造以获得具有精细轮廓的金属夹。因此,例如为了制造夹子,引线框架初始地可以被压模,并且引线框架的较大部分可以通过冲孔等方法而被去除。接着,可以使用激光切割、激光磨削(ablation)、蚀刻等等方法获得精细轮廓。可替换地,冲孔步骤可以被激光切割、激光磨削、蚀刻等替代。
一旦制造了引线框架,优选的将其电镀以使其可以焊接。这样,例如可以使用铜制造引线框架并且使用化学镍浸金(ENiG)进行电镀。
为了在引线框架中将夹子32、34、36、38、40、42电气地并且机械地连接到适当的电极,导电粘合剂可以沉积在半导体10的电极上或者引线框架上。导电粘合剂例如焊剂可以以胶体形式而沉积在电极或者引线框架上。可替换地,可以通过将引线框架浸入熔融焊剂而将引线框架进行预焊。在根据本发明的封装中使用的适当焊剂可以为金/锡焊剂,其中包括大约80%(按重量计算)的金和大约20%的锡。
不管使用哪种方法施加焊剂,半导体晶片和引线框架都被置于对方之上并且应用回流焊步骤以将夹子32、34、36、38、40、42连接到适当电极。优选的,可以在适当环境(例如压缩氧、真空、合成气体等等)中使用激光焊接而进行所述回流焊步骤。
一旦半导体晶片和引线框架被焊接到对方,则可以应用清洁步骤(如果需要的话),并且然后对半导体晶片和引线框架的组合体进行钝化。为了钝化所述组合体,优选的将所述组合体浸入至适当钝化材料中,此后钝化体被固化(cure)(如果需要的话)。适当的钝化材料可以为聚合物,例如聚硅氧烷基钝化聚合物。
此后,引线框架可以被孤立化。也就是说,各个夹子可以从引线框架排列切割出来以制造根据本发明的封装。激光切割、激光磨削、蚀刻等等可以作为孤立化的适当方法,因为这些方法能够制造精细轮廓。
尽管根据本发明的封装制造看起来相对复杂并且涉及多个步骤,但是该工艺并不昂贵,因为多数步骤可以在相同的激光设备上进行,这样使得可以通过一台机器执行若干步骤。而且,激光制造相对很快。例如,专门用于这种类型的加工的激光能够在一分钟内切割超过10米的在此描述尺寸的材料。
尽管参考特定实施例描述了本发明,各种其他变化、修改以及其他使用对于本领域技术人员而言是显见的。因此,优选的,本发明并不限于在此公开的特定内容,而是仅由所附权利要求限制。
Claims (24)
1.一种半导体封装,包括:
半导体晶片,至少具有第一功率电极和第二功率电极,每一个功率电极包括多个间隔的功率耙指,所述功率耙指被排列为交叉梳状图案;
包括多个第一耙指的第一导电夹,每一个所述第一耙指电气地并且机械地连接到所述第一功率电极的对应功率耙指;
与所述第一耙指形成整体的第一公共连接器;
包括多个第二耙指的第二导电夹,每一个所述第二耙指电气地并且机械地连接到所述第二功率电极的对应功率耙指;
与所述第二耙指形成整体的第二公共连接器;以及
至少封装所述半导体晶片的钝化体,其中所述第一耙指和所述第二耙指被排列为交叉梳状图案,其中所述第一和第二公共连接器彼此相对排列,并且其中所述钝化体通过能够保护所述半导体晶片的钝化材料形成而不需要其他封装元件。
2.根据权利要求1所述的半导体封装,其中所述半导体晶片由III-氮化物半导体组成。
3.根据权利要求2所述的半导体封装,其中所述III-氮半导体为InAlGaN的合金。
4.根据权利要求1所述的半导体封装,其进一步包括第一控制电极,以及电气地并且机械地连接到所述第一控制电极的第一导电控制电极夹。
5.根据权利要求4所述的半导体封装,其进一步包括电流检测电极,以及电气地并且机械地连接到所述电流检测电极的电流检测夹。
6.根据权利要求1所述的半导体封装,其中所述半导体晶片包括:第一控制电极,电气地并且机械地连接到所述第一控制电极的第一导电控制夹,第二控制电极,以及电气地并且机械地连接到所述第二控制电极的第二导电控制夹。
7.根据权利要求6所述的半导体封装,其进一步包括至少一个电流检测电极,以及电气地并且机械地连接到所述电流检测电极的电流检测夹。
8.根据权利要求1所述的半导体封装,其中所述第一导电夹和第二导电夹通过导电粘合剂电气地并且机械地连接到所述第一功率电极和第二功率电极。
9.根据权利要求8所述的半导体封装,其中所述导电粘合剂由金和锡的合金组成。
10.根据权利要求8所述的半导体封装,其中所述导电粘合剂为焊剂或者导电聚合物。
11.根据权利要求1所述的半导体封装,其中所述钝化体由聚合物组成。
12.根据权利要求11所述的半导体封装,其中所述聚合物包括聚硅氧烷。
13.一种半导体封装,包括:
半导体晶片,至少具有第一功率电极和第二功率电极,各个功率电极包括多个间隔的功率耙指,所述功率耙指被排列为交叉梳状图案,并且所述第一功率耙指连接到第一公共电源馈线,所述第二功率耙指连接到第二公共电源馈线;
电气地并且机械地连接到所述第一公共电源馈线的第一导电夹;
电气地并且机械地连接到所述第二公共电源馈线的第二导电夹;以及
封装所述半导体晶片的钝化体。
14.根据权利要求13所述的半导体封装,其中所述半导体晶片由III-氮化物半导体组成。
15.根据权利要求14所述的半导体封装,其中所述III-氮化物半导体为InAlGaN的合金。
16.根据权利要求13所述的半导体封装,其进一步包括第一控制电极,以及电气地并且机械地连接到所述第一控制电极的第一导电控制夹。
17.根据权利要求16所述的半导体封装,其进一步包括电流检测电极,以及电气地并且机械地连接到所述电流检测电极的电流检测夹。
18.根据权利要求13所述的半导体封装,其中所述半导体晶片包括第一控制电极,电气地并且机械地连接到所述第一控制电极的第一导电控制夹,第二控制电极,以及电气地并且机械地连接到所述第二控制电极的第二导电控制夹。
19.根据权利要求18所述的半导体封装,其进一步包括至少一个电流检测电极,以及电气地并且机械地连接到所述电流检测电极的电流检测夹。
20.根据权利要求13所述的半导体封装,其中所述第一导电夹和第二导电夹通过导电粘合剂电气地并且机械地连接到所述第一功率电极和第二功率电极。
21.根据权利要求20所述的半导体封装,其中所述导电粘合剂为焊剂或者导电聚合物。
22.根据权利要求21所述的半导体封装,其中所述导电粘合剂由金/锡焊剂组成。
23.根据权利要求13所述的半导体封装,其中所述钝化体由聚合物组成。
24.根据权利要求23所述的半导体封装,其中所述聚合物包括聚硅氧烷。
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- 2005-09-13 JP JP2007531463A patent/JP5497985B2/ja active Active
- 2005-09-13 WO PCT/US2005/032743 patent/WO2006031886A2/en active Application Filing
- 2005-09-13 US US11/225,720 patent/US7466012B2/en active Active
- 2005-09-13 CN CNB2005800299898A patent/CN100444371C/zh active Active
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2008
- 2008-09-10 US US12/283,204 patent/US9048196B2/en active Active
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2015
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Patent Citations (5)
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US5393705A (en) * | 1991-12-03 | 1995-02-28 | Nec Corporation | Molded semiconductor device using intermediate lead pattern on film carrier formed from lattice pattern commonly available for devices and process of fabrication thereof |
US6093970A (en) * | 1994-11-22 | 2000-07-25 | Sony Corporation | Semiconductor device and method for manufacturing the same |
US20010042906A1 (en) * | 1997-01-31 | 2001-11-22 | Hisao Nakamura | Semiconductor device and process for producing the same |
US20010033022A1 (en) * | 2000-04-26 | 2001-10-25 | International Rectifier Corp. | Nickel-iron expansion contact for semiconductor die |
US20020011651A1 (en) * | 2000-07-26 | 2002-01-31 | Nec Corporation | Semiconductor device and packaging method thereof |
Also Published As
Publication number | Publication date |
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US20090008804A1 (en) | 2009-01-08 |
JP2008512876A (ja) | 2008-04-24 |
WO2006031886A2 (en) | 2006-03-23 |
US7466012B2 (en) | 2008-12-16 |
CN101015055A (zh) | 2007-08-08 |
US20060131760A1 (en) | 2006-06-22 |
JP5497985B2 (ja) | 2014-05-21 |
US9620471B2 (en) | 2017-04-11 |
US20150262960A1 (en) | 2015-09-17 |
US9048196B2 (en) | 2015-06-02 |
WO2006031886A3 (en) | 2006-06-15 |
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