CN100444371C - 功率半导体封装 - Google Patents

功率半导体封装 Download PDF

Info

Publication number
CN100444371C
CN100444371C CNB2005800299898A CN200580029989A CN100444371C CN 100444371 C CN100444371 C CN 100444371C CN B2005800299898 A CNB2005800299898 A CN B2005800299898A CN 200580029989 A CN200580029989 A CN 200580029989A CN 100444371 C CN100444371 C CN 100444371C
Authority
CN
China
Prior art keywords
electrode
power
semiconductor packages
packages according
electrically
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CNB2005800299898A
Other languages
English (en)
Other versions
CN101015055A (zh
Inventor
M·施坦丁
R·J·克拉克
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon science and technology Americas
Original Assignee
International Rectifier Corp USA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Rectifier Corp USA filed Critical International Rectifier Corp USA
Publication of CN101015055A publication Critical patent/CN101015055A/zh
Application granted granted Critical
Publication of CN100444371C publication Critical patent/CN100444371C/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/33Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/293Organic, e.g. plastic
    • H01L23/296Organo-silicon compounds
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/4824Pads with extended contours, e.g. grid structure, branch structure, finger structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49503Lead-frames or other flat leads characterised by the die pad
    • H01L23/4951Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49541Geometry of the lead-frame
    • H01L23/49562Geometry of the lead-frame for devices being provided for in H01L29/00
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003Nitride compounds
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/201Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725Source or drain electrodes for field effect devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312Gate electrodes for field effect devices
    • H01L29/42316Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0556Disposition
    • H01L2224/05568Disposition the whole external layer protruding from the surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05573Single external layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/29198Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29199Material of the matrix
    • H01L2224/2929Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/29198Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298Fillers
    • H01L2224/29299Base material
    • H01L2224/293Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/2954Coating
    • H01L2224/29599Material
    • H01L2224/296Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29601Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/29611Tin [Sn] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/2954Coating
    • H01L2224/29599Material
    • H01L2224/296Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29638Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29644Gold [Au] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/2954Coating
    • H01L2224/29599Material
    • H01L2224/2969Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81053Bonding environment
    • H01L2224/81054Composition of the atmosphere
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812Applying energy for connecting
    • H01L2224/8121Applying energy for connecting using a reflow oven
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812Applying energy for connecting
    • H01L2224/8122Applying energy for connecting with energy being in the form of electromagnetic radiation
    • H01L2224/81224Applying energy for connecting with energy being in the form of electromagnetic radiation using a laser
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818Bonding techniques
    • H01L2224/81801Soldering or alloying
    • H01L2224/81815Reflow soldering
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • H01L2224/83801Soldering or alloying
    • H01L2224/83815Reflow soldering
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • H01L2224/8384Sintering
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • H01L2224/8385Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83851Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester being an anisotropic conductive adhesive
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00011Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01013Aluminum [Al]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01033Arsenic [As]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01049Indium [In]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01078Platinum [Pt]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01082Lead [Pb]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/0132Binary Alloys
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/014Solder alloys
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06Polymers
    • H01L2924/0715Polysiloxane
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/102Material of the semiconductor or solid state bodies
    • H01L2924/1025Semiconducting materials
    • H01L2924/1026Compound semiconductors
    • H01L2924/1032III-V
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/12Passive devices, e.g. 2 terminal devices
    • H01L2924/1203Rectifying Diode
    • H01L2924/12032Schottky diode
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/12Passive devices, e.g. 2 terminal devices
    • H01L2924/1204Optical Diode
    • H01L2924/12042LASER
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/12Passive devices, e.g. 2 terminal devices
    • H01L2924/1204Optical Diode
    • H01L2924/12044OLED
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1306Field-effect transistor [FET]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1306Field-effect transistor [FET]
    • H01L2924/13062Junction field-effect transistor [JFET]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1306Field-effect transistor [FET]
    • H01L2924/13064High Electron Mobility Transistor [HEMT, HFET [heterostructure FET], MODFET]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1306Field-effect transistor [FET]
    • H01L2924/13091Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • H01L2924/186Material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/30101Resistance

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Led Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Die Bonding (AREA)

Abstract

一种功率半导体封装,包括:具有至少两个功率电极的半导体晶片,以及电气地并且机械地连接到各个功率电极的导电夹。

Description

功率半导体封装
相关申请
本申请基于2004年9月13日提交的名称为“FINE CONNECT PACKAGINGFOR NEXT GENERATION HIGH-PERFORMANCE POWER DEVICES”的美国临时申请No.60/609,597并且要求其优先权,其公开内容作为引用结合于此。
技术领域
本发明涉及功率半导体封装,以及制造功率半导体封装的工艺。
背景技术
最新一代功率半导体晶片(die)尺寸很小但是功率容量更高。因此,功率半导体封装必须能够与新一代功率半导体设备进行很小的但是低电阻的连接,并且仍然为终端用户提供可用的接出引脚和外部连接性能。
发明内容
根据本发明的功率半导体封装包括:至少具有第一功率电极和第二功率电极的功率半导体晶片,电气地并且机械地连接到所述第一功率电极的第一导电夹,以及电气地并且机械地连接到所述第二功率电极的第二导电夹。
根据本发明一个方面,钝化体封装半导体晶片,优选地至少封装第一和第二导电夹的部分。钝化体是能够保护半导体晶片的绝缘聚合物的薄膜而不需要通过例如塑模(mold)复合物或者任何其他类型封装材料制成的封装。形成钝化体的适当材料是聚硅氧烷基聚合物。
根据本发明另一个方面,半导体晶片的各个电极包括电连接并且机械连接到各个夹子的对应耙指(finger)的多个间隔的功率耙指。
根据本发明的半导体封装最适合用于基于III-氮化物(III-nitridebased)的半导体设备,例如基于InAlGaN的合金(例如GaN,A1GaN)的功率半导体设备,因为这些设备具有很小的物理尺寸但是很高的功率容量,需要低电阻连接。然而,本发明概念同样可以应用到使用传统技术不能连接到外部元件的小型的硅基设备。
本发明的其他特征和优点通过下面的参考附图的详细描述可以更加明白。
附图说明
图1示意显示了本发明一个优选实施例中使用的半导体晶片的顶视平面图;
图2示意显示了根据本发明优选实施例的功率半导体封装的底视平面图;
图3示意显示了图2中的封装从箭头3-3方向看去的侧视平面图;
图4示意显示了图2中的封装从箭头4-4方向看去的侧视平面图;
图5示意显示了图2中的封装沿着直线5-5从箭头方向看去的截面图;
图6示意显示了图2中的封装沿着直线6-6从箭头方向看去的截面图。
具体实施方式
参考图1,在根据本发明的封装中使用的功率半导体晶片10至少包括:半导体衬底(body)9、第一功率电极(源极或者漏极)12、以及第二功率电极(源极或者漏极)14。优选的,功率电极12、14均置于半导体衬底9的相同表面上,并且分别包括多个间隔(spaced)的功率耙指16、18,所述功率耙指被排列为交叉梳状(interdigitated)图案,并且通过公共电源馈线(power feed)20、22互相连接。
在优选实施例中,功率半导体晶片10是双向功率设备,至少包括:第一控制电极(第一栅极)24、第二控制电极(第二栅极)26、第一电流检测电极28、以及第二电流检测电极30。美国专利申请序列号11/056,062公开了双向功率半导体设备的一个示例。根据本发明的封装中的半导体晶片10优选的是通过InAlGaN合金(例如GaN,AlGaN)形成的基于III-氮化物的功率设备。例如,半导体晶片10可以为基于III-氮化物的肖特基设备,或者高电子迁移率晶体管(HEMT),高电子迁移率晶体管(HEMT)例如为金属绝缘半导体异质结场效应晶体管(MISHFET)或者金属氧化物半导体异质结场效应晶体管(MOSHFET)或者任何其他基于III-氮化物的异质结场效应晶体管(HFET)。
根据本发明的封装的半导体晶片10的一个示例为大约1.8mmx3.6mm的尺寸,并且优选的为具有电流检测功能的双向开关设备。为了通过这种半导体晶片实现良好性能,这种半导体晶片的电极应当连接到更大(moresubstantial)的物体。否则,将会累积大量的扩展电阻。并且,由于晶片的尺寸小,用户不能通过传统的表面安装技术而直接连接电极的节距(pitch)。因此,封装必须将电极重新分布为终端用户的传统生产环境中可以处理的尺寸和布局。例如,在功率半导体设备中,具有0.8mm或者更小尺寸的针脚的功率电极很难直接连接到电路板的导电垫(pad),即使接受大幅度的性能损失。而且,在长度仅为3.6mm(或者更小)的晶片中,即使针脚降低至大约0.8mm,合理地也不会超过四个功率电极。根据本发明的封装概念适合于具有针脚为大约0.8mm或者更小的功率电极的功率半导体设备。
根据本发明的封装提供了与晶片的连接,并且通过使用精细几何结构的夹子接合而实现了重新分布。优选实施例中的夹子由相对较薄(0.100mm或者更低数量级)的铜体制成,所述铜体被电镀以保护铜并且提供良好的与焊料相容的表层(finish)。
下面参考图2,根据本发明优选实施例的功率半导体封装30包括半导体晶片10,以及至少包括电气地且机械地连接到第一功率电极的第一导电夹,以及电气地并且机械地连接到第二功率电极的第二导电夹34。各个导电夹优选的包括多个间隔的耙指。因此,第一导电夹包括电气地并且机械地连接到功率耙指16的耙指33,并且第二导电夹34包括电气地并且机械地连接到耙指18的耙指35。耙指33与第一公共连接器31形成整体,并且耙指35与第二公共连接器37形成整体。公共连接器31、37用作外部功率引线(lead)。根据优选实施例的设备可以进一步包括电气地并且机械地连接到各个剩余电极的导电夹。因此,根据本发明的功率半导体封装进一步包括:电气地并且机械地连接到第一控制电极24的第一控制夹36、电气地并且机械地连接到第二控制电极26的第二控制夹38、电气地并且机械地连接到第一电流检测电极28的第一电流检测夹40、以及电气地并且机械地连接到第二电流检测电极30的第二电流检测夹42。
参考图3至图6,根据本发明一个方面,半导体封装30由钝化体44保护,钝化体44至少覆盖半导体晶片10。优选的,夹子32、34、36、38、40、42除了外部连接到电路板的导电垫的部分之外也可以被钝化体44覆盖。钝化体44由能够保护半导体晶片10的材料制成。因此,根据本发明的封装不需要通过例如塑模复合物或者任何其他封装材料制成的封装。
应当注意,夹子32、34、36、38、40、42用作封装30的外部连接器或者引线。因此,各个夹子32、34、36、38、40、42包括配置成用于外部连接到例如基底上的导电垫的部分。如图2至图6所示,各个夹子32、34、36、38、40、42的配置成用于外部连接的部分可以被扩大,可能需要扩展到半导体晶片10的外边界之外。因此,如图2至图6所示,夹子32、34、36、38、40、42从半导体晶片10的外边缘向外具有凸缘。因此,优选为共面的连接表面(配置成用于外部连接的表面)46可以被加宽。由此,原本不能表面安装的微小半导体晶片能够很容易安装到例如电路板的导电垫上。应当注意,连接表面46优选的与半导体晶片10间隔,这样在需要时可以进行安装后焊剂残留物的清除和/或对连接表面46与基底的导电垫的连接进行检验。
在优选实施例中,各个夹子32、34、36、38、40、42通过适当的导电粘合剂48例如焊剂、导电环氧树脂等等而电气地并且机械地连接到半导体晶片10的各个电极。可替换的,可以使用冷焊接以获得所需的电气地和机械地连接。
优选实施例的夹子32、34、36、38、40、42为引线框架的一部份,可以使用适当的方法或者方法的组合而制造以获得具有精细轮廓的金属夹。因此,例如为了制造夹子,引线框架初始地可以被压模,并且引线框架的较大部分可以通过冲孔等方法而被去除。接着,可以使用激光切割、激光磨削(ablation)、蚀刻等等方法获得精细轮廓。可替换地,冲孔步骤可以被激光切割、激光磨削、蚀刻等替代。
一旦制造了引线框架,优选的将其电镀以使其可以焊接。这样,例如可以使用铜制造引线框架并且使用化学镍浸金(ENiG)进行电镀。
为了在引线框架中将夹子32、34、36、38、40、42电气地并且机械地连接到适当的电极,导电粘合剂可以沉积在半导体10的电极上或者引线框架上。导电粘合剂例如焊剂可以以胶体形式而沉积在电极或者引线框架上。可替换地,可以通过将引线框架浸入熔融焊剂而将引线框架进行预焊。在根据本发明的封装中使用的适当焊剂可以为金/锡焊剂,其中包括大约80%(按重量计算)的金和大约20%的锡。
不管使用哪种方法施加焊剂,半导体晶片和引线框架都被置于对方之上并且应用回流焊步骤以将夹子32、34、36、38、40、42连接到适当电极。优选的,可以在适当环境(例如压缩氧、真空、合成气体等等)中使用激光焊接而进行所述回流焊步骤。
一旦半导体晶片和引线框架被焊接到对方,则可以应用清洁步骤(如果需要的话),并且然后对半导体晶片和引线框架的组合体进行钝化。为了钝化所述组合体,优选的将所述组合体浸入至适当钝化材料中,此后钝化体被固化(cure)(如果需要的话)。适当的钝化材料可以为聚合物,例如聚硅氧烷基钝化聚合物。
此后,引线框架可以被孤立化。也就是说,各个夹子可以从引线框架排列切割出来以制造根据本发明的封装。激光切割、激光磨削、蚀刻等等可以作为孤立化的适当方法,因为这些方法能够制造精细轮廓。
尽管根据本发明的封装制造看起来相对复杂并且涉及多个步骤,但是该工艺并不昂贵,因为多数步骤可以在相同的激光设备上进行,这样使得可以通过一台机器执行若干步骤。而且,激光制造相对很快。例如,专门用于这种类型的加工的激光能够在一分钟内切割超过10米的在此描述尺寸的材料。
尽管参考特定实施例描述了本发明,各种其他变化、修改以及其他使用对于本领域技术人员而言是显见的。因此,优选的,本发明并不限于在此公开的特定内容,而是仅由所附权利要求限制。

Claims (24)

1.一种半导体封装,包括:
半导体晶片,至少具有第一功率电极和第二功率电极,每一个功率电极包括多个间隔的功率耙指,所述功率耙指被排列为交叉梳状图案;
包括多个第一耙指的第一导电夹,每一个所述第一耙指电气地并且机械地连接到所述第一功率电极的对应功率耙指;
与所述第一耙指形成整体的第一公共连接器;
包括多个第二耙指的第二导电夹,每一个所述第二耙指电气地并且机械地连接到所述第二功率电极的对应功率耙指;
与所述第二耙指形成整体的第二公共连接器;以及
至少封装所述半导体晶片的钝化体,其中所述第一耙指和所述第二耙指被排列为交叉梳状图案,其中所述第一和第二公共连接器彼此相对排列,并且其中所述钝化体通过能够保护所述半导体晶片的钝化材料形成而不需要其他封装元件。
2.根据权利要求1所述的半导体封装,其中所述半导体晶片由III-氮化物半导体组成。
3.根据权利要求2所述的半导体封装,其中所述III-氮半导体为InAlGaN的合金。
4.根据权利要求1所述的半导体封装,其进一步包括第一控制电极,以及电气地并且机械地连接到所述第一控制电极的第一导电控制电极夹。
5.根据权利要求4所述的半导体封装,其进一步包括电流检测电极,以及电气地并且机械地连接到所述电流检测电极的电流检测夹。
6.根据权利要求1所述的半导体封装,其中所述半导体晶片包括:第一控制电极,电气地并且机械地连接到所述第一控制电极的第一导电控制夹,第二控制电极,以及电气地并且机械地连接到所述第二控制电极的第二导电控制夹。
7.根据权利要求6所述的半导体封装,其进一步包括至少一个电流检测电极,以及电气地并且机械地连接到所述电流检测电极的电流检测夹。
8.根据权利要求1所述的半导体封装,其中所述第一导电夹和第二导电夹通过导电粘合剂电气地并且机械地连接到所述第一功率电极和第二功率电极。
9.根据权利要求8所述的半导体封装,其中所述导电粘合剂由金和锡的合金组成。
10.根据权利要求8所述的半导体封装,其中所述导电粘合剂为焊剂或者导电聚合物。
11.根据权利要求1所述的半导体封装,其中所述钝化体由聚合物组成。
12.根据权利要求11所述的半导体封装,其中所述聚合物包括聚硅氧烷。
13.一种半导体封装,包括:
半导体晶片,至少具有第一功率电极和第二功率电极,各个功率电极包括多个间隔的功率耙指,所述功率耙指被排列为交叉梳状图案,并且所述第一功率耙指连接到第一公共电源馈线,所述第二功率耙指连接到第二公共电源馈线;
电气地并且机械地连接到所述第一公共电源馈线的第一导电夹;
电气地并且机械地连接到所述第二公共电源馈线的第二导电夹;以及
封装所述半导体晶片的钝化体。
14.根据权利要求13所述的半导体封装,其中所述半导体晶片由III-氮化物半导体组成。
15.根据权利要求14所述的半导体封装,其中所述III-氮化物半导体为InAlGaN的合金。
16.根据权利要求13所述的半导体封装,其进一步包括第一控制电极,以及电气地并且机械地连接到所述第一控制电极的第一导电控制夹。
17.根据权利要求16所述的半导体封装,其进一步包括电流检测电极,以及电气地并且机械地连接到所述电流检测电极的电流检测夹。
18.根据权利要求13所述的半导体封装,其中所述半导体晶片包括第一控制电极,电气地并且机械地连接到所述第一控制电极的第一导电控制夹,第二控制电极,以及电气地并且机械地连接到所述第二控制电极的第二导电控制夹。
19.根据权利要求18所述的半导体封装,其进一步包括至少一个电流检测电极,以及电气地并且机械地连接到所述电流检测电极的电流检测夹。
20.根据权利要求13所述的半导体封装,其中所述第一导电夹和第二导电夹通过导电粘合剂电气地并且机械地连接到所述第一功率电极和第二功率电极。
21.根据权利要求20所述的半导体封装,其中所述导电粘合剂为焊剂或者导电聚合物。
22.根据权利要求21所述的半导体封装,其中所述导电粘合剂由金/锡焊剂组成。
23.根据权利要求13所述的半导体封装,其中所述钝化体由聚合物组成。
24.根据权利要求23所述的半导体封装,其中所述聚合物包括聚硅氧烷。
CNB2005800299898A 2004-09-13 2005-09-13 功率半导体封装 Active CN100444371C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US60959704P 2004-09-13 2004-09-13
US60/609,597 2004-09-13

Publications (2)

Publication Number Publication Date
CN101015055A CN101015055A (zh) 2007-08-08
CN100444371C true CN100444371C (zh) 2008-12-17

Family

ID=36060673

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB2005800299898A Active CN100444371C (zh) 2004-09-13 2005-09-13 功率半导体封装

Country Status (4)

Country Link
US (3) US7466012B2 (zh)
JP (1) JP5497985B2 (zh)
CN (1) CN100444371C (zh)
WO (1) WO2006031886A2 (zh)

Families Citing this family (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5497985B2 (ja) 2004-09-13 2014-05-21 インターナショナル レクティフィアー コーポレイション 半導体パッケージ
US20060202320A1 (en) * 2005-03-10 2006-09-14 Schaffer Christopher P Power semiconductor package
US7671455B2 (en) * 2005-11-02 2010-03-02 International Rectifier Corporation Semiconductor device package with integrated heat spreader
US20070187288A1 (en) * 2006-02-16 2007-08-16 Haggard Clifton C Disk holding device
US7674666B2 (en) * 2007-02-23 2010-03-09 Sensor Electronic Technology, Inc. Fabrication of semiconductor device having composite contact
US7655962B2 (en) * 2007-02-23 2010-02-02 Sensor Electronic Technology, Inc. Enhancement mode insulated gate heterostructure field-effect transistor with electrically isolated RF-enhanced source contact
US8174099B2 (en) * 2008-08-13 2012-05-08 Atmel Corporation Leadless package with internally extended package leads
US8338871B2 (en) * 2008-12-23 2012-12-25 Sensor Electronic Technology, Inc. Field effect transistor with electric field and space-charge control contact
US8395392B2 (en) * 2008-12-23 2013-03-12 Sensor Electronic Technology, Inc. Parameter extraction using radio frequency signals
JP5468804B2 (ja) * 2009-03-31 2014-04-09 古河電気工業株式会社 半導体チップ、半導体パッケージ、パワーモジュール、及び半導体パッケージの製造方法
US8564110B2 (en) * 2009-10-27 2013-10-22 Alpha & Omega Semiconductor, Inc. Power device with bottom source electrode
US9391005B2 (en) * 2009-10-27 2016-07-12 Alpha And Omega Semiconductor Incorporated Method for packaging a power device with bottom source electrode
DE102011008952A1 (de) * 2011-01-19 2012-07-19 Texas Instruments Deutschland Gmbh Mehrchipmodul, Verfahren zum Betreiben desselben und DC/DC-Wandler
US8586997B2 (en) 2011-02-15 2013-11-19 Sensor Electronic Technology, Inc. Semiconductor device with low-conducting field-controlling element
WO2013036593A1 (en) 2011-09-06 2013-03-14 Sensor Electronic Technology, Inc. Semiconductor device with low-conducting field-controlling element
US9263533B2 (en) 2011-09-19 2016-02-16 Sensor Electronic Technology, Inc. High-voltage normally-off field effect transistor including a channel with a plurality of adjacent sections
US9748362B2 (en) 2011-09-19 2017-08-29 Sensor Electronic Technology, Inc. High-voltage normally-off field effect transistor with channel having multiple adjacent sections
US9673285B2 (en) 2011-11-21 2017-06-06 Sensor Electronic Technology, Inc. Semiconductor device with low-conducting buried and/or surface layers
US8994035B2 (en) 2011-11-21 2015-03-31 Sensor Electronic Technology, Inc. Semiconductor device with low-conducting buried and/or surface layers
US8581660B1 (en) * 2012-04-24 2013-11-12 Texas Instruments Incorporated Power transistor partial current sensing for high precision applications
CN103545268B (zh) * 2012-07-09 2016-04-13 万国半导体股份有限公司 底部源极的功率器件及制备方法
TWI503929B (zh) * 2012-07-09 2015-10-11 萬國半導體股份有限公司 底部源極的功率裝置及製備方法
US9184111B2 (en) * 2013-11-09 2015-11-10 Delta Electronics, Inc. Wafer-level chip scale package
KR102163725B1 (ko) 2013-12-03 2020-10-08 삼성전자주식회사 반도체 소자 및 그 제조방법
KR102153041B1 (ko) 2013-12-04 2020-09-07 삼성전자주식회사 반도체소자 패키지 및 그 제조방법
US10515910B2 (en) 2014-11-07 2019-12-24 Infineon Technologies Ag Semiconductor device having a porous metal layer and an electronic device having the same
US9324819B1 (en) 2014-11-26 2016-04-26 Delta Electronics, Inc. Semiconductor device
TWI604583B (zh) * 2016-10-05 2017-11-01 矽品精密工業股份有限公司 線路結構及疊層組合
US10074597B2 (en) 2017-01-20 2018-09-11 Infineon Technologies Austria Ag Interdigit device on leadframe for evenly distributed current flow
US10692801B2 (en) 2018-05-31 2020-06-23 Infineon Technologies Austria Ag Bond pad and clip configuration for packaged semiconductor device
US11289407B2 (en) * 2020-06-23 2022-03-29 Vanguard International Semiconductor Corporation Package structure
KR20220064662A (ko) * 2020-11-12 2022-05-19 삼성전자주식회사 반도체 소자 패키지 및 그 제조방법
JP2023131475A (ja) 2022-03-09 2023-09-22 株式会社東芝 半導体装置

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5393705A (en) * 1991-12-03 1995-02-28 Nec Corporation Molded semiconductor device using intermediate lead pattern on film carrier formed from lattice pattern commonly available for devices and process of fabrication thereof
US6093970A (en) * 1994-11-22 2000-07-25 Sony Corporation Semiconductor device and method for manufacturing the same
US20010033022A1 (en) * 2000-04-26 2001-10-25 International Rectifier Corp. Nickel-iron expansion contact for semiconductor die
US20010042906A1 (en) * 1997-01-31 2001-11-22 Hisao Nakamura Semiconductor device and process for producing the same
US20020011651A1 (en) * 2000-07-26 2002-01-31 Nec Corporation Semiconductor device and packaging method thereof

Family Cites Families (39)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3878553A (en) * 1972-12-26 1975-04-15 Texas Instruments Inc Interdigitated mesa beam lead diode and series array thereof
JPS55130178A (en) * 1979-03-30 1980-10-08 Fujitsu Ltd Semiconductor device
US4390598A (en) * 1982-04-05 1983-06-28 Fairchild Camera & Instrument Corp. Lead format for tape automated bonding
US4721986A (en) * 1984-02-21 1988-01-26 International Rectifier Corporation Bidirectional output semiconductor field effect transistor and method for its maufacture
US4635092A (en) * 1984-06-04 1987-01-06 General Electric Company Tape automated manufacture of power semiconductor devices
US4755697A (en) * 1985-07-17 1988-07-05 International Rectifier Corporation Bidirectional output semiconductor field effect transistor
GB8519373D0 (en) 1985-08-01 1985-09-04 Unilever Plc Encapsulation of fet transducers
JPS62188275A (ja) 1986-02-13 1987-08-17 Nec Corp 電界効果トランジスタ
JP2698645B2 (ja) * 1988-05-25 1998-01-19 株式会社東芝 Mosfet
FR2691836B1 (fr) * 1992-05-27 1997-04-30 Ela Medical Sa Procede de fabrication d'un dispositif a semi-conducteurs comportant au moins une puce et dispositif correspondant.
JP3350152B2 (ja) * 1993-06-24 2002-11-25 三菱電機株式会社 半導体装置およびその製造方法
US5847436A (en) * 1994-03-18 1998-12-08 Kabushiki Kaisha Tokai Rika Denki Seisakusho Bipolar transistor having integrated thermistor shunt
US5864178A (en) * 1995-01-12 1999-01-26 Kabushiki Kaisha Toshiba Semiconductor device with improved encapsulating resin
DE69723765T2 (de) 1996-05-17 2004-04-15 Eastman Kodak Co. Elektrofotografische Elemente mit bevorzugter Pigmentpartikelgrößenverteilung gewählte Titel weicht ab
JPH1074793A (ja) * 1996-08-30 1998-03-17 Sony Corp 半導体装置と、半導体装置の製造方法と、半導体製造装置
JPH10223901A (ja) * 1996-12-04 1998-08-21 Sony Corp 電界効果型トランジスタおよびその製造方法
US6166436A (en) * 1997-04-16 2000-12-26 Matsushita Electric Industrial Co., Ltd. High frequency semiconductor device
JP4122600B2 (ja) 1998-11-12 2008-07-23 三菱電機株式会社 電解効果トランジスタおよび半導体回路
KR20000057810A (ko) * 1999-01-28 2000-09-25 가나이 쓰토무 반도체 장치
JP3393602B2 (ja) * 2000-01-13 2003-04-07 松下電器産業株式会社 半導体装置
KR100699552B1 (ko) * 2000-02-10 2007-03-26 인터내쇼널 렉티파이어 코포레이션 단일면 상에 돌출 접촉부를 갖는 수직 전도성의 플립칩디바이스
US6777805B2 (en) * 2000-03-31 2004-08-17 Toyoda Gosei Co., Ltd. Group-III nitride compound semiconductor device
JP4055459B2 (ja) 2001-04-24 2008-03-05 日産化学工業株式会社 シリカ系被膜及びその形成方法、並びに、シリカ系被膜を形成するための塗布液及びその製造方法
JP4041660B2 (ja) 2001-05-31 2008-01-30 ユーディナデバイス株式会社 半導体装置及びその製造方法
WO2003015169A1 (fr) * 2001-08-07 2003-02-20 Renesas Technology Corp. Dispositif semi-conducteur et carte ci
US6936855B1 (en) * 2002-01-16 2005-08-30 Shane Harrah Bendable high flux LED array
JP2003258179A (ja) * 2002-02-28 2003-09-12 Sanyo Electric Co Ltd 半導体装置およびその製造方法
JP2003258001A (ja) 2002-03-05 2003-09-12 Murata Mfg Co Ltd 高周波半導体装置
US6853072B2 (en) * 2002-04-17 2005-02-08 Sanyo Electric Co., Ltd. Semiconductor switching circuit device and manufacturing method thereof
US20030218246A1 (en) * 2002-05-22 2003-11-27 Hirofumi Abe Semiconductor device passing large electric current
JP2004039657A (ja) * 2002-06-28 2004-02-05 Renesas Technology Corp 半導体装置
JP4463482B2 (ja) * 2002-07-11 2010-05-19 パナソニック株式会社 Misfet及びその製造方法
JP2004080221A (ja) * 2002-08-13 2004-03-11 Fujitsu Media Device Kk 弾性波デバイス及びその製造方法
TW200427111A (en) * 2003-03-12 2004-12-01 Shinetsu Chemical Co Material for coating/protecting light-emitting semiconductor and the light-emitting semiconductor device
US20050199899A1 (en) * 2004-03-11 2005-09-15 Ming-Der Lin Package array and package unit of flip chip LED
US7475964B2 (en) * 2004-08-06 2009-01-13 Hewlett-Packard Development Company, L.P. Electrical contact encapsulation
JP5497985B2 (ja) * 2004-09-13 2014-05-21 インターナショナル レクティフィアー コーポレイション 半導体パッケージ
US7288803B2 (en) * 2004-10-01 2007-10-30 International Rectifier Corporation III-nitride power semiconductor device with a current sense electrode
US7402845B2 (en) * 2005-12-30 2008-07-22 International Rectifier Corporation Cascoded rectifier package

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5393705A (en) * 1991-12-03 1995-02-28 Nec Corporation Molded semiconductor device using intermediate lead pattern on film carrier formed from lattice pattern commonly available for devices and process of fabrication thereof
US6093970A (en) * 1994-11-22 2000-07-25 Sony Corporation Semiconductor device and method for manufacturing the same
US20010042906A1 (en) * 1997-01-31 2001-11-22 Hisao Nakamura Semiconductor device and process for producing the same
US20010033022A1 (en) * 2000-04-26 2001-10-25 International Rectifier Corp. Nickel-iron expansion contact for semiconductor die
US20020011651A1 (en) * 2000-07-26 2002-01-31 Nec Corporation Semiconductor device and packaging method thereof

Also Published As

Publication number Publication date
US20090008804A1 (en) 2009-01-08
JP2008512876A (ja) 2008-04-24
WO2006031886A2 (en) 2006-03-23
US7466012B2 (en) 2008-12-16
CN101015055A (zh) 2007-08-08
US20060131760A1 (en) 2006-06-22
JP5497985B2 (ja) 2014-05-21
US9620471B2 (en) 2017-04-11
US20150262960A1 (en) 2015-09-17
US9048196B2 (en) 2015-06-02
WO2006031886A3 (en) 2006-06-15

Similar Documents

Publication Publication Date Title
CN100444371C (zh) 功率半导体封装
CN102308383B (zh) 半导体管芯封装件及其制造方法
CN101971332B (zh) 包括嵌入倒装芯片的半导体管芯封装
US7906375B2 (en) Compact co-packaged semiconductor dies with elevation-adaptive interconnection plates
US7443014B2 (en) Electronic module and method of assembling the same
JP2009302564A (ja) 直付リード線を備えるicチップパッケージ
WO2007027790A2 (en) Reversible-multiple footprint package and method of manufacturing
EP3690938B1 (en) Semiconductor device and production method therefor
US5299091A (en) Packaged semiconductor device having heat dissipation/electrical connection bumps and method of manufacturing same
US20130221504A1 (en) Semiconductor module and method of manufacturing a semiconductor module
CN114823597A (zh) 半导体器件封装和制造半导体器件封装的方法
CN109698180A (zh) 半导体器件和制造方法
EP1696484A1 (en) Process for assembling a double-sided circuit component
CN101019226B (zh) 表面贴装的正面接触制备
CN103972199A (zh) 线键合方法和结构
CN104425413A (zh) 半导体装置及其制造和运行方法和制造半导体组件的方法
CN102315135A (zh) 芯片封装及其制作工艺
CN103594388A (zh) 具有侧壁间隔物的接触垫及其制作方法
US10930604B2 (en) Ultra-thin multichip power devices
US10236244B2 (en) Semiconductor device and production method therefor
US20080006937A1 (en) Solderability Improvement Method for Leaded Semiconductor Package
CN111354703A (zh) 一种封装电子元件及其制造方法
US20230027138A1 (en) Power module
CN1207760C (zh) 半导体器件上形成导电覆层的方法
EP3955289A1 (en) Four terminal transistor package

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CP01 Change in the name or title of a patent holder

Address after: American California

Patentee after: Infineon science and technology Americas

Address before: American California

Patentee before: International Rectifier Corporation

CP01 Change in the name or title of a patent holder