CN100440494C - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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Publication number
CN100440494C
CN100440494C CNB2006101079976A CN200610107997A CN100440494C CN 100440494 C CN100440494 C CN 100440494C CN B2006101079976 A CNB2006101079976 A CN B2006101079976A CN 200610107997 A CN200610107997 A CN 200610107997A CN 100440494 C CN100440494 C CN 100440494C
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salient point
semiconductor device
base portion
semiconductor chip
electrode pad
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Expired - Fee Related
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CNB2006101079976A
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CN101017801A (zh
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西村隆雄
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Socionext Inc
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Fujitsu Ltd
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Abstract

提供一种高性能、高可靠性半导体器件及其低成本、高效的制造方法，在该半导体器件中，在用于将半导体芯片安装(例如倒装芯片安装)在衬底上的粘合剂中具有较少气泡。本发明的半导体器件(10)包括：半导体芯片(11)，具有多个电极焊盘(12)；和衬底(14)，在与电极焊盘(12)相对应的位置具有多个电极端子(15)。均由基部(13A)和直径小于基部(13A)的突起部(13B)构成的多个凸点(13)形成在至少所述电极焊盘(12)中的一个电极焊盘上，且在同一个电极焊盘上的各相邻凸点的各基部相互接触，以及在将凸点(13)与电极端子(15)电连接的状态下，用粘合剂(17)将半导体芯片(11)与衬底(14)接合。

Description

半导体器件及其制造方法
技术领域
本发明涉及一种其中用于将半导体芯片安装(例如，倒装芯片安装)在衬底上的粘合剂中具有较少气泡的高性能、高可靠性半导体器件，以及用于制造所述半导体器件的低成本、高效率的方法。
背景技术
因为倒装芯片安装方法可简化制造工艺，从而可实现短时间、低成本的半导体安装，因此常将这种方法用作将半导体芯片安装在衬底上的方法。例如，以下是公知的倒装芯片安装方法：先将粘合剂涂覆到衬底；在半导体芯片的电极焊盘上形成由例如金或铜形成的凸点；将半导体芯片面向下安装在衬底上以使得其凸点面向衬底的相应电极端子；将负载施加于半导体芯片以使得凸点与电极端子电连接；以及固化粘合剂。以这种方式，将半导体芯片连接(安装)在衬底上。
由于使用这种安装方法可容易地形成凸点，所以能够实现薄型(low-profile)半导体器件的低成本制造，在该半导体器件中使用具有相对少量(从几十到几百)电极焊盘的半导体芯片。因此，倒装芯片安装广泛应用于数字家电，例如移动电话、数码相机和闪速存储器。
在倒装芯片安装方法中，凸点被称为“钉头凸点”(stud bumps)，每一钉头凸点由基部以及基部上的突起部构成。通过使用由例如金或铜所构成的金属线而进行的所谓的球焊工艺，金属球通过压焊工艺或使用超声波的压焊工艺固定到半导体芯片的电极焊盘上。注意，基于平坦化的需求，可对基部上的突起部进行平坦化处理。
粘合剂被称为底部填充材料，并充满半导体芯片和衬底之间的间隙。对于所述粘合剂，使用例如由环氧树脂构成的绝缘粘合剂，以及通过将导电颗粒添加到诸如环氧树脂的绝缘树脂中而获得的各向异性导电粘合剂。可通过固化粘合剂将半导体芯片和衬底接合在一起，从而保证半导体芯片的凸点和衬底的电极端子之间的电连接。另外，密封在凸点和电极端子之间的连接以及半导体芯片的电路元件，能够对它们提供保护。粘合剂的填充可以在进行如上所述的倒装芯片安装时通过预先将粘合剂置于半导体芯片和半导体衬底之间来实现，或者可以通过倒装芯片安装方法将凸点与电极端子进行电连接之后，将粘合剂注入在半导体芯片和半导体衬底之间的间隙来实现。
另外，随着近来对于半导体器件尺寸小型化以及更高封装密度的需求，为了减小半导体芯片尺寸或增加半导体芯片的电极焊盘的数量，半导体芯片的电极焊盘的尺寸和电极焊盘间距已经逐渐减小。因此，当电极焊盘的尺寸和电极间距两者均减小时，使用倒装芯片安装方法制造的半导体器件在电极焊盘上也会具有微凸点。
然而，微凸点引起一电连接的接触区域的减少，并且由于在半导体芯片和半导体衬底之间的导热系数差异而引起的在电连接上的应力集中会变得明显。因此，当将半导体芯片倒装芯片安装在衬底上时，在电连接处会发生断裂，即使在此时没有发生断裂，剩余应力也会集中在所述电连接上，导致完成的半导体器件自身的可靠性下降。
为了避免这种问题，提出如下的半导体器件，其中具有在每一电极焊盘上形成的多个钉头凸点的半导体芯片被面向下安装在衬底上，以提高电连接的可靠性(参见日本专利申请公开说明书(JP-A)10-233401、11-307581和2000-286295)。因为可分散施加在一连接处上的应力，所以这种半导体器件提供在连接处的更好的可靠性。
微凸点的形成需要使用较小直径的金属线。然而，随着线直径减小，在球焊工艺中使用的球的直径和将形成的凸点的高度也减小。因此，当在衬底上安装半导体芯片时，在它们之间形成的间隙变小，导致在倒装芯片安装期间或之后在其中注入的粘合剂的流动性下降。因此，由粘合剂流动所产生的气泡没有完全去除到半导体芯片的外部；它们残留在粘合剂中。特别地，因为在粘合剂中与凸点连接接近的位置形成微凹和微凸形状，所以很可能气泡残留在那里，使得非常难以在不包含气泡的情况下将粘合剂填充到间隙中。
例如，当在每一电极上形成多个微钉头凸点时，如在日本专利申请公开说明书10-233401、11-307581和2000-286295中所公开的半导体器件的情况，在邻近的钉头凸点之间的间隔(尤其是钉头凸点的邻近基部之间的间隔)变得很小。因此，在这种半导体器件中，这种问题变得更加明显。当在主板等上通过回流焊来安装半导体器件时，在粘合剂中残留的气泡中的水分会引起爆发从而导致粘合剂的膨胀和/或脱落，在某种情况下引起在凸点连接处的电连续性故障。然而，当在凸点连接的接近位置出现气泡时，气泡中的水分和/或杂质(例如，离子)引起邻接凸点之间的电流泄漏，导致半导体器件特性降低以及在某种情况下导致半导体器件失效。因此，残留在粘合剂中的气泡对半导体器件的可靠性起到负面影响。
需要提供一种高性能、高可靠性半导体器件以及用于制造所述半导体器件的低成本、高效率的方法，其中用于将半导体芯片安装(例如，倒装芯片安装)在衬底上的粘合剂中具有较少气泡。特别是需要开发一种技术，其能够减少具有较窄凸点间距的微凸点的半导体芯片的粘合剂中的气泡。
发明内容
本发明能够解决上述问题，并实现以下所述的目的。具体地，本发明的目的在于提供一种高性能、高可靠性半导体器件以及用于制造所述半导体器件的低成本、高效率的方法，其中用于将半导体芯片安装(例如，倒装芯片安装)在衬底上的粘合剂中具有较少气泡。
以下是用于解决上述问题的技术方案。
本发明的半导体器件包括：半导体芯片，其上设置有多个电极焊盘；和衬底，其在与所述电极焊盘相对应的位置具有多个电极端子，其中，均由基部和突起部构成的多个凸点形成在所述电极焊盘中的至少一个电极焊盘上，且在同一个电极焊盘上的各相邻凸点的各基部相互接触，所述突起部的直径小于所述基部的直径，以及在所述凸点电连接到所述电极端子的状态下，所述半导体芯片利用粘合剂接合到所述衬底。
在所述半导体器件中，在所述多个电极焊盘中的至少一个电极焊盘上形成所述多个凸点，使得能够分散施加在一个凸点连接处的应力，从而防止由于应力集中引起的连接断裂。另外，以各基部相互接触的方式形成所述凸点。因此，当使用粘合剂将半导体芯片安装(例如，倒装芯片安装)在衬底上时，能够减少残留在粘合剂中的气泡，从而防止出现由于粘合剂的膨胀和/或脱落而在电连接处引起的电连续性故障以及由于残留在气泡中的水分和/或杂质(例如，离子)而在相邻凸点之间引起的电流泄漏。因此，本发明的半导体器件具有高性能和高可靠性。
本发明的半导体器件的制造方法包括如下步骤：在半导体芯片上形成的多个电极焊盘的至少一个电极焊盘上形成多个凸点，所述多个凸点中的每个凸点均由基部和突起部构成且所述突起部的直径小于所述基部的直径，且在同一个电极焊盘上的各相邻凸点的各基部相互接触；以面向衬底的方式排列所述半导体芯片，所述衬底在与所述半导体芯片的电极焊盘相对应的位置具有多个电极端子，从而通过使得所述凸点与所述电极端子接触来电连接所述凸点与所述电极端子；以及在所述半导体芯片和所述衬底之间涂覆粘合剂，以将所述半导体芯片接合到所述衬底。
在凸点形成步骤中，以各基部相互接触的方式在半导体芯片的多个电极焊盘的至少一个电极焊盘上形成多个凸点。在凸点连接步骤中，以面向衬底的方式排列半导体芯片，通过使得凸点与电极端子接触来电连接凸点与电极端子。在粘合剂涂覆步骤中，在半导体芯片和衬底之间填充粘合剂。以这种方式将半导体芯片和衬底接合在一起。因此，能够分散施加在一个凸点连接处的应力，并防止由于应力集中引起的连接断裂。另外，当将半导体芯片安装(例如，倒装芯片安装)在衬底上时，在粘合剂和衬底之间的界面的邻近区域减少了残留在粘合剂中的气泡。因此，使用这种方法，能够高效制造高性能、高可靠性的半导体器件。
附图说明
图1是本发明半导体器件第一实施例(实施例1)的垂直剖视图。
图2A是在本发明半导体器件第一实施例(实施例1)中使用的凸点的邻近区域的放大垂直剖视图。
图2B是在本发明半导体器件第一实施例(实施例1)中使用的凸点的邻近区域的放大顶视图。
图3A是在本发明半导体器件第一实施例(实施例1)中使用的凸点的邻近区域修改例的放大垂直剖视图。
图3B是在本发明半导体器件第一实施例(实施例1)中使用的凸点的邻近区域修改例的顶视图。
图4A是在本发明半导体器件第一实施例(实施例1)中使用的凸点的邻近区域另一修改例的放大垂直剖视图。
图4B是在本发明半导体器件第一实施例(实施例1)中使用的凸点的邻近区域另一修改例的顶视图。
图5A是说明本发明第一实施例(实施例1)半导体器件的制造方法中的凸点形成步骤示例的第一剖视图。
图5B是说明本发明第一实施例(实施例1)半导体器件的制造方法中的凸点形成步骤示例的第二剖视图。
图5C是说明本发明第一实施例(实施例1)半导体器件的制造方法中的凸点形成步骤示例的第三剖视图。
图5D是说明本发明第一实施例(实施例1)半导体器件的制造方法中的凸点形成步骤示例的第四剖视图。
图5E是说明本发明第一实施例(实施例1)半导体器件的制造方法中的凸点形成步骤示例的第五剖视图。
图5F是说明本发明第一实施例(实施例1)半导体器件的制造方法中的凸点形成步骤示例的第六剖视图。
图6A是说明本发明第一实施例(实施例1)半导体器件的制造方法中的凸点形成步骤另一示例的第一剖视图。
图6B是说明本发明第一实施例(实施例1)半导体器件的制造方法中的凸点形成步骤另一示例的第二剖视图。
图6C是说明本发明第一实施例(实施例1)半导体器件的制造方法中的凸点形成步骤另一示例的第三剖视图。
图6D是说明本发明第一实施例(实施例1)半导体器件的制造方法中的凸点形成步骤另一示例的第四剖视图。
图6E是说明本发明第一实施例(实施例1)半导体器件的制造方法中的凸点形成步骤另一示例的第五剖视图。
图6F是说明本发明第一实施例(实施例1)半导体器件的制造方法中的凸点形成步骤另一示例的第六剖视图。
图6G是说明本发明第一实施例(实施例1)半导体器件的制造方法中的凸点形成步骤另一示例的第七剖视图。
图6H是说明本发明第一实施例(实施例1)半导体器件的制造方法中的凸点形成步骤另一示例的第八剖视图。
图6I是说明本发明第一实施例(实施例1)半导体器件的制造方法中的凸点形成步骤另一示例的第九剖视图。
图6J是说明本发明第一实施例(实施例1)半导体器件的制造方法中的凸点形成步骤另一示例的第十剖视图。
图6K是说明本发明第一实施例(实施例1)半导体器件的制造方法中的凸点形成步骤另一示例的第十一剖视图。
图6L是说明本发明第一实施例(实施例1)半导体器件的制造方法中的凸点形成步骤另一示例的第十二剖视图。
图7是本发明半导体器件第二实施例(实施例2)的垂直剖视图。
图8A是在本发明半导体器件第二实施例(实施例2)中使用的凸点的邻近区域的放大垂直剖视图。
图8B是在本发明半导体器件第二实施例(实施例2)中使用的凸点的邻近区域的放大顶视图。
图9A是说明本发明第二实施例(实施例2)半导体器件的制造方法中的凸点形成步骤示例的第一剖视图。
图9B是说明本发明第二实施例(实施例2)半导体器件的制造方法中的凸点形成步骤示例的第二剖视图。
图9C是说明本发明第二实施例(实施例2)半导体器件的制造方法中的凸点形成步骤示例的第三剖视图。
图9D是说明本发明第二实施例(实施例2)半导体器件的制造方法中的凸点形成步骤示例的第四剖视图。
图9E是说明本发明第二实施例(实施例2)半导体器件的制造方法中的凸点形成步骤示例的第五剖视图。
图9F是说明本发明第二实施例(实施例2)半导体器件的制造方法中的凸点形成步骤示例的第六剖视图。
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图9H是说明本发明第二实施例(实施例2)半导体器件的制造方法中的凸点形成步骤示例的第八剖视图。
图9I是说明本发明第二实施例(实施例2)半导体器件的制造方法中的凸点形成步骤示例的第九剖视图。
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图9K是说明本发明第二实施例(实施例2)半导体器件的制造方法中的凸点形成步骤示例的第十一剖视图。
图9L是说明本发明第二实施例(实施例2)半导体器件的制造方法中的凸点形成步骤示例的第十二剖视图。
图10是说明凸点形成缺陷的示意图。
图11是本发明半导体器件第三实施例(实施例3)的垂直剖视图。
图12A是在本发明半导体器件第三实施例(实施例3)中使用的凸点的邻近区域的放大垂直剖视图。
图12B是在本发明半导体器件第三实施例(实施例3)中使用的凸点的邻近区域的放大顶视图。
图13A是在本发明半导体器件第三实施例(实施例3)中使用的凸点的邻近区域修改例的垂直剖视图。
图13B是在本发明半导体器件第三实施例(实施例3)中使用的凸点的邻近区域修改例的放大顶视图。
图14A是在本发明半导体器件第三实施例(实施例3)中使用的凸点的邻近区域另一修改例的垂直剖视图。
图14B是在本发明半导体器件第三实施例(实施例3)中使用的凸点的邻近区域另一修改例的放大顶视图。
图14C是在出现凸点形成缺陷之后的凸点邻近区域的放大垂直剖视图。
图14D是出现凸点形成缺陷之后的凸点邻近区域的放大顶视图。
图15A是在本发明半导体器件第四实施例(实施例4)中使用的半导体芯片上形成的电极焊盘布局示例的顶视图。
图15B是在本发明半导体器件第四实施例(实施例4)中使用的半导体芯片上形成的电极焊盘布局另一示例的顶视图。
图15C是在本发明半导体器件第四实施例(实施例4)中使用的半导体芯片上形成的电极焊盘布局又一示例的顶视图。
图15D是在本发明半导体器件第四实施例(实施例4)中使用的半导体芯片上形成的电极焊盘布局再一示例的顶视图。
图16A是说明用于制造半导体器件的本发明方法示例的第一剖视图。
图16B是说明用于制造半导体器件的本发明方法示例的第二剖视图。
图16C是说明用于制造半导体器件的本发明方法示例的第三剖视图。
图16D是说明用于制造半导体器件的本发明方法示例的第四剖视图。
图16E是说明用于制造半导体器件的本发明方法示例的第五剖视图。
图17A是现有技术半导体器件示例中凸点邻近区域的顶视图。
图17B是现有技术半导体器件示例中凸点邻近区域的垂直剖视图。
图17C是说明现有技术半导体器件的实施例中凸点形成缺陷的垂直剖视图。
图18A是说明本发明半导体器件中不产生空隙的机制的示意图。
图18B是说明现有技术半导体器件中产生空隙的机制的示意图。
具体实施方式
以下，将参照实施例来描述本发明的半导体器件及其制造方法，但是这些描述不应理解为对本发明的限制。
实施例1
图1示出本发明的半导体器件的第一实施例，图1是该半导体器件的垂直剖视图。
图1所示的半导体器件10由例如有机材料(诸如玻璃环氧树脂、玻璃BT和聚酰亚胺等)、陶瓷或玻璃构成。在衬底14的表面上形成由例如Cu形成的互连层，并通过使用粘合剂17将半导体芯片11固定到衬底14。
在半导体芯片11上形成多个电极焊盘12，并且在至少一个电极焊盘12上形成多个凸点13。
图2A和图2B分别显示在图1中所示半导体器件10中使用的凸点13邻近区域的放大图及其顶视图。如图2A所示，在电极焊盘12的表面保护层11B的开口中形成两个凸点13，其中所述电极焊盘12形成在诸如硅衬底的半导体衬底11A上。请注意在图2A中没有显示在半导体衬底11A上设置的诸如导电层和绝缘层的其它层。
电极焊盘12的组成材料、形状、结构、尺寸等不受特别限制，并且可根据预期目的来适当确定。组成材料的示例包括Al、Cu以及Al和Cu合金(例如，Al(95％)-Cu(5％)合金)。电极焊盘12的节距(pitch)为例如40μm。电极焊盘12的表面保护层11B的开口尺寸为34×74μm。另外，表面保护层11B的示例包括由SiN/SiO2双层形成的绝缘层。
如图2A和2B所示，每一凸点13由基部13A和突起部13B构成，其中突起部13B设置在基部13A上，并具有小于基部13A直径的直径。两个凸点13形成在电极焊盘12上，它们的各基部13A相互接触。
凸点13的组成材料、形状、结构、尺寸、高度(厚度)等不受特别限制，并且可根据预期目的来适当确定。组成材料的示例包括Au、Al、Cu及其合金。凸点13的尺寸优选为：基部13A的直径是28μm至34μm，突起部13B的直径是18μm至28μm。另外，凸点13的高度(厚度)优选的是：基部13A的高度(厚度)是6μm至10μm，突起部13B的高度(厚度)是20μm至70μm。
只要凸点13的数量为2个或更多，则其数量不受特别限制，并且可根据例如电极焊盘12的尺寸来适当确定。
同时，如图1所示，在衬底14的主(前)表面上与半导体芯片11的电极焊盘12相应的位置形成多个电极端子15，并且在后表面上形成多个焊料球16作为外部端子。例如，在凸点13的突起部13B和电极端子15电连接在一起的状态下，将由环氧树脂等形成的粘合剂17填充到在半导体芯片11和衬底14之间形成的间隙。以这种方式将半导体芯片11和衬底14接合在一起。
粘合剂17不受特别限制，并且可根据预期目的来适当选择；示例包括各向异性导电粘合剂以及由环氧树脂形成的绝缘粘合剂。
因为在电极焊盘12上形成凸点13，并使它们的各基部13A相互接触，所以在本实施例中在凸点13之间不形成间隙，因此当通过使用粘合剂17将半导体芯片11安装(例如，倒装芯片安装)在衬底上时减少了在粘合剂17中的气泡。进而也防止出现由于粘合剂的膨胀和/或脱落而在凸点连接处引起的电连续性故障，以及防止出现由于残留在气泡中的水分和/或杂质(例如，离子)而在邻近凸点之间引起的电流泄漏。因此，本实施例的半导体器件10具有高性能和高可靠性。
以下将说明对实施例1的半导体器件10的凸点13进行的修改。如图3A所示，可将凸点13的突起部13D的顶部压扁，从而其直径大于图2B所示的凸点13的突起部13B的顶部，如图3B所示。另外，如图4A所示，可在电极焊盘12上安装三个凸点13。如图4B所示，可将三个凸点13排列在一排，并使它们的各基部13C连接在一起。请注意，图3A和图4A均显示用在图1所示半导体器件中的凸点13的修改例的放大图，图3B和图4B分别是图3A和图4A的顶视图。
接下来，将参照附图来描述用于形成图2A和图2B所示的凸点13的方法的示例(本方法相当于本发明半导体器件的制造方法中的凸点形成步骤)。
可使用金属线通过球焊工艺来形成凸点13。更具体地，如图5A所示，直径为18μm的金属线19的顶端延伸到焊针18A的外部，通过使用焊炬电极(torch electrode)18B应用高压火花将所述顶端熔化成球形，从而使其形成球部19A。如图5B所示，然后将球部19A与电极焊盘12在表面保护层11B的开口处接触，接着利用焊针18A来对球部19A施加负载和超声波。之后，如图5C所示，垂直升高焊针18A，断开金属线19以形成由基部13A和突起部13B构成的第一凸点13。用相似的处理，如图5D所示，在金属线19的顶端形成另一球部19A，并且如图5E所示，以与第一凸点13的基部13A的周边部分地接触的方式将该另一球部19A放置在电极焊盘12上，接着利用焊针18A来对球部19A施加负载和超声波。之后，如图5F所示，垂直升高焊针18A，断开金属线19以形成由基部13A和突起部13B构成的第二凸点13。以这种方式，可获得按图2A和图2B所示排列的两个凸点13。
应该注意的是，金属线19的直径不受特别限制，并且可根据待形成的凸点的直径来适当确定。
接下来，将参照附图来描述用于形成图3A和图3B所示凸点13的方法的示例(本方法相当于本发明半导体器件的制造方法中的凸点形成步骤)。
如上所述，使用金属线通过球焊工艺来形成凸点13。更具体地，如图6A所示，直径为18μm的金属线19的顶端延伸到焊针18A的外部，通过使用焊炬电极18B应用高压火花将所述顶端熔化成球形，从而使其形成球部19A。如图6B所示，然后，将球部19A与电极焊盘12在表面保护层11B的开口处接触，接着利用焊针18A来对球部19A施加负载和超声波。在如图6C所示垂直升高焊针18A之后，如图6D所示，在与半导体衬底11A的表面水平的方向上移动焊针18A。然后，如图6E所示，通过焊针18A来压扁球部19A的顶部，并再次在与半导体衬底11A的表面水平的方向上移动焊针18A。如图6F所示，垂直升高焊针18A，以断开金属线19，形成由基部13C和突起部13D构成的第一凸点13。使用相似的处理，如图6G所示，在金属线19的顶端形成另一球部19A，并且如图6H所示，以与第一凸点13的基部13C的周边部分地接触的方式将该另一球部19A放置在电极焊盘12上。在如图6I所示垂直升高焊针18A之后，如图6J所示，在与半导体衬底11A的表面水平的方向上移动焊针18A。如图6K所示，然后通过焊针18A来压扁球部19A的顶部，并且如图6L所示，垂直升高焊针18A，以断开金属线19，形成由基部13C和突起部13D构成的第二凸点13。通过以这样的方式压下突起部13D的顶部，能够在形成连接在一起的凸点13时防止第一凸点13的突起部13D与焊针18A接触。
应该注意的是，可以用与用于形成图3A和图3B所示的凸点13所使用的相似的方法来形成图4A和图4B中所示的凸点13。
如上所述，在形成第二凸点13时，可以将金属线19的球部19A以与第一凸点13的基部13A(或13C)接触的方式置于电极焊盘12上。或者，可通过以不与第一凸点13的基部13A(或13C)接触的方式将球部19A置于电极焊盘12上，并通过压下其顶部来使球部19A变形，从而将第一凸点13的基部13A(或13C)与第二凸点13的基部13A(或13C)相互接触。
实施例2
图7中示出本发明的半导体器件的第二实施例，图7是该半导体器件的垂直的剖视图。
图7中所示的半导体器件20与图1中所示的半导体器件10相似，其中在电极焊盘12上形成的两个凸点之一的基部在高度上与另一凸点的基部不同。
图8A和图8B分别显示在图7中所示半导体器件20中使用的凸点13的邻近区域的放大图及其顶视图。如图8A所示，在电极焊盘12的表面保护层11B的开口中形成两个不同的凸点21和22，其中所述电极焊盘12形成在诸如硅衬底的半导体衬底11A上。请注意在图8A中没有显示设置在半导体衬底11A上的诸如导电层和绝缘层的其它层。
如图8A和图8B所示，凸点21由基部21A和突起部21B构成，突起部21B在直径上小于基部21A，并且凸点22由基部22A和突起部22B构成，其中基部22A在高度和直径上大于基部21A，突起部22B在直径上小于基部22A。两个凸点21和22形成在电极焊盘12上，以使各基部21A和22A相互接触。
接下来，将参照附图来描述用于形成图8A和图8B中所示凸点21和22的方法的示例(本方法相当于本发明半导体器件的制造方法中的凸点形成步骤)。
可以使用金属线通过球焊工艺来形成凸点21和22。如图9A所示，直径为18μm的金属线19的顶端延伸到焊针18A的外部，通过使用焊炬电极18B应用高压火花将所述顶端熔化成球形，从而使其形成球部19A。如图9B所示，然后将球部19A与电极焊盘12在表面保护层11B的开口处接触，接着利用焊针18A来对球部19A施加负载和超声波。在如图9C所示垂直升高焊针18A之后，如图9D所示，在与半导体衬底11A的表面水平的方向上移动焊针18A。然后，如图9E所示，通过焊针18A来压扁球部19A的顶部，并再次在与半导体衬底11A的表面水平的方向上移动焊针18A。如图9F所示，垂直升高焊针18A，以断开金属线23，形成由基部21A和突起部21B构成的第一凸点21。随后，如图9G所示，使用直径大于前述金属线的金属线23(其直径为20μm)，在金属线23的顶端形成球部23A，并且如图9H所示，以与第一凸点21的基部21A的周边部分地接触的方式将该球部23A放置在电极焊盘12上。在如图9I所示垂直升高焊针18A之后，如图9J所示，在与半导体衬底11A的表面水平的方向上移动焊针18A。如图9K所示，然后通过焊针18A来压扁球部23A的顶部，并且如图9L所示，垂直升高焊针18A，以断开金属线23，形成由基部22A和突起部22B构成的第二凸点22。以这种方式，可获得按图8A和图8B所示排列的两个不同的凸点21和22。
在如图10所示形成具有相同高度的基部的两个凸点25和26的情况下，当形成第二凸点或凸点26时焊针18A的顶端会与先前形成的凸点25相互妨碍，引起凸点26从电极焊盘12上脱落。与此相对照，在实施例2中，凸点21的基部21A在高度上与凸点22的基部22A不同(在实施例2中，基部22A高于基部21A)。因此，在实施例2中，能够在焊针18A不与先前形成的凸点21相互妨碍的情况下形成凸点22。因此，能够防止凸点21或22从电极焊盘脱落，因此将这些凸点可靠地固定到电极焊盘，从而增加制造产量并提高所制造的半导体器件20的可靠性。
应该注意的是，在形成第二凸点或凸点22时，代替使用上述的不同直径的金属线，还可以通过以下方式使得基部22A高于第一凸点或凸点21的基部21A，即通过在不同于凸点21的焊接条件下来形成凸点22，例如通过使得凸点22的负载或超声波输出与凸点21相比较小。
实施例3
在图11中示出本发明的半导体器件的第三实施例，图11是该半导体器件的垂直的剖视图。
图11中显示的半导体器件30与图1中显示的半导体器件10相似，不同点在于电极焊盘12上形成的两个凸点中每个的基部均是多台阶(stage)的。
图12A和图12B分别显示在图11中所示半导体器件30中使用的凸点的邻近区域的放大图及其顶视图。如图12A所示，在电极焊盘12的表面保护层11B的开口中形成两个凸点31，其中电极焊盘12形成在诸如硅衬底的半导体衬底11A上。请注意在图12A中没有显示设置在半导体衬底11A上的诸如导电层和绝缘层的其它层。
如图12A和图12B所示，每一凸点31由基部31A和突起部31B构成，突起部31B在直径上小于基部31A，基部31A是两台阶的。凸点31以各基部31A相互接触的方式形成。
应该注意的是，尽管本实施例中每个基部31A是两台阶的，但是台阶的数量不受特别限制，并且可根据预期目的来适当确定。
在实施例3中，因为每一凸点31的基部31A是多台阶(在实施例3中为2台阶)的，可以将凸点31的总高度设成足够高，以使得半导体芯片11和衬底14相隔给定距离，从而避免它们相互接触。因此，当为将半导体芯片11安装在衬底14上而将粘合剂17置于半导体芯片11和衬底14之间时，粘合剂17可容易地在半导体芯片11的整个表面上流动，减少与此相关联的如下问题的可能性：例如，在未被粘合剂17充满的间隙中产生空间，或者在粘合剂17中出现空隙。因此，在半导体器件11中可容易地实现微细的电极焊盘12节距。
当采用诸如焊料或导电粘合剂的粘合部件来将凸点31连接到衬底14的电极端子15时，可增加覆盖凸点31的这种粘合部件的占有体积，使得能够更有效地分散施加在凸点连接上的应力集中，并从而进一步增加连接可靠性。
以下将描述对实施例3的半导体器件30的凸点31进行的进一步修改。如图13A所示，可以将凸点31的突起部31D的顶部压扁，从而其直径大于图12B中所示凸点31的突起部31B的直径，如图13B所示。
如图14A所示，优选的是可以如下方式形成两个凸点31，即两台阶基部31A中每个基部的上基部31b的直径小于其下基部31a的直径，并且各基部31a和基部31b分别相互连接。例如，如图14C和14D所示，当每个由基部32A和突起部32B构成的凸点32的基部32A包括相等直径的两台阶时，上基部32b的形成位置偏离下基部32a的形成位置，在某些情况下引起与在相邻电极焊盘上形成的凸点短路的风险。为了避免这种问题，使得上基部31b的直径小于下基部31a的直径，如图14A和14B中所示。利用这种结构，能增加上基部31b的偏离容限(deviation tolerance)，并增加产量。
用于形成凸点31的方法不受特别限制，并且可根据预期目的来适当确定；可适当采用以上使用金属线进行的上述球焊工艺。在形成图14A和14B中所示的凸点31时，可以将用于形成上基部31b的金属线直径设置为小于用于形成下基部31a的金属线直径。或者，形成上基部31b的焊接条件可以与用于下基部31a的条件不同，例如用于形成上基部31b的负载或超声波输出与用于下基部31a的负载或超声波输出相比更小。
实施例4
图15A至图15D中显示本发明半导体器件的第四实施例。这些附图是在其上形成电极焊盘的半导体芯片的顶视图，每个图显示了在其上形成有凸点的电极焊盘的布局的示例。
图15A和图15B均显示具有***两排电极焊盘12的半导体芯片11，图15C显示具有***四排电极焊盘12的半导体芯片11，图15D显示具有中央一排电极焊盘12的半导体芯片11。在每种情况下，在至少位于每一焊盘排的端部位置的电极焊盘12上形成两个凸点，并且它们的基部相互接触，其中所述两个凸点中的每一个均由基部和突起部构成，所述突起部在直径上小于基部。
更具体地，在图15A中，沿着半导体芯片11的两边来排列两个焊盘排40，每个焊盘排包括多个电极焊盘12，并且以各基部13A相互接触的方式在每一电极焊盘12上形成在实施例1中制备的两个凸点13，其中两个凸点13中的每一个均由基部13A和突起部13B构成。相似的，在图15B中，沿着半导体芯片11的两边来排列两个电极排41，其中每个电极排包括多个电极焊盘12，并且以各基部13A相互接触的方式在位于每一焊盘排41两端部的两个电极焊盘12中的每一个上均形成在实施例1中制备的两个凸点13，其中所述两个凸点13中的每一个均由基部13A和突起部13B构成。另一方面，每一焊盘排41的每一其它电极焊盘12(包括焊盘排41的中央)均设置有一个凸点13。
在图15C中，在半导体芯片11的周边排列四个焊盘排42，其每个焊盘排42包括多个电极焊盘12，并且以各基部13A相互接触的方式在位于每个焊盘排42两端的三个电极焊盘12中的每个上形成在实施例1中制备的两个凸点13，其中两个凸点13的每个由基部13A和突起部13B构成。另一方面，每一焊盘排42的每一其它电极焊盘12(包括焊盘排42的中央)设置有一个凸点13。
在图15D中，在中央处沿半导体芯片11排列包括多个电极焊盘12的焊盘排43，并且以各基部13A相互接触的方式在位于焊盘排43两端的四个电极焊盘12中的每个上形成在实施例1中制备的两个凸点13，其中两个凸点13中的每一个均由基部13A和突起部13B构成。另一方面，焊盘排43的每一其它电极焊盘12(包括焊盘排43的中央)均设置有一个凸点13。
应该注意的是，焊盘排的布局以及在每一电极焊盘上形成的凸点的尺寸和数量不限于在图15A至图15D中所示的情况，并且可根据预期目的来适当确定。
当将粘合剂填充在半导体芯片和衬底之间以在衬底上安装半导体芯片时，粘合剂在半导体芯片的整个表面上流动，并将气泡挤出。然而，由于这种气泡易于残留在接近于半导体芯片周边的位置，存在如下问题：很可能在凸点连接处产生气泡，其中所述凸点形成在排列在半导体芯片周边附近的电极焊盘排的端部。而实施例4的半导体器件能够在不在每一电极焊盘上形成多个凸点的情况下局部地防止气泡的产生，从而使得能够以高效率和低成本提供高性能半导体器件。尽管在位于焊盘排端部的凸点连接处的应力集中大于位于焊盘排中央的凸点连接处的应力集中，但是这些多个凸点可分散这种应力集中。因此，能够保证位于焊盘排端部的凸点连接的强度，并增加所制造的半导体器件的可靠性。
实施例5
作为本发明半导体器件的制造方法的示例，将参照附图来描述用于形成图1中所示本发明第一实施例的半导体器件10的方法。
如图16A中所示，首先在半导体芯片11上形成的电极焊盘12上形成凸点13。如在实施例1中所述，如图5A至图5F所示，使用金属线通过球焊工艺来形成凸点13。这是本发明半导体器件制造方法中的凸点形成步骤。
如图16B中所示，预先在衬底14上涂覆粘合剂17。这是本发明方法中的粘合剂涂覆步骤。
如图16B中所示，然后，将衬底14固定于被加热到例如70℃的接合台(未显示)。将半导体芯片11固定于接合工具50，并将半导体芯片11水平移动，以使半导体芯片11与衬底14正确对准。此时，通过预先已经被加热到给定温度(例如215℃)的接合工具50来加热半导体芯片11。接下来，如图16C所示，下移接合工具50，使得凸点13的突起部13B与在衬底14上形成的多个电极端子15接触。进一步下移接合工具50，以将负载施加于半导体芯片11上，使得凸点13的突起部13B变形。保持接合工具50在给定时间段(例如，5至10秒)施加给定应力(例如，78.46mN至196.1mN(8gf至20gf))。此时，粘合剂17在半导体芯片11和衬底14的整个表面上流动，并且通过加热来固化。然而，应该注意的是，在如此短的时间段内不能完全固化粘合剂17。这是本发明方法中的凸点连接步骤。
接下来，如图16D所示，基于对粘合剂17完全固化的需求，优选地将在其上安装有半导体芯片11的衬底14在150℃的恒温槽中放置30分钟。这是本发明方法中的粘合剂固化步骤。
随后，如图16E所示，在衬底14的背面上形成焊料球16。按这样的方式来制造如图1所示的半导体器件10。
尽管在此实施例中是在凸点连接步骤之前进行粘合剂涂覆步骤，也可以在凸点连接步骤之后进行粘合剂涂覆步骤。在这种情况下，可通过将粘合剂17注入在半导体芯片11和衬底14之间形成的间隙中来实现粘合剂17的涂覆。
当在凸点形成步骤之前进行粘合剂涂覆步骤时，在将凸点13连接到电极端子15之前将粘合剂17填充在半导体芯片11和衬底14之间，在将半导体芯片11倒装芯片安装在衬底14上的同时用粘合剂17来填充间隙。因此，能够简化制造处理，并且能够更低成本地制造半导体器件。在这种情况下，与在凸点形成步骤之后进行粘合剂涂覆步骤的情况相比，在邻近凸点13之间更容易发生空隙残留。因此，在这种情况下，本发明的空隙减少效果变得突出。
另外，倒装芯片安装方法不受特别限制，并且可根据预期目的来适当确定；示例包括热压接合、超声波压缩接合和使用粘合部件的接合方法。
如本实施例中所述，热压接合是包括施加热和负载的方法。在使用粘合剂17来将半导体芯片11倒装芯片安装在衬底14上的情况下，其中通过在凸点连接步骤之前进行粘合剂涂覆步骤来将粘合剂1 7***在半导体芯片11和衬底14之间，使用将各向异性导电树脂粘合剂用作粘合剂17的ACF方法、ACP方法或者类似方法来实现热压接合。或者，使用将绝缘树脂粘合剂用作粘合剂17的NCF方法、NCP方法或者类似方法等来实现热压接合。在凸点连接步骤之后进行粘合剂涂覆步骤的情况下，通过使用金属将凸点13与衬底14的电极端子15接合到一起以及通过将粘合剂17注入在半导体芯片11和衬底14之间的间隙来实现热压接合。
超声波压缩接合是包括施加超声波和负载的方法，或者包括施加超声波、负载和热的方法。另外，在此方法中，可以在凸点连接步骤之后或者之前实施粘合剂涂覆步骤。
使用粘合部件的接合方法是包括使用诸如焊料或导电粘合剂的粘合部件的方法。另外，在此方法中，可以在凸点连接步骤之后或之前实施粘合剂涂覆步骤。
现有技术半导体器件的示例
图17A至图17C中显示了现有技术半导体器件中的凸点的布局的示例。
图17A是在半导体芯片110的电极焊盘120上形成的凸点130的布局的顶视图，图17B是图17A的侧视图，图17C是现有技术半导体器件100的垂直剖视图，其中在衬底140上安装半导体芯片110。
如图17A和图17B所示，在多个电极焊盘120的每个电极焊盘上形成两个凸点130。在每一电极焊盘120上的两个凸点130相互分离，从而，在它们之间存在细小的空间。因此，如图17C所示，当在使得衬底140上形成的电极端子150与凸点130接触的情况下使用粘合剂170将半导体芯片110和衬底140接合在一起时，在粘合剂170中的两个凸点130之间形成的空间中产生空隙(或气泡)180。
实施例6
以下，对于在本发明的半导体器件和具有现有技术凸点布局的半导体器件，将对它们的粘合剂中的空隙(气泡)的发生率进行评估。
首先，将参照图18A和图18B来描述空隙产生机制。
图18A是本发明半导体器件(例如，在实施例1中制备的半导体器件)的一部分的凸点布局的顶视图。
如图18A所示，在半导体芯片11上的每一电极焊盘12上形成分别由基部13A和突起部13B构成的两个凸点13，以使各基部13A相互接触。图18B是现有技术凸点布局的示例的顶视图。如图18B所示，在每一电极焊盘12上形成的两凸点相互分离。
当在这种状态下将每一半导体芯片11以倒装芯片方式安装在衬底14上时，粘合剂在邻近电极焊盘12之间流动，如附图中粗箭头所指示——从中心到半导体芯片11的边缘(在图18A和18B中从左至右)。此时，在图18B中所示的现有技术凸点布局中，因为凸点13相互分离，所以在每一电极焊盘12上两凸点13之间形成空间S。当粘合剂在邻近电极焊盘12之间流动时，位于半导体芯片11的中心侧的两个凸点13之一阻挡粘合剂的流动。如图18B中细箭头所指示，粘合剂在空间S中流动。在空间S中的粘合剂的流速降低，使得在空间S中容易产生气泡。这些气泡残存在空间S中而不被挤出到半导体芯片11的边缘，从而导致形成空隙。
相比而言，在如图18A中所示的本发明的凸点布局中，在每一电极焊盘12上形成的两个凸点13的基部13A相互接触，因此在它们之间不形成空间，因此降低粘合剂的流速的可能性减小(即流速降低很小)。因此，如图18A中由细箭头所指示，气泡被挤出到半导体芯片11的边缘的可能性更大，而气泡残存在两个接触凸点13中每一个的受限制部分K处形成的空间中的可能性较小，从而防止空隙的产生。
根据以下所述的过程来确定在粘合剂中的气泡(空隙)的发生率(例如，空隙数量除以电极焊盘总量)。
对固化的粘合剂的横截面(包括凸点基部)进行抛光，以得到平坦表面。使用体视显微镜观察固化的粘合剂抛光后的平坦表面，用以获得在凸点的邻近位置所产生的空隙数量。用这种方式，以电极焊盘的总量除空隙总量的形式来评估空隙的发生率。对于实施例1的半导体器件和使用现有技术凸点布局的半导体器件分别准备了五个样品。应该注意的是，使用在图16A至16D所示的实施例5中说明的制造方法来制造实施例1的半导体器件。在两种不同条件下测量这些样品的空隙发生率。
<样品构成>
(1)对于测量1
以50μm节距安装的板上芯片(COB)
芯片尺寸：6.2mm×6.2mm×200μm
焊盘节距：50μm
表面保护层中的焊盘开口的尺寸：44μm×94μm
电极焊盘的数量：392
衬底：由玻璃BT(B一三氮树脂)构成的双面布线板
粘合剂：膏状的热固绝缘环氧树脂
用于凸点的金线的线直径：20μm
(2)对于测量2
以40μm节距安装的叠层芯片(COC)
芯片尺寸：5mm×3mm×200μm
焊盘节距：40μm
表面保护层中的焊盘开口的尺寸：34μm×74μm
电极焊盘的数量：372
衬底：硅衬底
粘合剂：膏状的热固绝缘环氧树脂
用于凸点的金线的线直径：18μm
<样品的制备>
-钉头凸点的形成-
对于本发明的半导体器件和具有现有技术凸点布局的半导体器件(以下，在某些情况下称为“现有技术半导体器件”)分别制备用于测量1和2的五个样品。即，使用在图5A至5C中所示的形成方法(拉切(pull-cut)方法)在半导体器件样品的每个电极焊盘上形成两个相等尺寸的钉头凸点。此时，在本发明的半导体器件中，两个凸点13以各基部13A相互接触的方式而形成，如图2A、2B和18A所示。另一方面，在现有技术半导体器件中，两个凸点13以各基部13A相互分离的方式而形成，如图18B所示。
-凸点形状-
(1)对于测量1
在本发明的半导体器件和现有技术的半导体器件中，基部的直径是36μm至42μm，基部的厚度是14μm至16μm，凸点的高度是35μm至41μm。
另外，在现有技术半导体器件中，相邻凸点之间的距离(凸点节距)是10μm至20μm。
(2)对于测量2
在本发明的半导体器件和现有技术的半导体器件中，基部的直径是30μm至34μm，基部的厚度是10μm至12μm，凸点的高度是28μm至33μm。
另外，在现有技术半导体器件中，邻近凸点之间的距离(凸点节距)是6μm至14μm。
-倒装芯片方法-
对测量1和2采用粘合剂介质热压接合。更具体地，通过如图16A至16D所示的步骤来制备样品。
表1列出通过以下方程确定的测量1和2中的空隙的发生率：
空隙的发生率(％)＝空隙的数量/电极焊盘的数量
表1
Figure C20061010799700241
表1中所示的结果表明，在本发明的半导体器件中的凸点的邻近位置中存在少量空隙，而在现有技术半导体器件中空隙的发生率较高，从而得出现有技术半导体器件质量较差的结论。
随后，根据以下描述的过程，对于测量1和2的本发明半导体器件和现有技术半导体器件进行吸湿/回流试验，以评估它们的性能。
<吸湿/回流试验>
为了吸湿测试，使得用于测量1和2的本发明的半导体器件和现有技术半导体器件在相对湿度为80％、温度为30℃的环境下保持72小时。其后，使用回流装置，采用250℃峰值温度对它们进行加热处理。进行两次这种吸湿/回流处理。对于这些半导体器件中的每一个分别制备五个样品，并根据以下描述的过程，检查每一样品的外观和内部。另外，还检测每一样品的传导电阻。
-外观检查-
使用20x放大倍率的显微镜，检查每一样品是否出现外观缺陷。-内部检查-
使用C-模式扫描超声波显微镜(C-SAM)，检查每一样品的内部，以确认半导体器件中的粘合剂和半导体芯片之间以及粘合剂和衬底之间的分离(分层)。
-传导电阻检测-
对于传导电阻检测，通过确定以菊链方式(daisy-chained)连接的传导电阻值的变化来评估经由凸点而以菊链方式连接在一起的半导体芯片和衬底的接合可靠性。评估标准如下：显示传导电阻值比原始组装状态增加10％的样品被认为是失效。
作为这些检查和检测的结果，在用于测量1和2的本发明半导体器件和现有技术半导体器件的样品中没有观察到失效。
随后，对于本发明半导体器件和现有技术半导体器件的各五个样品进行可靠性试验，即经受前述的吸湿/回流试验。
<可靠性试验>
作为可靠性试验，对于每一样品进行热循环试验和恒温恒湿试验，随后是外观检查和传导电阻检测。
-热循环试验-
在热循环试验中，将每一样品交替地置于两个不同的环境中——在-55℃的低温环境下放置25分钟，以及在125℃的高温环境下放置25分钟。
-恒温恒湿试验-
在恒温恒湿试验中，使得每一样品保持在温度121℃下和相对湿度85％下。
接下来，对于已经经受热循环试验和恒温恒湿试验的半导体器件样品进行外观检查和传导电阻检测。
-外观检查-
使用20x放大倍率的显微镜，检查每一样品是否出现外部缺陷。
-传导电阻检测-
对于传导电阻检测，通过确定以菊链方式连接的传导电阻值的变化来评估经由凸点而以菊链方式连接在一起的半导体芯片和衬底的接合可靠性。评估标准如下：显示传导电阻值比原始组装状态增加10％的样品被认为是失效。
在热循环试验中，直至以下条件出现才观察到失效：对于测量1的本发明半导体器件的样品中进行了1750次循环；对于测量2的本发明半导体器件的样品中进行了1900次循环；对于测量1的现有技术半导体器件的样品中进行了1600次循环；以及对于测量2的现有技术半导体器件的样品中进行了1750次循环。
另外，在恒温恒湿试验中，直至如下条件出现才观察到失效：对于测量1的本发明半导体器件的样品中持续了672个小时；对于测量2的本发明半导体器件的样品中持续了840个小时；对于测量1的现有技术半导体器件的样品中持续了504个小时；以及对于测量2的现有技术半导体器件的样品中持续了672个小时。
因此，由于现有技术半导体器件会产生空隙，所以在现有技术半导体器件中出现由于粘合剂的膨胀和/或脱落而在凸点连接处引起的电连续性故障以及由于残留在气泡中的水分和/或杂质(例如，离子)而在相邻凸点之间引起的电流泄漏的可能性要高于本发明半导体器件。
根据本发明，能够解决上述现有技术问题，并提供高性能、高可靠性半导体器件以及用于制造所述半导体器件的低成本、高效方法，在所述半导体器件中，在用于将半导体芯片安装(例如，倒装芯片安装)在衬底上的粘合剂中具有较少气泡。
因为在用于将半导体芯片安装(例如，倒装芯片安装)在衬底上的粘合剂中具有较少气泡，所以本发明的半导体器件具有高性能和高可靠性，从而防止出现由于粘合剂的膨胀和/或脱落而在凸点连接处引起的电连续性故障以及由于残留在气泡中的水分和/或杂质(例如，离子)而在相邻凸点之间引起的电流泄漏。
用于形成半导体器件的本发明的方法可实现以高效、低成本来制造高性能、高可靠性的半导体器件，其中，在用于将半导体芯片安装(例如，倒装芯片安装)在衬底上的粘合剂中具有较少气泡。

Claims (13)

1.一种半导体器件，包括
半导体芯片，其上设置有多个电极焊盘；和
衬底，其在与所述电极焊盘相对应的位置具有多个电极端子，
其中，均由基部和突起部构成的多个凸点形成在所述电极焊盘中的至少一个电极焊盘上且在同一个电极焊盘上的各相邻凸点的各基部互相接触，所述突起部的直径小于所述基部的直径，以及
在所述凸点电连接到所述电极端子的状态下，所述半导体芯片利用粘合剂接合到所述衬底。
2.根据权利要求1所述的半导体器件，其中，所述凸点使用金属布线方法中的球焊工艺形成。
3.根据权利要求1所述的半导体器件，其中，所述多个凸点中的至少一个凸点的基部高度与位于该凸点邻近区域的凸点的基部高度不同。
4.根据权利要求1所述的半导体器件，其中，所述凸点中的每一凸点的基部均包括多个台阶。
5.根据权利要求4所述的半导体器件，其中，所述凸点中的每一凸点的基部包括两个台阶。
6.根据权利要求4所述的半导体器件，其中，所述基部的最高台阶的直径小于在所述最高台阶下的台阶的直径。
7.根据权利要求1所述的半导体器件，其中，所述电极焊盘排列成一排以形成焊盘排，和
其中，以各基部相互接触的方式在至少位于所述焊盘排的端部的电极焊盘上形成均由基部和突起部构成且所述突起部的直径小于所述基部的直径的多个凸点。
8.根据权利要求7所述的半导体器件，其中，所述焊盘排的端部位于所述半导体芯片的周边附近。
9.一种半导体器件的制造方法，包括如下步骤：
在半导体芯片上形成的多个电极焊盘的至少一个电极焊盘上形成多个凸点，所述多个凸点中的每个凸点均由基部和突起部构成且所述突起部的直径小于所述基部的直径，且在同一个电极焊盘上的各相邻凸点的各基部相互接触；
以面向衬底的方式排列所述半导体芯片，所述衬底在与所述半导体芯片的电极焊盘相对应的位置具有多个电极端子，从而通过使得所述凸点与所述电极端子接触来电连接所述凸点与所述电极端子；以及
在所述半导体芯片和所述衬底之间涂覆粘合剂，以将所述半导体芯片接合到所述衬底。
10.根据权利要求9所述的半导体器件的制造方法，其中，在所述凸点连接步骤之前进行所述粘合剂涂覆步骤。
11.根据权利要求9所述的半导体器件的制造方法，其中，所述凸点形成步骤采用球焊工艺，该球焊工艺使用金属布线方法。
12.根据权利要求11所述的半导体器件的制造方法，其中，通过如下步骤来形成每一所述凸点：通过球焊工艺在所述电极焊盘上形成基部；在与所述电极焊盘的表面水平的方向上移动焊针；用所述焊针顶端将从所述基部突起的金属线压下以使所述基部变形，从而形成突起部；以及切断所述金属线。
13.根据权利要求9所述的半导体器件的制造方法，还包括以下步骤：在所述半导体芯片和所述衬底之间涂覆所述粘合剂之后固化所述粘合剂。
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US7679188B2 (en) 2010-03-16
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