TWI345293B - Semiconductor package-on-package (pop) device avoiding crack at solder joints of micro-contacts during semiconductor stacking - Google Patents

Semiconductor package-on-package (pop) device avoiding crack at solder joints of micro-contacts during semiconductor stacking Download PDF

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Publication number
TWI345293B
TWI345293B TW096117980A TW96117980A TWI345293B TW I345293 B TWI345293 B TW I345293B TW 096117980 A TW096117980 A TW 096117980A TW 96117980 A TW96117980 A TW 96117980A TW I345293 B TWI345293 B TW I345293B
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Taiwan
Prior art keywords
bumps
semiconductor package
substrate
stacking device
wafer
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Application number
TW096117980A
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Chinese (zh)
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TW200847380A (en
Inventor
Wen Jeng Fan
Li Chih Fang
Iwata Ron
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Powertech Technology Inc
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Priority to TW096117980A priority Critical patent/TWI345293B/en
Publication of TW200847380A publication Critical patent/TW200847380A/en
Application granted granted Critical
Publication of TWI345293B publication Critical patent/TWI345293B/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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  • Wire Bonding (AREA)

Description

1-345293 九、發明說明： 【發明所屬之技術領域】 本發明係有關於將多個半導體封裝件高密度3D堆 疊的架構，特別係有關於一種避免半導體堆疊發生微接 觸辉點斷裂之半導體封裝堆疊裝置 (Package-〇n_Package device, p〇p)。 【先前技術】 當一電路板越來越小時，其表面可供安裝元件的面 積亦縮小。以往可以將多個半導體封裝件並排 (side_by-side)方式直接接合到電路板，在先進的微小化 電子產品將無法達成，故有人提出可以將多個半導體封 裝件縱向3D堆疊以符合小变表面接合面積與高密度元 件設置之要求，即稱之為半導體封裝堆疊裝置 (Package-〇n_package device，POP)。目前在兩個半導體 封裝件之轉接機構是得球或是上下表面皆有銲料之轉 接板’採用銲球除了會有斷裂問題，銲球必須變大可提 供堆疊間隔’故易有銲球橋接與銲料污染的問題，並且 習知間隔銲球無法達到微接觸之型態，導致接腳數與走 線佈線受到限制。採用轉接板，則必須在轉接板中間設 容置開口槽，並且開口槽周邊設有導通孔，元件成本較 高01-345293 IX. Description of the Invention: [Technical Field] The present invention relates to an architecture for high-density 3D stacking of a plurality of semiconductor packages, and more particularly to a semiconductor package for avoiding micro-contact flash breaks in a semiconductor stack Stack-〇n_Package device (p〇p). [Prior Art] When a board becomes smaller and smaller, the area on which the surface can be mounted is also reduced. In the past, a plurality of semiconductor packages can be directly bonded to a circuit board in a side-by-side manner, which cannot be achieved in advanced miniaturized electronic products. It has been proposed that a plurality of semiconductor packages can be vertically stacked in 3D to conform to a small variable surface. The bonding area and the requirement of high-density component setting are called a package-〇n_package device (POP). At present, the adapter mechanism of the two semiconductor packages is a ball or a soldering plate with solder on the upper and lower surfaces. In addition to the problem of cracking in the solder ball, the solder ball must be enlarged to provide a stacking interval. Bridging and solder contamination problems, and the known gap solder balls can not reach the micro-contact type, resulting in limited pin count and routing. When the adapter plate is used, the opening slot must be disposed in the middle of the adapter plate, and the through hole is provided around the opening slot, and the component cost is high.

Fujitsu公司於美國專利第6476503以及Tessera公 司於美國專利公開第2006/0138647號各提出一種可應 用於封裴堆疊之微接觸架構。請參閱第1圖所示，一種 6 1-345293 習知半導體封裝堆疊裝置100主要包含一笛一 乐一半導體 封裝件110、一第二半導體封裝件120以及銲料， 其中該第二半導體封襞件12〇係堆疊在該第—半導體 封裝件110之上’並以銲才斗130連接兩半導體封裝件 110與120〇該第一半導體封裝件11〇係具有—第一美 板111、一設置於該第—基板ηι之一上表面之 第一晶片U2以及複數個形成於該基板之一下表面 111B之凸塊113。利用複數個第一銲線114通過該第一 基板111之一第一槽孔luc,以電性連接該第一晶片 112之銲墊至該第一基板1U，並以一第—封膠體 密封該些第一銲線114。如同第一半導體封裝件ιι〇 一 般，該第二半導體封裝件12〇係具有一第二基板in、 一設置於該第二基板121之一上表面U1A之第二晶片 122以及複數個形成於該基板之一下表面i2ib之凸塊 123，例如銅凸塊或其它不可回銲之柱狀凸塊。複數個 第二銲線124通過.該第二基板ι21之一第二槽孔 121C’而電性連接該第二晶片1：22至該第二基板121， 並以一第二封膠體丨2 5密封該些第二銲線i 2 4。習知在 該第一半導體封裝件110之該第一基板1U之上表面 U1A係設有複數個平墊狀之連接墊U1D,藉由該些銲 料130接合該第二半導體封裝件ι2〇之該些凸塊^至 該第一半導體封裝件110之對應連接墊111D，藉以達 到微接觸之型態，封裝件丨丨〇與丨2 〇堆疊時以該些凸塊 3作為微小化接點，可增加訊號接腳數（high pin count) 1-345293A microcontacting structure that can be applied to a sealed stack is proposed by Fujitsu Corporation in U.S. Patent No. 6,647,503, and to Tessera, U.S. Patent Publication No. 2006/0138647. Referring to FIG. 1 , a 6 1-345293 conventional semiconductor package stacking device 100 mainly includes a flute-one semiconductor package 110, a second semiconductor package 120, and solder, wherein the second semiconductor package 12 堆叠 is stacked on the first semiconductor package 110 ′ and connects the two semiconductor packages 110 and 120 with the soldering hopper 130 . The first semiconductor package 11 has a first slab 111 and a a first wafer U2 on one surface of the first substrate η1 and a plurality of bumps 113 formed on a lower surface 111B of the substrate. Passing a plurality of first bonding wires 114 through the first slot luc of the first substrate 111 to electrically connect the pads of the first wafer 112 to the first substrate 1U, and sealing the first sealing body with a first sealing body Some first bonding wires 114. As with the first semiconductor package, the second semiconductor package 12 has a second substrate in, a second wafer 122 disposed on an upper surface U1A of the second substrate 121, and a plurality of A bump 123 of a lower surface i2ib of the substrate, such as a copper bump or other non-reflowable stud bump. The plurality of second bonding wires 124 are electrically connected to the second wafer 1:22 to the second substrate 121 through a second slot 121C' of the second substrate ι21, and a second sealing body 丨25 The second bonding wires i 2 4 are sealed. It is known that the upper surface U1A of the first substrate 1U of the first semiconductor package 110 is provided with a plurality of flat pad-shaped connection pads U1D, and the solder 130 is bonded to the second semiconductor package ι2 The bumps are connected to the corresponding connection pads 111D of the first semiconductor package 110 to form a micro-contact type, and the bumps 3 are used as micro-contacts when the package 丨丨〇 and 丨 2 〇 are stacked. Increase the number of signal pins (high pin count) 1-345293

並可增加走線面積，更可以縮小封裝堆疊間隙（small POP stacking Standoff) »由於銲接的接合形狀與面積的 不匹配’銲料130於回銲後對於該些凸塊123之輝接強 度以及對於該些連接墊111D之焊接強度兩者不相同。 特別是’該銲料130在該些連接墊U1D之焊接表面為 平面狀’對於剪向應力（即第一基板ηι熱脹冷縮產生 之熱應力）的抵抗力較弱β此外，習知該些連接塾11工d 之表面係電鑛有鎳金層，金層會炫入銲料130内產生金 跪效應，烊接界面的強度將變得更薄弱。因此，當習知 半導體封裝堆疊裝置100在高速運算下或處於散熱不 良之％*兄，容易在該些連接墊1UD與銲料13〇接觸界 面，或是凸塊123之表面產生微接觸銲點斷裂。 【發明内容】 發 本發明之主要目的係在於提供一種避免半導體堆疊 生微接觸銲點斷裂之半導體封裝堆叠裝置，能均勻化The wiring area can be increased, and the small POP stacking standoff can be reduced. ● The solder joint strength and the area mismatch are the soldering strength of the solder 130 after the solder reflow, and The soldering strength of some of the connection pads 111D is different. In particular, 'the solder 130 is planar in the soldering surface of the connection pads U1D'. The resistance to the shear stress (ie, the thermal stress generated by the thermal expansion and contraction of the first substrate ηι) is weaker. Further, it is known that The surface of the 塾11 worker d has a nickel-gold layer, and the gold layer will sneak into the solder 130 to produce a gold 跪 effect, and the strength of the splicing interface will become weaker. Therefore, when the conventional semiconductor package stacking device 100 is under high-speed operation or in the case of poor heat dissipation, it is easy to cause micro-contact solder joint breakage at the interface between the connection pads 1UD and the solder 13 , or the surface of the bump 123. . SUMMARY OF THE INVENTION The main object of the present invention is to provide a semiconductor package stacking device that avoids semiconductor chip micro-contact solder joint breakage and can be homogenized.

知料接13形狀與面積，违至丨丨僻备车道 ^運到避免牛導體堆疊發生微接觸 銲點斷裂之功效。 本發明之次一目的係在於提供一種避免半導體堆璧 發生微接觸銲點斷 』_點斷裂之丰導體封裝堆疊裝置，能兼具准 政熱性與微問隔維持之功效。 本發明％目的卩解決其技術問題是採用以下技術；5 八實見的依據本發明，一種半導體封裝堆疊裝置主 要包含-第—半導體封裝件、一第二半導體封裝件以及 複數個銲料。兮绝_ + & 〃 丰導體封裝件係包含一第一基板 8 1-34.5293 一第一晶片以及複數個上層凸塊，其中該些上層凸塊 該第一晶片係設置於該第一基板之一上表面。該第二 導體封裝件係包含一第二基板、一第二晶片以及複數 下層凸塊，其中該些下層凸塊係設置於該第二基板之 下表面，該第二晶片係設置於該第二基板之一上表面 該些銲料係接合該些上層凸塊與該些下層凸塊。其中 該第二半導體封裝件係疊設在該第一半導體封裝件 上，並使該些下層凸塊對準於該些上層凸塊，以利均 焊接。 本發明的目的及解決其技術問題還可採用以下技 措施進一步實現。 在前述的半導體封裝堆疊裝置中，該第一半導體 裝件可更包含複數個第二下層凸塊，該些第二下層凸 係設置於該第一基板之一下表面。 在前述的半導體封裝堆疊裝置中，可另包含第二 料，其係包覆該些第二下層凸塊。 在前述的半導體封裝堆疊裝置中，該第二半導體 裝件可更包含複數個第二上層凸塊，該些第二上層凸 係設置於該第二基板之一上表面。 在前述的半導體封裝堆疊裝置中，該第一半導體 裝件可更包含複數個第一銲線，該第一基板係具有一 一槽孔，該些第一銲線係通過該第一槽孔而電性連接 第一晶另與該第一基板。 在前述的半導體封裝堆疊裝置中，該第一半導體 與 半 個 之 勻 術 封 塊 銲 封 塊 封 第 該 封 9 1-34,5293 骏件可更包含一第一封膠體，其係形成於該第一槽孔， 以密封該些第一銲線。 在前述的半導體封裝堆疊裝置中，該第一封膠體係 可不覆蓋該第一晶片。 在前述的半導體封裝堆疊裝置中，該第二半導體封 裝件係可實質相同於該第一半導體封裝件，而包含有複 數個第二鮮線與一第二封膠體。 在前述的半導體封裝堆疊裝置中，該些下層凸塊與 該些上層凸塊係可具有相同尺寸與外形。 、 在前述的半導體封料疊裝置中，該些下層凸塊與 該些上層凸塊係可具有半錐形戴面。 遠些下層凸塊與 在前述的半導體封裝堆疊裝置中 該些上層凸塊係可為鋼柱。 該第二半導體套 在前述的半導體封裝堆疊裝置中 裝件係彳纟有複數個i置凸塊，其係設於該第二基板戈 下表面，並位於該第一半導體封裝件之該第一晶片』 方’以供散熱。 在前述的半導體封裝堆疊裝置中，該些虛置凸塊令 可接觸該第一晶片之背面。 在前述的半導體封裝堆疊裝置中，該些銲料係可具琴 η形輝·接截面。 【實施方式】 依據本發明之第一具趙實施例，揭示一種避免半導 隹且發生微接觸銲點斷裂之半導體封裝堆疊裝置。 134.5293 請參閱第2圖所示，一種半導體封裝堆疊裝置200 主要包含一第一半導體封裝件21〇、一第二半導體封裝 件2 2 0以及複數個銲料2 3 〇。 該第一半導體封裝件210係主要包含一第一基板 211、一第一晶片212以及複數個第一上層凸塊213’ 其中該些第一上層凸塊213與該第一晶片212係設置於 該第一基板211之一上表面211A。該第一基板211係 為雙面導通之電路板，如印刷電路板。該第一晶片212 之主動面係朝向該第一基板2 1 1，以黏晶膠、膠帶或覆 晶凸塊接合在該第一基板211之上表面211Α»在本實 施例中’該第一基扳2 1 1係具有一第一槽孔2 1 1 C，其 係貫穿該第一基板211之上表面211A與下表面211B。 而該第一半導體封裝件210可更包含複數個第一銲線 2丄5，該些第一銲線2 1 5係以打線方式形成，通過該第 〆槽孔211C而電性連接該第一晶片212之複數個第一 在單勢212A與該第一基板211。 該第一半導體封裝件 210可更包含一第一封膠體 2 i 6，以壓模或點膠方式，使其係形成於該第一槽孔 2llC，以密封該些第一銲線215。該第一封膠體216係 寸不覆蓋該第一晶片2 1 2，以使該第一晶片2 1 2之背面 為顯露，有利於散熱與封裝薄化。 該第二半導體封裝件220係包含一第二基板221、 /第二晶片222以及複數個第一下層凸塊223，其中該 止b第一下層凸塊223係設置於該第二基板221之一下表Knowing the shape and area of the 13, it is against the secluded lane. It is transported to avoid the micro-contact solder joint breakage effect of the cattle conductor stack. A second object of the present invention is to provide a conductor package stacking device which avoids the micro-contact solder joint breakage of the semiconductor stack, and which can maintain the heat of quasi-positive heat and micro-interval. SUMMARY OF THE INVENTION The object of the present invention is to solve the technical problem by employing the following technique; 5 According to the present invention, a semiconductor package stacking device mainly comprises a - - a semiconductor package, a second semiconductor package and a plurality of solders.兮 _ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + An upper surface. The second conductor package includes a second substrate, a second wafer, and a plurality of lower bumps, wherein the lower bumps are disposed on a lower surface of the second substrate, and the second wafer is disposed on the second The solder on one of the upper surfaces of the substrate bonds the upper bumps and the lower bumps. The second semiconductor package is stacked on the first semiconductor package, and the lower bumps are aligned with the upper bumps for uniform soldering. The object of the present invention and solving the technical problems thereof can be further achieved by the following technical measures. In the foregoing semiconductor package stacking device, the first semiconductor package may further include a plurality of second lower bumps, and the second lower bumps are disposed on a lower surface of the first substrate. In the foregoing semiconductor package stacking device, a second material may be further included which covers the second lower bumps. In the foregoing semiconductor package stacking device, the second semiconductor package may further include a plurality of second upper bumps, and the second upper bumps are disposed on an upper surface of the second substrate. In the foregoing semiconductor package stacking device, the first semiconductor package may further include a plurality of first bonding wires, the first substrate has a slot, and the first bonding wires pass through the first slot. The first crystal is electrically connected to the first substrate. In the foregoing semiconductor package stacking device, the first semiconductor and the half of the uniform seal sealing block seal the first seal 9 1-34, 5293 may further comprise a first sealant, which is formed in the a first slot to seal the first bonding wires. In the aforementioned semiconductor package stacking device, the first encapsulating system may not cover the first wafer. In the foregoing semiconductor package stacking device, the second semiconductor package may be substantially identical to the first semiconductor package and include a plurality of second fresh lines and a second seal. In the foregoing semiconductor package stacking device, the lower bumps and the upper bumps may have the same size and shape. In the foregoing semiconductor package stacking device, the lower layer bumps and the upper layer bumps may have a semi-conical surface. The far lower bumps and the above-described semiconductor package stacking device may be steel pillars. The second semiconductor sleeve is mounted on the semiconductor package stacking device with a plurality of i-shaped bumps disposed on the lower surface of the second substrate and located at the first portion of the first semiconductor package The wafer is 'square' for heat dissipation. In the aforementioned semiconductor package stacking device, the dummy bumps are made to contact the back surface of the first wafer. In the foregoing semiconductor package stacking device, the solder systems may have a n-shaped junction. [Embodiment] According to a first embodiment of the present invention, a semiconductor package stacking device that avoids semi-conducting defects and breaks micro-contact solder joints is disclosed. 134.5293 Referring to FIG. 2, a semiconductor package stacking device 200 mainly includes a first semiconductor package 21A, a second semiconductor package 2200, and a plurality of solders 2 3 〇. The first semiconductor package 210 includes a first substrate 211, a first wafer 212, and a plurality of first upper bumps 213'. The first upper bumps 213 and the first wafers 212 are disposed on the first substrate 212. One of the upper surfaces 211A of the first substrate 211. The first substrate 211 is a circuit board that is double-sided conductive, such as a printed circuit board. The active surface of the first wafer 212 faces the first substrate 21, and is bonded to the upper surface 211 of the first substrate 211 by a die bond, a tape or a flip chip. In this embodiment, the first The base plate 2 1 1 has a first slot 2 1 1 C which extends through the upper surface 211A and the lower surface 211B of the first substrate 211. The first semiconductor package 210 may further include a plurality of first bonding wires 2丄5, wherein the first bonding wires 2 15 are formed by wire bonding, and the first bonding holes 211C are electrically connected to the first A plurality of first wafers 212 are in a single potential 212A and the first substrate 211. The first semiconductor package 210 may further include a first encapsulant 2 i 6 formed in the first slot 2llC by compression molding or dispensing to seal the first bonding wires 215. The first encapsulant 216 is not covered by the first wafer 2 1 2 so that the back surface of the first wafer 2 1 2 is exposed, which is advantageous for heat dissipation and thinning of the package. The second semiconductor package 220 includes a second substrate 221, a second wafer 222, and a plurality of first lower bumps 223. The first lower bumps 223 are disposed on the second substrate 221. One of the following

S 11 134,5293 面221B’該第二晶片222係設置於該第二基板221之 —上表面22 1.A。 較佳地’該第二半導體封裝件220係可實質相同於 δ玄第一半導體封裝件21〇，而包含有複數個第二銲線 225與一第二封膠體226。該些第二銲線225係通過該 第二槽孔22 1C而電性連接該第二晶片222之複數個第 二銲墊222Α與該第二基板22卜並被該第二封膠體226 所密封。在本實施例中，該第一半導體封裝件2 1 0町更 包含複數個第二下層凸塊214，該些第二下層凸塊214 係設置於該第一基板211之一下表面211Β。該第二爭 導體封裝件220可更包含複數個第二上層凸塊224，該 此第二上層凸塊224係設置於該第二基板22 1之一上表 面 221Α。 該些銲料2 3 0係接合該些第一上層凸塊2 1 3與該些 第〆下層凸塊223。其中，該第二半導體封裝件220係 聲設在該第一半導體封裝件210之上，並使該些第〆下 廣凸塊223對準於該些第一上層凸塊213，以利均勻焊 接.通常該些銲料230係可為無鉛銲劑，以錫96.5%-銀銅0.5°/。之銲料而言，在到達回銲溫度約攝氏217 度以上，最高溫約為攝氏245度時能產生焊接之濕潤 性，然而該些第—上層凸塊213與該些第一下層凸塊 2 2 3則必須具有南於上述回銲溫度之溶點。 如第3圖所示，該些第一下層凸塊22 3與該些第〆 上廣凸塊213係可具有相同尺寸與外形，例如該些第 12 1345293 下層凸塊223與該些第一上層凸塊213係可具有半錐形 截面，如半圓錐體或梯形體，亦可為打線形成之結線凸 塊°該些第一下層凸塊223與該些第一上層凸塊213係 可為銅柱或其它不需要回銲之凸塊。該些第一下層凸塊 223與該些第—上層凸塊213係具有微接觸之型態。以 習知雙倍資料傳輸速率第二代（DDR2)之動態隨機存取 s己憶體所使用之窗口型球格陣列封裝構造（wBGA)為 例’習知封裝構造之錫球直徑約為〇 45mm，可接合錫 球之基板互連接墊開口約為0 · 3 5 mm至〇.4mm之間，在 表面黏著（SMT)完成之間隔高度（standoff height)約為 0.3 mm左右。相對地’本發明之第一下層凸塊223與第 一上層凸塊213的高度約可介於0.08爪爪至0.15 mm之 間’凸塊頂端表面在0.06mm以上，凸塊底部尺寸在 左右，該第一半導體封裝件21〇與該第二半導 體封裝件220兩者堆疊結合後間隔高度約為〇.275mm。 因此，本發明可供接合凸塊之基板互連接墊之間距可更 加縮小，以符合高密度多端子數的要求。 π再如第3圖所示，該些銲料23〇將具有H形焊接截面， :得上下焊接的強度為一致且對於剪向應力的抵抗力較 換言之，該些第-上層凸塊213與該些第—下層凸塊⑵ 另可達到具有相同的銲料接人你 # 了寸丧D形狀與面積。是故，能均勻 化鲜料接合形狀與面積，達到 避免牛導體堆疊發生微接 觸銲點斷裂之功效，進而提異 疋叩奴昇了兩面堆疊之上板可靠度 (board level reliability) 〇S 11 134, 5293 surface 221B' is disposed on the upper surface 22 1.A of the second substrate 221. Preferably, the second semiconductor package 220 is substantially the same as the δ first semiconductor package 21 〇, and includes a plurality of second bonding wires 225 and a second sealing body 226. The second bonding wires 225 are electrically connected to the second plurality of pads 222 and the second substrate 22 of the second wafer 222 through the second slot 22 1C and are sealed by the second sealing body 226. . In this embodiment, the first semiconductor package 2101 includes a plurality of second lower bumps 214, and the second lower bumps 214 are disposed on a lower surface 211 of the first substrate 211. The second contiguous conductor package 220 can further include a plurality of second upper bumps 224 disposed on one of the surfaces 221 of the second substrate 22 1 . The solders 230 are bonded to the first upper bumps 2 1 3 and the second lower bumps 223. The second semiconductor package 220 is disposed on the first semiconductor package 210, and the second lower bumps 223 are aligned with the first upper bumps 213 for uniform soldering. Usually, the solder 230 can be a lead-free solder with a tin content of 96.5% - silver copper 0.5 ° /. For the solder, the wettability of the solder can be generated when the reflow temperature is about 217 degrees Celsius or higher, and the highest temperature is about 245 degrees Celsius. However, the first-upper bumps 213 and the first lower bumps 2 2 3 must have a melting point south of the above reflow temperature. As shown in FIG. 3, the first lower bumps 22 3 and the second upper bumps 213 may have the same size and shape, for example, the 12th 1345293 lower bumps 223 and the first The upper bump 213 may have a semi-conical section, such as a semi-conical or trapezoidal body, or may be a wire-forming bump formed by the wire. The first lower bump 223 and the first upper bump 213 may be It is a copper post or other bump that does not require reflow. The first lower bumps 223 and the first upper bumps 213 have a microcontact type. The window type ball grid array package structure (wBGA) used in the second generation (DDR2) dynamic random access s memory of the double data rate is known as a conventional package. The diameter of the solder ball is about 〇. The 45mm, bondable solder ball substrate interconnect pad opening is between 0. 3 5 mm and 〇.4 mm, and the standoff height at the surface adhesion (SMT) is about 0.3 mm. In contrast, the height of the first lower bump 223 and the first upper bump 213 of the present invention may be between about 0.08 claws and 0.15 mm. The surface of the bump top is 0.06 mm or more, and the bottom of the bump is about the left and right. The first semiconductor package 21 〇 and the second semiconductor package 220 are stacked and combined with a height of about 275 mm. Therefore, the distance between the substrate interconnection pads of the bonding bumps of the present invention can be further reduced to meet the requirements of high-density multi-terminal numbers. π, as shown in FIG. 3, the solders 23〇 will have an H-shaped soldering cross section, and the strength of the upper and lower soldering is uniform and the resistance to the shear stress is inferior, in other words, the first-upper bumps 213 and the Some of the first-lower bumps (2) can also be reached with the same solder to connect you to the shape and area. Therefore, it is possible to homogenize the shape and area of the fresh material joints, so as to avoid the micro-contact solder joint breakage of the cattle conductor stack, and then raise the board level reliability.

S 13 1-345293 如第4圖所示，該半導體封裝堆疊裝置_可另 含第二銲料240,其係包覆該些第二下層凸塊21〇 .半導體封裝堆疊裝置2〇〇係藉由該些第二鲜料24〇對 ' 接合至一外部電路板10。而在該半導體封裝堆疊裝 -200之上方可再任意堆疊適當數量之該第二半導體封 • 件220 ’達到記憶體容量或是功能的擴充β 依據本發明之第二具體實施例，揭示另一種半導 封裝堆疊裝置’請參閱第5圖所示，該半導體封裝堆 φ 裝置3〇〇主要包含一第一半導體封裝件310、一第二 導體封裝件320以及複數個第一銲料330。該第一半 體封裝件310係包含一第一基板311、一第一晶片3 以及複數個上層凸塊313’其中該些上層凸塊313與 • 第一晶片312係設置於該第—基板3 ! J之一上表 3 1 1 A。在本實施例中，該第一晶片3丨2設置於該第一 板3 1 1之方式係為覆晶接合。 該第二半導體封裝件320係包含一第二基板321 _ 一第二晶片322以及複數個下層凸塊323，其中該些 層凸塊323係設置於該第二基板321之一下表 3HB，該第二晶片322係設置於該第二基板321之一 表面321 A。 該些第一銲料330係接合該些上層凸塊313與該 下層凸塊3 23。其中’該第二半導體封裝件3 20係疊 在該第一半導體封裝件310之上，並使該些下層凸 323對準於該些上層凸塊313，以利均勻焊接。而較 包 該 外 置 裝 體 疊 半 導 12 該 面 基 下 面 上 些 設 塊 隹 14 1-34.5293 地’該些上層凸塊313與該些下層凸塊3 23之鐸料接合 形狀係為開口擴大的U形。 該第一半導體封裝件310可更包含複數個下層凸塊 314，該些下層凸塊314係設置於該第一基板311之一 下表面311B。該半導體封裝堆疊裝置3〇〇可另包含第 二銲料340，其係包覆該些下層凸塊314。 較佳地，該第二半導體封裝件32〇係可具有複數個 虛置凸塊324 ’其係設於該第二基板321之下表面 321B，並位於該第一半導體封裝件31〇之該第一晶片 312上方，以供散熱。該些虛置凸塊324係可接觸該第 一晶片312之背面，故該些虛置凸塊324除了能增進散 熱性’兼具有微間隔維持之功效。 以上所述，僅是本發明的較佳實施例而已並非對 本發明作任何形式上的限制，本發明技術方案範圍當依 所附申請專利範圍為準。任何熟悉本專業的技術人員可 利用上述揭示的技術内容作出些許更動或修飾為等同 變化的等效實施例，但凡是未脫離本發明技術方案的内 容，依據本發明的技術實質對以上實施例所作的任何簡 單修改 '等同變化與修飾，均仍屬於本發明技術方案二 範圍内。 、的 【圖式簡單說明】 第1圖：一種習知半導體封裝堆疊裝置之截面示意圖。 第2圖：依據本發明之第一具體實施例，一種半導體封 裝堆疊裝置之截面示意圖。 15 1-345293 第3圖··依據本發明之第一具體實施例，該半導體封裝 .堆疊裝置中第一半導體封裝件與第二半導體 封裝件在銲料接合處之局部截面示意圖。 第4圖：依據本發明之第一具體實施例，可由複數個半 導體封裝件組成之半導體封裝堆疊裝置接合 至一外部電路板之載面示意圖。 第5圖：依據本發明之第二具體實施例，另一種半導體 封裝堆疊裝置之截面示意圖。 【主要元件符號說明】 10 電路板 100半導體封裝堆疊裝置 110第一半導體封裝件 111 第一 基板 111A上表面 111B 下表面 111C 第- -槽孔 1 11D連接墊 112第一晶片 113 凸塊 114 第一 銲線 11 5第一封膠體 120第二半導體 封裝件 121 第二 基板 121A上表面 121B 下表面 121C :第二槽孔 122第二晶片 123 凸塊 124 第二 銲線 125第二封膠體 130銲料 200半導體封裝堆疊裝置 210第一半導體封裝件 211第一基板 211A上表面 211B下表面 211C第一槽孔 16 134.5293S 13 1-345293, as shown in FIG. 4, the semiconductor package stacking device may further include a second solder 240 covering the second lower bumps 21. The semiconductor package stacking device 2 is The second fresh materials 24' are joined to an external circuit board 10. Further, an appropriate number of the second semiconductor package 220' can be stacked on top of the semiconductor package stack-200 to achieve memory capacity or function expansion. According to the second embodiment of the present invention, another The semiconductor package stack φ device 3 〇〇 mainly includes a first semiconductor package 310, a second conductor package 320, and a plurality of first solders 330. The first semiconductor package 310 includes a first substrate 311, a first wafer 3, and a plurality of upper bumps 313'. The upper bumps 313 and the first wafer 312 are disposed on the first substrate 3. One of J is shown in Table 3 1 1 A. In this embodiment, the first wafer 3丨2 is disposed on the first plate 3 1 1 in a flip chip bonding manner. The second semiconductor package 320 includes a second substrate 321 _ a second wafer 322 and a plurality of lower bumps 323 , wherein the plurality of bumps 323 are disposed on one of the second substrates 321 , 3HB The two wafers 322 are disposed on one surface 321 A of the second substrate 321 . The first solders 330 are bonded to the upper bumps 313 and the lower bumps 323. The second semiconductor package 306 is stacked on the first semiconductor package 310, and the lower bumps 323 are aligned with the upper bumps 313 for uniform soldering. And the outer package body of the semiconductor package 12 is provided on the lower surface of the substrate 隹14 1-34.5293. The material of the upper layer bumps 313 and the lower layer bumps 3 23 are open-ended. U shape. The first semiconductor package 310 may further include a plurality of lower bumps 314 disposed on a lower surface 311B of the first substrate 311. The semiconductor package stacking device 3 can further include a second solder 340 that coats the lower bumps 314. Preferably, the second semiconductor package 32 can have a plurality of dummy bumps 324 ′′ disposed on the lower surface 321B of the second substrate 321 and located in the first semiconductor package 31 Above a wafer 312 for heat dissipation. The dummy bumps 324 can contact the back surface of the first wafer 312, so that the dummy bumps 324 can improve the heat dissipation and have the effect of maintaining the micro-interval. The above is only a preferred embodiment of the present invention and is not intended to limit the scope of the present invention. The scope of the present invention is defined by the scope of the appended claims. Any person skilled in the art can make some modifications or modifications to the equivalent embodiments by using the technical content disclosed above, but the content of the technical solution of the present invention is made according to the technical essence of the present invention without departing from the technical solution of the present invention. Any simple modification 'equivalent change and modification' is still within the scope of the second embodiment of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic cross-sectional view showing a conventional semiconductor package stacking device. Figure 2 is a cross-sectional view showing a semiconductor package stacking apparatus in accordance with a first embodiment of the present invention. 15 1-345293 FIG. 3 is a partial cross-sectional view of the first semiconductor package and the second semiconductor package at the solder joint in the semiconductor package according to the first embodiment of the present invention. Fig. 4 is a schematic view showing the mounting of a semiconductor package stacking device composed of a plurality of semiconductor packages to an external circuit board in accordance with a first embodiment of the present invention. Fig. 5 is a cross-sectional view showing another semiconductor package stacking apparatus in accordance with a second embodiment of the present invention. [Major component symbol description] 10 circuit board 100 semiconductor package stacking device 110 first semiconductor package 111 first substrate 111A upper surface 111B lower surface 111C first - slot 1 1 11D connection pad 112 first wafer 113 bump 114 first Bonding wire 11 5 first encapsulant 120 second semiconductor package 121 second substrate 121A upper surface 121B lower surface 121C: second slot 122 second wafer 123 bump 124 second bonding wire 125 second encapsulant 130 solder 200 Semiconductor package stacking device 210 first semiconductor package 211 first substrate 211A upper surface 211B lower surface 211C first slot 16 134.5293

212第一晶片 212A第一銲墊 214第二下層凸塊215第一銲線 220第二半導體封裝件 221A上表面 221B下表面 222第二晶片 222A第二銲墊 224第二上層凸塊225第二銲線 230銲料 240第二銲料 300半導體封裝堆疊裝置 310第一半導體封裝件 311A上表面 311B下表面 313上層凸塊 314下層凸塊 320第二半導體封裝件 321A上表面 321B下表面 323下層凸塊 324虛置凸塊 330第一銲料 340第二銲料 213第一上層凸塊 216第一封膠體 221第二基板 22 1C第二槽孔 223第一下層凸塊 226第二封膠體 3 11第一基板 312第一晶片 321第二基板 322第二晶片212 first wafer 212A first pad 214 second lower bump 215 first bonding wire 220 second semiconductor package 221A upper surface 221B lower surface 222 second wafer 222A second pad 224 second upper bump 225 second Bonding wire 230 solder 240 second solder 300 semiconductor package stacking device 310 first semiconductor package 311A upper surface 311B lower surface 313 upper layer bump 314 lower layer bump 320 second semiconductor package 321A upper surface 321B lower surface 323 lower layer bump 324 Dummy bump 330 first solder 340 second solder 213 first upper bump 216 first encapsulant 221 second substrate 22 1C second slot 223 first lower bump 226 second encapsulant 3 11 first substrate 312 first wafer 321 second substrate 322 second wafer

1717

Claims (1)

1345293 ;年月曰修正替換頁ί 十、申請專利範圍： -m 5. g 、 1、一種半導體封裝堆疊裝置，包含： 一第一半導體封裝件，其係包含一第一基板、一第一晶 片以及複數個上層凸塊，其中該些上層凸塊與該第一 晶片係設置於該第一基板之—上表面； 一第二半導體封裝件，其係包含一第二基板、一第二晶 片以及複數個下層凸塊，其中該些下層凸塊係設置於1345293; 年 曰 替换 替换 十 十 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 And a plurality of upper bumps, wherein the upper bumps and the first wafer are disposed on an upper surface of the first substrate; and a second semiconductor package includes a second substrate, a second wafer, and a plurality of lower bumps, wherein the lower bumps are disposed on 該第二基板之一下表面，該第二晶片係設置於該第二 基板之一上表面；以及 複數個銲料，其係接合該些上層凸塊與該些下層凸塊； 其中，該第一半導體封裝件係疊設在該第一半導體封裝 件之上，並使該些下層凸塊對準於該些上層凸塊，以 利均勻焊接； 其中，該些銲料係具有一 Η形焊接截面以在該些上層凸 塊與該些下層占塊之間形成一焊接間隙，該焊接間隙a lower surface of the second substrate, the second wafer is disposed on an upper surface of the second substrate; and a plurality of solders bonding the upper bumps and the lower bumps; wherein the first semiconductor a package is stacked on the first semiconductor package, and the lower bumps are aligned with the upper bumps for uniform soldering; wherein the solders have a meandering soldering cross section to Forming a solder gap between the upper bumps and the lower layer occupying blocks, the solder gap 係】於該些上層凸塊與該些下層凸塊之任一凸塊高 度。 2、如申請專利範圍第丨項所述之半導體封裝堆疊裝置， 其中該第一半導體封裝件更包含複數個第二下層凸 塊，該些第二下層凸塊係設置於該第一基板之一下表 面。 18 1345293 中該第二半導體封裝件更包含複數個第二上層凸 ’該些第二上層凸塊係設置於該第二基板之一上表 5、 如申請專利範圍第丨項所述之半導體封裝堆疊裝置， 其中該第一半導體封裝件更包含複數個第一銲線，該第 一基板係具有一第一槽孔，該些第一銲線係通過該第一 槽孔而電性連接該第一晶片與該第一基板。The height of any of the upper bumps and the lower bumps. 2. The semiconductor package stacking device of claim 2, wherein the first semiconductor package further comprises a plurality of second lower bumps, the second lower bumps being disposed under one of the first substrates surface. The first semiconductor package further includes a plurality of second upper bumps. The second upper bumps are disposed on one of the second substrates. Table 5 is a semiconductor package according to the above application. a stacking device, wherein the first semiconductor package further comprises a plurality of first bonding wires, the first substrate has a first slot, and the first bonding wires are electrically connected to the first through the first slot A wafer and the first substrate. 6、 如申請專利範圍第5項所述之半導體封裝堆疊裝置， 其中該第一半導體封裝件更包含一第一封膠體，其係形 成於該第一槽孔，以密封該些第一銲線。 7、 如申請專利範圍第6項所述之半導體封裝堆疊裝置， 其中该第一封膠體係不覆蓋該第一晶片。 8、 如申請專利範圍第6項所述之半導體封裝堆疊裝置， 其中該第二半導體封裝件係實質相同於該第一半導體 封裝件，而包含有複數個第二銲線與一第二封膠體。6. The semiconductor package stacking device of claim 5, wherein the first semiconductor package further comprises a first encapsulant formed in the first slot to seal the first bonding wires . 7. The semiconductor package stacking device of claim 6, wherein the first encapsulation system does not cover the first wafer. 8. The semiconductor package stacking device of claim 6, wherein the second semiconductor package is substantially identical to the first semiconductor package and includes a plurality of second bonding wires and a second sealing body. . 其 塊 面 9、 如申請專利範圍第！項所述之半導體封裝堆疊裝置， 其中該些下詹&塊與該些上層凸塊係具有相同尺寸與 外形。 10、 如申請專利範圍帛Μ所述之半導體封裝㈣裝置， 其中該些下層凸塊與該些上層凸塊係具有半錐形截面。 11、 如申請專利範圍帛1項戶斤述之半導體封裝堆疊裝置， 其中該些下層凸塊與該些上層凸塊係為鋼柱。 !2、如申請專利範圍第i項所述之半導體封裝堆疊裝置， 其中該第二半導體封裝件係具有複數個虛置凸塊，其係 19 1345293 丨替換頁I 設於該第二基板之下表面，並位於該第一n體封‘件、’ • 之該第一晶片上方，以供散熱。 - 13、如申請專利範圍第12項所述之半導體封裝堆疊裝置， 、 其中該些虛置凸塊係接觸該第一晶片之背面。 • 14、如申請專利範圍第1至13項中任一項所述之半導體 封裝堆疊裝置，其中該Η形焊接截面之端部係焊接在 該第一基板之該上表面之墊周邊與焊接在該第二基板 之該下表面之墊周邊，以完全包覆該些上層凸塊與該些 # 下層凸塊。 15、 如申請專利範圍第1項所述之半導體封裝堆疊裝置， 其中該些銲料係為無鉛銲劑。 〇 16、 一種半導體封裴堆疊裝置，包含複數個相互堆疊之半 導體封裝件，每一半導體封裝件係包含一基板、一晶 片、複數個下層凸塊以及複數個上層凸塊，其中該些 下層凸塊係设置於該基板之一下表面，該些上層凸塊 •與該晶片係設置於該基板之一上表面，並且該些上層 凸塊與該些下層凸塊係具有相同的銲料接合形狀與面 積·，該半導體封裝堆疊裝置係另包含複數個銲料Υ其 係接合該些上層凸塊與該些下層凸塊；其中，該些銲 料係具有一Η形焊接截面以在該些上層凸塊與該些下 層凸塊之間形成一焊接間隙，該焊接間隙係小於該些 上層凸塊與該些下層凸塊之任一凸塊高度。 17、 如申請專利範圍第16項所述之半導體封裝堆疊裝置， 其中該些上層凸塊與該些下層凸塊之銲料接合形狀係 20 1345293 - iSo \曰释替換頁 為開口擴大的u形。 ㈣丄 • I8、如申請專利範圍第16項所述之半導體封裝堆疊骏置， 其中每一半導體封裝件更包含複數個銲線，該基板係具 、 有一槽孔，該些銲線係通過該槽孔而電性連接該晶片與 - 該基板。 ' 19、如申請專利範圍第18項所述之半導體封裝堆疊裝置， 其中每一半導體封裝件更包含一封膠體，其係形成於該 槽孔，以密封該些銲線。 鲁 2°、如申請專利範圍第19項所述之半導體封裝堆疊裝置， 其中母一封膠體係不覆蓋該晶片。 t 2卜如申請專利範圍第16項所述之半導體封裝堆疊裝置， 其中該些下層凸塊與該些上層凸塊係具有半錐形截面。 22、 如申請專利範圍第16項所述之半導體封裝堆疊裝置， 其中該些下層凸塊與該些上層凸塊係為銅柱。 23、 如申請專利範圍第16項所述之半導體封裝堆疊裝置， • 其中每一半導體封裝件係具有複數個虛置凸塊，其係設 於該基板之下表面，以供散熱。 24'如申請專利範圍第16至23項中任一項所述之半導體 封裝堆疊裝置，其中該Η形焊接截面之端部係焊接在 該基板之該上表面之墊周邊與焊接在該基板之該下表 面之墊周邊，以完全包覆該些上層凸塊與該些下層凸 塊0 21Its block surface 9, such as the scope of patent application! The semiconductor package stacking device of the present invention, wherein the lower Zhan & blocks have the same size and shape as the upper bumps. 10. The semiconductor package (4) device of claim 1, wherein the lower bumps and the upper bumps have a semi-tapered cross section. 11. The semiconductor package stacking device of claim 1, wherein the lower bumps and the upper bumps are steel pillars. 2. The semiconductor package stacking device of claim 1, wherein the second semiconductor package has a plurality of dummy bumps, wherein the 19 1345293 丨 replacement page I is disposed under the second substrate a surface and located above the first wafer of the first n-body package, for dissipation. The semiconductor package stacking device of claim 12, wherein the dummy bumps contact the back surface of the first wafer. The semiconductor package stacking device according to any one of claims 1 to 13, wherein the end portion of the meandering welded section is welded to the periphery of the upper surface of the first substrate and soldered to And surrounding the pad of the lower surface of the second substrate to completely cover the upper bumps and the lower bumps. 15. The semiconductor package stacking device of claim 1, wherein the solder is a lead-free solder.半导体16. A semiconductor package stacking device comprising a plurality of semiconductor packages stacked on each other, each semiconductor package comprising a substrate, a wafer, a plurality of lower bumps, and a plurality of upper bumps, wherein the lower bumps The block is disposed on a lower surface of the substrate, the upper bumps and the wafer are disposed on an upper surface of the substrate, and the upper bumps and the lower bumps have the same solder joint shape and area The semiconductor package stacking device further includes a plurality of solders that bond the upper bumps and the lower bumps; wherein the solder traces have a meandering soldering cross section to the upper bumps A solder gap is formed between the lower bumps, and the solder gap is smaller than the height of any of the upper bumps and the lower bumps. The semiconductor package stacking device of claim 16, wherein the solder joint shape of the upper bumps and the lower bumps is a u-shaped opening. (4) The semiconductor package stacking device of claim 16, wherein each semiconductor package further comprises a plurality of bonding wires, the substrate device has a slot, and the bonding wires pass through the The slot is electrically connected to the wafer and the substrate. 19. The semiconductor package stacking device of claim 18, wherein each of the semiconductor packages further comprises a gel formed in the slot to seal the bonding wires. The semiconductor package stacking device of claim 19, wherein the master adhesive system does not cover the wafer. The semiconductor package stacking device of claim 16, wherein the lower bumps and the upper bumps have a semi-conical cross section. The semiconductor package stacking device of claim 16, wherein the lower bumps and the upper bumps are copper pillars. 23. The semiconductor package stacking device of claim 16, wherein each of the semiconductor packages has a plurality of dummy bumps disposed on a lower surface of the substrate for heat dissipation. The semiconductor package stacking device according to any one of claims 16 to 23, wherein an end portion of the meandering welded section is welded to a periphery of the upper surface of the substrate and soldered to the substrate The periphery of the pad of the lower surface to completely cover the upper bumps and the lower bumps 0 21
TW096117980A 2007-05-21 2007-05-21 Semiconductor package-on-package (pop) device avoiding crack at solder joints of micro-contacts during semiconductor stacking TWI345293B (en)

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