CN100364070C - 半导体元件与其形成方法 - Google Patents
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Abstract
本发明提供一种半导体元件与其形成方法。该半导体元件包括：基底；位于该基底上的栅极；源极与漏极形成在栅极两侧的基底中；以及具有第一层与第二层的薄间隙壁形成于栅极侧壁，其中第一层与第二层具有在使用相同刻蚀剂时具有相当的刻蚀速率，这里相当的刻蚀速率表示该两刻蚀速率的差距在±10%之间，且其至少为每分钟10埃。本发明提供的半导体元件，其间隙壁的厚度既能保持接触刻蚀停止层的作用，又能有效控制短沟道效应。
Description
技术领域
本发明涉及一种半导体元件，特别是涉及一种具有间隙壁的半导体元件及其形成方法。
背景技术
半导体元件的性能与载流子迁移率有关。例如，在金属氧化物半导体(MOS)元件中，元件沟道的载流子迁移率越高，在沟道中的电流就越快，则元件的执行速度就越快。
载流子迁移率是由半导体元件的特性(如晶格常数)所决定的。例如，半导体衬底中的应力可改变晶格常数，以使迁移率改变，而增加对衬底应力的方法之一就是使用接触刻蚀停止层。此外，栅极电极侧壁间隙壁(spacer)的厚度也可影响应力对衬底的效应，较厚的间隙壁会降低应变的接触刻蚀停止层所欲造成的影响。然而，又需要较厚的间隙壁在半导体元件的制造中来控制短沟道效应。因此，为得到性能良好的半导体元件，间隙壁厚度的取舍是一个矛盾点。
发明内容
有鉴于此，本发明的目的在于提供一种形成半导体元件的方法以及使用该方法形成的半导体元件，使间隙壁的厚度达到最佳，使其既能保持接触刻蚀停止层的作用，又能有效控制短沟道效应。
为了实现上述目的，本发明提供一种形成半导体元件的方法，包括：形成栅极于半导体衬底上；形成第一间隙壁层，其中该第一间隙壁层为氧化物；形成多个浅轻掺杂区于栅极两侧的衬底中且通过第一间隙壁层偏离栅极；形成氮化物所组成的第二间隙壁层于第一间隙壁层上，并选择工艺参数，以使相同刻蚀剂对该第一间隙壁层和第二间隙壁层的刻蚀速率的差距在±10％之间；刻蚀第一与第二间隙壁层以形成厚间隙壁；形成多个源极与漏极区于栅极两侧的衬底中且通过厚间隙壁偏离栅极；以及刻蚀厚间隙壁以形成薄间隙壁。
本发明所述的形成半导体元件的方法，所述刻蚀厚间隙壁的步骤包括以氢氟酸刻蚀该厚间隙壁。
本发明所述的形成半导体元件的方法，所述形成第二间隙壁层的步骤包括选择工艺参数，以形成具有高氢氟酸刻蚀速率的该第二间隙壁层，该高氢氟酸刻蚀速率至少为每分钟10埃。
本发明所述的形成半导体元件的方法，所述形成第二间隙壁层的步骤包括在小于630℃下沉积一个具有对氢氟酸至少每分钟10埃的刻蚀速率的氮化硅层。
本发明所述的形成半导体元件的方法，所述形成第一与第二间隙壁层的步骤包括形成具有氧化硅的该第一间隙壁层且形成含氮的该第二间隙壁层。
本发明所述的形成半导体元件的方法，所述刻蚀厚间隙壁的步骤包括以氢氟酸湿刻蚀该厚间隙壁。
本发明所述的形成半导体元件的方法，还包括对所述源极与漏极区执行退火处理以缩小所述第二间隙壁层。
本发明所述的形成半导体元件的方法，还包括对所述源极与漏极区执行退火处理以缩小所述厚间隙壁。
本发明所述的形成半导体元件的方法，所述形成第二间隙壁层的步骤包括利用前驱物，该前驱物是六氯乙硅烷、双叔丁基胺基硅烷、二氯甲硅烷、乙硅烷、SiH4、NH3、C2H4、N2其中之一或其组合。
为了实现上述目的，本发明还提供一种半导体元件，包括：衬底；位于衬底上的栅极；源极与漏极形成在栅极两侧的衬底中；以及具有衬层与含氮层的薄间隙壁形成于栅极侧壁，其中，衬层与含氮层具有相当的氢氟酸刻蚀速率，其中该衬层为氧化物，这里的“相当的刻蚀速率”表示该两刻蚀速率的差距在±10％之间。
本发明所述的半导体元件，所述含氮层包括掺杂质，该掺杂质是砷、硼、氯其中之一或其组合。
本发明所述的半导体元件，所述含氮层包括掺杂质，该掺杂质是碳、氧、氟其中之一或其组合。
本发明所述的半导体元件，所述衬层包括氧化物。
本发明所述的半导体元件，所述含氮层具有大约每分钟10至1000埃的氢氟酸刻蚀速率。
为了实现上述目的，本发明还提供一种半导体元件，包括：衬底；位于衬底上的栅极；源极与漏极形成在栅极两侧的衬底中；以及具有第一层与第二层的薄间隙壁形成于栅极侧壁，其中，第一层与第二层在使用相同刻蚀剂时具有相当的刻蚀速率，这里的“相当的刻蚀速率”表示该两刻蚀速率的差距在±10％之间，其至少为每分钟10埃。
本发明所述的半导体元件，所述第二层包括掺杂质，该掺杂质是砷、硼、氯其中之一或其组合。
本发明所述的半导体元件，所述第二层包括掺杂质，该掺杂质是碳、氧、氟其中之一或其组合。
本发明所述的半导体元件，所述第一层由低介电常数材料组成，其介电常数不大于3.7。
本发明所述的半导体元件，所述第一层由碳化物、氮化物其中之一或其组合组成。
本发明所述的半导体元件，所述第二层具有大约每分钟10至1000埃的氢氟酸刻蚀速率。
本发明提供的形成半导体元件的方法以及使用该方法形成的半导体元件，在源极与漏极离子注入时具有厚间隙壁的优点，能够控制短沟道效应。在源极与漏极离子注入后，再回刻蚀厚间隙壁，且在形成源极与漏极的退火步骤与HF湿刻蚀工艺时将间隙壁缩小，以形成薄间隙壁。由于磷酸刻蚀可靠度差且难以控制，而本发明的工艺无需使用磷酸刻蚀就可形成薄间隙壁轮廓。具有该薄间隙壁的半导体元件，其应力由应变沟道刻蚀停止层所诱发，以影响载流子迁移率，从而得到所需的元件性能。
附图说明
图1A至1G是一系列半导体元件在各制造过程中的简化剖面图。
图2是低压化学气相沉积HCD氮化硅在各温度下的HF刻蚀速率图。
图3是低压化学气相沉积TEOS氧化物在各温度下的HF刻蚀速率图。
具体实施方式
为使本发明的上述和其他目的、特征和优点能更明显易懂，下文特举出较佳实施例，并结合附图加以详细说明。
图1A至1G是半导体元件10在各制造步骤中的简化剖面图，以说明该元件制造方法的一个实施例。在图1A中，栅极结构14形成于半导体衬底12上。半导体衬底12可为硅、应变硅、硅锗(silicon-germanium，SixGey)、绝缘覆硅(SOI)或其它合适的材料。栅极结构14可以是堆迭的结构，包括介电层与位于介电层上的多晶硅层。栅极电极还可用其它材料形成，例如经掺杂的多晶硅、硅锗、金属、硅化物等，而栅极介电质可为氧化物、氮氧化物、氮化物、高介电常数(k)材料、硅酸盐、多层膜堆迭或其它适合的材料或组成。栅极介电质可利用化学气相沉积(CVD)形成。栅极结构1 4可利用光刻技术形成。栅极结构14可为单栅极结构、多栅极结构、鳍型(Fin)FET栅极结构或T栅极结构。
在图1B中，间隙壁衬层16形成或沉积于栅极结构14与衬底12上，间隙壁衬层16可为氧化物、氮氧化物、氮化物、高k材料或低k材料。间隙壁衬层16的厚度约为1至50nm，且该厚度较佳为2至10nm，前驱物材料或气体反应物可包括原硅酸四乙酯(tetraethyl orthosilicate，简称TEOS，Si(OC2H5)4)、三乙氧基硅烷(triethoxysilane，简称TRIES)、双叔丁基胺基硅烷(bis tertbutylamino silane，简称BTBAS)、六氯乙硅烷(hexachlorodisilane，简称HCD)、O2、N2O、NO或其它材料。用以形成间隙壁衬层16的沉积方法可为低压化学气相沉积(LPCVD)、等离子增强式化学气相沉积(PECVD)、高密度等离子化学气相沉积(HPCVD)、常压化学气相沉积(APCVD)、自由基增强式化学气相沉积(RECVD)、原子层沉积(ALD)、原子层化学气相沉积(ALCVD)，或者其它现有或以后研发出来的技术。
在图1C中，适当材料离子经由间隙壁衬层16注入栅极结构14两侧的衬底12中，以形成轻掺杂漏极(LDD)18或袋状结构，而间隙壁衬层16在此轻掺杂漏极注入中作为一个掩膜。在图1D中，氮化硅(silcon nitride)间隙壁层20沉积于间隙壁衬层16上，氮化硅层20可通过CVD技术(例如LPCVD或以上列举出的方法)沉积，其前驱反应物可包括HCD、BTBAS、二氯甲硅烷(dichlorosilane，简称DCS，SiH2Cl2)、乙硅烷(DS)、SiH4、NH3、C2H4、N2或其它材料，且可通过调整CVD步骤的工艺参数使氢氟酸(HF)对氮化硅层20的刻蚀速率高得与HF对间隙壁衬层16的刻蚀速率相当。这里的“相当的刻蚀速率”表示两个刻蚀速率的差距在±10％之间。例如，调整沉积温度、压力、气体流速、前驱物与掺杂浓度等，以使氮化硅层20在室温下用100∶1的HF刻蚀的刻蚀速率约为每分钟30至1000埃，且其低沉积温度可小于630℃，且可使用0.1至10torr(1torr＝133.32Pa)的反应室压力，间隙壁20的氮浓度可为1至70％原子百分比。间隙壁层20还可包括掺杂质，例如碳、氧、氟、氯、硼、砷等。氮化硅层20的刻蚀速率较佳与氧化物间隙壁衬层16相同。接下来，间隙壁层20与间隙壁衬层16两者皆被回刻蚀，以形成厚间隙壁结构21，如图1E所示。例如，该厚间隙壁的厚度约为1至200nm，厚间隙壁结构21可以使用适当的干刻蚀技术形成。
在图1E中，通过注入适当的杂质形成源极与漏极区22与24。此外，半导体元件10可包括凸起的硅锗漏极与源极区或其它合适的结构。在图1F中，厚间隙壁结构21进一步被回刻蚀，以形成厚间隙壁25，接着再对源极与漏极区22与24进行退火处理，且此退火步骤也可在间隙壁回刻蚀工艺前进行。此退火步骤可包括快速热退火、激光退火或炉管退火。此退火步骤可使间隙壁层在不使用磷酸刻蚀的情况下缩小且致密化。间隙壁层的收缩率可通过形成间隙壁层时的沉积参数来控制。由于磷酸的刻蚀速率难以控制且不稳定，所以磷酸刻蚀并不好用。因此，本发明形成间隙壁的工艺无需使用磷酸刻蚀，以避免磷酸刻蚀缺点的产生。在一个实施例中，在室温下使用49％的HF与水的比例为1∶100时，间隙壁的刻蚀速率约为每分钟30至1000埃，在退火处理后，间隙壁的刻蚀速率在相同条件下约为每分钟10至500埃。
如图1G所示，硅化物层26形成于源极、漏极与栅极电极上。例如，硅化物层26可为硅化钴(CoSi2)、硅化镍(NiSi2)、硅化钛(TiSi2)、硅化钼(MoSi2)、硅化铂(PtSi)、硅化钨(WSi2)、硅化钽(TaSi2)等。硅化物层26的厚度约为3至100nm。此外，接触刻蚀停止层28形成于源极、漏极与栅极上，接触刻蚀停止层28可以是以沉积技术形成的氮化硅。接触刻蚀停止层28可由具有约2至2GPa应力且厚度约为100至1000埃的高应变氮化硅膜形成。接触刻蚀停止层28可由氧化物、氮化物、氮氧化物、掺杂的氮化物或多层堆迭结构形成，之后，执行金属化工艺以形成源极、漏极与栅极接触插塞。
图2是低压化学气相沉积HCD氮化硅在各温度下HF刻蚀速率图，间隙壁层20的刻蚀速率与间隙壁衬层16的刻蚀速率相当。这里的“相当的刻蚀速率”表示该两刻蚀速率的差距在±10％之间，所以两者皆可由相同刻蚀工艺作回刻蚀。刻蚀速率可以通过沉积参数如温度、压力、气体流速与掺杂等调整； 间隙壁衬层与间隙壁层的刻蚀速率应可使HF湿刻蚀工艺达到所需的薄间隙壁轮廓。如图2所示，经碳掺杂或未经碳掺杂的氮化硅在各温度下的刻蚀速率可与图3所示的TEOS氧化物在各温度下的刻蚀速率作比较。
因此，本发明在源极与漏极离子注入时具有厚间隙壁的优点，例如能够控制短沟道效应。在源极与漏极离子注入后，再回刻蚀厚间隙壁，且在形成源极与漏极的退火步骤与HF湿刻蚀工艺时将间隙壁缩小，以形成薄间隙壁，其中以HF湿刻蚀工艺为间隙壁缩小的主要因素。间隙壁衬层与间隙壁层的刻蚀速率可由工艺参数控制，以使间隙壁衬层与间隙壁层可在相同刻蚀工艺下作回刻蚀。由于磷酸刻蚀可靠度差且难以控制，而本发明的工艺无需使用磷酸刻蚀就可形成薄间隙壁轮廓。具有该薄间隙壁的半导体元件，其应力由应变沟道刻蚀停止层所诱发，以影响载流子迁移率，从而得到所需的元件性能。
虽然本发明已通过较佳实施例说明如上，但该较佳实施例并非用以限定本发明。本领域的技术人员，在不脱离本发明的精神和范围内，应有能力对该较佳实施例做出各种更改和补充，因此本发明的保护范围以权利要求书的范围为准。
附图中符号的简单说明如下：
10：半导体元件 20：氮化硅间隙壁层
12：半导体衬底 21：厚间隙壁结构
14：栅极结构 22、24：源极与漏极区
16：间隙壁衬层 25：厚间隙壁
18：轻掺杂漏极 26：硅化物层
Claims (20)
1.一种形成半导体元件的方法，其特征在于包括：
在一个半导体衬底上形成一个栅极；
形成第一间隙壁层，其中该第一间隙壁层为氧化物；
形成多个浅轻掺杂区于该栅极两侧的衬底中且通过该第一间隙壁层偏离该栅极；
在该第一间隙壁层上形成氮化物所组成的第二间隙壁层，并选择工艺参数，以使相同刻蚀剂对该第一间隙壁层和第二间隙壁层的刻蚀速率的差距在±10％之间；
刻蚀该第一与第二间隙壁层以形成一个厚间隙壁；
形成多个源极与漏极区于该栅极两侧的衬底中且通过该厚间隙壁偏离该栅极；以及
刻蚀该厚间隙壁以形成一个薄间隙壁。
2.根据权利要求1所述的形成半导体元件的方法，其特征在于所述刻蚀厚间隙壁的步骤包括以氢氟酸刻蚀该厚间隙壁。
3.根据权利要求1所述的形成半导体元件的方法，其特征在于所述形成第二间隙壁层的步骤包括选择工艺参数，以形成具有高氢氟酸刻蚀速率的该第二间隙壁层，该高氢氟酸刻蚀速率至少为每分钟10埃。
4.根据权利要求1所述的形成半导体元件的方法，其特征在于所述形成第二间隙壁层的步骤包括在小于630℃下沉积一个具有对氢氟酸至少每分钟10埃的刻蚀速率的氮化硅层。
5.根据权利要求1所述的形成半导体元件的方法，其特征在于所述形成第一与第二间隙壁层的步骤包括形成具有氧化硅的该第一间隙壁层且形成含氮的该第二间隙壁层。
6.根据权利要求1所述的形成半导体元件的方法，其特征在于所述刻蚀厚间隙壁的步骤包括以氢氟酸湿刻蚀该厚间隙壁。
7.根据权利要求1所述的形成半导体元件的方法，其特征在于还包括对所述源极与漏极区执行退火处理以缩小所述第二间隙壁层。
8.根据权利要求1所述的形成半导体元件的方法，其特征在于还包括对所述源极与漏极区执行退火处理以缩小所述厚间隙壁。
9.根据权利要求1所述的形成半导体元件的方法，其特征在于所述形成第二间隙壁层的步骤包括利用前驱物，该前驱物是六氯乙硅烷、双叔丁基胺基硅烷、二氯甲硅烷、乙硅烷、SiH4、NH3、C2H4、N2其中之一或其组合。
10.一种半导体元件，其特征在于包括：
一个衬底；
一个栅极位于该衬底上；
一个源极与漏极形成在该栅极两侧的该衬底中；以及
具有一个衬层和一个含氮层的一个间隙壁形成于该栅极侧壁，其中该衬层与该含氮层具有相当的氢氟酸刻蚀速率，其中该衬层为氧化物，且该相当的氢氟酸刻蚀速率表示对该衬层和该含氮层的氢氟酸刻蚀速率的差距在±10％之间。
11.根据权利要求10所述的半导体元件，其特征在于所述含氮层包括掺杂质，该掺杂质是砷、硼、氯其中之一或其组合。
12.根据权利要求10所述的半导体元件，其特征在于所述含氮层包括掺杂质，该掺杂质是碳、氧、氟其中之一或其组合。
13.根据权利要求10所述的半导体元件，其特征在于所述衬层包括氧化物。
14.根据权利要求10所述的半导体元件，其特征在于所述含氮层具有每分钟10至1000埃的氢氟酸刻蚀速率。
15.一种半导体元件，其特征在于包括：
一个衬底；
一个栅极位于该衬底上；
一个源极与漏极形成在该栅极两侧的该衬底中；以及
具有第一层与第二层的一个薄间隙壁形成于该栅极侧壁，其中该第一层与第二层在使用相同刻蚀剂时的湿刻蚀速率的差距在±10％之间，该湿刻蚀速率至少为每分钟10埃。
16.根据权利要求15所述的半导体元件，其特征在于所述第二层包括掺杂质，该掺杂质是砷、硼、氯其中之一或其组合。
17.根据权利要求15所述的半导体元件，其特征在于所述第二层包括掺杂质，该掺杂质是碳、氧、氟其中之一或其组合。
18.根据权利要求15所述的半导体元件，其特征在于所述第一层由低介电常数材料组成，其介电常数不大于3.7。
19.根据权利要求15所述的半导体元件，其特征在于所述第一层由碳化物、氮化物其中之一或其组合组成。
20.根据权利要求15所述的半导体元件，其特征在于所述第二层具有每分钟10至1000埃的氢氟酸刻蚀速率。
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| US20060094194A1 (en) * | 2004-11-04 | 2006-05-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Advanced disposable spacer process by low-temperature high-stress nitride film for sub-90NM CMOS technology |
| KR100558047B1 (ko) * | 2004-12-28 | 2006-03-07 | 주식회사 하이닉스반도체 | 반도체 장치의 제조방법 |
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| US20060172556A1 (en) * | 2005-02-01 | 2006-08-03 | Texas Instruments Incorporated | Semiconductor device having a high carbon content strain inducing film and a method of manufacture therefor |
| US7298011B2 (en) * | 2005-08-30 | 2007-11-20 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device with recessed L-shaped spacer and method of fabricating the same |
| US20070197011A1 (en) * | 2006-02-22 | 2007-08-23 | Freescale Semiconductor Inc. | Method for improving self-aligned silicide extendibility with spacer recess using a stand-alone recess etch integration |
| JP4960007B2 (ja) * | 2006-04-26 | 2012-06-27 | 株式会社東芝 | 半導体装置及び半導体装置の製造方法 |
| US20090283922A1 (en) * | 2007-12-27 | 2009-11-19 | Willy Rachmady | Integrating high stress cap layer in high-k metal gate transistor |
| US7745320B2 (en) * | 2008-05-21 | 2010-06-29 | Chartered Semiconductor Manufacturing, Ltd. | Method for reducing silicide defects in integrated circuits |
| US8236678B2 (en) * | 2008-12-17 | 2012-08-07 | Globalfoundries Singapore Pte. Ltd. | Tunable spacers for improved gapfill |
| US8889235B2 (en) | 2009-05-13 | 2014-11-18 | Air Products And Chemicals, Inc. | Dielectric barrier deposition using nitrogen containing precursor |
| US8264032B2 (en) | 2009-09-01 | 2012-09-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Accumulation type FinFET, circuits and fabrication method thereof |
| CN102054675B (zh) * | 2009-11-02 | 2012-03-07 | 中芯国际集成电路制造(上海)有限公司 | 偏移侧墙及mos晶体管的形成方法 |
| US8563095B2 (en) * | 2010-03-15 | 2013-10-22 | Applied Materials, Inc. | Silicon nitride passivation layer for covering high aspect ratio features |
| CN102214574B (zh) * | 2010-04-07 | 2013-06-12 | 中国科学院微电子研究所 | 一种半导体器件的制造方法 |
| US20110256734A1 (en) | 2010-04-15 | 2011-10-20 | Hausmann Dennis M | Silicon nitride films and methods |
| US9076646B2 (en) | 2010-04-15 | 2015-07-07 | Lam Research Corporation | Plasma enhanced atomic layer deposition with pulsed plasma exposure |
| US9373500B2 (en) | 2014-02-21 | 2016-06-21 | Lam Research Corporation | Plasma assisted atomic layer deposition titanium oxide for conformal encapsulation and gapfill applications |
| US9390909B2 (en) | 2013-11-07 | 2016-07-12 | Novellus Systems, Inc. | Soft landing nanolaminates for advanced patterning |
| US8956983B2 (en) | 2010-04-15 | 2015-02-17 | Novellus Systems, Inc. | Conformal doping via plasma activated atomic layer deposition and conformal film deposition |
| US9997357B2 (en) | 2010-04-15 | 2018-06-12 | Lam Research Corporation | Capped ALD films for doping fin-shaped channel regions of 3-D IC transistors |
| US9257274B2 (en) | 2010-04-15 | 2016-02-09 | Lam Research Corporation | Gapfill of variable aspect ratio features with a composite PEALD and PECVD method |
| US9611544B2 (en) | 2010-04-15 | 2017-04-04 | Novellus Systems, Inc. | Plasma activated conformal dielectric film deposition |
| US9892917B2 (en) | 2010-04-15 | 2018-02-13 | Lam Research Corporation | Plasma assisted atomic layer deposition of multi-layer films for patterning applications |
| US8637411B2 (en) | 2010-04-15 | 2014-01-28 | Novellus Systems, Inc. | Plasma activated conformal dielectric film deposition |
| US9685320B2 (en) | 2010-09-23 | 2017-06-20 | Lam Research Corporation | Methods for depositing silicon oxide |
| US8524612B2 (en) | 2010-09-23 | 2013-09-03 | Novellus Systems, Inc. | Plasma-activated deposition of conformal films |
| TWI455316B (zh) * | 2011-01-28 | 2014-10-01 | Richtek Technology Corp | 高壓多閘極元件及其製造方法 |
| US8377786B2 (en) * | 2011-02-03 | 2013-02-19 | GlobalFoundries, Inc. | Methods for fabricating semiconductor devices |
| DE102011005641B4 (de) * | 2011-03-16 | 2018-01-04 | GLOBALFOUNDRIES Dresden Module One Ltd. Liability Company & Co. KG | Verfahren zur Leistungssteigerung in Transistoren durch Reduzierung der Absenkung aktiver Gebiete und durch Entfernen von Abstandshaltern |
| US8647993B2 (en) | 2011-04-11 | 2014-02-11 | Novellus Systems, Inc. | Methods for UV-assisted conformal film deposition |
| US8324059B2 (en) | 2011-04-25 | 2012-12-04 | United Microelectronics Corp. | Method of fabricating a semiconductor structure |
| US9034701B2 (en) * | 2012-01-20 | 2015-05-19 | International Business Machines Corporation | Semiconductor device with a low-k spacer and method of forming the same |
| US8592328B2 (en) | 2012-01-20 | 2013-11-26 | Novellus Systems, Inc. | Method for depositing a chlorine-free conformal sin film |
| US8728955B2 (en) | 2012-02-14 | 2014-05-20 | Novellus Systems, Inc. | Method of plasma activated deposition of a conformal film on a substrate surface |
| US8809194B2 (en) * | 2012-03-07 | 2014-08-19 | Tokyo Electron Limited | Formation of SiOCl-containing layer on spacer sidewalls to prevent CD loss during spacer etch |
| US8765536B2 (en) | 2012-09-28 | 2014-07-01 | International Business Machines Corporation | Stress engineered multi-layers for integration of CMOS and Si nanophotonics |
| US9355839B2 (en) | 2012-10-23 | 2016-05-31 | Lam Research Corporation | Sub-saturated atomic layer deposition and conformal film deposition |
| SG2013083654A (en) | 2012-11-08 | 2014-06-27 | Novellus Systems Inc | Methods for depositing films on sensitive substrates |
| SG2013083241A (en) | 2012-11-08 | 2014-06-27 | Novellus Systems Inc | Conformal film deposition for gapfill |
| US9153668B2 (en) | 2013-05-23 | 2015-10-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Tuning tensile strain on FinFET |
| CN103489787B (zh) * | 2013-09-22 | 2016-04-13 | 上海华力微电子有限公司 | 提高源漏接触和氮化硅薄膜黏附力的方法 |
| US9214334B2 (en) | 2014-02-18 | 2015-12-15 | Lam Research Corporation | High growth rate process for conformal aluminum nitride |
| US10468528B2 (en) | 2014-04-16 | 2019-11-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFET device with high-k metal gate stack |
| US9178067B1 (en) * | 2014-04-25 | 2015-11-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Structure and method for FinFET device |
| US9721955B2 (en) | 2014-04-25 | 2017-08-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Structure and method for SRAM FinFET device having an oxide feature |
| CN105097929A (zh) * | 2014-05-22 | 2015-11-25 | 中芯国际集成电路制造(上海)有限公司 | 半导体器件及其制作方法 |
| US9224736B1 (en) | 2014-06-27 | 2015-12-29 | Taiwan Semicondcutor Manufacturing Company, Ltd. | Structure and method for SRAM FinFET device |
| US9478411B2 (en) | 2014-08-20 | 2016-10-25 | Lam Research Corporation | Method to tune TiOx stoichiometry using atomic layer deposited Ti film to minimize contact resistance for TiOx/Ti based MIS contact scheme for CMOS |
| US9478438B2 (en) | 2014-08-20 | 2016-10-25 | Lam Research Corporation | Method and apparatus to deposit pure titanium thin film at low temperature using titanium tetraiodide precursor |
| US9564312B2 (en) | 2014-11-24 | 2017-02-07 | Lam Research Corporation | Selective inhibition in atomic layer deposition of silicon-containing films |
| US10566187B2 (en) | 2015-03-20 | 2020-02-18 | Lam Research Corporation | Ultrathin atomic layer deposition film accuracy thickness control |
| US9502238B2 (en) | 2015-04-03 | 2016-11-22 | Lam Research Corporation | Deposition of conformal films by atomic layer deposition and atomic layer etch |
| US10526701B2 (en) | 2015-07-09 | 2020-01-07 | Lam Research Corporation | Multi-cycle ALD process for film uniformity and thickness profile modulation |
| JP6594804B2 (ja) * | 2016-03-11 | 2019-10-23 | 株式会社Ｋｏｋｕｓａｉ Ｅｌｅｃｔｒｉｃ | 半導体装置の製造方法、基板処理装置およびプログラム |
| US9773643B1 (en) | 2016-06-30 | 2017-09-26 | Lam Research Corporation | Apparatus and method for deposition and etch in gap fill |
| US10062563B2 (en) | 2016-07-01 | 2018-08-28 | Lam Research Corporation | Selective atomic layer deposition with post-dose treatment |
| US10037884B2 (en) | 2016-08-31 | 2018-07-31 | Lam Research Corporation | Selective atomic layer deposition for gapfill using sacrificial underlayer |
| US10269559B2 (en) | 2017-09-13 | 2019-04-23 | Lam Research Corporation | Dielectric gapfill of high aspect ratio features utilizing a sacrificial etch cap layer |
| US10566441B2 (en) * | 2018-02-14 | 2020-02-18 | Globalfoundries Singapore Pte. Ltd. | Methods of forming integrated circuits with solutions to interlayer dielectric void formation between gate structures |
| CN115084024B (zh) * | 2022-07-19 | 2022-11-18 | 合肥晶合集成电路股份有限公司 | 半导体器件及其制备方法 |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5430313A (en) * | 1990-08-29 | 1995-07-04 | Kabushiki Kaisha Toshiba | Transistor with an offset gate structure |
| CN1183642A (zh) * | 1996-11-27 | 1998-06-03 | Lg半导体株式会社 | 制造半导体器件的方法 |
| CN1183638A (zh) * | 1996-11-27 | 1998-06-03 | Lg半导体株式会社 | 半导体器件的制造方法 |
| US5940692A (en) * | 1995-10-18 | 1999-08-17 | Micron Technology, Inc. | Method of forming a field effect transistor |
| US6261913B1 (en) * | 2000-08-23 | 2001-07-17 | Micron Technology, Inc. | Method for using thin spacers and oxidation in gate oxides |
| US6429083B1 (en) * | 1999-09-24 | 2002-08-06 | Advanced Micro Devices, Inc. | Removable spacer technology using ion implantation to augment etch rate differences of spacer materials |
| JP2003023154A (ja) * | 2001-06-28 | 2003-01-24 | Hynix Semiconductor Inc | 半導体素子の製造方法 |
| CN2805096Y (zh) * | 2004-04-29 | 2006-08-09 | 台湾积体电路制造股份有限公司 | 半导体元件 |
Family Cites Families (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2875945B2 (ja) * | 1993-01-28 | 1999-03-31 | アプライド マテリアルズ インコーポレイテッド | Ｃｖｄにより大面積のガラス基板上に高堆積速度でシリコン窒化薄膜を堆積する方法 |
| US6124610A (en) * | 1998-06-26 | 2000-09-26 | Advanced Micro Devices, Inc. | Isotropically etching sidewall spacers to be used for both an NMOS source/drain implant and a PMOS LDD implant |
| US20030042551A1 (en) * | 1999-04-20 | 2003-03-06 | Paul D. Agnello | Partially removable spacer with salicide formation |
| US6506653B1 (en) * | 2000-03-13 | 2003-01-14 | International Business Machines Corporation | Method using disposable and permanent films for diffusion and implant doping |
| JP2002141420A (ja) * | 2000-10-31 | 2002-05-17 | Mitsubishi Electric Corp | 半導体装置及びその製造方法 |
| KR100441682B1 (ko) * | 2001-06-14 | 2004-07-27 | 삼성전자주식회사 | 엘디디형 소오스/드레인 영역을 갖는 반도체 장치 및 그제조 방법 |
| KR100395878B1 (ko) * | 2001-08-31 | 2003-08-25 | 삼성전자주식회사 | 스페이서 형성 방법 |
| US6764911B2 (en) * | 2002-05-10 | 2004-07-20 | Taiwan Semiconductor Manufacturing Co., Ltd | Multiple etch method for fabricating spacer layers |
| US6884464B2 (en) * | 2002-11-04 | 2005-04-26 | Applied Materials, Inc. | Methods for forming silicon comprising films using hexachlorodisilane in a single-wafer deposion chamber |
| US6835640B2 (en) * | 2002-12-06 | 2004-12-28 | Taiwan Semiconductor Manufacturing Company | Method of forming a novel composite insulator spacer |
| DE10339989B4 (de) * | 2003-08-29 | 2008-04-17 | Advanced Micro Devices, Inc., Sunnyvale | Verfahren zur Herstellung eines konformen Abstandselements benachbart zu einer Gateelektrodenstruktur |
| TWI314768B (en) * | 2003-09-04 | 2009-09-11 | United Microelectronics Corp | Method of manufacturing metal-oxide-semiconductor transistor |
| JP2005109381A (ja) * | 2003-10-02 | 2005-04-21 | Oki Electric Ind Co Ltd | 半導体装置の製造方法 |
| US6991991B2 (en) * | 2003-11-12 | 2006-01-31 | United Microelectronics Corp. | Method for preventing to form a spacer undercut in SEG pre-clean process |
-
2004
- 2004-04-29 US US10/834,474 patent/US7259050B2/en active Active
- 2004-10-18 TW TW093131572A patent/TWI236091B/zh active
- 2004-11-26 CN CNU2004201159159U patent/CN2805096Y/zh not_active Expired - Lifetime
- 2004-11-26 CN CNB2004100960657A patent/CN100364070C/zh active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5430313A (en) * | 1990-08-29 | 1995-07-04 | Kabushiki Kaisha Toshiba | Transistor with an offset gate structure |
| US5940692A (en) * | 1995-10-18 | 1999-08-17 | Micron Technology, Inc. | Method of forming a field effect transistor |
| CN1183642A (zh) * | 1996-11-27 | 1998-06-03 | Lg半导体株式会社 | 制造半导体器件的方法 |
| CN1183638A (zh) * | 1996-11-27 | 1998-06-03 | Lg半导体株式会社 | 半导体器件的制造方法 |
| US6429083B1 (en) * | 1999-09-24 | 2002-08-06 | Advanced Micro Devices, Inc. | Removable spacer technology using ion implantation to augment etch rate differences of spacer materials |
| US6261913B1 (en) * | 2000-08-23 | 2001-07-17 | Micron Technology, Inc. | Method for using thin spacers and oxidation in gate oxides |
| JP2003023154A (ja) * | 2001-06-28 | 2003-01-24 | Hynix Semiconductor Inc | 半導体素子の製造方法 |
| CN2805096Y (zh) * | 2004-04-29 | 2006-08-09 | 台湾积体电路制造股份有限公司 | 半导体元件 |
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|---|---|
| CN2805096Y (zh) | 2006-08-09 |
| TWI236091B (en) | 2005-07-11 |
| US7259050B2 (en) | 2007-08-21 |
| US20050242376A1 (en) | 2005-11-03 |
| CN1694231A (zh) | 2005-11-09 |
| TW200536044A (en) | 2005-11-01 |
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