CN100350468C - CD recording signal control circuit - Google Patents
CD recording signal control circuit Download PDFInfo
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- CN100350468C CN100350468C CNB031502938A CN03150293A CN100350468C CN 100350468 C CN100350468 C CN 100350468C CN B031502938 A CNB031502938 A CN B031502938A CN 03150293 A CN03150293 A CN 03150293A CN 100350468 C CN100350468 C CN 100350468C
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Abstract
The present invention relates to a compact disc recording signal control circuit which uses a responsibility period regulating unit to regulate the responsibility period of the recording signal. The compact disc recording signal control circuit comprises an EFM encoder, a recording strategic wave form generating unit, a responsibility period regulating unit and a responsibility period detecting unit, wherein the EFM encoder is used for receiving input signals and encoding into EFM signals; the recording strategic wave form generating unit is used for receiving the EFM signals and generating multiple groups of recording signals according to the EFM signals; the responsibility period regulating unit is used for receiving the multiple groups of recording signals, regulating the responsibility periods of the multiple groups of recording signals and outputting multiple groups of regulated recording signals; the responsibility period detecting unit is used for receiving the multiple groups of regulated recording signals output by the responsibility period regulating unit, detecting the responsibility periods of the multiple groups of regulated recording signals and outputting responsibility period regulating signals. The responsibility period regulating unit also receives the responsibility period regulating signals so as to regulate the responsibility periods of the multiple groups of recording signals.
Description
Technical field
The present invention relates to a kind of CD baking signal control circuit.
Background technology
Fig. 1 shows in the general CD baking device, the calcspar of burning signal control circuit.As shown in the drawing, this burning signal control circuit 10 comprises an EFM scrambler (Eight-to-Fourteen Modulationencoder) 11, one recording strategy waveform generation unit (write strategy waveformgenerator) 12, one LD driver element (Laser diode driver) 13 and one LASER Light Source (LD) 14.EFM scrambler 11 receives the input data (input data) of wanting burning, and produces the EFM signal according to the EFM coding rule.Recording strategy waveform generation unit 12 is to receive the EFM signal, and according to this EFM signal and the characteristic of wanting the disc of burning, produces a plurality of burning signals (write signals), and for example shown in Figure 1 is three burning signals.Recording strategy waveform generation unit 12 generally is to comprise a recording strategy pulse generation unit 121, a flip-flop 122 and a burning signal computing unit 123.LD driver element 13 receives a plurality of burning signals, and produces one and drive signal and come driving laser light source 14.How producing a plurality of burning signals according to the EFM signal as for recording strategy waveform generation unit 12 is the known technology of the sector, and for example the U.S. the 6th, 445, and No. 661 patent discloses this technology in detail, therefore not repeat specification.
Along with the lifting of the replication rate of CD-ROM drive, more rigorous (critical) that the sequential of burning signal also becomes.Relative, because the digital logic gate of recording strategy waveform generation unit, impact damper and the output waveform that driver element caused are out of shape also become even more serious.The waveform that Figure 2 shows that three desirable burning signals and drive signal, wherein Fig. 2 (A) be three burning signals of recording strategy waveform generation unit 12 and Fig. 2 (B) driving signal for the generation of LD driver element.Because three burning signal WS1, WS2, WS3 do not produce distortion, so the driving signal that the LD driver element produces is quite desirable.
Figure 3 shows that the burning signal of distortion and drive signal that wherein Fig. 3 (A) be three burning signals of recording strategy waveform generation unit 12 and Fig. 3 (B) driving signal for the generation of LD driver element.As shown in Figure 3, because the responsibility cycle of three burning signal WS1, WS2, WS3 is non-50%, so the driving signal that produces of LD driver element gross distortion.If CD-ROM drive comes driving laser light source 14 with the driving signal that this is out of shape, then the data mistake takes place in the anxiety that the data of institute's burning may be wrong when reading this CD after causing.
Therefore, how to provide a burning signal to become an important problem with average responsibility cycle.
Summary of the invention
Because the problems referred to above, the purpose of this invention is to provide a kind of uneven CD baking signal control circuit of responsibility cycle of avoiding the burning signal, this device is to carry out responsibility cycle in advance to proofread and correct, adjust the responsibility cycle of each burning signal again, use the responsibility cycle inequality of avoiding the burning signal.
CD baking signal control circuit of the present invention is realized by following technical scheme.
A kind of CD baking signal control circuit comprises:
One EFM scrambler, receiving inputted signal also is encoded into the EFM signal;
One recording strategy waveform generation unit receives aforementioned EFM signal, and produces many group burning signals according to this EFM signal; It is characterized in that being provided with:
One responsibility cycle adjusting unit receives aforementioned many group burning signals, and adjusts the responsibility cycle of these many group burning signals, and the many groups of output adjusted burning signal.
Described CD baking signal control circuit, it is characterized in that: also comprise a responsibility cycle detecting unit, be to receive many groups adjusted burning signal that aforementioned responsibility cycle adjusting unit is exported, and detect the responsibility cycle of these many group adjusted burning signals, and the output responsibility cycle is adjusted signal.
Described CD baking signal control circuit is characterized in that: aforementioned responsibility cycle adjusting unit also receives aforementioned responsibility cycle and adjusts signal, uses the responsibility cycle of adjusting aforementioned many group burning signals.
Described CD baking signal control circuit is characterized in that: aforementioned CD baking signal control circuit also comprises:
One laser diode driver element is to receive aforementioned many group adjusted burning signals, and produces a drive signal; And
One laser diode is to receive aforementioned drive signal, and produces laser.
Described CD baking signal control circuit is characterized in that: aforementioned responsibility cycle adjusting unit is incorporated in the aforementioned recording strategy waveform generation unit.
Described CD baking signal control circuit is characterized in that: aforementioned responsibility cycle detecting unit is to be incorporated in the aforementioned recording strategy waveform generation unit.
Described CD baking signal control circuit is characterized in that: aforementioned EFM scrambler also receives a correction signal, uses when this correction signal is enabled, and the output responsibility cycle is that 50% reference signal replaces aforementioned EFM signal.
Described CD baking signal control circuit is characterized in that: aforementioned responsibility cycle adjusting unit has many group adjusting modules, and each adjusting module comprises:
One delay position control module receives aforementioned burning signal, and exports a delay position signal according to the state of this burning signal; And
One delay cell receives aforementioned burning signal and aforementioned delay position signal, and exports aforementioned adjusted burning signal according to this delay position signal;
Wherein, aforementioned delay position control module also receives aforementioned responsibility cycle and adjusts signal and aforementioned corrected signal, uses when this states the correction signal activation, adjusts the signal sets delay position according to this responsibility cycle.
Described CD baking signal control circuit is characterized in that: aforementioned delay cell comprises:
The delay bag of a plurality of serial connections receives aforementioned burning signal, and exports the inhibit signal of a plurality of different time delays; And
One multiplexer receives inhibit signal and the aforementioned delay position signal of aforementioned a plurality of different time delays, and selects one of them inhibit signal output according to this delay position signal, as aforementioned adjusted burning signal.
CD baking signal control circuit of the present invention comprises: an EFM scrambler is a receiving inputted signal and be encoded into the EFM signal; One recording strategy waveform generation unit is to receive the EFM signal, and produces many group burning signals according to this EFM signal; One responsibility cycle adjusting unit is to receive many group burning signals, and adjusts the responsibility cycle of these many group burning signals, and the many groups of output adjusted burning signal; And a responsibility cycle detecting unit, be to receive many groups adjusted burning signal that responsibility cycle adjusting unit is exported, and detect the responsibility cycle of these many group adjusted burning signals, and the output responsibility cycle is adjusted signal.And this responsibility cycle adjusting unit also receives responsibility cycle and adjusts signal, uses the responsibility cycle of adjusting many group burning signals.
The invention has the advantages that:
Can avoid the responsibility cycle inequality of burning signal, proofread and correct, adjust the responsibility cycle of each burning signal again, use the inequality of the responsibility cycle of avoiding the burning signal by carrying out responsibility cycle in advance.
Below enumerate specific embodiment and describe CD baking signal control circuit of the present invention with reference to the accompanying drawings in detail.
Description of drawings
Fig. 1 shows in the general CD baking device, the calcspar of burning signal control circuit.
Fig. 2 (A) is desirable burning signal.
The driving signal that Fig. 2 (B) is produced according to the burning signal of Fig. 2 (A) for the LD driver element.
Fig. 3 (A) is the burning signal of distortion.
The driving signal that Fig. 3 (B) is produced according to the burning signal of Fig. 3 (A) for the LD driver element.
Fig. 4 shows the calcspar of burning signal control circuit of the present invention.
In the responsibility cycle adjusting unit of Fig. 5 displayed map 4, the adjustment embodiment of circuit of each burning signal.
Fig. 6 (A) is the signal waveform of EFM scrambler output in the circuit of Fig. 4.
Fig. 6 (B) is the signal waveform of recording strategy pulse generation unit output in the circuit of Fig. 4.
Fig. 6 (C) is the signal waveform of flip-flop output in the circuit of Fig. 4.
Fig. 6 (D) is the signal waveform of burning signal computing unit output in the circuit of Fig. 4.
Fig. 6 (E) is the signal waveform of responsibility cycle adjusting unit output in the circuit of Fig. 4.
Fig. 7 shows the process flow diagram of bearing calibration of the responsibility cycle of burning signal of the present invention.
Fig. 8 shows the embodiment of circuit for detecting of the responsibility cycle of burning signal control circuit of the present invention.
Embodiment
Because known burning signal control circuit is directly to export the LD driver element to after producing the burning signal, further whether the responsibility cycle of this burning signal of detecting is not average.So this burning signal control circuit may cause burning signal skew or responsibility cycle inequality owing to digital logic gate, impact damper and output driver element equal error.Therefore, the present invention is in order to address this problem, utilize a responsibility cycle detecting unit to detect the responsibility cycle of burning signal especially, and utilize responsibility cycle adjusting unit to adjust the responsibility cycle of burning signal, make the responsibility cycle of the burning signal that exports the LD driver element to can be correct.
Fig. 4 shows the calcspar of burning signal control circuit of the present invention.This burning signal control circuit 40 comprises an EFM scrambler 41, a recording strategy waveform generation unit 42, a LD driver element 43, a LASER Light Source 44, a responsibility cycle adjusting unit 45 and a responsibility cycle detecting unit 46.EFM scrambler 41 receives the input data of wanting burning, and produces the EFM signal according to the EFM coding rule.Recording strategy waveform generation unit 42 is to receive the EFM signal, and produces a plurality of burning signals according to the EFM signal, and for example present embodiment is three burning signal WS1, WS2, WS3.Responsibility cycle adjusting unit 45 receives these a plurality of burning signal WS1, WS2, WS3, and after adjusting the responsibility cycle of each burning signal WS1, WS2, WS3, output adjusted burning signal AWS1, AWS2, AWS3.LD driver element 43 receives these a plurality of adjusted burning signal AWS1, AWS2, AWS3, and produces one and drive signal and come driving laser light source 44.The framework of recording strategy waveform generation unit 42, LD driver element 43 and LASER Light Source 44 is identical with function and known techniques, no longer repeat specification.And responsibility cycle detecting unit 46 is to receive and detect adjusted burning signal AWS1, AWS2, AWS3, and output responsibility cycle control signal is given responsibility cycle adjusting unit 45.
Burning signal control circuit 40 of the present invention has two kinds of operator schemes, and a kind of is that correction mode and another kind are operating modes.Correction mode is before the 40 beginning burnings of burning signal control circuit, proofreaies and correct the responsibility cycle of each burning signal earlier, and produces correction parameter; And the operating mode general burning pattern that is burning signal control circuit 40.
When burning signal control circuit 40 is in correction mode, responsibility cycle detecting unit 46 receives adjusted burning signal AWS1, AWS2, AWS3, and after detecting the responsibility cycle of each adjusted burning signal, produce the responsibility cycle control signal and give responsibility cycle adjusting unit 45.Responsibility cycle adjusting unit 45 is promptly adjusted correction parameter according to the responsibility cycle control signal, makes the responsibility cycle of each burning signal average.
In the responsibility cycle adjusting unit of Fig. 5 displayed map 4, the adjustment embodiment of circuit of each burning signal.As shown in Figure 5, the adjustment circuit of each burning signal of responsibility cycle adjusting unit 45 comprises a delay cell 51 and a delay position control module 54.Delay cell 51 is made of the delay bag (delaycell) 52 and a multiplexer 53 of a plurality of serial connections, is to be used for the output of inhibit signal.After a plurality of delay bags 52 receive burning signal WS, produce the inhibit signal of a plurality of different time delays, and export these inhibit signals to multiplexer 53.The retardation that multiplexer 53 is promptly exported according to delay position control module 54 is chosen inhibit signal output from a plurality of inhibit signals.Certainly, delay cell 51 only is a kind of embodiment, and other delay cell that can reach this function all can be applicable to the present invention.
Delay position control module 54 is to receive the responsibility cycle control signal, and sets correction parameter according to this responsibility cycle control signal when correction mode.At this, the burning signal is divided into leading edge and trailing edge, leading edge represents that the burning signal becomes high levels by low level, trailing edge represents that the burning signal becomes low level by high levels.When the responsibility cycle of burning signal greater than 50% the time, the cycle of expression high levels is long than the cycle of low level, therefore can utilize the delay leading edge to export the cycle that shortens high levels; Otherwise, when the responsibility cycle of burning signal less than 50% the time, the cycle of the cycle higher levels of expression low level is long, therefore can utilize the delay trailing edge to export the cycle that shortens low level.
Delay position control module 54 can utilize two counters to write down the retardation of leading edge and trailing edge respectively.For example, delay position control module 54 is when correction mode, and the responsibility cycle that shows the burning signal when the responsibility cycle control signal is greater than 50% the time, and then the count value with the leading edge counter adds 1, increases the output delay amount of leading edge; Otherwise the responsibility cycle that shows the burning signal when the responsibility cycle control signal is less than 50% the time, and then the count value with the trailing edge counter adds 1, increases the output delay amount of trailing edge.If be T1 each time delay that postpones bag 52, retardation of then every increase, expression is with T1 time of signal delay.
Because responsibility cycle adjusting unit 45 is for the retardation of the leading edge of burning signal and trailing edge and inequality, therefore, delay position control module 54 also must be according to the different retardation of the accurate output in the position of burning signal to delay cell 51.When delay position control module 54 became high levels at the burning signal by low level, the count value of output leading edge counter was as retardation, and delay cell 51 can postpone the leading edge of output burning signal according to this retardation.Opposite, when delay position control module 54 became low level at the burning signal by high levels, the count value of output trailing edge counter was as retardation, and delay cell 51 can postpone the trailing edge of output burning signal according to this retardation.
The waveform of part signal in the circuit of Fig. 6 displayed map 4, wherein Fig. 6 (A) is the signal waveform of recording strategy pulse generation unit output, the signal waveform that Fig. 6 (C) exports for flip-flop, the burning signal waveform that Fig. 6 (D) is the output of burning signal computing unit, the adjusted burning signal waveform that Fig. 6 (E) exports for responsibility cycle adjusting unit for signal waveform, Fig. 6 (B) of the output of EFM scrambler.As shown in Figure 6, when burning signal control circuit 40 was correction mode, the 1T signal of EFM scrambler 41 outputs 50% responsibility cycle was used the delay parameter that is used for proofreading and correct the burning signal.With shown in 6 (D), cause the responsibility cycle inequality of the signal of recording strategy pulse generation unit, flip-flop and the output of burning signal computing unit as Fig. 6 (B), Fig. 6 (C) owing to the characteristic of recording strategy waveform generation unit 42.But,, export that the responsibility cycle of adjusted burning signal of LD driver element 43 is modulated to be made into 50% to through after the adjustment of responsibility cycle adjusting unit 45.
Fig. 7 shows the process flow diagram of bearing calibration of the responsibility cycle of burning signal of the present invention.As shown in the drawing, its step is as follows:
Step S702:, and set the number of corrections initial value with the correction signal activation.That is, will proofread and correct times N and be set at 0.
Step S704: the reference signal of exporting 50% responsibility cycle.After the correction signal activation, EFM scrambler 41 is promptly exported the signal of 50% responsibility cycle as the reference signal.
Step S706: the responsibility cycle of detecting burning signal.If responsibility cycle greater than 50%, then skips to step S708, otherwise skips to step S710.
Step S708: reduce responsibility cycle.The count value that also is about to the leading edge counter adds 1, or the count value of trailing edge counter is subtracted 1 (when the count value of trailing edge counter greater than 0 the time).Afterwards, skip to step S714.
Step S710: the responsibility cycle of detecting burning signal.If responsibility cycle less than 50%, then skips to step S712, otherwise skips to step S714.
Step S712: improve responsibility cycle.The count value that also is about to the trailing edge counter adds 1, or the count value of leading edge counter is subtracted 1 (when the count value of leading edge counter greater than 0 the time).Afterwards, and skip to step S714.
Step S714: the number of corrections that adds up N.That is, N=N+1.
Step S716: compare number of corrections N.As number of corrections N during greater than a default value M, then finish to proofread and correct, otherwise rebound step S706.
Because the present invention utilizes a responsibility cycle adjusting unit to adjust the responsibility cycle of each burning signal, therefore, the responsibility cycle that can guarantee to export to the burning signal of LD driver element 43 is 50%.
Fig. 8 shows the embodiment of circuit for detecting of the responsibility cycle of burning signal control circuit of the present invention.As shown in Figure 8, the input signal Vin of this circuit for detecting 80 is adjusted burning signal AWS1, AWS2 or AWS3, and utilize a plurality of nmos pass transistor NG, a plurality of PMOS transistor PG, a reverser 81 and a capacitor C to detect the responsibility cycle of each adjusted burning signal, produce responsibility cycle control signal Vduty.This responsibility cycle control signal Vduty is directly proportional with responsibility cycle.That is, when this responsibility cycle control signal is pressed Vduty greater than a critical voltage value (Threshold) Vth, represent responsibility cycle greater than 50%, otherwise, as this responsibility cycle control signal Vduty during less than this critical voltage value Vth, the expression responsibility cycle is less than 50%.Delay position control module 54 is promptly adjusted retardation according to this responsibility cycle control signal Vduty.Delay position control module 54 can utilize two counters to write down the retardation of leading edge and trailing edge respectively.For example, delay position control module 54 is when correction mode, and as responsibility cycle control signal Vduty during greater than critical voltage value, then the count value with the leading edge counter adds 1, increase the output delay amount of leading edge, or the trailing edge counter is subtracted 1 greater than 1 the time when the trailing edge counter; Otherwise as responsibility cycle control signal Vduty during less than critical voltage value, then the count value with the trailing edge counter adds 1, increases the output delay amount of trailing edge, or the leading edge counter is subtracted 1 greater than 1 the time when the leading edge counter.
Though more than with embodiment the present invention is described, therefore do not limit scope of the present invention, only otherwise break away from main idea of the present invention, the sector person can carry out various distortion or change.For example, the responsibility cycle detecting unit among the embodiment is also configurable in the recording strategy waveform generation unit.
Claims (9)
1, a kind of CD baking signal control circuit comprises:
One EFM scrambler, receiving inputted signal also is encoded into the EFM signal;
One recording strategy waveform generation unit receives aforementioned EFM signal, and produces a plurality of burning signals according to this EFM signal; It is characterized in that being provided with:
One responsibility cycle adjusting unit receives aforementioned a plurality of burning signal, and adjusts the responsibility cycle of aforementioned a plurality of burning signals, and the many groups of output adjusted burning signal.
2, CD baking signal control circuit according to claim 1, it is characterized in that: also comprise a responsibility cycle detecting unit, be to receive a plurality of adjusted burning signals that aforementioned responsibility cycle adjusting unit is exported, and detect the responsibility cycle of aforementioned a plurality of adjusted burning signals, and the output responsibility cycle is adjusted signal.
3, CD baking signal control circuit according to claim 2 is characterized in that: aforementioned responsibility cycle adjusting unit also receives aforementioned responsibility cycle and adjusts signal, uses the responsibility cycle of adjusting aforementioned a plurality of burning signals.
4, CD baking signal control circuit according to claim 3 is characterized in that: aforementioned CD baking signal control circuit also comprises:
One laser diode driver element is to receive aforementioned a plurality of adjusted burning signals, and produces a drive signal; And
One laser diode is to receive aforementioned drive signal, and produces laser.
5, CD baking signal control circuit according to claim 2 is characterized in that: aforementioned responsibility cycle adjusting unit is incorporated in the aforementioned recording strategy waveform generation unit.
6, CD baking signal control circuit according to claim 5 is characterized in that: aforementioned responsibility cycle detecting unit is to be incorporated in the aforementioned recording strategy waveform generation unit.
7, CD baking signal control circuit according to claim 1 is characterized in that: aforementioned EFM scrambler also receives a correction signal, uses when this correction signal is enabled, and the output responsibility cycle is that 50% reference signal replaces aforementioned EFM signal.
8, CD baking signal control circuit according to claim 1, it is characterized in that: aforementioned responsibility cycle adjusting unit comprises:
One delay position control module receives aforementioned burning signal, and exports a delay position signal according to the state of this burning signal; And
One delay cell receives aforementioned burning signal and aforementioned delay position signal, and exports aforementioned adjusted burning signal according to this delay position signal;
Wherein, aforementioned delay position control module also receives a responsibility cycle and adjusts a signal and a correction signal, uses when the activation of aforementioned corrected signal, adjusts the signal sets delay position according to this responsibility cycle.
9, CD baking signal control circuit according to claim 8, it is characterized in that: aforementioned delay cell comprises:
The delay bag of a plurality of serial connections receives aforementioned burning signal, and exports the inhibit signal of a plurality of different time delays; And
One multiplexer receives inhibit signal and the aforementioned delay position signal of aforementioned a plurality of different time delays, and selects one of them inhibit signal output according to this delay position signal, as aforementioned adjusted burning signal.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB031502938A CN100350468C (en) | 2003-07-23 | 2003-07-23 | CD recording signal control circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB031502938A CN100350468C (en) | 2003-07-23 | 2003-07-23 | CD recording signal control circuit |
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| CN1571025A CN1571025A (en) | 2005-01-26 |
| CN100350468C true CN100350468C (en) | 2007-11-21 |
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1312553A (en) * | 2000-02-26 | 2001-09-12 | 三星电子株式会社 | Circuit and method for preventing recording error and method thereof |
| US20020051415A1 (en) * | 2000-10-26 | 2002-05-02 | Matsushita Electric Industrial Co., Ltd. | Recording waveform generator and disk recording device |
| US6445661B1 (en) * | 1999-08-11 | 2002-09-03 | Oak Technology, Inc. | Circuit, disk controller and method for calibrating a high precision delay of an input signal |
| JP2002334434A (en) * | 2001-05-01 | 2002-11-22 | Matsushita Electric Ind Co Ltd | Delay control circuit |
| US20030107967A1 (en) * | 1999-09-09 | 2003-06-12 | Calimetrics, Inc. | Programmable write signal generator |
| CN1114905C (en) * | 1998-11-06 | 2003-07-16 | 松下电器产业株式会社 | Method and device for finding conditions on recording pulse of optical disk |
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2003
- 2003-07-23 CN CNB031502938A patent/CN100350468C/en not_active Expired - Fee Related
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1114905C (en) * | 1998-11-06 | 2003-07-16 | 松下电器产业株式会社 | Method and device for finding conditions on recording pulse of optical disk |
| US6445661B1 (en) * | 1999-08-11 | 2002-09-03 | Oak Technology, Inc. | Circuit, disk controller and method for calibrating a high precision delay of an input signal |
| US20030107967A1 (en) * | 1999-09-09 | 2003-06-12 | Calimetrics, Inc. | Programmable write signal generator |
| CN1312553A (en) * | 2000-02-26 | 2001-09-12 | 三星电子株式会社 | Circuit and method for preventing recording error and method thereof |
| US20020051415A1 (en) * | 2000-10-26 | 2002-05-02 | Matsushita Electric Industrial Co., Ltd. | Recording waveform generator and disk recording device |
| JP2002334434A (en) * | 2001-05-01 | 2002-11-22 | Matsushita Electric Ind Co Ltd | Delay control circuit |
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