JP2002334434A - Delay control circuit - Google Patents
Delay control circuitInfo
- Publication number
- JP2002334434A JP2002334434A JP2001133737A JP2001133737A JP2002334434A JP 2002334434 A JP2002334434 A JP 2002334434A JP 2001133737 A JP2001133737 A JP 2001133737A JP 2001133737 A JP2001133737 A JP 2001133737A JP 2002334434 A JP2002334434 A JP 2002334434A
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- Prior art keywords
- delay
- reference clock
- buffer
- delay amount
- stages
- Prior art date
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- Signal Processing For Digital Recording And Reproducing (AREA)
- Optical Recording Or Reproduction (AREA)
- Pulse Circuits (AREA)
Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明は、CD−R,CD−
RW等の光ディスクに記録する制御装置における遅延制
御回路に関するものである。TECHNICAL FIELD The present invention relates to a CD-R, a CD-R,
The present invention relates to a delay control circuit in a control device that records data on an optical disk such as an RW.
【0002】[0002]
【従来の技術】書き換え可能型光ディスク媒体の一つと
してCD−RWがある。CD−RWは、CDフォーマッ
トである3T〜11Tの長さの図4(a)のようなEF
M信号をレーザー光の照射により記録するもので、レー
ザーの照射方法として一つのマーク長に対して図4
(b)に示すような複数のパルス光を一定間隔で照射す
ることにより図4(c)に示すように一つのマーク長を
書き込むというものである。2. Description of the Related Art One of rewritable optical disk media is a CD-RW. The CD-RW is an EF as shown in FIG.
The M signal is recorded by irradiating a laser beam. The laser irradiation method is shown in FIG.
By irradiating a plurality of pulsed lights as shown in (b) at regular intervals, one mark length is written as shown in FIG. 4 (c).
【0003】CD−R,CD−RW等では、形成しよう
とするマーク長に対するパルスの全体の幅は余熱の影響
を考慮して、図4(d)のパルス波形のようにマーク長
より幾分小さく設定して図4(e)に示すように書き込
む必要があり、さらに、マーク長の長さ、前書き込みか
らの距離、時間によっても余熱の影響が異なるため、パ
ルス波形の長さには細かい設定が必要である。その上、
光ディスクに情報を記録する場合、高倍速での書き込み
が必須条件となりつつある。したがって、高倍速での書
き込みではそれぞれのパルス幅をより高精度で細かく調
整する必要がある。In CD-R, CD-RW, etc., the overall width of the pulse with respect to the mark length to be formed is somewhat smaller than the mark length as shown in the pulse waveform of FIG. As shown in FIG. 4 (e), it is necessary to perform writing with a small value. Further, the influence of residual heat varies depending on the length of the mark, the distance from the previous writing, and the time. Settings are required. Moreover,
When recording information on an optical disk, writing at a high speed is becoming an essential condition. Therefore, in writing at a high speed, it is necessary to finely adjust each pulse width with higher accuracy.
【0004】図5は従来の遅延制御回路を示し、図6は
基準クロックと遅延信号との関係を示す。図5におい
て、2は光ディスクに書き込みする信号の基準クロック
1を遅延させる遅延バッファ、3は遅延量セレクタ、4
は基準クロック1周期遅延セレクタ、5は基準クロック
1周期検出回路、6は基準クロック1周期遅延信号、7
は基準クロック1周期遅延段数信号、8は遅延量選択回
路、9は遅延バッファ段数選択信号、10は遅延信号で
ある。FIG. 5 shows a conventional delay control circuit, and FIG. 6 shows a relationship between a reference clock and a delay signal. In FIG. 5, reference numeral 2 denotes a delay buffer for delaying a reference clock 1 of a signal to be written on an optical disk, 3 denotes a delay amount selector,
Is a reference clock one cycle delay selector, 5 is a reference clock one cycle detection circuit, 6 is a reference clock one cycle delay signal, 7
Is a reference clock one cycle delay stage number signal, 8 is a delay amount selection circuit, 9 is a delay buffer stage number selection signal, and 10 is a delay signal.
【0005】基準クロック1が基準クロック1周期遅延
セレクタ4および基準クロック1周期検出回路5に入力
され、遅延量選択回路8で選択された遅延バッファ段数
だけ遅延バッファ2を通り、任意の遅延量の遅延信号1
0が出力される。A reference clock 1 is input to a reference clock one-cycle delay selector 4 and a reference clock one-cycle detection circuit 5, passes through the delay buffer 2 by the number of delay buffers selected by the delay amount selection circuit 8, and has an arbitrary delay amount. Delay signal 1
0 is output.
【0006】この際、温度変化や電圧変動などの外的要
因によって遅延バッファ2の遅延量が変化するので、ま
ず基準クロック1周期検出回路5で、図6(e)のよう
に基準クロック1の1周期分だけ遅延したことを検出
し、遅延バッファ2の段数mを得る。At this time, since the delay amount of the delay buffer 2 changes due to external factors such as temperature change and voltage change, first, the reference clock 1 cycle detection circuit 5 detects the reference clock 1 as shown in FIG. Detecting that the signal is delayed by one cycle, the number m of stages of the delay buffer 2 is obtained.
【0007】ここで、遅延バッファ2は全て同じ性能の
バッファを用いた構成にしておくと、図6(b)のよう
に各遅延バッファ2の遅延量はほぼ同じであると考えら
れるため、(遅延バッファ1段の遅延量)=(基準クロ
ック周期)/(1周期分の段数m)となる。Here, if the delay buffers 2 are all configured to use buffers having the same performance, the delay amounts of the delay buffers 2 are considered to be substantially the same as shown in FIG. The delay amount of one stage of the delay buffer) = (reference clock cycle) / (the number m of stages for one cycle).
【0008】例として具体的に数値を挙げると、基準ク
ロック1の周期が4.8nsecで、図7のように、遅延バッ
ファ2が24段で基準クロック1周期と検出された場
合、例えば1.2nsecは遅延バッファ2の6段目、2.4nsec
は遅延バッファ2の12段目を選択することになる。As a specific example, when the numerical value of the reference clock 1 is 4.8 nsec and the delay buffer 2 detects one cycle of the reference clock in 24 stages as shown in FIG. 6th stage of delay buffer 2, 2.4nsec
Selects the twelfth stage of the delay buffer 2.
【0009】このようにして遅延バッファ2の段数を、
遅延量選択回路8で選択した遅延バッファ段数選択信号
9を遅延量セレクタ3に入力し、遅延信号10を出力し
ている。Thus, the number of stages of the delay buffer 2 is
A delay buffer stage number selection signal 9 selected by the delay amount selection circuit 8 is input to the delay amount selector 3 and a delay signal 10 is output.
【0010】[0010]
【発明が解決しようとする課題】しかしながら、高倍速
での書き込みが必須条件となってきているため、高倍速
になるほどより精度の高い遅延信号が要求されてくる。
従来、各遅延バッファは同じ性能のバッファを使用する
ことで図6のように各遅延バッファの遅延量はほぼ同じ
として遅延信号を生成していたが、実際は配線負荷等の
影響で各遅延バッファの遅延量にはバラツキがあり、書
き込みが高倍速になるほどこのバラツキによる遅延量の
誤差が書き込みの精度に影響してくる。However, since writing at a high speed is becoming an essential condition, a higher accuracy delay signal is required at higher speeds.
Conventionally, each delay buffer uses the same performance buffer to generate a delay signal assuming that the delay amount of each delay buffer is almost the same as shown in FIG. The amount of delay varies, and the error in the amount of delay due to the variation affects the accuracy of writing as the writing speed increases.
【0011】本発明は、上記問題点を解決し、各遅延バ
ッファのバラツキも考慮して遅延量を計算することによ
り、より高精度の遅延信号を生成することができる遅延
制御回路を提供することを目的とする。An object of the present invention is to provide a delay control circuit which can solve the above problems and calculate a delay amount in consideration of variations in delay buffers to generate a more accurate delay signal. With the goal.
【0012】[0012]
【課題を解決するための手段】本発明の遅延制御回路
は、各遅延バッファのバラツキも考慮して遅延バッファ
遅延量テーブルを設け、遅延バッファ遅延量テーブルの
遅延量を測定したときの基準クロック1周期分だけ遅延
する遅延バッファの段数nと、基準クロック1周期検出
回路で検出した段数mの比n/mを遅延バッファ遅延量
テーブルの遅延量に乗じて補正することにより、より高
精度の遅延信号を生成する。The delay control circuit of the present invention provides a delay buffer delay amount table in consideration of the variation of each delay buffer, and uses the reference clock 1 when measuring the delay amount in the delay buffer delay amount table. By correcting the ratio n / m of the number n of stages of the delay buffer that is delayed by the period and the number m of stages detected by the reference clock one-cycle detection circuit by multiplying the delay amount in the delay buffer delay amount table, a more accurate delay is achieved. Generate a signal.
【0013】この構成によると、より高精度の遅延信号
を生成することができる。According to this configuration, a more accurate delayed signal can be generated.
【0014】[0014]
【発明の実施の形態】本発明の遅延制御回路は、光ディ
スクに書き込む信号の基準クロックを遅延させる遅延バ
ッファと、前記基準クロックが1周期分遅延したことを
検出する基準クロック1周期検出回路と、前記基準クロ
ック1周期検出回路によって検出された前記遅延バッフ
ァの段数を切り換える基準クロック1周期遅延セレクタ
と、前記遅延バッファのそれぞれの遅延情報を格納して
ある遅延バッファ遅延量テーブルと、前記基準クロック
1周期検出回路によって検出された前記遅延バッファの
段数と前記遅延バッファ遅延量テーブルの情報を元に遅
延量を計算し選択する遅延量選択回路と、前記遅延量選
択回路によって選択された前記遅延バッファの段数を切
り換える遅延量セレクタとを設けたことを特徴とする。DESCRIPTION OF THE PREFERRED EMBODIMENTS A delay control circuit according to the present invention comprises: a delay buffer for delaying a reference clock of a signal to be written on an optical disk; a reference clock one cycle detection circuit for detecting that the reference clock is delayed by one cycle; A reference clock one-period delay selector for switching the number of stages of the delay buffer detected by the reference clock one-period detection circuit, a delay buffer delay amount table storing delay information of each of the delay buffers, A delay amount selection circuit that calculates and selects a delay amount based on the number of stages of the delay buffer detected by the cycle detection circuit and information of the delay buffer delay amount table; and a delay amount selection circuit that selects the delay buffer selected by the delay amount selection circuit. A delay amount selector for switching the number of stages is provided.
【0015】以下、本発明の実施の形態を図1と図2,
図3に基づいて説明する。図1は本発明の遅延制御回路
を示す。2は光ディスクに書き込みする信号の基準クロ
ック1を遅延させる遅延バッファ、3は遅延量セレク
タ、4は基準クロック1周期遅延セレクタ、5は基準ク
ロック1周期検出回路、6は基準クロック1周期遅延信
号、7は基準クロック1周期遅延段数信号、8aは遅延
量選択回路、9は遅延量選択信号、10は遅延信号、1
1は遅延バッファ遅延量テーブルである。An embodiment of the present invention will be described below with reference to FIGS.
This will be described with reference to FIG. FIG. 1 shows a delay control circuit according to the present invention. 2 is a delay buffer for delaying a reference clock 1 of a signal to be written on the optical disk, 3 is a delay amount selector, 4 is a reference clock 1 cycle delay selector, 5 is a reference clock 1 cycle detection circuit, 6 is a reference clock 1 cycle delay signal, 7 is a reference clock one cycle delay stage number signal, 8a is a delay amount selection circuit, 9 is a delay amount selection signal, 10 is a delay signal, 1
1 is a delay buffer delay amount table.
【0016】遅延量選択回路8aに接続された遅延バッ
ファ遅延量テーブル11には、遅延バッファ2のそれぞ
れの遅延情報を格納してある。遅延量選択回路8aは、
基準クロック1周期検出回路5によって検出された前記
遅延バッファ2の段数と前記遅延バッファ遅延量テーブ
ル11の情報を元に遅延量を計算し選択するよう構成さ
れている。The delay buffer delay amount table 11 connected to the delay amount selection circuit 8a stores delay information of each of the delay buffers 2. The delay amount selection circuit 8a
The delay amount is calculated and selected based on the number of stages of the delay buffer 2 detected by the reference clock 1 cycle detection circuit 5 and the information of the delay buffer delay amount table 11.
【0017】遅延量選択回路8aの構成を動作に基づい
て詳細に説明する。任意の遅延量を選択する場合、例え
ばレイアウト情報を元にシミュレーションをするなどし
て配線負荷などを考慮した各遅延バッファ2の遅延量の
情報を求め、図2(a)のような遅延バッファ遅延量テ
ーブル11を設ける。The configuration of the delay amount selection circuit 8a will be described in detail based on the operation. When an arbitrary delay amount is selected, information on the delay amount of each delay buffer 2 in consideration of the wiring load and the like is obtained by performing a simulation based on layout information, for example, and the delay buffer delay as shown in FIG. A quantity table 11 is provided.
【0018】そして従来と同様に、まず基準クロック1
周期検出回路5で、基準クロック1の1周期分だけ遅延
する遅延バッファ2の段数mを検出し基準クロック1周
期遅延信号6を出力する。温度変化や電圧変動などの外
的要因によって各遅延バッファ2の遅延量が変化するの
で、遅延量選択回路8aは、遅延バッファ遅延量テーブ
ル11の遅延量を測定したときの基準クロック1周期分
だけ遅延する遅延バッファ2の段数nと、基準クロック
1周期検出回路5で検出した段数mの比に応じて、遅延
バッファ遅延量テーブル11の遅延量に n/m を乗
じて遅延量を補正するように構成されている。Then, as in the prior art, first, the reference clock 1
The cycle detection circuit 5 detects the number m of stages of the delay buffer 2 that is delayed by one cycle of the reference clock 1 and outputs a reference clock one cycle delay signal 6. Since the delay amount of each delay buffer 2 changes due to an external factor such as a temperature change or a voltage change, the delay amount selection circuit 8a operates only for one cycle of the reference clock when the delay amount of the delay buffer delay amount table 11 is measured. The delay amount is corrected by multiplying the delay amount in the delay buffer delay amount table 11 by n / m according to the ratio of the number n of stages of the delay buffer 2 to be delayed to the number m of stages detected by the reference clock 1 cycle detection circuit 5. Is configured.
【0019】例えば、図2(a)のような遅延バッファ
遅延量テーブル11で、基準クロック1が4.8nsec、遅
延バッファ2が24段で基準クロック1周期と検出され
た場合、すなわち遅延バッファ遅延量テーブル11の遅
延量を測定したときと同条件で動作している場合、図2
(b)に示すように1.2nsecは遅延バッファ2の7段
目、2.4nsecは13段目、3.6nsecは19段目となり、実
際の遅延量はそれぞれ1.22nsec,2.41nsec,3.63nsecとな
る。括弧内の遅延量は遅延バッファ遅延量テーブル後円
量から計算した値である。For example, in the delay buffer delay amount table 11 as shown in FIG. 2A, when the reference clock 1 is detected as 4.8 nsec and the delay buffer 2 is detected as one cycle of the reference clock in 24 stages, that is, the delay buffer delay amount When operating under the same conditions as when measuring the delay amount in Table 11, FIG.
As shown in (b), 1.2nsec is the seventh stage of the delay buffer 2, 2.4nsec is the 13th stage, and 3.6nsec is the 19th stage, and the actual delay amounts are 1.22nsec, 2.41nsec and 3.63nsec, respectively. The delay amount in parentheses is a value calculated from the circle amount after the delay buffer delay amount table.
【0020】それに対して遅延バッファ遅延量テーブル
11を有していない従来の回路では、図2(c)に示す
ように1.2nsecは遅延バッファ2の段数が6段目、2.4ns
ecは12段目、3.6nsecは18段目となり、実際の遅延
量はそれぞれ1.07nsec,2.23nsec,3.46nsecとなるので、
この実施の形態よりも誤差が大きいことがわかる。On the other hand, in the conventional circuit having no delay buffer delay amount table 11, as shown in FIG. 2C, the number of stages of the delay buffer 2 is 1.2 ns and the delay buffer 2 is 2.4 ns.
ec is the 12th stage, 3.6nsec is the 18th stage, and the actual delay amounts are 1.07nsec, 2.23nsec, 3.46nsec, respectively.
It can be seen that the error is larger than in this embodiment.
【0021】上記のように遅延バッファ遅延量テーブル
11の遅延量を測定して書き込んでおくと、基準クロッ
ク1周期検出回路5によって、遅延バッファ2が16段
で基準クロック1周期と検出された場合には、遅延量選
択回路8aは図3(a)の遅延量のように遅延バッファ
遅延量テーブル11の遅延量に24/16をかけた値が
各遅延バッファ2の遅延量と計算処理され、遅延バッフ
ァ2の段数は、図3(b)に示すように1.2nsecは4
段、2.4nsecは9段、3.6nsecは13段となり、実際の遅
延量はそれぞれ1.11nsec,2.52nsec,3.68nsecとなる。As described above, if the delay amount in the delay buffer delay amount table 11 is measured and written, the reference clock 1 cycle detection circuit 5 detects that the delay buffer 2 has one cycle of the reference clock in 16 stages. 3A, the delay amount selection circuit 8a calculates a value obtained by multiplying the delay amount of the delay buffer delay amount table 11 by 24/16 like the delay amount of FIG. As shown in FIG. 3B, the number of stages of the delay buffer 2 is 1.2 nsec = 4.
The stages, 2.4 nsec are 9 stages, and 3.6 nsec are 13 stages, and the actual delay amounts are 1.11 nsec, 2.52 nsec, and 3.68 nsec, respectively.
【0022】この場合も、従来の回路での遅延バッファ
2の段数は、図3(c)に示すように1.2nsecは4段、
2.4nsecは8段、3.6nsecは12段となり、実際の遅延量
はそれぞれ1.11nsec、2.20nsec,3.39nsecとなり、この
実施の形態の方が誤差が小さいことがわかる。Also in this case, the number of stages of the delay buffer 2 in the conventional circuit is 1.2 nsec, as shown in FIG.
2.4nsec has 8 stages and 3.6nsec has 12 stages, and the actual delay amounts are 1.11nsec, 2.20nsec, and 3.39nsec, respectively. It can be seen that the error is smaller in this embodiment.
【0023】このようにして遅延バッファ2の段数を遅
延量選択回路8aで選択した遅延バッファ段数選択信号
9を遅延量セレクタ3に入力して遅延信号10を出力す
る。The delay buffer stage number selection signal 9 having the number of stages of the delay buffer 2 selected by the delay amount selection circuit 8a is input to the delay amount selector 3 and the delay signal 10 is output.
【0024】[0024]
【発明の効果】以上のように本発明は、各遅延バッファ
のバラツキも考慮して遅延バッファ遅延量テーブルを設
け、遅延バッファ遅延量テーブルの遅延量を測定したと
きの基準クロック1周期分だけ遅延する遅延バッファの
段数nと、基準クロック1周期検出回路で検出した段数
mの比n/mを遅延バッファ遅延量テーブルの遅延量に
乗じて補正することにより、より高精度の遅延信号を生
成することができ、この遅延信号を用いて書き込みのパ
ルスを生成することで、配線負荷等の原因で各遅延バッ
ファの遅延量のバラツキが生じることによる高倍速の書
き込み精度を上げることができる。また、拡散工程で生
じるバラツキの影響についても軽減させることができ
る。As described above, according to the present invention, a delay buffer delay amount table is provided in consideration of the variation of each delay buffer, and the delay is delayed by one reference clock cycle when the delay amount of the delay buffer delay amount table is measured. By multiplying the ratio n / m of the number of stages n of the delay buffer to be executed and the number m of stages detected by the reference clock one-cycle detection circuit by the delay amount in the delay buffer delay amount table, a more accurate delay signal is generated. By generating a write pulse using this delay signal, it is possible to increase the write accuracy at a high double speed due to a variation in the delay amount of each delay buffer due to a wiring load or the like. In addition, it is possible to reduce the influence of variations generated in the diffusion step.
【図1】本発明の実施の形態の遅延制御回路の構成図FIG. 1 is a configuration diagram of a delay control circuit according to an embodiment of the present invention.
【図2】同実施の形態の遅延バッファ遅延量テーブルの
説明図FIG. 2 is an explanatory diagram of a delay buffer delay amount table according to the embodiment;
【図3】同実施の形態の実動作時の遅延量の説明図FIG. 3 is an explanatory diagram of a delay amount in an actual operation of the embodiment.
【図4】信号書き込み時の波形図FIG. 4 is a waveform diagram at the time of signal writing.
【図5】従来の構成における遅延制御回路の構成図FIG. 5 is a configuration diagram of a delay control circuit in a conventional configuration.
【図6】従来の構成における基準クロックと遅延信号と
の関係を示すタイミング図FIG. 6 is a timing chart showing a relationship between a reference clock and a delay signal in a conventional configuration.
【図7】従来の構成における遅延バッファの遅延量の説
明図FIG. 7 is an explanatory diagram of a delay amount of a delay buffer in a conventional configuration.
1 基準クロック 2 遅延バッファ 3 遅延量セレクタ 4 基準クロック1周期遅延セレクタ 5 基準クロック1周期検出回路 6 基準クロック1周期遅延信号 7 基準クロック1周期遅延段数信号 8a 遅延量選択回路 9 遅延量選択信号 10 遅延信号 11 遅延バッファ遅延量テーブル DESCRIPTION OF SYMBOLS 1 Reference clock 2 Delay buffer 3 Delay amount selector 4 Reference clock 1 cycle delay selector 5 Reference clock 1 cycle detection circuit 6 Reference clock 1 cycle delay signal 7 Reference clock 1 cycle delay stage number signal 8a Delay amount selection circuit 9 Delay amount selection signal 10 Delay signal 11 Delay buffer delay amount table
フロントページの続き Fターム(参考) 5B079 AA10 CC02 DD06 5D044 AB01 BC04 CC06 GM02 GM15 5D090 AA01 BB03 BB07 CC01 DD05 EE01 FF17 FF21 KK04 5J001 AA11 DD09 Continued on the front page F term (reference) 5B079 AA10 CC02 DD06 5D044 AB01 BC04 CC06 GM02 GM15 5D090 AA01 BB03 BB07 CC01 DD05 EE01 FF17 FF21 KK04 5J001 AA11 DD09
Claims (1)
を遅延させる遅延バッファと、 前記基準クロックが1周期分遅延したことを検出する基
準クロック1周期検出回路と、 前記基準クロック1周期検出回路によって検出された前
記遅延バッファの段数を切り換える基準クロック1周期
遅延セレクタと、 前記遅延バッファのそれぞれの遅延情報を格納してある
遅延バッファ遅延量テーブルと、 前記基準クロック1周期検出回路によって検出された前
記遅延バッファの段数と前記遅延バッファ遅延量テーブ
ルの情報を元に遅延量を計算し選択する遅延量選択回路
と、 前記遅延量選択回路によって選択された前記遅延バッフ
ァの段数を切り換える遅延量セレクタとを設けた遅延制
御回路。1. A delay buffer for delaying a reference clock of a signal to be written on an optical disk, a reference clock one-cycle detection circuit for detecting that the reference clock is delayed by one period, and a detection signal detected by the reference clock one-cycle detection circuit. A reference clock one-cycle delay selector for switching the number of stages of the delay buffer, a delay buffer delay amount table storing delay information of each of the delay buffers, and the delay buffer detected by the reference clock one-cycle detection circuit. A delay amount selection circuit that calculates and selects a delay amount based on the number of stages and the information of the delay buffer delay amount table, and a delay amount selector that switches the number of stages of the delay buffer selected by the delay amount selection circuit. Delay control circuit.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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JP2001133737A JP2002334434A (en) | 2001-05-01 | 2001-05-01 | Delay control circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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JP2001133737A JP2002334434A (en) | 2001-05-01 | 2001-05-01 | Delay control circuit |
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JP2002334434A true JP2002334434A (en) | 2002-11-22 |
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JP2001133737A Pending JP2002334434A (en) | 2001-05-01 | 2001-05-01 | Delay control circuit |
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Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100633000B1 (en) | 2003-12-17 | 2006-10-11 | 세이코 엡슨 가부시키가이샤 | Delay adjustment circuit, integrated circuit device, and delay adjustment method |
CN100350468C (en) * | 2003-07-23 | 2007-11-21 | 联发科技股份有限公司 | CD recording signal control circuit |
US7471599B2 (en) | 2003-07-04 | 2008-12-30 | Mediatek Inc. | Write signal control circuit in an optical disk drive |
WO2010098460A1 (en) * | 2009-02-27 | 2010-09-02 | 古野電気株式会社 | Phase determining device and frequency determining device |
-
2001
- 2001-05-01 JP JP2001133737A patent/JP2002334434A/en active Pending
Cited By (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7471599B2 (en) | 2003-07-04 | 2008-12-30 | Mediatek Inc. | Write signal control circuit in an optical disk drive |
CN100350468C (en) * | 2003-07-23 | 2007-11-21 | 联发科技股份有限公司 | CD recording signal control circuit |
KR100633000B1 (en) | 2003-12-17 | 2006-10-11 | 세이코 엡슨 가부시키가이샤 | Delay adjustment circuit, integrated circuit device, and delay adjustment method |
US7126400B2 (en) | 2003-12-17 | 2006-10-24 | Seiko Epson Corporation | Delay adjustment circuit, integrated circuit device, and delay adjustment method |
WO2010098460A1 (en) * | 2009-02-27 | 2010-09-02 | 古野電気株式会社 | Phase determining device and frequency determining device |
EP2402772A1 (en) * | 2009-02-27 | 2012-01-04 | Furuno Electric Co., Ltd. | Phase determining device and frequency determining device |
CN102334038A (en) * | 2009-02-27 | 2012-01-25 | 古野电气株式会社 | Phase determining device and frequency determining device |
EP2402772A4 (en) * | 2009-02-27 | 2012-08-22 | Furuno Electric Co | Phase determining device and frequency determining device |
CN102334038B (en) * | 2009-02-27 | 2013-11-06 | 古野电气株式会社 | Phase determining device and frequency determining device |
US8738312B2 (en) | 2009-02-27 | 2014-05-27 | Furuno Electric Co., Ltd. | Phase measuring device and frequency measuring device |
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