CN105405866B - OLED display and its manufacturing method - Google Patents
OLED display and its manufacturing method Download PDFInfo
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- CN105405866B CN105405866B CN201511029765.9A CN201511029765A CN105405866B CN 105405866 B CN105405866 B CN 105405866B CN 201511029765 A CN201511029765 A CN 201511029765A CN 105405866 B CN105405866 B CN 105405866B
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
- H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
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Abstract
The present invention provides a kind of manufacturing method of OLED display, the manufacturing method of the OLED display includes: offer substrate, forms source, drain electrode and channel on the substrate；The first gate insulation layer is formed on the substrate；First grid is formed on first gate insulation layer；Using the first grid as exposure mask, first gate insulation layer is etched；The second gate insulation layer is formed on the first grid；And second grid is formed on second gate insulation layer；Wherein, the distance of the first grid to channel is different at a distance from the second grid to channel.Thus the gate insulation layer of different-thickness can be used in pixel region and peripheral circuit area, to can have both the on-state current for reducing pixel region and guarantee that GIP circuit region in periphery has larger current.
Description
Technical field
The present invention relates to display fabrication techniques field, in particular to a kind of OLED display and its manufacturing method.
Background technique
In recent years, monitor market center is gradually shared by flat-panel monitor (Flat Panel Display, FPD)
According to.Large scale can be manufactured using FPD and thin and light display equipment.This kind of FPD includes liquid crystal display (Liquid
Crystal Display, LCD), plasma display panel (Plasma Display Panel, PDP), organic light-emitting diodes
Manage (Organic Light Emitting Diode, OLED) display etc..
OLED display is a kind of emerging flat-panel monitor, has self-luminous, and it is high, thick to be not required to backlight, contrast
It is excellent to spend that thin, visual angle is wide, reaction speed is fast, it is wide to can be used for flexibility panel, use temperature range, construction and processing procedure are simpler etc.
Characteristic, therefore have extraordinary development prospect.
High PPI (number of pixels that per inch is possessed) is the trend of display industry future development, the promotion of PPI so that
The area of unit pixel (Pixel) constantly reduces, and the area of luminous zone is corresponding after elemental area reduces reduces, required luminous electricity
Stream becomes smaller therewith, it is therefore desirable to be transformed the structure of thin film transistor (TFT) (TFT) to reduce on-state current again.
But in the existing solution for reducing on-state current, there are in periphery GIP (Gate In Panel) circuit
The inadequate problem of electric current, and high PPI display need periphery GIP circuit have biggish electric current guarantee transmission and transmission speed,
Therefore existing solution has some limitations.
Summary of the invention
The purpose of the present invention is to provide a kind of OLED display and its manufacturing methods, to solve OLED in the prior art
Display cannot have both the on-state current for reducing pixel region and guarantee that GIP circuit region in periphery has the problem of larger current.
In order to solve the above technical problems, the present invention provides a kind of manufacturing method of OLED display, the OLED display
Manufacturing method include:
Substrate is provided, forms source, drain electrode and channel on the substrate；
The first gate insulation layer is formed on the substrate；
First grid is formed on first gate insulation layer；
Using the first grid as exposure mask, first gate insulation layer is etched；
The second gate insulation layer is formed on the first grid；And
Second grid is formed on second gate insulation layer；
Wherein, the distance of the first grid to channel is different at a distance from the second grid to channel.
Optionally, in the manufacturing method of the OLED display, first gate insulation layer is described including being formed in
The first silicon oxide layer on substrate and the first silicon nitride layer being formed on first silicon oxide layer.
Optionally, in the manufacturing method of the OLED display, using the first grid as exposure mask, described the is etched
Only first silicon nitride layer is performed etching in one gate insulation layer.
Optionally, in the manufacturing method of the OLED display, using the first grid as exposure mask, described the is etched
First silicon nitride layer and the first silicon oxide layer are performed etching in one gate insulation layer.
Optionally, in the manufacturing method of the OLED display, the first grid is the grid in pixel region,
The second grid is the grid in peripheral circuit area.
Optionally, in the manufacturing method of the OLED display, the first grid is the part in pixel region
Part of grid pole in grid and/or peripheral circuit area, the second grid are part of grid pole and/or periphery in pixel region
Part of grid pole in circuit region.
Optionally, in the manufacturing method of the OLED display, the thickness of second gate insulation layer is than described
The thickness of one gate insulation layer is small.
Optionally, in the manufacturing method of the OLED display, the second gate insulation includes the second silicon nitride layer.
Optionally, in the manufacturing method of the OLED display, further includes: form interlayer on the second grid
Dielectric layer.
Optionally, in the manufacturing method of the OLED display, further includes: the successively shape on the interlayer dielectric layer
At anode, organic luminous layer and cathode.
The present invention also provides a kind of OLED display, the OLED display includes:
Substrate forms source, drain electrode and channel on the substrate；
Gate insulation layer on the substrate；
First grid and second grid on the gate insulation layer；
Wherein, the distance of the first grid to channel is different at a distance from the second grid to channel.
Optionally, in the OLED display, the first grid is the grid in pixel region, the second gate
Grid extremely in peripheral circuit area.
Optionally, in the OLED display, the first grid is part of grid pole and/or week in pixel region
Part of grid pole in the circuit region of side, the second grid are in part of grid pole and/or peripheral circuit area in pixel region
Part of grid pole.
Optionally, in the OLED display, further includes:
The interlayer dielectric layer being formed on the second grid；
The anode being formed on the interlayer dielectric layer；
The organic luminous layer being formed on the anode；And
The cathode being formed on the organic luminous layer.
Inventor has found that the prior art is by increasing the thickness of gate insulation layer or doing double after having extensively studied the prior art
Gate insulation layer is weighed to reduce on-state current, which can make the on-state current of pixel region and peripheral circuit area drop simultaneously
It is low, but this point is but had ignored in the prior art, reduction cannot be had both so as to cause OLED display in the prior art
On-state current and guarantee periphery GIP circuit have the problem of larger current.
Therefore, in the OLED display and its manufacturing method that invention provides, by forming the first gate insulation on substrate
Layer；First grid is formed on first gate insulation layer；Using the first grid as exposure mask, first gate insulation is etched
Layer；The second gate insulation layer is formed on the first grid；And second grid is formed on second gate insulation layer, to make
The distance for obtaining the first grid to channel is different at a distance from the second grid to channel, i.e. pixel region and peripheral circuit
The gate insulation layer of different-thickness can be used in region, thus can have both the on-state current for reducing pixel region and guarantee periphery GIP
Circuit region has larger current.
Detailed description of the invention
FIG. 1 to FIG. 4 is that the manufacturing method of the OLED display of the embodiment of the present invention is formed by the diagrammatic cross-section of structure.
Specific embodiment
OLED display proposed by the present invention and its manufacturing method are made below in conjunction with the drawings and specific embodiments further
It is described in detail.According to following explanation and claims, advantages and features of the invention will be become apparent from.It should be noted that attached drawing
It is all made of very simplified form and uses non-accurate ratio, only to convenient, lucidly the aid illustration present invention is implemented
The purpose of example.
FIG. 1 to FIG. 4 is please referred to, the manufacturing method for the OLED display of the embodiment of the present invention is formed by cuing open for structure
Face schematic diagram.
As shown in Figure 1, in the embodiment of the present application, provide a substrate 10 first, formed on the substrate 10 source 11,
Channel 12 between drain electrode 13 and source-drain electrode.Preferably, the substrate 10 is glass substrate, further, the glass base
Insulating layer can also be formed on plate.Preferably, the material of the channel 12 is polysilicon.
With continued reference to FIG. 1, in the embodiment of the present application, then, the first gate insulation layer 14 is formed on the substrate 10,
I.e. described first gate insulation layer 14 covers the source electrode 11, drain electrode 13, the channel 12 between source-drain electrode and the substrate exposed
10.Preferably, first gate insulation layer 14 is double-layer structure, including the first silicon oxide layer being formed on the substrate 10
14a and the first silicon nitride layer 14b being formed on the first silicon oxide layer 14a.
Then, first grid 15 is formed on first gate insulation layer 14.In the embodiment of the present application, only in pixel region
Grid (i.e. first grid 15) is formed on first gate insulation layer 14 in domain.
Referring to FIG. 2, being then exposure mask with the first grid 15, first gate insulation layer 15 is etched.In the application
In embodiment, only the first silicon nitride layer 14b is performed etching.Further, only retain what the first grid 15 was protected
First silicon nitride layer 14b eliminates all first silicon nitride layer 14b in remaining region.
It, can also be equal to the first silicon nitride layer 14b and the first silicon oxide layer 14a in the other embodiments of the application
It performs etching.Specifically, can only retain the first silicon nitride layer 14b and the first silicon oxide layer that the first grid 15 is protected
14a eliminates the of all first silicon nitride layer 14b in remaining region and the full depth in remaining region or segment thickness
One silicon nitride layer 14b.
Then, as shown in figure 3, forming the second gate insulation layer 16 on the first grid 15, the i.e. described second gate herein
The first silicon oxide layer 14a that insulating layer 16 covers the first grid 15 and exposes.In the embodiment of the present application, described first
The thickness of gate insulation layer 14 and second gate insulation layer 16 and (15 protection zone of first grid is with exterior domain) first grid are exhausted
The overall thickness that edge layer 14 etches remainder is different.Specifically, the thickness of first gate insulation layer 14 is more exhausted than the second gate
Edge layer 16 and the overall thickness of (15 protection zone of first grid is with exterior domain) the first gate insulation layer 14 etching remainder are big.Into
One step, the thickness of second gate insulation layer 16 is smaller than the thickness of first gate insulation layer 14.Preferably, the second gate
Insulating layer 16 is single layer structure comprising the second silicon nitride layer.
As shown in figure 4, forming second grid 17 on second gate insulation layer 16.Preferably, only in periphery circuit region
Grid (i.e. second grid 17) is formed in domain.I.e. in the embodiment of the present application, the first grid 15 is the grid in pixel region
Pole, the second grid 17 are the grid in peripheral circuit area.Thus can have both reduce pixel region on-state current and
Guarantee that GIP circuit region in periphery has larger current.
In the other embodiments of the application, can also the first grid be pixel region in part of grid pole and/or
Part of grid pole in peripheral circuit area, the second grid are part of grid pole and/or peripheral circuit area in pixel region
In part of grid pole.There are part first grid and/or part second grid in pixel region, has part in peripheral circuit area
First grid and/or part second grid.I.e. so that the thin film transistor (TFT) in entire OLED display has two different grid
Thickness of insulating layer, so as to meet different design requirements.
Subsequently, interlayer dielectric layer (ILD) (being not shown in Fig. 4) then can be formed on the second grid 17, i.e. institute
The second gate insulation layer 16 that interlayer dielectric layer covers the second grid 17 and exposes is stated, the interlayer dielectric layer can be used
The prior art, while can continue to execute subsequent technique using the prior art, successively shape is specifically included on the interlayer dielectric layer
At structures such as anode, organic luminous layer and cathodes, the application repeats no more this.
After above-mentioned technique, OLED display can be formed, the OLED display includes: substrate 10, the substrate
Source 11, drain electrode 13 and channel 14 are formed on 10；Gate insulation layer on the substrate 10；On the gate insulation layer
First grid 15 and second grid 17；Wherein, the first grid 15 is to the distance of channel and the second grid 17 to ditch
The distance in road is different.Further, the first grid 15 to channel distance than the second grid 17 to channel distance
Greatly.Further, the OLED display further include: the interlayer dielectric layer being formed on the second grid；It is formed in described
Anode on interlayer dielectric layer；The organic luminous layer being formed on the anode；And it is formed in the yin on the organic luminous layer
The structures such as extremely.In the embodiment of the present application, the first grid 15 is the grid in pixel region, and the second grid 17 is week
Grid in the circuit region of side.In the other embodiments of the application, the first grid 15 is the part grid in pixel region
Part of grid pole in pole and/or peripheral circuit area, the second grid 17 are part of grid pole and/or periphery in pixel region
Part of grid pole in circuit region.The on-state current for reducing pixel region can be had both as a result, and guarantees periphery GIP circuit region
There is larger current；Or make the thin film transistor (TFT) in entire OLED display that there are two different gate insulation layer thickness, it is full
The different design requirement of foot.
Foregoing description is only the description to present pre-ferred embodiments, not to any restriction of the scope of the invention, this hair
Any change, the modification that the those of ordinary skill in bright field does according to the disclosure above content, belong to the protection of claims
Range.
Claims (9)
1. a kind of manufacturing method of OLED display characterized by comprising
Substrate is provided, forms source, drain electrode and channel on the substrate；
The first gate insulation layer is formed on the substrate；
First grid is formed on first gate insulation layer；
Using the first grid as exposure mask, first gate insulation layer is etched；
The second gate insulation layer is formed on the first grid；And
Second grid is formed on second gate insulation layer；
Wherein, the distance of the first grid to channel is different at a distance from the second grid to channel, the first grid
Correspond to different transistors with the second grid；The thickness of second gate insulation layer is thicker than first gate insulation layer
It spends small.
2. the manufacturing method of OLED display as described in claim 1, which is characterized in that first gate insulation layer includes shape
The first silicon oxide layer on substrate described in Cheng Yu and the first silicon nitride layer being formed on first silicon oxide layer.
3. the manufacturing method of OLED display as claimed in claim 2, which is characterized in that using the first grid as exposure mask,
It etches in first gate insulation layer and only first silicon nitride layer is performed etching.
4. the manufacturing method of OLED display as claimed in claim 2, which is characterized in that using the first grid as exposure mask,
It etches in first gate insulation layer and first silicon nitride layer and the first silicon oxide layer is performed etching.
5. the manufacturing method of OLED display as described in any one of claims 1 to 4, which is characterized in that the first grid
Grid extremely in pixel region, the second grid are the grid in peripheral circuit area.
6. the manufacturing method of OLED display as described in any one of claims 1 to 4, which is characterized in that the first grid
The extremely part of grid pole in pixel region and/or the part of grid pole in peripheral circuit area, the second grid are pixel region
In part of grid pole and/or the part of grid pole in peripheral circuit area.
7. the manufacturing method of OLED display as described in any one of claims 1 to 4, which is characterized in that the second gate
Insulating layer includes the second silicon nitride layer.
8. the manufacturing method of OLED display as described in any one of claims 1 to 4, which is characterized in that further include: in institute
It states and forms interlayer dielectric layer on second grid.
9. the manufacturing method of OLED display as claimed in claim 8, which is characterized in that further include: in the inter-level dielectric
Anode, organic luminous layer and cathode are sequentially formed on layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201511029765.9A CN105405866B (en) | 2015-12-31 | 2015-12-31 | OLED display and its manufacturing method |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201511029765.9A CN105405866B (en) | 2015-12-31 | 2015-12-31 | OLED display and its manufacturing method |
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| CN105405866A CN105405866A (en) | 2016-03-16 |
| CN105405866B true CN105405866B (en) | 2019-01-04 |
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| CN110660814A (en) * | 2019-09-29 | 2020-01-07 | 合肥京东方卓印科技有限公司 | Array substrate, display panel and manufacturing method of array substrate |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06151852A (en) * | 1992-11-04 | 1994-05-31 | Casio Comput Co Ltd | Thin film transistor |
| US6452212B1 (en) * | 1993-11-02 | 2002-09-17 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for operating the same |
| CN1691353A (en) * | 2004-04-26 | 2005-11-02 | 统宝光电股份有限公司 | Thin-film transistor and method for making same |
-
2015
- 2015-12-31 CN CN201511029765.9A patent/CN105405866B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06151852A (en) * | 1992-11-04 | 1994-05-31 | Casio Comput Co Ltd | Thin film transistor |
| US6452212B1 (en) * | 1993-11-02 | 2002-09-17 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for operating the same |
| CN1691353A (en) * | 2004-04-26 | 2005-11-02 | 统宝光电股份有限公司 | Thin-film transistor and method for making same |
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| CN105405866A (en) | 2016-03-16 |
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