CA939757A - Digital signal synchronizing system - Google Patents

Digital signal synchronizing system

Info

Publication number
CA939757A
CA939757A CA102,259A CA102259A CA939757A CA 939757 A CA939757 A CA 939757A CA 102259 A CA102259 A CA 102259A CA 939757 A CA939757 A CA 939757A
Authority
CA
Canada
Prior art keywords
digital signal
synchronizing system
signal synchronizing
digital
synchronizing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
CA102,259A
Other languages
English (en)
Other versions
CA102259S (en
Inventor
Robert D. Houston
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Xerox Corp
Original Assignee
Xerox Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Xerox Corp filed Critical Xerox Corp
Application granted granted Critical
Publication of CA939757A publication Critical patent/CA939757A/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00Arrangements for synchronising receiver with transmitter
    • H04L7/02Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0331Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08Details of the phase-locked loop
    • H03L7/099Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H03L7/0991Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider
    • H03L7/0992Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider comprising a counter or a frequency divider
    • H03L7/0993Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider comprising a counter or a frequency divider and a circuit for adding and deleting pulses

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
CA102,259A 1970-05-01 1971-01-08 Digital signal synchronizing system Expired CA939757A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US3380570A 1970-05-01 1970-05-01

Publications (1)

Publication Number Publication Date
CA939757A true CA939757A (en) 1974-01-08

Family

ID=21872537

Family Applications (1)

Application Number Title Priority Date Filing Date
CA102,259A Expired CA939757A (en) 1970-05-01 1971-01-08 Digital signal synchronizing system

Country Status (4)

Country Link
US (1) US3671776A (de)
CA (1) CA939757A (de)
DE (1) DE2121405A1 (de)
GB (1) GB1353791A (de)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3736516A (en) * 1971-06-14 1973-05-29 Lorain Prod Corp Variable frequency pulse generating circuit
US3798555A (en) * 1972-11-16 1974-03-19 Motorola Inc Pulse recovery system
JPS5926136B2 (ja) * 1975-01-25 1984-06-25 日本電気株式会社 クロツク再生回路
US4208724A (en) * 1977-10-17 1980-06-17 Sperry Corporation System and method for clocking data between a remote unit and a local unit
US4229824A (en) * 1978-07-21 1980-10-21 Cubic Corporation Method and apparatus for synchronizing electrical signals
DE2935353A1 (de) * 1979-09-01 1981-03-19 Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt Einrichtung zum synchronisieren des empfangsbittaktes eines datenempfaengers entsprechend den bituebergaengen des datensignals
US4280099A (en) * 1979-11-09 1981-07-21 Sperry Corporation Digital timing recovery system
US4298986A (en) * 1979-12-26 1981-11-03 General Electric Company Receiver for phase-shift modulated carrier signals
US4308619A (en) * 1979-12-26 1981-12-29 General Electric Company Apparatus and methods for synchronizing a digital receiver
DE3124516A1 (de) * 1981-06-23 1983-05-26 AEG-Telefunken Nachrichtentechnik GmbH, 7150 Backnang Anordnung zur verminderung von phasenschwankungen im ausgangstakt von elastischen speichern
US4450573A (en) * 1981-12-07 1984-05-22 Motorola Inc. Bit data operated squelch
US4455664A (en) * 1981-12-07 1984-06-19 Motorola Inc. Carrier data operated squelch
US4546486A (en) * 1983-08-29 1985-10-08 General Electric Company Clock recovery arrangement
US4600845A (en) * 1983-12-30 1986-07-15 The Charles Stark Draper Laboratory, Inc. Fault-tolerant clock system
US4618920A (en) * 1984-05-24 1986-10-21 Westinghouse Electric Corp. Frequency control circuit
US4740997A (en) * 1985-08-05 1988-04-26 Hayes Microcomputer Products, Inc. Band clock offset phase locked loop
JP2512586B2 (ja) * 1990-03-08 1996-07-03 富士通株式会社 フレ―ム同期依存型ビット同期抽出回路
DE4426713C2 (de) * 1994-07-21 1997-03-27 Siemens Ag Verfahren zum Messen des Phasenjitters eines Datensignals
US5572554A (en) * 1994-07-29 1996-11-05 Loral Corporation Synchronizer and method therefor
US6052748A (en) * 1997-03-18 2000-04-18 Edwin A. Suominen Analog reconstruction of asynchronously sampled signals from a digital signal processor
US20040059446A1 (en) * 2002-09-19 2004-03-25 Goldberg Mark L. Mechanism and method for audio system synchronization

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3102164A (en) * 1963-08-27 Pulses on
US2980858A (en) * 1959-12-07 1961-04-18 Collins Radio Co Digital synchronization circuit operating by inserting extra pulses into or delayingpulses from clock pulse train
US3185963A (en) * 1960-11-25 1965-05-25 Stelma Inc Synchronizing system having reversible counter means
US3209265A (en) * 1963-07-09 1965-09-28 Bell Telephone Labor Inc Data receiver synchronizer for advancing or retarding phase of output after sampling over period of time
US3544717A (en) * 1967-10-18 1970-12-01 Bell Telephone Labor Inc Timing recovery circuit

Also Published As

Publication number Publication date
DE2121405A1 (de) 1971-11-18
US3671776A (en) 1972-06-20
GB1353791A (en) 1974-05-22

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