CA2302020A1 - Interface circuit for full-custom and semi-custom clock domains - Google Patents

Interface circuit for full-custom and semi-custom clock domains Download PDF

Info

Publication number
CA2302020A1
CA2302020A1 CA002302020A CA2302020A CA2302020A1 CA 2302020 A1 CA2302020 A1 CA 2302020A1 CA 002302020 A CA002302020 A CA 002302020A CA 2302020 A CA2302020 A CA 2302020A CA 2302020 A1 CA2302020 A1 CA 2302020A1
Authority
CA
Canada
Prior art keywords
custom
semi
full
interface circuit
interface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA002302020A
Other languages
French (fr)
Other versions
CA2302020C (en
Inventor
Jurgen Niedermaier
Uwe Weder
Korbinian Engl
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Publication of CA2302020A1 publication Critical patent/CA2302020A1/en
Application granted granted Critical
Publication of CA2302020C publication Critical patent/CA2302020C/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Logic Circuits (AREA)
  • Paper (AREA)
  • Continuous Casting (AREA)
  • Radar Systems Or Details Thereof (AREA)

Abstract

The inventive integrated circuit has an interface circuit between the anolog circuit part (FC, or "full-custom") and the digital circuit part (SC, or "semicustom") for each signal to be exchanged. Said interface circuits are assembled in a central block of interfaces. In this way, line lengths and loads are predetermined, making the dimensioning of the gates and their drivers more simple and ensuring an exact timing simulation of the semi-custom part. Improved embodiments relate to the application of predetermined signals and to the series-connection of a signal to the outputs of the interface which face towards the digital circuit part.
CA002302020A 1997-08-28 1998-08-19 Interface circuit for full-custom and semi-custom clock domains Expired - Fee Related CA2302020C (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE19737589A DE19737589C1 (en) 1997-08-28 1997-08-28 Interface arrangement for IC with full-custom and semi-custom clock domain
DE19737589.8 1997-08-28
PCT/DE1998/002431 WO1999012090A1 (en) 1997-08-28 1998-08-19 Interface circuit for full-custom and semi-custom timing domains

Publications (2)

Publication Number Publication Date
CA2302020A1 true CA2302020A1 (en) 1999-03-11
CA2302020C CA2302020C (en) 2006-12-12

Family

ID=7840502

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002302020A Expired - Fee Related CA2302020C (en) 1997-08-28 1998-08-19 Interface circuit for full-custom and semi-custom clock domains

Country Status (7)

Country Link
EP (1) EP1010053B1 (en)
JP (1) JP2001515238A (en)
CN (1) CN100392556C (en)
AT (1) ATE221679T1 (en)
CA (1) CA2302020C (en)
DE (2) DE19737589C1 (en)
WO (1) WO1999012090A1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7031421B2 (en) 2001-04-30 2006-04-18 Infineon Technologies Ag Method and device for initializing an asynchronous latch chain

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10122702C2 (en) 2001-05-10 2003-08-21 Infineon Technologies Ag Method and device for generating a second signal with a clock based on a second clock from a first signal with a first clock
CN112949830B (en) * 2021-03-09 2022-12-06 合肥辉羲智能科技有限公司 Intelligent inference network system and addition unit and pooling unit circuitry

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JPS58169220A (en) * 1982-03-31 1983-10-05 Fujitsu Ltd Clock synchronization system
JPS61276441A (en) * 1985-05-31 1986-12-06 Nec Corp Synchronizing circuit
JPH0756503B2 (en) * 1985-11-26 1995-06-14 株式会社日立製作所 Logic circuit diagnosis method
JPS62172751A (en) * 1986-01-24 1987-07-29 Nec Corp Semiconductor integrated circuit device
JPS63310159A (en) * 1987-06-11 1988-12-19 Mitsubishi Electric Corp Semiconductor device
JP2656504B2 (en) * 1987-09-25 1997-09-24 株式会社日立製作所 Semiconductor device
US4922492A (en) * 1988-05-13 1990-05-01 National Semiconductor Corp. Architecture and device for testable mixed analog and digital VLSI circuits
JPH0375976A (en) * 1989-08-18 1991-03-29 Fujitsu Ltd Semiconductor integrated circuit device
JP2633980B2 (en) * 1990-09-11 1997-07-23 シャープ株式会社 Digital / analog mixed LSI
JPH04176164A (en) * 1990-11-08 1992-06-23 Nec Corp Semiconductor integrated circuit
JPH04296918A (en) * 1991-01-17 1992-10-21 Matsushita Electron Corp Semiconductor integrated circuit device
IL100871A (en) * 1991-02-22 1994-11-28 Motorola Inc Apparatus and method for clock rate matching in independent networks
JPH05143187A (en) * 1991-03-29 1993-06-11 Hitachi Ltd Semiconductor integrated circuit and data processing processor
JPH04324510A (en) * 1991-04-25 1992-11-13 Sharp Corp Digital/analog-mixed semiconductor device
JPH04348559A (en) * 1991-05-27 1992-12-03 Hitachi Ltd Protecting circuit
US5256912A (en) * 1991-12-19 1993-10-26 Sun Microsystems, Inc. Synchronizer apparatus for system having at least two clock domains
JP3180421B2 (en) * 1992-03-30 2001-06-25 日本電気株式会社 Mixed analog / digital master with built-in test circuit
JPH0658997A (en) * 1992-08-06 1994-03-04 Mitsubishi Electric Corp Semiconductor logic device
JPH06162224A (en) * 1992-11-20 1994-06-10 Nippon Motorola Ltd Digital/analog mixed type semiconductor integrated circuit reduced inmutual interference
JPH06283999A (en) * 1993-03-30 1994-10-07 Mitsubishi Electric Corp Semiconductor integrated circuit device and its manufacture
JPH07249744A (en) * 1994-03-14 1995-09-26 Hitachi Ltd Power supply control circuit and signal transmission control circuit
US5548620A (en) * 1994-04-20 1996-08-20 Sun Microsystems, Inc. Zero latency synchronized method and apparatus for system having at least two clock domains
US5638015A (en) * 1995-06-21 1997-06-10 Unisys Corporation Avoiding instability
US5646521A (en) * 1995-08-01 1997-07-08 Schlumberger Technologies, Inc. Analog channel for mixed-signal-VLSI tester
JP3468977B2 (en) * 1996-03-14 2003-11-25 京セラ株式会社 Method and apparatus for controlling data stream between synchronous circuits
JPH09321225A (en) * 1996-05-30 1997-12-12 Nec Corp Semiconductor integrated circuit device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7031421B2 (en) 2001-04-30 2006-04-18 Infineon Technologies Ag Method and device for initializing an asynchronous latch chain

Also Published As

Publication number Publication date
CN100392556C (en) 2008-06-04
EP1010053A1 (en) 2000-06-21
ATE221679T1 (en) 2002-08-15
EP1010053B1 (en) 2002-07-31
DE59805029D1 (en) 2002-09-05
CA2302020C (en) 2006-12-12
CN1269028A (en) 2000-10-04
DE19737589C1 (en) 1998-11-26
JP2001515238A (en) 2001-09-18
WO1999012090A1 (en) 1999-03-11

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EEER Examination request
MKLA Lapsed

Effective date: 20140819