CA1218423A - Integrated digital circuit and a method of manufacturing a digital filter arrangement as an integrated circuit - Google Patents

Abstract

ABSTRACT:

A digital filter in the customary manner com-prises a plurality of delay circuits, a plurality of multipliers and at least one summation device. The multi-pliers for fixed coefficients may be formed by means of adders and, if a pipeline structure is used, the summation device may also be formed by a plurality of adders. A
result of this, only two different types of circuits are required, namely adders and delay circuits. In accord-ance with the invention it is proposed to initially integrate a plurality of adders and delay circuits in a regular structure without interconnections and to form the interconnections in a subsequent step after the filter structure has been defined. Suitably, the individual cir-cuits are designed for one bit only and so-called cells are formed which each comprise a l-bit full adder and a plurality of registers, the cells being arranged in rows and columns. The connections of the elements within one or more cells are made by means of conductor tracks which all extend in one direction only and which intersect con-necting lines which issue from the circuits.

Description

PHD 82-0~9 1 11~2.~3 "An in-tegrltell digital circuit and a method of manufacturing a digital filter arrangement as an integrated circuit"

The invention relates to an integrated digital circuit and to a method of manufacturing a digital fil-ter arrangement comprising a plurality of delay circuits and a plurality of adder circuits as an integrated circuit on a single semiconductor wafer.
Such filter arrangements are generally known, for example from the maga7ine "Electronik", Vol. 3 (1982), pages 73 to 74. ~asically, digital filter arrangements comprise signal delay circuits and arithmetic circuits.
The input ~ignal is applied to a summation device both directly and delayed by means of register~, whilst moreover the individual delayed signals may be multiplied by weighting coefficients. The sum of all the signals then constitutes the outpu-t signal.
~ lternatively, multiplication may be effected by carrying out a plurality of additions of each time two signals, which enables the use of a 30-called "pipeline" structure as described in the above-mentioned publication.
When a digital filter arrangement i9 manufactured in the form of an integrated circuit the required elements and interconnections are generally integrated on a single semiconductor wafer in known manner. Such a method requires a multiplicity of separate manufacturing steps and masks. If the characteristic of a specific digital filter is to be changed it is often also neces~ary to change the number and/or the arrangement of the individual elements and their interconnections. For integrating such a digital filter it is then necessary to design a completely new circuit arrangement, which normally requires the design of new mask3, which is rather costly.

8~3 PHD 82-029 2 11.2.83 I-t is -the object of the invention to provide an in-legra'~ed ligi-tal eircuit and a method of the type mentioned in the opening paragraph which enables different digital filter arrangements to be manufactured rapidly and at loi~ c!~st30 ~ ccording to -the invantion this object is achieved in that initially the delay circuits and the adder circuits are formed on the semiconductor wafer wi-thout interconnec-tions and the interconnec-tions are formed in a subsequent manufacturing stepafter tlle filter characteristic~ in particular the transfer function, has been defined. Thus, initially all the elements are in~egrated and only the last mask for -the manufacture of -the in-terconnections between the elements have to be manufactured separately in conformity with the desired filter characters-tic. In particular if the initially integrated elements are arranged regularly, this manufacture and/or design of the last wiring mask can be automated partly, thereby allowing a fast, simple and cheap manufacture of different filters. The possibili-ty of replacing multiplications by additions is then utilized, so that in fact only two types of different elements or circuits have to be formed on the semiconductor wafer.
~ccording to the invention the integrated digi-tal circuit comprising a plurality of identical cells, each cell including at least one electric circuit, is characterized in that the cells are arranged in several parallel columns, whereby input and ou-tput connecting lines of each cell extend in a first direction perpendicularly to the columns and connections between inpu-t - and/or output connec-ting lines of different cells extend in a direction perpendicularly to the first direction and are formed in a manufacturing step subse-quently to the manufacturing step of the input- and output connecting lines.
The connections may be manufactured in various rnanners. ~or example, the connections may be manufactured ,, , ,.. ,~ . ,~.

L'MD ~2-0'-~9 3 11.2.~3 by a separately formed connecting pattern or the connec-tions rnay be formed by controllable switches. These switches may already be integrated on the semiconductor wafer and maybe activated or connected in a subsequent manufacturlng step. It is particularly effective -to employ a combination of -the two possibilities, in such a way -tha-t a part of the connections are constituted by a separately formed connecting pa-ttern and the other connections are constituted by controllable swi-tches.
This is par-ticularly favourable because in the case of electrical control of the filter characteristic upon completion of the manufacture only a few connections have to be changed by means of -the controllable switches, a part of the connections being the same for different characteristics. This simplifies the control method.
For controlling the controllable switches it is effective when connections are formed betweerl-the con-trol inpu-ts of the controllable switches and a binary memory is present on the semiconductor wafer. This enables the filter characteristic to be changed by means of a larger number of switches via a few control inputs only.
In order to obtain different switchable filter characteristics it is effective if the connections for the control inputs of the controllable switches are also formed in the subsequent manufacturing stepr As a result of this only one mask is required for all the connections, i.e. both for the connectiors which cannot be changed and for the connections which can be changed by means of the controllable switches. Another possibility is that the memory is a read-only memory and the memory conten-ts is defined in the subsequent manufacturing step.
The connections for the control inputs of the controllable switches may then already be present and in order to render a switch inoperative the read-only memory is given such a contents tha-t -the relevant swi-tch is not activated.
In order to enable the manufacture of as many as . .

PIID ,~2 029 4 11.2.83 possible digital filters which occur in practice, an adequate rlumber of delay and adder circuits should be formed on the semiconductor wafer in -the af`orementioned manufacturing step. ~Ioreover, if the various elements or circuits are arranged on the semiconductor wafer in a ~pecific pat-tern, it is conceivable that for some filter characteristics the connections to be formed in the individual circuits are difficult or intricate. Then it is effective if only some of the circuits, in particular the delay circuits, are provided with connections. Some of the circuits then remain unused, but this need not be a disadvantage from the point of view of manufacturing technology because -the complexity and costs of manufac-turing a digital filter arrangement in accordance with 15the inventive method is mainly determined by the subsequent manufacturing step, whereas the previous manufacture of the elements on the semiconductor wafer without connections is an inexpensive standard manufacturing process.
In order to minimize the power dissipation if individual circuits are not provided with connections and are therefore not used, it is effective if the power-supply connecti ng lines of individual cells also extend in the first direction and that power supply connections are also formed in the subsequent manufacturing step, and that the power-supply connections for cells without input or ou-tputconnections are also dispensed with. This does not further complicate the manufacturing process.
The delay and adder circuits may be arranged on the semiconductor wafer in various manners. A
particularly effective arrangemen-t, which allows the connections to be formed in a simple manner during the subsequent manufacturing step is characterized in that a plurality of cells, which cells each comprise a linear array of an adder circuit and a plurality of delay circui-ts f`or one bit each, connecting lines extending from said cells parallel to each other and substan~ially perpendicu-larly to said linear array, and during the subsequent ~IID ~2-029 5 11.2,8 manufacturing step connection points are formed on the connecting lines and conductor tracks are formed, which tracks extend in a direction parallel to the columns, ~hich t-acks intersect the connecting lines and which contact the connection points, This results in a convenient-ly arranged and regular structure in which the connections between the individual elements are generally short and in which only a limited number of conductor tracks are required, ~ince each basic cell processes only one bit, the individual bits of the multi-bit binary words applied to the filter may be applied to the various cells in a column. A mul-tiplication by the factor 2 or 1/2 then resul-ts in a shift by one bit order, i.e. the information changes from one column to the nex-t in the presen-t arrangement.
l~'or a compact construction in which the connec-tions between adjacent columns can also be formed in a satisfactory manner, it is effective that the cells in a column of cells are shi~ted by a part of the length of a cell relative to the cells in an adjacent column.
A further embodiment, in which the connections within the cells and those to adjacent colu~m of cells can be short, is characterized in that for each cell are provided further connecting lines which extend at least across the entire width of the cell, extend parallel to the input- and outpu-t connecting lines and are arranged between the circuits of said cell, and the conductor tracks formed during the subsequent manufacturing step in-tersect the further connecting lines on both sides of the circuits. By means of the further connecting lines between the circuits of each cell it is even possible to skip a complete column or a plurality of columns of cells. For interconnecting the circuits in cells of one column it is effective if the conductor tracks extend over a plurality of basic cells of one column. This results also in short connections, Embodiments of the invention will now be 3'~23 P~ID 82-029 6 11.2.83 described in more detail, by way of example, with reference to the drawing. In the drawing Iig. 1 shows -the general structure of a digital transverse filter, Fig. 2 shows such a filter having a pipeline structure, Fig. 3 shows the general arrangernent of the delay and iadder circuit on a semiconductor ~afer and their connections for obtaining digital filter structures, Fig. 4 shows the structure of cells and their arrangement in various columns, ~ig. 5 shows a special digital fil-ter wi-th a predetermined transfer function.
Fig. 6 shows the arrangement of a plurality of cells with the interconnections required for obtaining the filter shown in Fig. 5.
In the circuit arrangement shown in Fig. 1 the input 1 receives a sequence of binary words, which represent the sampled values of an analog signal. Trhe binary words are applied in bit-parallel in the customary manner so that the connections in Fig. 1 in fact comprise a plurali-ty of parallel lines.
The binary words are applied to a chain of delay circuits 2, 4, 6 and 8, of which each delay circuit comprises a digital register with a plurality of storage elements for the storage of one binary word each. All the delay circuits receive shift clock pulses from a common clock signal source, not shown, in response to which each delay circuit transfers the binary word on its input to its 011tpUt. The chain of delay circuits 2 to 8 thus forms a multi-stage shift register for multi-bit binary words.
~lultipliers 10, 12, 14, 16 and 18 are connected to the respective inputs and outputs of all the delay circuits, which multipliers multiply the binary words received from -the corresponding connections of delay circuits 2 to 8 by a fixed coefficient as indica-ted in PilD (~2-029 7 11.2.83 these multipliers. In -the present example the first mnltiplier 10 effects a multiplication by the factor 1, i.e. the binary word received appears unchanged on the outpuc of the mul-tiplier 10. The other coefficients k1 to k~ may differ from 1 and may be negative.
'~lae olll,pll~3 of all -tlle multipliers 10 -to -l~
are connected to a summation circuit 20 which forms the sum of all the simultaneously applied binary words and transfers this sum to the output 19. The binary words available on this output represent the sampled values of ~he filtered analog signals, the filtration complying witll the f'ollowing complex transfer function:
Il(z) = 1.z +k1.z + k2-Z . k3z 3 + k4.z 4 T}-nls, the transfer function is determined by the coeffi-cients k1 to k4 by which the binary words are multiplied in the multipliers 12 to 18 and by the number of coeffi-cients or the length of the chain of delay circuits 2

2~ to ~. In general the number of delay circuits determines the slope of the transfer function at the cut-off frequency or the cut-off frequencies.
The summation device 20 in Fig. 1 is generally constructed as an accumulator which consec-utively forms the sum of`-the output signals of the multipliers. This sequential processing limits the maximum frequency of -the shift clock pulses with which a new binary word on input 1 can be transferred. In order to increase -this frequency the filter shown in Fig. 1 may be given the pipeline structure shown in Fig. 2. The binary words applied to the input 1 are then transferred from the delay circuits 22 to 26 to a shift register, the multipliers 10 and 'l8 being again connected to the input and output of said register and between the connections. The outputs of the multipliers 12 to 18 are each connected to a regis-ter 36 to 42, which can each store one binary word.
These regis-ters 36 to 42 receive the same clock signal as the delay circuits 22 to 26 a-nd therefore also produce ~2~8~3 PIID S2-029 8 11.2.83 a signal delay. The outputs of every two of these registers are connected to an adder, i.eO the outputs of the registers 36 and 38 are connected to the adder circuit 44 and -the outputs of the registers 40 and 42 are connected -to the adder circuit 480 The outputs of this adder circuit are each connected to a register 46 and 50 respec-tivelv, which registers receive the same clock signal as the registers 36 to 42, so that a full clock phase is av~ilable as processing time for the adder circuits Ll4 and l~8~ The outputs of the registers 46 to 50 are coIlnected to a further adder circuit 52, ~hose output is again connected to a register 54, so that the foregoing also applies to the processing time of -the adder circuit 52. The output of the register 54 and the outpu-t of the multiplier 10 are connected to an adder circuit 56, ~hich is arranged after the register 60 and which in the present case is not strictly necessary for processing. The same binary words as on the output 19 of the circuit arrangement shown in Fig. 1 now appear on the output 59, but now delayed by two or three clock periods respectively. The summation device 20 shown in Fig. 2 comprises a plurality of adder circuits, which together with the interposed registers have the advantage tha-t the ma~imum frequency of the clock signals for the registers only depends on the processing time of one arithme-tic element, i.e.of one multiplier or one adder.
The multipliers 10 to 18 may also comprise adder circuits,which add the shifted input words to each other. ~ result of this only two different types of circuits are required for -the filter, namely the delay circuits in the form of digital registers and digital adder circuits.
Fig. 3 schematically shows a part of a semi-conductor wafer, on which a plurality of adder circuits 62, 64, 66 and 74, 76 and 78 plus a plurality of delay circuits 68, 70 and 72 are arranged in a regular structure of rows and columns. In the following it is assumed that , . . . . .

~2~ 3 I'TID 82-029 9 11.2.83 each circuit processes only one bit because this allows a more fle~ible arrangemen-t of the connections, as will be explained hereinafter. In the present case only a small number of adder circuits and delay circuits are shown for the sake of simplicity, but in practice a substantialLy larger number of such circuits must be accommodated on each semiconductor wafer for greater word-length and more complex struc-tures.
Theindividual circuits are connected to an area 80 or 82 via connecting lines 61, 63, 67 and 69, the direction of the arrow for example indicating the difference between inputs and outputs. Fur-ther connecting lines 71, 73, 75 and 77 interconnect the areas 80 and 82 and other areas, not shown. The sa-d ~dder circuits and delay circuits as well as the connecting lines are alwavs formed, regardless of the desired filter structure.
The desired structure is obtained in a snbseqllent manufacturing step, during which connections are made between specific ones of the connecting lines 2~
61, 63, 57, 69 as well as 71, 73, 75 and 77, in par-ticular by means of conductor tracks which extend to the areas 80 and 82 respectively. The connecting lines, which may be vacuum-deposited metal tracks or polysilicon tracks are initially covered with an insulating layer, in particular SiO2, during the manufacture of the regular struc-ture. This is also advantageous because such structures can now be stored more simply until the final filter ~tructure is laid down in the subsequent manu-facturing step, without the risk of surface contamination.
In the subsequent manufacturing step holes are etched at specific locations in the insulating layer which covers the connecting lines, in known manner by means of a photomask and subsequently a well-defined pattern of conductor tracks, suitably of aluminium, is formed by means of a further mask. Thus, only two dedicated masks are required for the manufacture of a specific filter.

PIID 82-029 10 11~2.83 Another possibility of forming the connec-tions in a subsequen-t manufacturing step is obtained if during -the preceding manufacture of the regular structure electrically controllable electronic switches are formed at the location of at least a part of the intersections of the connecting lines and the conductor tracks which end t J~ia-ds -tile areas 80 and 3" respac~ rely . rhe 3 e switches may for e~ample take the form of field-effec-t transistors, During the subsequent manufacturing step conductor tracks for the control inputs of the switches are formed in addition to the conductor tracks a-t those ends of the switches which are remote from the connecting lines, SinCe,even i-f a part of -the connec-tions of the connecting lines to each other are formed directly by conductor tracks, the number oi` _wi~ches is scill cornparatively large, it is generally not effective to lead the control inputs of the switchas out the semi-conductor wafer by means of separate lines. Ins-tead of -this, -the conductor tracks of the control inpu-ts of the switches are connected to a memory 84 which is controlled and addressed respectively via the inputs 83, This memory 84 may be designed so that it can be loaded e~ternally, but in general it will be effective if the memory 84 is a read-only memory, so that upon read out of a specific address of the memory a specific combination of switches is actuated and thus a filter with a specific structure corresponding to a desired transfer function is obtained. In the subsequent manufacturing step not only the connections between the control inputs of the switches and the memory are formed, but the contents of the memory 84 must also be defined. In this way it is simply possible to derive a plurality of different filters from a regular structure of adder circuits and delay circuits during the subsequent manufacturing step.
Fig. 4 shows the arr~gement of some so-called cells 100, 120 and 130 relative to each other and the .

~2~84;23 PIID 82-029 11 11.Z.83 internal structure of the cell 100, The cell 100 comprises a one-bit r..ll adder 102 having three inputs for the two terms of the sum and the carry si~al from the preceding bi-t stage, which inputs are connected to the input connecting lines 103, a sum output which is connected to the output connecting line 109 and two carry outputs, wIIich are connected to the outpu-t connecting lines 111 and 117 respecti~ely. The duplication of the carry output~
is favour~le t`or the manufactllre of the connection~ in the subsequent manufacturing step because especially for the following cells the connecting line 117 can ~e connec-ted easil~r ~o an input connecting line of a cell situated to its left, l~hich cell serves for processing the bits of the ne~t higller significance in the applied binary words. This is the normal carry-processing. Howe~er, if the output signal of the adder 10~ is to be multiplied by the l`actor 1/~ tIle sum output signal on the output connectiIlg line 109 must be processed further in the ne~t column further to the right, W}liCh is not ~hown, but wI1icII ~erves for processing bits of the ne.~t lower gignificance, whilst the carry output signals on the connecting line 111 must be processed further in the same column of cells.
The cell 100 further comprises four registers 104, 106, 108 and 110 for one bit each. The information input of each register is connected to a connecting line 103, whilst the output of each register is again connected to a respective connecting line 105 or 115 on both sides. A~ a result of this it is easy to process the output signals in the same or in the ne~t higher column of cells.

PHD 82-029 12 11,2.83 The eonnecting lines are interconnected by means of conductor tracks whose locations are indicated by the broken lines 101. Thus the set of lines 101 represents the area 80 or ~2 in I`ig. 3. For the eonnec-tions of the conductor tracks to thelines 101 in the various columns of cells there are provided in particular t~e furtller connecting lines 107 which even extend over three columns of eells, as can be seen, if the regular structure of the cells is maintained at the edges. For the remain~ler clle connecting lines to the inputs and outputs or` the adders and the registers extend at least partly at the loca-tion of adjacent columns of eells through which the lines 101 e~tend, so that at these locations conductor tracks may be formed during the sub~equent manufacturing step. The conneeting lines 105 and 107 between the connecting lines 103 and 109 e~tend for example from the cell into the adjacent column, as is apparent from the connecting point of the two eells 100 and 120. The eonnections via tlle conductor traeks is obtained in that at the intersection of the desired connecting line and one of the lines 101 an aperture is etched in the insulating layer (not shown) which has been deposited on the eonnecting lines during the preceding manufacturing step, after whieh the conductor track is ~ormed.
The conductor traeks 11 9 serve for applying the power-supply current and the clock signals, which traeks e~tend via the adder and delay eireuit and may also be formed during the ~ubsequent manufacturing step as described above for the conductor tracks which connect the conneeting leads, whilst in eireuit~ whose eonneeting lines are not eonneeted to subsequently formed eonductor tracks no apertures for the conductor traeks 11~ are etched into the insulating layer, so that these eircuits cannot contribute to the power dissipation.

~2~ 3 ~I-ID 8~-029 13 11.2.83 The structure shown for each cell is merely an eYample hecallse in particular the number and arrangement of the registers relative to -the adder may differ, but the present arrangement with the possibility of arranging the conductor tracks on both sides of the registers is f`o~ d to be effective.
~ n example of a connecting pattern by means of conductor tracks for connecting the connecting lines of` the individual cells of a specific filter will now be described in more detail with reference to Fig. 6, the structure of the filter thus obtained being shown in Fig. 5. The incoming binary words are applied in bit parallel -to a chain of f`our register stages 90, which produces a delay by four shift clock periods. The output of the register stages 90 is connected to the input of a further chain of register stages 91, which also comprises four stages and consequently produces a delay by four clock periods.
The input of the filter and the output of the register chain 91 are connected to the inpu-ts of an adder 92 for che addition of two multi-bit binary words.
If it is assumed for example that the input words have a length of four bi-ts, so tha-t the output words of the register chain 91 also have this length, five bits will appear on the output of the adder 92 as a result of the maximum carry signal. In practice, a higher number of parallel bits is generally selected.
The output of the adder 92 is now connected to one input of a further adder 93, whose other input receives the binary words appearing on the output of the register chain 90 via a multiplier 96. The multiplier 96 multiplies the binary words by the factor 2, which corresponds to a shift by one bit. The adder 93 now genera-tes six-bit outpu7t words, which are applied to a further multiplier g~ which effec-ts a multiplication by the factor 1/2. This corresponds to shift in -the opposite direction, the least-significant last bit being PHD 82-029 14 11.2.83 omitted.
The resulting five-bit binary words are now applied -to a further adder 95 and to a register chain 94 comprising two register stages, which consequen-tly provide a delay by two shift clock periods. The output of -this register chain 94 is connected to the other input of the adder 95, which again produces 6-bit words on the output. These words are applied to a further multiplier 98 which again effects a multiplication by the factor 1/2, _.e. the least significant bit is omitted and -the output signal of the filter consequently comprises five-bit binary words. The filter of the structure shown in Fig. 5 has tlle transfer function ~ ) 2 and is a low pass filter. Fig. 6 shows the structure of the filter shown in Fig. 5, which filter comprises separate cells for one bi-t each as shown in Fig. 4.
Since ma~imum si~ bits can occur in parallel the filter shown in Fig. 6 comprises six columns of cells, the boundaries between the individual cells no-t being shown. The four bits of the binary words applied to the filter are applied via connections 101 to the four right-hand columns of cells, the adder 102 in the first cell of each column not being connected. The adder 92 in Fig. 5 corresponds to the second adders 132 in the four righ-t-hand columns. Similarly, the first chain 90 of register stages corresponds to the first four registers 104, 106, 108, 110 in the four right-hand rows and the second chain 91 of register stages in Fig. 5 corresponds to the second group of four registers 134, 136, 138, 140. The two left-hand columns are employed for processing respectively the carries and the binary words whid~have been shifted by one bit in conformity with the multiplication in the multiplier 96. Adder 93 of I`ig, 5 shows si~ adders 142~ one in each column of . _ . . .. .

~21~3 ~23 PIID 82-()29 15 11.2.83 Fig. 6. The output words of -the filter are taken from the lasr- adders 152 in the columns, the adder 152 of the righc-1-~and column not being connected, which corresponds to the multiplicat on by the factor 1/2 in the multiplier 98 in Fig. 5. The del~y registers 94 of Fig. 5 comprise t~ro delay registers 144 and 146 in each column of` Fig. 6.
For simplicity only those connecting lines 103 and only those conductor tracks at the locations which sorrespond to ~he lines 101 in Fig. 4 are shown, the apertures in the insulating layer at which a connection is made between the connec-ting lines and the conductor tracks being marked by dots. The conductor -tracks for the power supply aIld the clock signals, which correspond to the conduc-tor tracks 119 in Fig. 4, are no-t shown.f`or the sake of simplicity.

"'`'~!t

Claims (7)

THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE PRO-PERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:

1. A method for manufacturing an integrated digital filter circuit arrangement comprising a plurality of delay circuits and adder circuits on a single semiconductor wafer whereby the delay and adder circuits firstly are formed on the semiconductor wafer without interconnections and the interconnections being formed in a subsequent manufacturing step for realizing the digital circuit arrangement, charac-terized in that the delay and adder circuits are arranged in columns, the columns are connected by connecting lines extending transversely to the columns and interconnecting tracks extending between the connecting lines being formed in the subsequent manufacturing step, the interconnecting tracks extending approximately parallel to each other and crossing the connecting lines.

2. A method as claimed in Claim 1, characterized in that the delay and adder circuits on the semiconductor wafer are not connected to a power supply and that the circuits interconnected in the subsequent manufacturing step are connected to the power supply in the subsequent manufactur-ing step.

3. An integrated digital filter circuit charac-terized in that a plurality of columnwise arranged cells, which cells each comprise a linear array of an adder circuit and a plurality of delay circuits one for each bit, and connecting lines extending in a transverse direction from the columnwise arranged cells and parallel to each other, said integrated digital circuit being further characterized in that connection points and conduction tracks are formed to interconnect the connecting lines where the connection points are formed on the connecting lines and the conduc-tion tracks extend in the columnwise cell direction to con-tact the connection points.

4. An integrated circuit as claimed in Claim 3, characterized in that adjacent columns of cells are shifted relative to each other by a part of the length of a cell.

5. An integrated circuit as claimed in Claim 3 or 4, characterized in that further connecting lines, extending at least across the entire width of the cell parallel to the said connecting lines, are provided for each cell and arranged between the circuits of said cells, the formed con-ductor tracks crossing the further connecting lines on both sides of the circuit.

6. An integrated circuit as claimed in Claim 3 or 4, characterized in that the conductor tracks extend over a plurality of cells of one column.

7. An integrated circuit as claimed in Claim 3 or 4, characterized in that further connecting lines, extending at least across the entire width of the cell parallel to the said connecting lines, are provided for each cell and arranged between the circuits of said cells, the formed con-ductor tracks crossing the further connecting lines on both sides of the circuit and characterized in that the conductor tracks extend over a plurality of cells of one column.