GB2104695A - Controllable shift matrix weighting function circuits and digital circuits especially filters using such a matrix - Google Patents

Abstract

A controllable shift matrix has inputs and outputs and is responsive to bits of an input signal word X(n) at the inputs of ascending order from a least significant bit position to a most significant bit position for controllably producing an output (weighted X(n) the outputs in which the input signal bits may occupy respectively different bit positions. The matrix comprises a plurality of sections (80-88) including at least one divide-by section (82) coupled between the inputs and outputs and including controlled switch means responsive to control signals (C1 ,C1) for selectively passing bits on divide-by input lines to divide-by output lines of the same order as said divide-by input line bit position, or transferring said divide-by input line bits to respective ones of said divide-by output lines which are more than one bit position lower in order than divide-by input line bit positions. A weighting function circuit comprises two such matrices which commonly receive the input word for shifting it in different ways, and a combining circuit for combining the shifted words produced by the matrices to produce a weighted word (Fig. 2 not shown). A digital filter comprises the weighting function circuit allowing reduced complexity and higher speed in coefficient multiplication. <IMAGE>

Description

SPECIFICATION Controllable shift matrix weighting function circuits and digital circuits especially filters using such a matrix This invention relates to controllable shift matrix weighting function circuits and digital circuits, especially filters using such a matrix.

One aspect of the invention provides a controllable shift matrix as set out in claim 1 to which attention is invited.

Another aspect is as set out in claim 7 to which attention is invited.

In a digital filter, time-sequential samples of a digital input signal are weighted by multiplying the respective samples by weighting coefficients.

The weighted samples are accumulated at an output which exhibits a desired response characteristic.

Digital filters may be constructed using either output-tapped digital shift registers or inputtapped digital shift registers. In the output-tapped variety, samples of the digital input signals are serially shifted through the register, which has a plurality of parallel output taps. Signals present at the output taps are weighted, and the weighted signals are then summed to produce a filtered digital output signal. In the input-tapped variety, samples of the digital input signal are applied in parallel to weighting function circuits. The resultant weighted signal samples are then applied in parallel to respective input taps of the shift register. Weighted samples are accumulated as the signal are shifted through the register to produce a filtered digital signal at the output of the last shift register stage.

The response characteristic of either filter is a function of both the number of samples that are accumulated, (also referred to as the filter order), and the values of the coefficients which weight the samples. Accordingly, it is desirable to be able to dynamically control the values of the weighting coefficients so that the response characteristic and the filter order may be altered dynamically so as to respond, for the instance, to different signal characteristics. For example, it is desirable for a chroma signal filter in a television receiver to exhibit a relatively wide passband when the chroma signal is relative noise-free and to exhibit a relatively narrow passband when the chroma signal is contaminated with noise.

Other aspects are set out in claims 8, 1 6 and 1 8 to which attention is invited.

In accordance with another aspect of the present invention, a weighting function circuit for a digital filter is provided which effectively multiplies a digital signal by a weighting coefficient expressed as a multiple of an inverse power of two. The weighting function circuit includes at least one shift matrix to shift the bits of the digital signal to lower order bit positions to form a weighted output signal.

In accordance with a further aspect of the present invention, the weighting function circuit includes first and second shift matrices for shifting the bit positions of the applied digital signal. The output signals of the shift matrices are summed to produce a weighted digital signal.

In accordance with yet another aspect of the present invention, at least one of the shift matrices is made programmable through the use of transmission gates to control the shifting. The transmission gates respond to coefficient control signals to shift the applied digital signal by a desired number of bit positions.

In a preferred embodiment of the present invention, sequential shifts of one, two or four bit positions may be achieved under control of the coefficient control signals. The shift matrix may also include the ability to provide a complemented or uncomplemented output signal form. The shift matrix may further include the ability to zero the applied signal, which may be done when it is desirable to change the filter order. The shift matrix is suitable for fabrication in integrated circuit form using a matrix of identically constructed transmission gate cells to provide both compactness and ease of iayout.

In the drawings:- Figure 1 illustrates, in block diagram form, a programmable digital filter; Figure 2 illustrates, in block diagram form, a weighting function circuit for a digital filter; Figure 3 illustrates, in block diagram form, a programmable shift matrix; Figures 4 and 5 illustrate, in block diagram and schematic diagram form, respectively, a coefficient control shift register suitable for use in the weighting function circuit of Figure 2; Figure 6 illustrates, in schematic diagram form, the programmable shift matrix of Figure 3; and Figure 7 illustrates, in schematic diagram form, a shifter cell of the shift matrix of Figure 6.

Referring to Figure 1, an input tap weighted digital filter is shown in block diagram form. A digital input signal x(n) is applied to inputs of weighting coefficient multipliers 20, 22, 24, 26 and 28. The weighting coefficient multipliers multiply the digital input signal by weighting functions aN " aN 2, aN 3, at and aO, respectively.

The weighting function values are established by weighting coefficient control words stored in latches, or shift registers 30, 32, 34, 36 and 38.

The coefficient control words are shifted serially into the latches on a coefficient control bus 77, which interconnects the latches.

Weighted input signals produced at the outputs of the multipliers 22, 24, 26, and 28 are applied to inputs of adders 10, 12, 14 and 16, which are separated by one-clock delay elements represented by the Z-transform Z-1. A weighted input signal produced at the output of multiplier 20 is applied to the input of the first delay element in the alternating sequence of delay elements and adders, which form a shift register of the digital filter. Weighted samples are accumulated in the adders as signals are shifted through the register, with a filtered output signal y(n) appearing at the output of the finai delay element. The order of the filter is determined by the number of delay elements in the shift register, which is also equal to the number of input taps in the embodiment of Figure 1.The five tapweighted inputs are separated by four delay elements and followed by a fifth delay element to form a fifth order filter. The filter order may be increased by inserting additional weighting function circuits, adders and delay elements in the location indicated by the broken lines to produce a filter with a different response characteristic.

The filter characteristic may also be altered by shifting different coefficient control words into the latches 30-38. The new coefficient control words will establish different values for the weighting functions a,--a,,, ,, causing the input signals to be weighted differently for the production of a different response characteristic for the filter.

The filter order may also be altered by the coefficient control words. For instance, coefficient control words can be shifted into latches 30 and 38 which will cause weighting functions a0 and aN, to have values of zero. This will cause multipliers 20 and 28 to produce zero value output signals. The filter of Figure 1 will then be a third order filter, with non-zero weighted signals applied to adders 10, 12 and 14. The output signal of the third order filter is produced at the output of adder 14 and delayed two clock cycles by the following delay elements.

The use of coefficient multipliers in a digital filter is generally undesirable due to their complexity and low speed. Figure 2 shows an arrangement for a weighting function circuit, which replaces the latch-multiplier pairs of Figure 1. In Figure 2, the coefficient control word latches comprise serially coupled semi-dynamic shift registers 72 and 74. Multiplication is performed by a shift-and-add technique by shift matrices 76 and 78 and an adder 70. The x(n) input signal is applied to the inputs of the shift matrices, which can shift the bit positions of the applied signal to the right (i.e., to lower-order bit positions) under control of the coefficient control words. Each shift matrix can pass also the applied signal without shifting, in which case the applied signal is weighted by a value of one.If the input signal is shifted to the right by one bit position, it is weighted by one-half. Two shifts produces signals weighted by one-fourth, and so on. The shifted signals produced by the shift matrices are combined in adder 70, which produces a properly weighted input signal for an input tap of the filter.

For example, assume that shift matrix 76 shifts the x(n) input signal to the right by three bit positions, which produces (1/8)x(n). Also assume that the shift matrix 78 shifts the x(n) input signal to the right by four bit positions, which produces (1/1 6)x(n). The adder 70 will add these two weighted signals to produce an output signal of (3/16)x(n). Thus, the weighting function circuit of Figure 2 produces an x(n) signal weighted by a term which is a sum of multiples of inverse powers of two.

In Figure 3, one of the shift matrices of Figure 2 is shown in further detail in block diagram form.

The shift matrix of Figure 3 receives control signal INVERT, C,, C2 and C4, and their complements, which are bits of the coefficient control word stored in the appropriate semidynamic shift register 72 or 74. An x(n) input signal of eight bits, in this example, is applied to the input of an invert section 80 of the shift matrix. The invert section 80 will invert the x(n) signal or pass it through uninverted in accordance with the values of complementary control signals INVERT and INVERT. The signal produced by the invert section is then applied to a one-half weighting section 82, where it may be weighted by one-half or passed through unweighted, in accordance with the values of complementary control signals C, and C,. A nine-bit signal is produced by the one-half weighting section and applied to a one-quarter weighting section 84.In this section, the signal may be further weighted by one-quarter or passed through unweighted, in accordance with the value of complementary control signals C2 and C2.

Eleven-bit signals produced by weighting section 84 are applied to a one-sixteenth weighting section 86, which may weight the signal by a further factor of one-sixteenth or pass it through unweighted in accordance with the setting of complementary control signals C4 and C4. The weighted signal is then applied to a zeroer and buffer section 88, which receives a control signal from an AND gate 87. When the C1, C2 and C4 control signals applied to AND gate 87 are all true, section 88 will produce a zero value output signal. Otherwise, the weighted x(n) signal is only buffered by section 88 and applied to adder 70 of Figure 3.

The shifter matrix of Figure 3 may be controlled to weight the x(n) signal by factors of one, 1/2, 1/4, 1/8, 1/16, 1/32 or 1/64 in accordance with the values of the control signals. The weighted signal may also be inverted (one's complemented) or passed uninverted in accordance with the values of the INVERT and INVERT control signals.

For example, if two weighted signals are to be subtracted, then the signal to be subtracted from the other must first be two's complemented. The two's complementing operation produces a signal which has a value which is the negative of the value of the input signal. To two's complement a binary signal, the input signal bits are first inverted, then a binary '1', is added to the result. If the weighted signals are to be two's complemented, the INVERT control signal may also be applied to the least significant (carry-in) bit position of the adder 70 to complete the two's complementing process by adding 1 to the sum of the addend and the augend.

Figure 4 illustrates a four state shift register suitable for use as either of the semi dynamic shift registers 72 or 74 of Figure 2. The coefficient control bus 77 applies coefficient control word information to the input of the first stage 40 of four serially coupled latch stages 40-46. The information is transferred through the stages by complementary clock signals 0 and 0. When the 0 and 4i clocks stop, the information is held in the stages by complementary WRITE and WRITE clocks. The coefficient control word information is serially clocked through all the latches in all the weighting function circuits of the filter until the appropriate words are held in the proper registers.

Under those conditions, complementary INVERT and INVERT signals are held in latch stage 40, C, and C, signals are held in stage 42 C and C2 signals ' 2 2 signals are held in stage 44, and signals C4 and C4 are held in stage 46.

Referring to Figure 5, a semidynamic latch suitable for use as a latch stage 40, 42, 44 or 46 in the shift register of Figure 4 is shown in schematic diagram form. Four of the latches of Figure 5 may be cascaded to produce the fourstage shift register of Figure 4.

In Figure 5, the coefficient control signal is applied to a transmission gate 200, including two source-to-drain coupled complementary p-and ntype MOS transistors 202 and 204. The output of the transmission gate 200 is coupled to the input of an inverter 208, the output of which is coupled to a second transmission gate 210, including source-to-drain coupled complementary MOS transistors 212 and 214. The output of transmission gate 210 is coupled to the input of an inverter 218, the output of which is coupled to the input of a third transmission gate 220, including source-to-drain coupled complementary MOS transistors 222 and 224. The output of transmission gate 220 is coupled to the input of inverter 208. Complementary output signal OUT and OUT are produced at the outputs of inverters 218 and 208.

The semidynamic latch stage of Figure 5 is clocked by complementary clock signals # and 0, while gate 220 is open because the WRITE signal is high and the WRITE signal is low. When the clock signal is low and the 4 clock signal is high, the coefficient control signal is conducted through transmission gate 200 and stored across the input capacitance 206 of inverter 208. The and clock signal then change state (i.e. the 0 clock is high and the 0 clock is high), which opens transmission gate 200 and renders transmission gate 210 conductive. The signal level at the input of inverter 208 is inverted, transmitted through gate 210, and held at the input capacitance 21 6 of inverter 218.Once the latch has been loaded with the desired values, the WRITE signal goes low and the WRITE signal goes high, which renders transmission gate 220 conductive. The signal level at the input of inverter 218 is inverted by that inverter and transmitted through gate 220, thereby reinforcing the signal level stored at the input of inverter 208. The output signal of inverter 208 continues to be conducted by gate 210 to reinforce the signal level held at the input of inverter 218. Thus, the stored signal levels are maintained at the inputs of the two inverters through positive feedback and complementary output signals OUT and OUT are presented to the shifter matrix by the latch.

A more detailed embodiment of the shifter matrices 76 or 78 of Figure 2, suitable for fabrication in MOS integrated circuit form, is shown in Figure 6. In this Figure, metallized paths are represented by heavy sold lines, diffusion layer paths are represented by thin solid lines, and polysiiicon paths are represented by thin broken lines. Intersections of paths of the same type connote connections at those points. Signals are routed through the matrix by transmission gates formed by the intersections of the diffusion layer paths and the polysilicon paths under control of the signal levels on the polysilicon paths. When the signal on the polysilicon path is high, signals may pass through that point in the diffusion layer path; when the signal on the polysilicon path is low, signals are inhibited from passing through that point in the diffusion layer path.Transmission gates 50 and 90 are examples and are discussed in more detail below.

Bits B7-B0 of an eight-bit x(n) input signal are applied to a first column 100 of eight inverters in the invert section of the shifter matrix. Each of these inverters is bypassed by a controlled signal path which is part metallized conductor and part diffusion layer path. The outputs of the first eight inverters are coupled to inputs of a second column 102 of eight inverters. Output signals are produced by the second column of inverters on seven diffusion layer signal paths 1 10--1 16, and on path 117, which is part metallized conductor and part diffusion path.

The eight signal paths 1 10--1 17 first pass through the one-half weighting section 82, including a polysilicon path 1 30 which carries control signal C, and a polysilicon and metallized signal path 132 which carries control signal C,.

The eight signal paths 1 10--1 17 and a lower order bit signal path 120 next pass through the one-quarter weighting section 84, including a polysilicon path 140 which carries control signal C2 and a polysilicon and metallized path 142 which carries control signal C2. The eight signal paths 1 10--1 17 and three lower order bit signal paths 120-1 22 then pass through the one-sixteenth weighting section 86, including a polysilicon path 1 50 which carries control signal C4 and a polysilicon and metallized path 1 52 which carries control signal C4. Finally, the eight signal paths 1 10--1 17 and the three lower order bit signals paths 120-122 pass through a zeroer and buffer section 88. A zeroing circuit 160, includes a polysilicon path 166, a diffusion layer and metallized signal path 162 and a metallized ground bus 1 64. The eleven signal paths then are coupled to buffer circuit inverters of columns 170 and 172, which produce eleven output bits WB7WB 3.

The zeroing circuit 1 60 is controlled by signals from an AND gate 87, which receives input signals from the Cr, C2 and C4paths132,142,and152.

The output of AND gate 87 is coupled to metallized and polysilicon path 162, and to the input of an inverter 1 65. The output of inverter 1 65 is coupled to polysilicon path 166.

If the x(n) input signal is not to be inverted, the INVERT signal is low and the INVERT signal is high. The low INVERT signal opens the transmission gates (as described above) in the signal paths which bypass the first inverters 100, and the high INVERT signal closes the transmission gates at the inputs to the first inverters 100. The eight bits of the input signal are then doubly inverted by two inverters in each bit path, and the signals on lines 1 10--1 17 are not inverted with respect to the input signals.

The INVERT signal is also applied to the inputs of three inverters 104, 106 and 108, the outputs of which are coupled to the inputs of lower order bit signal paths 1 20, 121 and 122, respectively.

When the input signal is not to be inverted, the high INVERT signal causes inverters 104, 106 and 108 to apply zero value signal levels at the inputs of the lower order bit signal paths 120, 121 and 122.

When the invert section 80 is to invert the input signal, the INVERT signal is low and the INVERT signal is high. The INVERT signal will then open the transmission gates at the inputs to the first column 100 of inverters, and the INVERT signal will close the paths which bypass the first inverters. The bits of the input signal will then be inverted only once by inverters 102. At the same time, the low INVERT signal at the inputs of inverters 104, 106 and 108 produces logical one level signals at the inputs of fractional bit paths 120,121, 122. This provides a fully complemented eleven bit signal at the output of the shift matrix.

When the input signal is to be weighted by one-half by weighting section 82, the C, signal is high and their signal is low. The high C, signal on control path 132 then closes the diagonal paths connecting adjacent signal paths. Control path 130 also opens the signal paths 1 10--1 16 and 120 at points following the take-off points for the diagonal paths and prior to the points at which the signals are applied to respectively lower paths. Thus, signals on conductor 11 7 will be conducted to path 11 6, signals on path 11 6 will be conducted to path 11 5, and so forth.

(Signals on path 11 7 will be passed through unaffected since path 11 7 is a metallized path.) If the weighting section 82 is to pass the input signal without shifting, the C, signal is low, which opens the diagonal paths, and the C, signal closes paths 1 10--1 16 and 120 through the section.

Sections 84 and 86 function in a similar manner as section 82, except that the input signal is shifted by two and four bit positions, respectively, by these sections. Controls paths 140 and 1 50 control transmission gates in the direct paths 1 10--1 16 and 120-122, and control paths 142 and 152 control transmission gates in the diagonal signal paths for shifting. All of the weighting sections 82, 84 and 86 also replicate the most significant bit B7 as the signal is shifted down, for subsequent two's complement adding. For instance, when the input signal is weighted by one-sixteenth by section 86, the B7 signal on path 11 7 is also applied to paths 116,1 15, and 114, as well as path 1 13by way of diffusion path 1 54.

When control signals C1, C2 and C4 are all high, the shift matrix signal will be zeroed. The ANDing of these three signals by AND gate 87 places a high signal on conductor 1 62. This high signal then connects signal paths 1 10--122 to the grounded bus 1 64. At the same time, inverter 1 65 and polysilicon path 166 open all of the signal paths (including 117, which is a diffusion layer path) prior to the points at which they are grounded. A signal of all zeroes is then produced at the output of the buffer inverters 170 and 172.

By way of example, assume that the x(n) input signal is to be weighted by a factor of 1/64. This is accomplished by the operation of weighting section 84 and 86, which together provide shift of six bit positions. Bit B5 will be placed on signal path 11 5, by inverters in columns 100 and 102, and will pass directly through the one-half weighting section 82 staying on signal path 11 5.

Bit B5 will then be conducted to signal path 113 by weighting section 84, then to signal path 120 by weighting section 86. The original B5 bit of the input signal will then pass through the output WB, a shift of six places from its original position. All of the bits of the input signal will be shifted in this manner, thereby weighting the x(n) input signal by a factor of 1/64.

By reason of the operation of the invert section 80, of the shift matrix weighting function circuits using the shift matrix of Figure 6 can provide x(n) input signals weighted by terms which are either a sum or a difference of multiples of inverse powers of two. For instance, assume that the weighting function circuit of Figure 2 is to weight an applied signal by a factor of 1 5/64. One of the shift matrices can be controlled to shift the applied signal by two bit positions, thereby producing a signal of the form (1/4)x(n). The other shift matrix can be controlled to shift the applied signal by six bit positions, thereby producing a signal of the form (1/64)x(n). If the signals from this shifter matrix are inverted and '1' added to the result, a signal of the form (-1/64)x(n) is produced. The inversion is produced by operation of the invert section 80 of the shift matrix, and the '1' is added by placing a '1' on the carry-in input of adder 7G, as described above. When the adder 70 adds these two signals, a weighted signal of the form (15/64)x(n) results. Such a term could not be produced by two shift matrices without the invert feature.

The shift matrix of Figure 6 may be comprised of a number of identically constructed cells, such as the cell shown in Figure 7. The shifter cell of Figure 7 contains portions of two shift matrices, and is used to construct the two shift matrices 76 and 78 of Figure 2. The finished cell array will contain the two matrices in an interwoven configuration for economical use of a semiconductor device.

The cell of Figure 7 comprises four transmission gates 50, 90, 50' and 90' each comprising parallel coupled MOS transistors.

Gates 50 and 90 direct bits of one shift matrix, and gates 50' and 90' direct bits of the second shift matrix. Bit B5 on conductor 11 5 of the first matrix is applied to transistors 52 and 54 of gate 50. Conductor 11 5 continues from the output of gate 50. Bit B6 on conductor 11 6 of the first matrix is applied to transistors 92 and 94 of gate 90. The output of gate 90 is also connected to the continuation of conductor 11 5. Transistors 52 and 94 are controlled by the C, signal on control line 132, and transistors 54 and 92 are controlled by the C, signal on control line 130.

The other half of the cell of Figure 7 directs bits of the second shift matrix and is constructed in a similar manner as the first half. Bit B5, on conductor 11 5' of the second matrix is coupled to the input of gate 50', the output of which is coupled to the continuation of conductor 11 5'. Bit B5, on conductor 116' of the second matrix is coupled to the input of gate 90', the output of which is also coupled to conductor 115'.

Transistors 92' and 54' of gates 90' and 50' are controlled by signal C,' on control line 132', and transistors 94' and 52' of gates 90' and 50' are controlled by signal C,', on control line 130'.

The cell of Figure 7 is arranged as a part of one-half weighting section 82 of Figure 6, in which transmission gates 50 and 90 are designated by corresponding reference numerals in the shifter matrix 76, of Figure 2, for example.

The two halves of the cell operate independently in accordance with the C1,C1, and C,', C,', control signals respectively. For instance, if control signal C, is low and signal C, is high, section 82 will pass the applied bits without shifting. Under these conditions, transistors 52 and 54 of gate 50 are conductive and transistors 92 and 94 of gate 90 are open. Bit B5 on conductor 11 5 is then conducted through gate 50 and appears on the continuation of conductor 11 5 at the output of the gate. Bit B5 then passes on to the next weighting section 84 of the first matrix.

When it is desired to weight the input signal by a factor of one-half, the C, signal is high and the C, signal is low. Under these conditions, transistors 92 and 94 are rendered conductive and transistors 52 and 54 are open. The B6 bit on conductor 11 6 is then conducted through gate 90 and appears on the continuation of conductor 11 5. Bit B, has now been shifted to the position of original bit B5, a shift of one bit position, and now passes on to the next weighting section 84.

The lower half of the cell performs a similar function in the second shift matrix 78 of Figure 2, for example. When signal C,' is low and signal C,' is high, bit Bsl on conductor 11 5' is conducted through gate 50' to the continuation of conductor 11 5' and on to the next section 84'. When signal C,' is high and signal C1, is low, gate 90', is conductive to pass bit B6, from conductor 11 6' to the continuation of conductor 11 5'.

When the cell of Figure 7 is fabricated as one of an array of similar cells on an integrated circuit chip, the two matrics are intertwined in a checkerboard pattern. The cell located beiow the cell of Figure 7 will receive bits B5, B4, B5,, and B4', and produce signals on the continuation of conductors 114 and 114'. In one-quarter weighting section 84, one cell will receive bits B,, B4, Bus', and B4', and will produce output signals on the continuation of conductors 114 and 1 14'.

It has been found that integrated circuit layout is eased by reversing the order of the matrices from one vertical cell to another. For instance, in Figure 7, bits B6 and B5 of the first matrix are applied to the upper half of the cell and bits B ,' and B5, of the second matrix are applied to the lower half of the cell. In the next vertical cell in the array, bits B5, and B4, of the second matrix are applied to the upper half of the cell and bits B6 and B4 of the first matrix are applied to the lower half.

It may also be appreciated that cells can be arranged with their inputs and outputs reversed from those shown in Figure 7. Instead of multiplexing two input bits to one output line, the cells can alternately be arranged to multiplex one input bit to one of two output lines.

The described weighting function circuits and shift matrices are particularly useful in a modular filter of the type described in United States patent application number 363,826, entitled "Folded FIR Filters", by Lauren A, Christopher and Steven A.

Steckler, corresponding to British Patent Application 22992/82 RCA 77399 entitled :'Digital Fir Filter".

Claims (15)

Claims

1. A controllable shift matrix having input and output terminals, responsive to bits of an input signal word at said input terminals of ascending order from a least significant bit position to a most significant bit position for controllably producing an output signal at said output terminals in which the input signal bits may occupy respectively different bit positions, comprising::- a plurality of sections including at least one divide-by section coupled between said input and output terminals having inputs and outputs and including controlled switch means responsive to a first control signal for selectively passing bits on said divide-by input lines to said divide-by output lines of the same order as said divide-by input line bit positions, or transferring said divide-by input line bits to respective ones of said divide-by output lines which are more than one bit position lower in order than said divide-by input line bit positions.

2. The controllable shift matrix of Claim 1, wherein said divide-by section comprises a divide-by-four section for selectively transferring said divide-by input line bits to respective ones of said divide-by output lines which are two bit positions lower in order than said divide-by input line bit positions; and further comprising: a divide-by-sixteen section coupled between said input terminals and said output terminals, having inputs and outputs and including controlled switch means responsive to a second control signal for selectively passing bits on said divide-by-sixteen input lines to said divide-bysixteen output lines of the same order as said divide-by-sixteen input line bit positions, or transferring said divide-by-sixteen input line bits to respective ones of said divide-by-sixteen output lines which are four bit positions lower in order then said divide-by-sixteen input line bit positions and a divide-by-two section coupled between said input and output terminals having inputs and outputs and including controlled switch means responsive to a third control signal for selectively passing said divide-by-two input signal bits to said divide-by-two output lines of the same order as said divide-by-two input bit positions, or transferring said divide-by-two input signal bits to respective ones of said divide-by-two output lines which are one bit position lower in order than said divide-by-two input bit positions.

3. The controllable shift matrix of Claim 2, further comprising an inverting section coupled between said input and output terminals having inputs and outputs and responsive to a fourth control signal for selectively passing the bits at said inverter inputs in an inverted form or a noninverted form to said inverter outputs.

4. The controllable shift matrix of Claim 2, further comprising a zeroing section coupled between said input and output terminals having inputs and outputs, and responsive to a fourth control signal for selectively passing bits present on said zeroer input lines to said zeroer outputs, or producing zero bit level signals at said zeroer Outputs.

5. The controllable shift matrix of Claim 2 further comprising a plurality of buffers coupled between said input and output terminals having respective inputs and a plurality of Outputs.

6. The controllable shift matrix of any preceding claim wherein said controlled switch means comprise transmission gates.

7. The controllable shift matrix of anyone of claims 1 to wherein said matrix is in a digital signal processing system, for controllably shifting the bits of applied digital words to different bit positions, said digital signal processing system comprising: a source of shift control signals; wherein said controlled shift matrix has said input terminals coupled to receive the bits of said digital words in parallel, said control signals are coupled to receive said shift control signals, and which produces controllably shifted digital words at said output terminals.

8. A plurality of controllable shift matrices, preferably of the type recited in Claim 1 wherein said matrices are in a digital filter which produces filtered output signals by combining weighted time-sequential samples of a digital input signal and includes a weighting function circuit comprising: a first controllable shift matrix having said input terminals receive a digital signal which is to be weighted, and said output terminals produce said digital signal shifted by a first predetermined number of bit positions; a second controllable shift matrix having said input terminals receive said digital signal, and said output terminals produce said digital signal shifted by a second predetermined number of bit positions; and an adder having a first input coupled to said output terminals of said first controllable shift matrix, a second input coupled to said output terminals of said second controllable shift matrix, and an output at which a weighted signal is produced.

9. The arrangement of Claim 8 further comprising: a source of shift matrix control signals; and a first register having an input coupled to receive said shift matrix control signals and an output coupled to said first controllable shift matrix, for supplying said control signals thereto, wherein said shift matrix control signals control said first controllable shift matrix so as to shift applied digital signals by said first predetermined number of bit positions.

10. The arrangement of Claim 9 further comprising: a second register having an input coupled to receive said shift matrix control signals and an output coupled to said second controllable shift matrix so as to control said second controllable shift matrix to shift applied digital signals by said second predetermined number of bit positions.

11. The arrangement of Claim 8 wherein said first controllable shift matrix comprises: said input terminals receiving bits of said digital signal in parallel; a first shift section coupled to said input terminal of said first shift matrix for controllabiy shifting said bits of said digital signal by one bit position; said divide-by section coupled to said first section for controllably shifting said bits of said digital signal by two bit positions; and a second shift section, coupled to said divideby section, for controllably shifting said bits of said digital signal by four bit positions.

1 2. The arrangement of Claim 11 wherein said shift and divide-by sections each include a plurality of transmission gates for controllably shifting bits of said digital signal to lower order bit positions of a digital output signal.

13. The arrangement of Claim 12 further comprising: an inverting section, coupled to said first shift section, for controllably complementing said bits of said digital signal.

14. The arrangement of Claim 12 further comprising: a zeroing section, coupled to said third shift section, for controllably forcing the bits of said digital signal to zero bit values.

1 5. A controllable shift matrix substantially as hereinbefore described with reference to Figure 3 or to Figure 3 together with one or more of Figures 4-7.

1 6. A digital filter comprising a controllable shift matrix according to anyone of claims 1-6 or

15.

1 7. A digital filter substantially as hereinbefore described with reference to Figures 1 and 3 optionally together with one or more of Figures 4-7.

1 8. A weighting function circuit comprising first and second controllable shift matrices, each according to anyone of Claims 1-6, and a combining circuit wherein the inputs of the matrices are both arranged to receive bits of an input signal word to be weighted and the outputs of the matrices are coupled to the combining circuit which is arranged to combine the bits produced at the outputs of the matrices to produce a weighted word.

1 9. A weighting circuit substantially as hereinbefore described with reference to Figures 2 and 3 and optionally one or more of Figures ai 7.