CA1144993A - Delay circuit - Google Patents
Delay circuitInfo
- Publication number
- CA1144993A CA1144993A CA000323403A CA323403A CA1144993A CA 1144993 A CA1144993 A CA 1144993A CA 000323403 A CA000323403 A CA 000323403A CA 323403 A CA323403 A CA 323403A CA 1144993 A CA1144993 A CA 1144993A
- Authority
- CA
- Canada
- Prior art keywords
- circuit
- flip
- output
- counter
- flop
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
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- Channel Selection Circuits, Automatic Tuning Circuits (AREA)
Abstract
ABSTRACT OF THE DISCLOSURE:
A delay circuit comprising a counter, a flip-flop circuit, a circuit for holding them to their reset conditions during presence of a first signal and a gate circuit having a second signal on its input and put to ON and OFF by the output from the flip-flop circuit, can provide in a digital manner a relatively long delay time from the end of the first signal to the stop of the output of the second signal and with ease even designed as an integrated circuit. The delay circuit is suitable to be used in a tuning ciruit of an electronic tuning type ratio receiver.
A delay circuit comprising a counter, a flip-flop circuit, a circuit for holding them to their reset conditions during presence of a first signal and a gate circuit having a second signal on its input and put to ON and OFF by the output from the flip-flop circuit, can provide in a digital manner a relatively long delay time from the end of the first signal to the stop of the output of the second signal and with ease even designed as an integrated circuit. The delay circuit is suitable to be used in a tuning ciruit of an electronic tuning type ratio receiver.
Description
?93 This invention concerns a digital type delay circuit capable of changing the output state with a predetermined time after the elimination of the input s lgnal .
To enable the prior art to be described with the aid of diagrams, the figures of the drawings will first be listed.
Fig. 1 is a circuit diagram showing a typical example of a conventional delay circuit;
Fig. 2 is a waveform chart for describing the operation of the circuit shown in Fig. l;
Fig. 3 is a block diagram showing a preferred embodiment of delay circuit according to this invention;
Fig. 4 is a block diagram showing an embodiment to which the delay circuit of this invention is applied;
and Fig. 5 and Fig. 6 are waveform charts for describing the operation of the circuit shown in Fig. 3.
Delay circuits or timer circuits for changing the output state a predetermined time after the elimination of the input signal have been employed in various control circuits or the likes. The conventional circuits of this type typically include an integration circuit using a resistor 12 and a capacitor 14 as shown in Fig. 1. In this circuit, each of pulse wave in continuous pulse waves 22 supplied to an input terminal 10 is smoothed through an integration circuit composed of the resistor 12 and the capacitor 14 as shown in a waveform 24, shaped in a buffer amplifier 18 and then issued from an output terminal 20 in a continuous waveform, that is, in a rectangular wave as shown in a waveform 26. Since the output waveform takes a level "1" during input of the pulse wave 22 and turns to a
To enable the prior art to be described with the aid of diagrams, the figures of the drawings will first be listed.
Fig. 1 is a circuit diagram showing a typical example of a conventional delay circuit;
Fig. 2 is a waveform chart for describing the operation of the circuit shown in Fig. l;
Fig. 3 is a block diagram showing a preferred embodiment of delay circuit according to this invention;
Fig. 4 is a block diagram showing an embodiment to which the delay circuit of this invention is applied;
and Fig. 5 and Fig. 6 are waveform charts for describing the operation of the circuit shown in Fig. 3.
Delay circuits or timer circuits for changing the output state a predetermined time after the elimination of the input signal have been employed in various control circuits or the likes. The conventional circuits of this type typically include an integration circuit using a resistor 12 and a capacitor 14 as shown in Fig. 1. In this circuit, each of pulse wave in continuous pulse waves 22 supplied to an input terminal 10 is smoothed through an integration circuit composed of the resistor 12 and the capacitor 14 as shown in a waveform 24, shaped in a buffer amplifier 18 and then issued from an output terminal 20 in a continuous waveform, that is, in a rectangular wave as shown in a waveform 26. Since the output waveform takes a level "1" during input of the pulse wave 22 and turns to a
- 2 -1~4~93 level "0" after a predetermined tlme ~t from the stop of the pulse wave input, a gate can be switched to open or close with a predetermined time ~t from the interruption of the input 22 if the gate is controlled by the output 26.
It is, however, difficult to set the time constant and, thus, the delay time ~t of the delay circuit to the value of milli seconds or more if the circuit is designed as an integrated circuit, since a capacitor that can be formed in an integrated circuit generally has a capacitance of an order as low as several picofarads.
This invention has been created in order to overcome such a disadvantage and the object thereof is to provide a delay circuit capable of having a delay time of a sufficient length even designed as an integrated circuit.
Another object of this invention is to provide a delay circuit capable of optionally varying the length of the delay time in a digital manner.
The delay circuit according to this invention comprises as RS (set and reset) flip-flop circuit and a counter and is adapted to hold the counter and the flip-flop circuit to their reset conditions while the input signal is present, release the above reset conditions to start the counting for clock signals at the instant the input signal ceases arriving, set the flip-flop by the output generated from the coun~er upon counting up to the predetermined counting value corres-ponding to a desired delay time, and put the gate to open or close by the output thereof. Without requiring for capacitor of great capacitance, this delay circuit can easily be designed as an integration circuit and optionally vary the delay time by merely changing the above predetermined counting value preset to the counter.
DETAILED DESCRIPTION OF THE EMBODIMENTS
. .
Referring to Fig. 3, a counter is constituted by a flip-flop circuit 32 having a clock signal Bo at its input terminals Cpl by way of a lead 42, and another flip-flop circuit 34 having a Q output from the flip-flop counter circuit 32 at its input terminal Cp2.
Reference numeral 30 denotes a NOR circuit, which receives signals X0 and Y0, and reference numeral 36 denotes as RS (set and reset) flip-flop circuit having the output from the above counter at its input and reference numeral 38 denotes an AND circuit having a Q output from the flip-flop circuit 36 to one of its input terminals by way of a lead 44 and a signal Sd to be described later at its other input terminal by way of a lead 46. The circuit 38 is further connected at its output by way of lead 48 to a multiplexer 62 or the like to be described later. The output of the NOR circuit 30 is delivered by way of a lead 40 to each of the input of reset terminals R of the flip-flop circuits 32, 34 and 36.
The delay circuit of this embodiment can be used in an automatic electronic tuning type car radio receiver. An audience for the automatic electronic tuning type radio receiver can take several means in channel selection. They include those tuning systems such as a digital tuning system in which numerical values corres-ponding to transmitting frequency for each of broadcasting stations are stored in a memory and the desired value among them are designated to select the channel, a search tuning system in which receivable frequency is continuously changed by way of electronic scanning to select the channels for each of the broadcasting stations in a broadcasting frequency band successively, and a manual ~49~3 tuning system in which tuning is executed by manually changing the receivable frequency by means of the ON-OFF
operation of a switch and the like. The digital setting system among the above tuning systems is to be outlined referring to Fig. 4. The present local oscillation frequency taken out from a tuning section 50 in a radio receiver is sampled and divided through a decimal counter 52 into 1/10 frequency to obtain each one pulse Pl on every 10 KHz for an AM band and on every 100 KHz for an FM
band. These pulses are counted in a counter 54 preset to an appropriate value to obtain a binary code P2 which starts from 000 ........ 0 at the beginning of each of broadcasting frequency bands for the AM and FM and increases by search one on every 30 KHz for the AM band and on every 400 KHz for the FM band. Since the frequency is allocated to each of the broadcasting stations by every ]0 KHz unit for the AM band and by every 100 KHz unit for the FM band, and the frequencies for the broadcasting stations in a same district are properly separated from each other, the frequency for each of the broadcasting stations can generally be expressed by one of the above binary codes P2. In the radio receiver, the same code as that of the above binary code P2 is written into the Read Only Memory in a digital setter 58 and one of the code P3 corresponding to the desired broadcasting station is read out by a switching operation and inputted to a comparator 56. The comparator 56 compares these codes P2 and P3 and outputs signals X0 or Y0 instructing the increase (if P2<P3) or decreases (if P2>P31 for the receiving frequency by way of an output control section 60. The signal X0 or Y0 is inputted by way of a multiplexer 62 selecting one of various channel B
selection systems into a voltage memory device 64 to instruct the gradual increase or decrease in its output voltage VO. The voltage memory device 64, basically, consists of an integration circuit, which integrates its positive or negative input voltage to result in gradual increase or decrease in the output voltage. When the input voltage becomes 0, the level of the output voltage resulted then is changed no further and the memory keeps to output it at that level for a long time. The output voltage VO is applied to a voltage-dependent variable capacitance diode not shown in the tuning section 50 to vary its capacitance value thereby increasing or 1~4~93 decr~asing the tuning frequency, that is, receiving (receivable) frequency. When the receiving frequency coincides with the frequency of a desired broadcasting station, the relation P2 = P3 is attained, that is, both of the signals X0 and Y0 take a low level L to stop the change in the out put voltage V0 from the voltage memory device 64, where the receiving condition is achieved.
The digital tuning has thus been completed and the output voltage from an automatic frequency control circuit (not shown) is now applied to the above voltage-dependent variable capacitance diode by way of the multiplexer 62 and so forth for automatic fine adjustment for the receiving frequency during the receiving states always to enable the reception at the best condition.
The transfer from the completion of the digital tuning to the AFC receiving condition or to.other tuning conditions is preferabl effected with a certain delay and the delay circuit shown in Fig. 3 is used for su'ch purpose.
The operation of the circuit shown in Fig. 3 is to be described referring to time charts shown in Fig. 5 and Fig. 6.
To the input terminal CPl of the flip-flop circuit 32, is inputted a clock signal Bo~ which is a "B" output from a decimal counter such as the counter 52 shown in Fig. 4 and has a waveform as shown in Fig. 5. In fig. 5, (S) represents the input signal l to the counter 52 and each of (A), (B), (C) and (D) represents l the output waveform from the counter corresponding to 2, 21, 2 l and 23 for each of the output stages A-D. Although the signal ll 1144993 Bo is delivered to the input of the counter consisting of the flip-flop cir~ts 32 and 34, counting is not executed while at least one of the signals X0 and Y0 is at a high level H since the output of the NOR circuit 30 remains at a low level L, which is delivered by~way of the lead 40 to the reset terminals R to reset the counters 32 and 34. The low level output L from the NOR circuit 30 is also applied to the flip-flop circuit 36 to reset it causing it ~ output to take a high level H as sho~n in Fig. 6 (Q3), which is delivered by way of the lead 44 to one of the input terminals of the AND circuit 38. Since the AND circuit 38 has at its the other input terminal the signal Sd which takes a high level EI upon digital tuning, the circuit 38 shows a high level output H, and it is inputted to the above multiplexer 62 to switch the tuning circuit into the digital tuning mode.
The signals X0 and Y0 alternately take a high level H
and a low level L and, as shown in (X0 + Y0) in Fig. 6, take a rectangular waveform with a smaller duty ratio if the receiving frequency is far from the set frequency and with a smaller duty ratio if the former comes closer to the latter. Such a waveform shaping is executed in the output control section 60 shown in Fig. 4 for the purpose of varying the tuning speed depending on th , detuning degree, for the provision of a time required for sampling and counting or the like. Accordingly, while the flip-flop circui ts 32 and 34 are reset and released from the reset repeatedly, they are securely kept reset at the point of inputting the clocks ~0 as apparent from Fig. 6 and the Q output from the flip-flop circuit 32 and the Q output from the flip-flop circuit 32 and the Q output from the fli.p-flop circuit 34 remain at the low level L and the high level H respectively during the presence of the signals X0 or Y0 as shown by (Ql) and (Q2) in Fig. 6.
Then when the relation P2 = P3 is attained at a point t and both of the signals X0 and Y0 take a low lwvel L, the output from the NOR circuit 30 takes a high level H as shown by (X0 + Y0) in F.ig. 5 to release the reset for the flip-flop circuits 32 and 34. Then, the counters 32 and 34 start to count the clock signals Bo~ Upon arrival of the first clock, the Q output Ql form the flip-flop circuit 32 takes a high level H and, upon arrival of the next clock, the output Ql takes a low level L and the output Q2 and Q3 from the flip-flop circuits 34 and 36 take a .
low level L thereby turning the output from the AND circuit 38 to a low level L. In this way, the digital tuning is stopped after 2 clocks, that is after a.time ~t (= 10 mS in this embodi-ment) from the elimination of the signals X0 and Y0 and switched to the AFC ~eceiving condition. It will be apparent that a greater time delay can be provided for the switching deponding on the value preset to the counters 32 and 34, that is, the number of the clocks supplied to them from the release of the reset and the generati.on of the counter output, which can optionally be increased.
g _ " , I
11~4~93 As foregoings, according to this invention, a digital type delay or timer circuit can be obtained which is free from the use of a large value capacitor and therefore extremely advantageous when designed as an integrated circuit. This invention is no way limited to the embodiment shown above but can take various other modifications within the scope of the invention.
It is, however, difficult to set the time constant and, thus, the delay time ~t of the delay circuit to the value of milli seconds or more if the circuit is designed as an integrated circuit, since a capacitor that can be formed in an integrated circuit generally has a capacitance of an order as low as several picofarads.
This invention has been created in order to overcome such a disadvantage and the object thereof is to provide a delay circuit capable of having a delay time of a sufficient length even designed as an integrated circuit.
Another object of this invention is to provide a delay circuit capable of optionally varying the length of the delay time in a digital manner.
The delay circuit according to this invention comprises as RS (set and reset) flip-flop circuit and a counter and is adapted to hold the counter and the flip-flop circuit to their reset conditions while the input signal is present, release the above reset conditions to start the counting for clock signals at the instant the input signal ceases arriving, set the flip-flop by the output generated from the coun~er upon counting up to the predetermined counting value corres-ponding to a desired delay time, and put the gate to open or close by the output thereof. Without requiring for capacitor of great capacitance, this delay circuit can easily be designed as an integration circuit and optionally vary the delay time by merely changing the above predetermined counting value preset to the counter.
DETAILED DESCRIPTION OF THE EMBODIMENTS
. .
Referring to Fig. 3, a counter is constituted by a flip-flop circuit 32 having a clock signal Bo at its input terminals Cpl by way of a lead 42, and another flip-flop circuit 34 having a Q output from the flip-flop counter circuit 32 at its input terminal Cp2.
Reference numeral 30 denotes a NOR circuit, which receives signals X0 and Y0, and reference numeral 36 denotes as RS (set and reset) flip-flop circuit having the output from the above counter at its input and reference numeral 38 denotes an AND circuit having a Q output from the flip-flop circuit 36 to one of its input terminals by way of a lead 44 and a signal Sd to be described later at its other input terminal by way of a lead 46. The circuit 38 is further connected at its output by way of lead 48 to a multiplexer 62 or the like to be described later. The output of the NOR circuit 30 is delivered by way of a lead 40 to each of the input of reset terminals R of the flip-flop circuits 32, 34 and 36.
The delay circuit of this embodiment can be used in an automatic electronic tuning type car radio receiver. An audience for the automatic electronic tuning type radio receiver can take several means in channel selection. They include those tuning systems such as a digital tuning system in which numerical values corres-ponding to transmitting frequency for each of broadcasting stations are stored in a memory and the desired value among them are designated to select the channel, a search tuning system in which receivable frequency is continuously changed by way of electronic scanning to select the channels for each of the broadcasting stations in a broadcasting frequency band successively, and a manual ~49~3 tuning system in which tuning is executed by manually changing the receivable frequency by means of the ON-OFF
operation of a switch and the like. The digital setting system among the above tuning systems is to be outlined referring to Fig. 4. The present local oscillation frequency taken out from a tuning section 50 in a radio receiver is sampled and divided through a decimal counter 52 into 1/10 frequency to obtain each one pulse Pl on every 10 KHz for an AM band and on every 100 KHz for an FM
band. These pulses are counted in a counter 54 preset to an appropriate value to obtain a binary code P2 which starts from 000 ........ 0 at the beginning of each of broadcasting frequency bands for the AM and FM and increases by search one on every 30 KHz for the AM band and on every 400 KHz for the FM band. Since the frequency is allocated to each of the broadcasting stations by every ]0 KHz unit for the AM band and by every 100 KHz unit for the FM band, and the frequencies for the broadcasting stations in a same district are properly separated from each other, the frequency for each of the broadcasting stations can generally be expressed by one of the above binary codes P2. In the radio receiver, the same code as that of the above binary code P2 is written into the Read Only Memory in a digital setter 58 and one of the code P3 corresponding to the desired broadcasting station is read out by a switching operation and inputted to a comparator 56. The comparator 56 compares these codes P2 and P3 and outputs signals X0 or Y0 instructing the increase (if P2<P3) or decreases (if P2>P31 for the receiving frequency by way of an output control section 60. The signal X0 or Y0 is inputted by way of a multiplexer 62 selecting one of various channel B
selection systems into a voltage memory device 64 to instruct the gradual increase or decrease in its output voltage VO. The voltage memory device 64, basically, consists of an integration circuit, which integrates its positive or negative input voltage to result in gradual increase or decrease in the output voltage. When the input voltage becomes 0, the level of the output voltage resulted then is changed no further and the memory keeps to output it at that level for a long time. The output voltage VO is applied to a voltage-dependent variable capacitance diode not shown in the tuning section 50 to vary its capacitance value thereby increasing or 1~4~93 decr~asing the tuning frequency, that is, receiving (receivable) frequency. When the receiving frequency coincides with the frequency of a desired broadcasting station, the relation P2 = P3 is attained, that is, both of the signals X0 and Y0 take a low level L to stop the change in the out put voltage V0 from the voltage memory device 64, where the receiving condition is achieved.
The digital tuning has thus been completed and the output voltage from an automatic frequency control circuit (not shown) is now applied to the above voltage-dependent variable capacitance diode by way of the multiplexer 62 and so forth for automatic fine adjustment for the receiving frequency during the receiving states always to enable the reception at the best condition.
The transfer from the completion of the digital tuning to the AFC receiving condition or to.other tuning conditions is preferabl effected with a certain delay and the delay circuit shown in Fig. 3 is used for su'ch purpose.
The operation of the circuit shown in Fig. 3 is to be described referring to time charts shown in Fig. 5 and Fig. 6.
To the input terminal CPl of the flip-flop circuit 32, is inputted a clock signal Bo~ which is a "B" output from a decimal counter such as the counter 52 shown in Fig. 4 and has a waveform as shown in Fig. 5. In fig. 5, (S) represents the input signal l to the counter 52 and each of (A), (B), (C) and (D) represents l the output waveform from the counter corresponding to 2, 21, 2 l and 23 for each of the output stages A-D. Although the signal ll 1144993 Bo is delivered to the input of the counter consisting of the flip-flop cir~ts 32 and 34, counting is not executed while at least one of the signals X0 and Y0 is at a high level H since the output of the NOR circuit 30 remains at a low level L, which is delivered by~way of the lead 40 to the reset terminals R to reset the counters 32 and 34. The low level output L from the NOR circuit 30 is also applied to the flip-flop circuit 36 to reset it causing it ~ output to take a high level H as sho~n in Fig. 6 (Q3), which is delivered by way of the lead 44 to one of the input terminals of the AND circuit 38. Since the AND circuit 38 has at its the other input terminal the signal Sd which takes a high level EI upon digital tuning, the circuit 38 shows a high level output H, and it is inputted to the above multiplexer 62 to switch the tuning circuit into the digital tuning mode.
The signals X0 and Y0 alternately take a high level H
and a low level L and, as shown in (X0 + Y0) in Fig. 6, take a rectangular waveform with a smaller duty ratio if the receiving frequency is far from the set frequency and with a smaller duty ratio if the former comes closer to the latter. Such a waveform shaping is executed in the output control section 60 shown in Fig. 4 for the purpose of varying the tuning speed depending on th , detuning degree, for the provision of a time required for sampling and counting or the like. Accordingly, while the flip-flop circui ts 32 and 34 are reset and released from the reset repeatedly, they are securely kept reset at the point of inputting the clocks ~0 as apparent from Fig. 6 and the Q output from the flip-flop circuit 32 and the Q output from the flip-flop circuit 32 and the Q output from the fli.p-flop circuit 34 remain at the low level L and the high level H respectively during the presence of the signals X0 or Y0 as shown by (Ql) and (Q2) in Fig. 6.
Then when the relation P2 = P3 is attained at a point t and both of the signals X0 and Y0 take a low lwvel L, the output from the NOR circuit 30 takes a high level H as shown by (X0 + Y0) in F.ig. 5 to release the reset for the flip-flop circuits 32 and 34. Then, the counters 32 and 34 start to count the clock signals Bo~ Upon arrival of the first clock, the Q output Ql form the flip-flop circuit 32 takes a high level H and, upon arrival of the next clock, the output Ql takes a low level L and the output Q2 and Q3 from the flip-flop circuits 34 and 36 take a .
low level L thereby turning the output from the AND circuit 38 to a low level L. In this way, the digital tuning is stopped after 2 clocks, that is after a.time ~t (= 10 mS in this embodi-ment) from the elimination of the signals X0 and Y0 and switched to the AFC ~eceiving condition. It will be apparent that a greater time delay can be provided for the switching deponding on the value preset to the counters 32 and 34, that is, the number of the clocks supplied to them from the release of the reset and the generati.on of the counter output, which can optionally be increased.
g _ " , I
11~4~93 As foregoings, according to this invention, a digital type delay or timer circuit can be obtained which is free from the use of a large value capacitor and therefore extremely advantageous when designed as an integrated circuit. This invention is no way limited to the embodiment shown above but can take various other modifications within the scope of the invention.
Claims (2)
1. A delay circuit comprising a counter for counting clocks, a flip-flop circuit to be set by the output generated from said counter upon counting up to a predetermined number of the clocks, a circuit for holding the counter and the flip-flop circuit to their reset conditions while a first input signal is present and a gate circuit applied with a second input signal and put to open and close by the output from said flip-flop circuit.
2. A delay circuit comprising a counter consisting of a plurality of flip-flop circuits in a cascade connection for counting clocks, an RS flip-flop circuit to be set by the output generated from said counter upon counting up to a predetermined number of the clocks, a NOR circuit inputted with each of instruction signals for the increase and decrease of the receiving signal in an electronic tuning type radio receiver and generating an output for holding the counter and the RS flip-flop circuit to their reset conditions while either of the above instruction signals is present and an AND circuit inputted with signals for instructing one out of various types of tuning modes and put to open and close by the output from said RS flip-flop circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA000323403A CA1144993A (en) | 1979-03-14 | 1979-03-14 | Delay circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA000323403A CA1144993A (en) | 1979-03-14 | 1979-03-14 | Delay circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1144993A true CA1144993A (en) | 1983-04-19 |
Family
ID=4113742
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000323403A Expired CA1144993A (en) | 1979-03-14 | 1979-03-14 | Delay circuit |
Country Status (1)
| Country | Link |
|---|---|
| CA (1) | CA1144993A (en) |
-
1979
- 1979-03-14 CA CA000323403A patent/CA1144993A/en not_active Expired
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MKEX | Expiry |