JPS61224448A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS61224448A
JPS61224448A JP60065231A JP6523185A JPS61224448A JP S61224448 A JPS61224448 A JP S61224448A JP 60065231 A JP60065231 A JP 60065231A JP 6523185 A JP6523185 A JP 6523185A JP S61224448 A JPS61224448 A JP S61224448A
Authority
JP
Japan
Prior art keywords
region
conductivity type
type impurity
insulating film
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60065231A
Other languages
Japanese (ja)
Inventor
Hiroshi Iwasaki
博 岩崎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP60065231A priority Critical patent/JPS61224448A/en
Priority to EP86102856A priority patent/EP0193934B1/en
Priority to DE86102856T priority patent/DE3688711T2/en
Publication of JPS61224448A publication Critical patent/JPS61224448A/en
Priority to US07/730,518 priority patent/US5144408A/en
Priority to US07/989,455 priority patent/US5280188A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8222—Bipolar technology
    • H01L21/8226—Bipolar technology comprising merged transistor logic or integrated injection logic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
    • H01L21/2257—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer being silicon or silicide or SIPOS, e.g. polysilicon, porous silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8248—Combination of bipolar and field-effect technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8248—Combination of bipolar and field-effect technology
    • H01L21/8249—Bipolar and MOS technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0214—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L
    • H01L27/0229—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L of bipolar structures
    • H01L27/0233—Integrated injection logic structures [I2L]
    • H01L27/0244—I2L structures integrated in combination with analog structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H01L29/456—Ohmic electrodes on silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors
    • H01L29/732—Vertical transistors
    • H01L29/7325—Vertical transistors having an emitter-base junction leaving at a main surface and a base-collector junction leaving at a peripheral surface of the body, e.g. mesa planar transistor

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Bipolar Transistors (AREA)
  • Bipolar Integrated Circuits (AREA)

Abstract

PURPOSE:To prevent fluctuation of the characteristics such as current amplification factor by a method wherein with the electrode material layer pattern CONSTITUTION:After a polycrystalline siicon layer 30 containing no impurity is deposited on the whole surface by the CVD method, arsenic is ion-implanted.

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明はウォールドエミッタ構造のパーティカルバイポ
ーラトラジスタ等、フィールド酸化膜端から二重拡散を
形成して半導体装置を製造する方法の改良に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an improvement in a method for manufacturing a semiconductor device such as a walled emitter structure particulate bipolar transistor by forming a double diffusion from the edge of a field oxide film.

（発明の技術的背景） フィールド酸化膜端から二重拡散による不純物領域を形
成したバイポーラ型半導体装置の代表例としては、第２
図に示すウォールドエミッタ構造のパーティカルＮＰＮ
トランジスタが挙げられる。(Technical Background of the Invention) As a typical example of a bipolar semiconductor device in which an impurity region is formed from the edge of a field oxide film by double diffusion,
Particle NPN with walled emitter structure shown in the figure
An example is a transistor.

同図において、１はＰ型シリコン基板、２はＮ＋型型埋
領領域３はＮ型エピタキシャルシリコン層、４はフィー
ルド酸化膜、５は絶縁分離膜、６はＰ＋型アインレーシ
ョン拡散層、７はＰ−型活性ベース領域、８はＰ４型外
部ベース領域、９はＮ＋＋エミッタ領域、１０はＮ＋＋
コレクタコンタクト領域、１１１．１１２は層間絶縁膜
、１３１は多結晶シリコン層からなるエミッタ電極、１
３２はアルミニウムによるエミッタ電極、１４はベース
電極、１５はコレクタ電極である。分離酸化膜５はウォ
ールドベース構造とするために設けられたもので、Ｐ″
″型活性ベース領域７はフィールド酸化膜４および分離
酸化膜５に接して形成されている。更に、Ｎ４型エミツ
タ領域９もフイ」ルド酸化膜４に接したウォールドエミ
ッタ構造で形成されている。また、多結晶シリコン層か
らなるエミッタ電極１３１には砒素がドープされており
、エミッタ領域９はこの砒素ドープ多結晶シリコン層１
３１を拡散源として形成されている。In the figure, 1 is a P type silicon substrate, 2 is an N+ type buried region 3 is an N type epitaxial silicon layer, 4 is a field oxide film, 5 is an insulating isolation film, 6 is a P+ type inlation diffusion layer, and 7 is a P type silicon substrate. P- type active base region, 8 is P4 type extrinsic base region, 9 is N++ emitter region, 10 is N++
Collector contact region, 111 and 112 are interlayer insulating films, 131 is an emitter electrode made of a polycrystalline silicon layer, 1
32 is an emitter electrode made of aluminum, 14 is a base electrode, and 15 is a collector electrode. The isolation oxide film 5 is provided to form a walled base structure, and P''
The N4 type active base region 7 is formed in contact with the field oxide film 4 and the isolation oxide film 5. Further, the N4 type emitter region 9 is also formed in a walled emitter structure in contact with the field oxide film 4. Further, the emitter electrode 131 made of a polycrystalline silicon layer is doped with arsenic, and the emitter region 9 is formed in this arsenic-doped polycrystalline silicon layer 1.
31 as a diffusion source.

上記のようにウォールドベースで且つウォールドエミッ
タによる構造（通称アイソプラナ−■）を採用すること
で自己整合での二重拡散形成が可能となり、素子寸法の
縮小による高速動作特性の向上図られる。また、エミッ
タ電極１３１を拡散源とした砒素拡散でエミッタ領域９
を形成することで浅いエミッタ接合を実現し、これによ
っても高速化が図られている。As described above, by employing a walled base and walled emitter structure (commonly known as isoplanar-2), double diffusion formation in self-alignment is possible, and high-speed operation characteristics can be improved by reducing element dimensions. Furthermore, the emitter region 9 is diffused by arsenic diffusion using the emitter electrode 131 as a diffusion source.
By forming a shallow emitter junction, a shallow emitter junction is realized, which also increases speed.

ところで上記パーティカルＮＰＮトランジスタを製造す
る際、活性ベース＠域７とエミッタ領域９の形成は次の
ようにして行なわれている。By the way, when manufacturing the above-mentioned particle NPN transistor, the active base @ region 7 and the emitter region 9 are formed as follows.

即ち、選択酸化によりフィールド酸化膜および分ｗｉ酸
化膜を形成した後、第３図（Ａ＞に示すように素子領域
表面を覆う熱酸化膜１６を緩衝膜としてボロンをイオン
注入してＰ−型活性ベース領域を形成する。次いで第３
図（Ｂ）に示すようにフィールド酸化膜４の上に係るよ
うにエミッタ拡散窓を開孔した後、第３図（Ｃ）に示す
ように砒素ドープされた多結晶シリコン層からなるエミ
ッタ電極１３１を形成し、該エミッタ電極１３１を拡散
源とする砒素の熱拡散によりＮ＋型型板ミッタ領域９形
成する。That is, after forming a field oxide film and a partial oxide film by selective oxidation, as shown in FIG. forming an active base region; then a third
After opening an emitter diffusion window on the field oxide film 4 as shown in FIG. 3(B), an emitter electrode 131 made of an arsenic-doped polycrystalline silicon layer is formed as shown in FIG. 3(C). is formed, and an N+ type plate emitter region 9 is formed by thermal diffusion of arsenic using the emitter electrode 131 as a diffusion source.

なお、ＩＺ　Ｌを構成するインバータトランジスタにつ
いても上記パーティカルＮＰＮトランジスタと同様のア
イソプラナ−■構造が採用されており（この場合に活性
ベース領域内に拡散形成されるのはコレクタ領域）、そ
の二重拡散は上記と同様の方法で形成されている。Note that the inverter transistor constituting IZL also adopts the isoplanar structure similar to the above-mentioned particle NPN transistor (in this case, the collector region is diffused within the active base region), and its double Diffusions are formed in a similar manner as described above.

（背景技術の問題点） 第３図（Ａ）〜（Ｃ）のようにしてアイソプラナ−■構
造を形成する従来の製造方法では、エミッタ拡散窓をフ
ィールド酸化膜４の端部に重ねて開孔する所謂オーバー
ロコス方式にてエツチング形成するから、その際のエツ
チングで熱酸化膜１６だけでなくフィールド酸化膜４も
エツチングされる。このため第３図（Ｂ）に示したよう
に、フィールド酸化膜４の端部は図中二点鎖線で示した
エツチング前の位置から後退してしまうことになり、こ
れに起因して次のような問題が生じている。(Problems in the Background Art) In the conventional manufacturing method of forming an isoplanar structure as shown in FIGS. Since the etching is performed using a so-called over-locos method, not only the thermal oxide film 16 but also the field oxide film 4 are etched. For this reason, as shown in FIG. 3(B), the edge of the field oxide film 4 retreats from the position before etching shown by the two-dot chain line in the figure, and due to this, the following Problems like this are occurring.

即ち、活性ベース領域のためのポロンのイオン注入はエ
ツチングで後退する前のフィールド酸化膜端からドープ
されるのに対し、エミッタ領域形成のための砒素の拡散
は後退したフィールド酸化膜端からドープされる。この
ためフィールド酸化膜の近傍では他の部分に比較してベ
ース幅が局部的に狭くなってしまい、電流増幅率のバラ
ツキ、或いは電流増幅率の局部的な増大による素子の熱
的破壊を生じる原因になっている。更に、極端な場合に
はエミッタ拡散がベース接合を突扱けてエミッタ／コレ
クタ間の短絡不良を生じ、製造歩留が低下するといった
問題がめる。That is, the boron ion implantation for the active base region is doped from the edge of the field oxide before it is etched back, whereas the arsenic diffusion to form the emitter region is doped from the edge of the field oxide that is recessed. Ru. Therefore, the base width becomes locally narrower in the vicinity of the field oxide film than in other parts, which causes variations in the current amplification factor or thermal destruction of the element due to local increases in the current amplification factor. It has become. Furthermore, in extreme cases, the emitter diffusion can overwhelm the base junction, causing a short circuit between the emitter and the collector, resulting in a reduction in manufacturing yield.

なお、アイソプラナ−■構造のＩ”　Ｌを製造する場合
にも上記と同様の問題を生じている。Incidentally, the same problem as above occurs also when manufacturing an I"L having an isoplanar -2 structure.

（発明の目的〕 本発明は上記事情に鑑みてなされたもので、フィールド
酸化膜端から二重拡散を形成する際、特にバイポーラ型
半導体装置を製造するに際し、フィールド酸化膜近傍に
おいても他の部分と同様の正常な拡散プロファイルを得
、以て電流増幅率等の特性のバラツキを防止すると共に
製造歩留を向上することを目的とするものである。(Object of the Invention) The present invention has been made in view of the above circumstances, and is useful when forming a double diffusion from the edge of a field oxide film, especially when manufacturing a bipolar semiconductor device, even in other parts near the field oxide film. The purpose of this invention is to obtain a normal diffusion profile similar to the above, thereby preventing variations in characteristics such as current amplification factor, and improving manufacturing yield.

（発明の概要） 本発明による半導体装置の製造方法は、第一導電型の半
導体層に選択的にフィールド絶縁膜を形成することによ
り該フィールド絶縁膜で囲まれた第一導電型半導体領域
を分離する工程と、前記第一導電型半導体層領域にコン
タクトし、且つ第一導電型不純物および該第一導電型不
純物よりも拡散係数の大きい第二導電型不純物を含む電
極材料層パターンを形成する工程と、該電極材料層パタ
ーンを拡散源として前記第一導電型半導体層領域内に第
一導電型不純物および第二導電型不純物を拡散すること
により、側端が前記フィールド絶縁膜に接した第二導電
型の不純物領域を形成すると同時に、該第二導電型不純
物領域内に包含され且つ側端が前記フィールド絶縁膜に
接した第一導電型不純物領域を形成する工程とを具備し
たことを特徴とするものである。(Summary of the Invention) A method for manufacturing a semiconductor device according to the present invention includes selectively forming a field insulating film on a semiconductor layer of a first conductive type, thereby separating a first conductive type semiconductor region surrounded by the field insulating film. and forming an electrode material layer pattern in contact with the first conductivity type semiconductor layer region and containing a first conductivity type impurity and a second conductivity type impurity having a larger diffusion coefficient than the first conductivity type impurity. Then, by diffusing a first conductivity type impurity and a second conductivity type impurity into the first conductivity type semiconductor layer region using the electrode material layer pattern as a diffusion source, a second conductivity type impurity whose side edge is in contact with the field insulating film is formed. It is characterized by comprising the step of forming a conductivity type impurity region and simultaneously forming a first conductivity type impurity region included in the second conductivity type impurity region and having a side end in contact with the field insulating film. It is something to do.

本発明において第二導電型不純物領域および第一導電型
不純物領域形成の拡散源に用いる前記電極材料層パター
ンとしては、多結晶シリコン層、或いは多結晶シリコン
層の上に金属シリサイド膜を積層したポリサイド層を用
いることができる。In the present invention, the electrode material layer pattern used as a diffusion source for forming the second conductivity type impurity region and the first conductivity type impurity region is a polycrystalline silicon layer or a polycide layer in which a metal silicide film is laminated on the polycrystalline silicon layer. Layers can be used.

この金属シリサイドとしては、タングステンシリサイド
（ＷＳ　ｉ　＞　、モリブデンシリサイド（ＭＯＳ　ｉ
　）　、チタンシリサイドｒｒｉｓｒ→等、高融点金属
のシリサイドを用いるのが望ましい。This metal silicide includes tungsten silicide (WS i >, molybdenum silicide (MOS i
), titanium silicide rrisr→, etc. It is desirable to use a silicide of a high melting point metal.

また、多結晶シリコン層の上に高融点金属膜を張付けた
積層膜を用いてもよい。Alternatively, a laminated film in which a high melting point metal film is pasted on a polycrystalline silicon layer may be used.

本発明は特にバーティカルバイポーラトランジスタの製
造成いはＩＬＬの製造に最も好適に適用することができ
る。即ち、この場合に前記第二導電型の不純物領域は活
性ベース領域であり、前記第一導電型不純物領域はバー
ティカルバイポーラトランジスタのエミッタ領域であっ
てもよく、またＩ２Ｌのコレクタ領域であってもよい。The present invention can be most suitably applied to the manufacture of vertical bipolar transistors or ILLs. That is, in this case, the second conductivity type impurity region is an active base region, and the first conductivity type impurity region may be an emitter region of a vertical bipolar transistor or a collector region of I2L. .

バーティカルバイポーラトランジスタの製造に適用した
場合、本発明では活性ベース領域およびエミッタ領域の
両者が同一の拡散源からの不純物拡散で形成される。従
って、エツチング等によりフィールド絶縁膜の端部が後
退したとしても、フィールド絶縁膜に接した部分でも他
の部分と同様の正常な二重拡散プロファイルが得られる
。When applied to the fabrication of vertical bipolar transistors, the present invention allows both the active base region and the emitter region to be formed by impurity diffusion from the same diffusion source. Therefore, even if the edge of the field insulating film recedes due to etching or the like, a normal double diffusion profile similar to that of other parts can be obtained in the part in contact with the field insulating film.

Ｉ”Ｌに適用した場合も同様である。The same applies when applied to I''L.

本発明の別の製造方法は、従来の製造方法と同様にして
予めウォールドベース構造で活性ベース領域を形成して
おき、その上で更に上記電極材料層パターンを拡散源と
した同時二重拡散を行なうものである。この方法では、
先に形成された活性ベース領域の不純物濃度プロファイ
ル、特にフィールド絶縁膜近傍における拡散プロファイ
ルが電極材料層パターンからの第二導電型不純物の拡散
で是正されるため、全体に適正な二重拡散プロファイル
が得られる。Another manufacturing method of the present invention is to form an active base region in advance with a walled base structure in the same manner as the conventional manufacturing method, and then perform simultaneous double diffusion using the electrode material layer pattern as a diffusion source. It is something to do. in this way,
Since the impurity concentration profile of the previously formed active base region, especially the diffusion profile near the field insulating film, is corrected by the diffusion of the second conductivity type impurity from the electrode material layer pattern, an appropriate double diffusion profile is obtained throughout. can get.

〔発明の実施例〕[Embodiments of the invention]

以下に第１図（Ａ）〜（Ｅ）を参照し、パーティカルＮ
ＰＮトランジスタ及びＩ２　Ｌを同一の基板に共存させ
たバイポーラ型半導体装置の製造に適用した本発明の詳
細な説明する。Referring to FIGS. 1(A) to (E) below, particle N
The present invention will be described in detail as applied to manufacturing a bipolar semiconductor device in which a PN transistor and an I2L coexist on the same substrate.

実施例１ （１）まず、Ｐ型シリコン基板２１表面からＮ型不純物
（例えばｓｂ＞を選択的に拡散し、パーティカルＮＰＮ
トランジスタのＮ＋型型埋領領域２２１、Ｉ”　ＬのＮ
＋型型埋領領域２２２形成した後、全面にＮ型エピタキ
シャル９９３２層２３を成長させる。続いてボロン等の
Ｐ型不純物の選択拡散を行ない、ＮＰＮトランジスタと
Ｉ２　Ｌとを分離するためのＰ＋型アイソレーション拡
散層２４を形成する。また、燐等のＮ型不純物を選択的
に拡散することにより、Ｎ＋型型埋領領域２２１達する
Ｎ４″型拡散領域（ＮＰＮトランジスタのコレクタ取出
し領域）２５と、Ｎ＋型型埋領領域２２２達する図示し
ないＮ＋＋拡散領域（Ｉ２Ｌの共通エミッタ取出し領域
）を形成する（第１図（Ａ＞図示）。Example 1 (1) First, an N-type impurity (for example, sb>) is selectively diffused from the surface of the P-type silicon substrate 21 to form a particle NPN.
N+ type buried region 221 of transistor, N of I”L
After forming the + type buried region 222, an N type epitaxial 9932 layer 23 is grown on the entire surface. Subsequently, a P type impurity such as boron is selectively diffused to form a P+ type isolation diffusion layer 24 for isolating the NPN transistor and I2L. In addition, by selectively diffusing N type impurities such as phosphorus, an N4'' type diffusion region (collector extraction region of an NPN transistor) 25 reaching the N+ type buried region 221 and an N+ type buried region 222 reaching the N+ type buried region 222 are formed. (FIG. 1 (A>Illustrated)).

（２）次に、選択酸化によりＮ４型埋込領域２２１．２
２２に達する埋込みフィールド酸化膜２６を形成して素
子間分離を行ない、またＮＰＮトランジスタをウォール
ドベース構造とするための分離酸化膜２７１、Ｉ”　Ｌ
の二つのインバータトランジスタを分離するための分離
酸化膜２７２を形成する。勿論、フィールド酸化膜２６
及び分離酸化膜２７１，２７２を同時形成してもよく、
第１図（Ｂ）は同時形成の場合を示している。続いて、
各素子領域の表面に膜厚５００〜１０００人の薄い熱酸
化膜２８を形成した後、選択エツチングによりＮＰＮト
ランジスタの素子領域表面を覆う熱酸化膜２８にエミッ
タ拡散窓２９を開孔すると共に、Ｉ２Ｌのコレクタ領域
予定部表面を覆っている熱酸化膜２８を除去する（第１
図（Ｂ）図示）。(2) Next, N4 type buried region 221.2 is formed by selective oxidation.
A buried field oxide film 26 reaching a depth of 22 is formed to provide isolation between elements, and an isolation oxide film 271, I"L, is used to form an NPN transistor into a walled base structure.
An isolation oxide film 272 is formed to isolate the two inverter transistors. Of course, the field oxide film 26
and isolation oxide films 271 and 272 may be formed simultaneously,
FIG. 1(B) shows the case of simultaneous formation. continue,
After forming a thin thermal oxide film 28 with a film thickness of 500 to 1000 on the surface of each device region, selective etching is performed to open an emitter diffusion window 29 in the thermal oxide film 28 covering the surface of the device region of the NPN transistor. The thermal oxide film 28 covering the surface of the planned collector region is removed (the first
Figure (B) (Illustrated).

なお、パーティカルＮＰＮトランスタをウォールドエミ
ッタ構造とするため、エミッタ拡散窓２９はフィールド
酸化膜２６の上に重ねて開孔する。また、Ｉ２Ｌのイン
バータトランジスタ部分についても、ウォールドコレク
タ構造とするため埋め込み酸化膜２７２．２６の上から
重ねてエツチングすることにより熱酸化Ｗ！Ａ２８を除
去する。Incidentally, since the particle NPN transistor has a walled emitter structure, the emitter diffusion window 29 is opened so as to overlap the field oxide film 26. Furthermore, the inverter transistor portion of I2L is also thermally oxidized by etching the buried oxide film 272.26 to form a walled collector structure. Remove A28.

従って、これら開孔部分ではエツチングによる埋め込み
酸化膜端の後退が生じる。Therefore, in these openings, the end of the buried oxide film recedes due to etching.

（３）次に、ＣｖＤ法ニヨリ膜厚５００〜２６００人ノ
不純物を含まない多結晶シリコン層３０を全面に堆積し
た後、該多結晶シリコン層３０にエミッタ領域形成用の
不純物として砒素（場合によっては燐、或いは燐と砒素
の併用でもよい）をイオン注入する（第１図（Ｃ）図示
）。(3) Next, after depositing an impurity-free polycrystalline silicon layer 30 with a film thickness of 500 to 2,600 using the CvD method over the entire surface, arsenic (in some cases) is added to the polycrystalline silicon layer 30 as an impurity for forming an emitter region. phosphorus or a combination of phosphorus and arsenic) is ion-implanted (as shown in FIG. 1C).

次いで膜厚１０００〜３０００人の高融点金属シリサイ
ド膜３１を全面に堆積し、活性ベース領域形成用の不純
物としてボロンをイオン注入する。このイオン注入はパ
ーティカルＮＰＮトランジスタ部分とＩ２１部分とで別
々に行ない、夫々に最適なドーズ量で行なう。必要に応
じて全面にＣＶＤ−３ｉ　０２膜１００を約２０００人
堆積し、８００°Ｃ〜９００　’Ｃの低温熱アニールを
施して不純物の均一化を図る。続いて、ＣＶＤ−３ｉ０
２膜とポリサイド積層膜を選択エツチングでパターンニ
ングし、ＮＰＮトランジスタのエミッタ電極パターン３
２、ＩＺ　Ｌのコレクタ電極パターン３３ｔ　、３３２
及び入力配線パターン３４を形成し、また必要なジャン
パー配線３５１，３５２　、インジェクタ領域を形成す
るためのマスクパターン３６１を形成する（第１図（Ｄ
）図示）。Next, a refractory metal silicide film 31 having a thickness of 1,000 to 3,000 thick is deposited over the entire surface, and boron ions are implanted as an impurity for forming an active base region. This ion implantation is performed separately for the particulate NPN transistor portion and the I21 portion, and is performed at an optimal dose for each. If necessary, approximately 2000 CVD-3i 02 films 100 are deposited over the entire surface, and low-temperature thermal annealing is performed at 800° C. to 900° C. to make impurities uniform. Next, CVD-3i0
2 film and the polycide laminated film by selective etching to form the emitter electrode pattern 3 of the NPN transistor.
2, IZ L collector electrode pattern 33t, 332
and an input wiring pattern 34, and also form necessary jumper wirings 351, 352 and a mask pattern 361 for forming an injector region (see FIG. 1(D)).
).

なお、図中Ｉ２　Ｌのインバータトランジスタ部分では
コレクタ電極パターン３３１，３３２が埋め込み酸化膜
上に亙って形成されていないが、これはコレクタ電極の
両側で金属配線層とのコンタクトを形成してベース抵抗
を低減するためである。Note that in the inverter transistor part of I2L in the figure, the collector electrode patterns 331 and 332 are not formed over the buried oxide film, but they are formed by forming contacts with the metal wiring layer on both sides of the collector electrode and forming the base. This is to reduce resistance.

但し、図示断面に直行する方向では、パーティカルＮＰ
Ｎトランジスタ部分と同様、ウォールドエミッタ構造と
するために埋め込み酸化膜上に互って形成されている。However, in the direction perpendicular to the illustrated cross section, particle NP
Similar to the N transistor portion, they are formed alternately on the buried oxide film to form a walled emitter structure.

（４）次に、ポリサイドパターン３２，３３１　。(4) Next, polycide patterns 32, 331.

３３２．３４，３５ｔ　、３５２．３６及び埋込酸化１
１１２６．２７ｔ　、２７２をマスクとしてボロンをイ
オン注入する。これにより、ＮＰＮトランジスタのＰ＋
型外部ベース領域３７、Ｉ２　ＬのＰ＋型外部ベース領
域３８１，３８２　、Ｉ２ＬのＰ′″型インジェクタ領
域３９が形成される（第１図（Ｅ）図示）。332.34, 35t, 352.36 and buried oxidation 1
Boron ions are implanted using 1126.27t and 272 as a mask. As a result, P+ of the NPN transistor
The mold external base region 37, the P+ type external base regions 381, 382 of I2L, and the P'' type injector region 39 of I2L are formed (as shown in FIG. 1(E)).

（５）次に、ポリサイドからなるエミッタ電極３２、コ
レクタ電極３３１，３３２を拡散源とするボロン及び砒
素の熱拡散を行なう。これにより、ボロンの拡散でＮＰ
ＮトランジスタのＰ−型活性ベース領域４０，１２１の
活性ベース領域４１１゜４１２が形成されると同時に、
砒素の拡散でＮＰＮトランジスタのＮ＋型エミッタ領域
４２、Ｉ２　ＬのＮ＋型コレクタ領域４３ｔ　、４３２
が形成さレル。次イテ、ＣＶＤ−３ｉ０２膜１００を取
除き、新たにＣＶＤ法により５ｉ０２等からなる眉間絶
縁膜４４を堆積する。続いてコンタクトホールの開孔、
アルミニウム合金膜の蒸着およびパターンニングを行な
い、電極配線４５〜４９を形成して装置を完成させる。(5) Next, thermal diffusion of boron and arsenic is performed using the emitter electrode 32 and collector electrodes 331 and 332 made of polycide as diffusion sources. As a result, boron diffusion causes NP
At the same time as the active base regions 411 and 412 of the P-type active base regions 40 and 121 of the N transistor are formed,
By diffusing arsenic, the N+ type emitter region 42 of the NPN transistor and the N+ type collector region 43t, 432 of I2L are formed.
is formed. In the next step, the CVD-3i02 film 100 is removed, and a new glabellar insulating film 44 made of 5i02 or the like is deposited by the CVD method. Next, contact hole opening,
The aluminum alloy film is deposited and patterned to form electrode wirings 45 to 49 to complete the device.

４５，４６，４７は夫々Ｎ　Ｐ　Ｎ　ｌ−ランジスタの
エミッタ端子、ベース端子、コレクタ端子である。また
、４８はＩ２　Ｌのインジェクタ端子、４９はＩ２　Ｌ
の共通入力配線である。（第１図（Ｆ）、第４図々示）
。なお、第４図は第１図（Ｆ）のＩＶ　−ＩＶ線に沿う
断面図で、図では隣接する他のＩ２　Ｌのインバータト
ランジスタ部分および他の配線層が図示されている。45, 46, and 47 are the emitter terminal, base terminal, and collector terminal of the N P N l-transistor, respectively. Also, 48 is the I2L injector terminal, 49 is the I2L
This is the common input wiring. (See Figure 1 (F) and Figure 4)
. Note that FIG. 4 is a cross-sectional view taken along the line IV--IV in FIG. 1(F), and the figure shows the inverter transistor portion of another adjacent I2L and other wiring layers.

上記実施例の製造方法によれば、パーティカルＮＰＮト
ランジスタ部分およびＩ２　Ｌのインバータトランジス
タ部分の何れにおいても、埋め込み酸化膜近傍での正常
な二重拡散プロファイルをもったアイソプラナ−■構造
を形成することができる。即ち、第１図（Ｂ）の段階で
拡散窓を開孔した際に、フィールド酸化膜や分離酸化膜
の端部が後退したことは全く影響しない。パーティカル
ＮＰＮトランジスタ部分について説明すると、Ｐ−型活
性ベース領域４０およびＮ＋型エミッタ領域４２は何れ
もエミッタ電極パターン３１からの不純物拡散で形成さ
れているから、フィールド酸化膜２６の端面近傍におけ
る拡散プロファイルも他の部分と同じ正常な拡散プロフ
ァイルで形成される。従って、従来のように局部的な電
流増幅率のバラツキが生じたり、エミッタ／コレクタ間
の短絡を生じるといった問題を防止することができる。According to the manufacturing method of the above embodiment, an isoplanar structure with a normal double diffusion profile near the buried oxide film can be formed in both the particulate NPN transistor part and the I2L inverter transistor part. I can do it. That is, when the diffusion window is opened at the stage shown in FIG. 1(B), the receding of the edges of the field oxide film and isolation oxide film has no effect at all. Regarding the partical NPN transistor portion, since both the P- type active base region 40 and the N+ type emitter region 42 are formed by impurity diffusion from the emitter electrode pattern 31, the diffusion profile near the end face of the field oxide film 26 is is also formed with the same normal diffusion profile as the other parts. Therefore, it is possible to prevent problems such as local variations in the current amplification factor and short circuits between the emitter and collector, which occur in the prior art.

Ｉ２　Ｌのインバータトランジスタ部分についても、ア
イソプラナ−■（この場合にはウォールドコレクタ）構
造になっている部分では同様の効果が得られる。また、
ＩＺ　１部分では拡散源として用いたポリサイドパター
ンを配線として自由に使用できるため、設計上の自由度
を増大でき且つＩ２　Ｌのインバータ動作速度を向上で
きる効果り（得られる。A similar effect can be obtained with respect to the inverter transistor portion of I2L having an isoplanar (walled collector in this case) structure. Also,
In the IZ1 portion, the polycide pattern used as the diffusion source can be freely used as a wiring, so that the degree of freedom in design can be increased and the operating speed of the I2L inverter can be improved.

実施例２ 本発明の別の製造方法の実施例を第５図（Ａ＞（８）を
参照して説明する。Example 2 An example of another manufacturing method of the present invention will be described with reference to FIG. 5 (A>(8)).

（１）まず、実施例１の場合と同様のプロセスで第１図
（Ａ＞の状態を得た後、選択酸化によりフィールド酸化
膜２６および分離酸化膜２７１゜２７２を形成し、更に
素子領域表面を覆う熱酸化膜２８を形成する。(1) First, after obtaining the state shown in FIG. 1 (A>) using the same process as in Example 1, a field oxide film 26 and isolation oxide films 271 and 272 are formed by selective oxidation, and then the surface of the element region is A thermal oxide film 28 is formed to cover.

（２）次に、フィールド酸化膜２６および分離酸化膜２
７１．２７２をブロッキングマスクとし、熱酸化膜２８
を緩衝膜として選択的にボロンをイオン注入することに
より、パーティカルＮＰＮトランジスタの活性ベース領
域４０’　と、Ｉ”　Ｌを構成するインバータトランジ
スタの活性ベース領域４１’　ｌ、４１’　２を形成す
る。続いて、実施例１の場合と同じく、選択エツチング
によりＮＰＮトランジスタの活性ベース領域表面を覆う
熱酸化膜２８にエミッタ拡散窓２９を開孔すると共に、
Ｉ２　Ｌのコレクタ領域予定部表面を覆っている熱酸化
膜２８を除去する　（第５図（Ａ＞図示）。(2) Next, field oxide film 26 and isolation oxide film 2
71.272 is used as a blocking mask, and the thermal oxide film 28
By selectively ion-implanting boron using this as a buffer film, an active base region 40' of a particle NPN transistor and active base regions 41' 1 and 41' 2 of an inverter transistor constituting I''L are formed. Subsequently, as in the case of Example 1, an emitter diffusion window 29 is opened in the thermal oxide film 28 covering the surface of the active base region of the NPN transistor by selective etching.
The thermal oxide film 28 covering the surface of the planned collector region of I2L is removed (FIG. 5 (A>illustration)).

（３）その後は実施例１と同じプロセスにより、第５図
（Ｂ）に示すバイポーラ型半導体装置が得られる。(3) Thereafter, the same process as in Example 1 is performed to obtain the bipolar semiconductor device shown in FIG. 5(B).

上記のように、この実施例では予めイオン注入で活性ベ
ース領域４１’　１．４１’　２を形成しているため、
このイオン注入部分の拡散プロファイルは実施例１の場
合と異なっている。第６図はパーティカルＮＰＮトラン
ジスタ部分の拡散プロファイルを模式的に示す線図で、
図中Ｐ（＋は予め行なわれたボロンのイオン注入による
プロファイル、Ｐｌはポリサイドのエミッタ電極から拡
散されたボロンによるプロファイルである。実施例１の
場合にはＰｏがない。As mentioned above, in this embodiment, the active base region 41'1.41' 2 is formed in advance by ion implantation.
The diffusion profile of this ion-implanted portion is different from that of the first embodiment. Figure 6 is a diagram schematically showing the diffusion profile of a particulate NPN transistor.
In the figure, P(+ is a profile due to boron ion implantation performed in advance, and Pl is a profile due to boron diffused from a polycide emitter electrode. In the case of Example 1, Po is absent.

また、従来の製造方法ではＰｏのみでＰｌによる寄与が
なく、この場合には既述のように電流増幅率の局部的な
バラツキやエミッタ／コレクタ間の短絡を生じることに
なる。これに対し、上記実施例ではＰｌの寄与でＰｏの
拡散プロファイルが補正されるため、フィールド酸化膜
近傍においても適正なベース幅が維持される。従って、
均一な電流増幅率が得られると共に、エミッタ／ベース
短絡による不良も防止され、製造歩留を顕著に向上でき
る。Further, in the conventional manufacturing method, there is no contribution from Pl only by Po, and in this case, as described above, local variations in the current amplification factor and short circuit between the emitter and collector occur. On the other hand, in the above embodiment, since the diffusion profile of Po is corrected by the contribution of Pl, an appropriate base width is maintained even in the vicinity of the field oxide film. Therefore,
In addition to obtaining a uniform current amplification factor, defects due to emitter/base short circuits are also prevented, and manufacturing yields can be significantly improved.

更に、実施例１の場合には活性ベース領域の不純物濃度
がポリサイドからのボロン拡散のみに依存するのに対し
、この実施例では予め行なうボロンのイオン注入によっ
てもベース濃度を制御できるため、電流増幅率の制御性
の点で量産化技術としては有利である。Furthermore, in the case of Embodiment 1, the impurity concentration in the active base region depends only on boron diffusion from polycide, whereas in this embodiment, the base concentration can also be controlled by boron ion implantation performed in advance. It is advantageous as a mass production technology in terms of rate controllability.

〔発明の効果〕〔Effect of the invention〕

以上詳述したように、本発明によればフィールド酸化膜
端から二重拡散を形成して半導体装置、就中バイポーラ
型半導体装置を製造するに際し、フィールド酸化膜近傍
においても他の部分と同様の正常な拡散プロファイルを
得、以て電流増幅率等の特性のバラツキを防止すると共
に製造歩留を向上することできる等、顕著な効果が得ら
れるものである。As described in detail above, according to the present invention, when manufacturing a semiconductor device, particularly a bipolar type semiconductor device, by forming double diffusion from the edge of the field oxide film, the same process can be performed near the field oxide film as in other parts. This provides remarkable effects such as obtaining a normal diffusion profile, thereby preventing variations in characteristics such as current amplification factor, and improving manufacturing yield.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図（Ａ）′−（Ｆ）は本発明の一実施例になるバイ
ポーラ型半導体装置の製造方法をその製造工程に沿って
説明するための断面図、第２図はウォールドエミッタ構
造によるパーティカルＮＰＮトランジスタの断面図であ
り、第３図（Ａ）〜（Ｃ）はその従来の製造方法におけ
る要部工程を説明するための断面図、第４図は第１図（
Ｆ）のＩＶ　−ＩＶ線に沿う断面図、第５図（Ａ＞（Ｂ
）は本発明の他の実施例になるバイポーラ型半導体装置
の製造方法を説明するための断面図であり、第６図はそ
のトランジスタ部分の拡散プロファイルを模式的に示す
線図である。 ２１・・・Ｐ型シリコン基板、２２１．２２２・・・Ｎ
＋型型埋領領域２３・・・Ｎ型エピタキシャルシリコン
層、２４・・・Ｐ＋型アイソレーション拡散層、２５・
・・Ｎ＋＋コレクタ取出し領域、２６・・・フィールド
酸化膜、２７１．２７２・・・分離酸化膜、２８・・・
熱酸化膜、２９・・・エミッタ拡散窓、３０・・・多結
晶シリコン層、３１・・・高融点金属シリサイド層、３
２・・・エミッタ電極、３３１，３３２・・・Ｉ２　Ｌ
のコレクタ出力電極、３４・・・１２１入力配線、３５
１．３５２・・・ジャンパ配線、３６ｔ　、３６２・・
・マスクパターン、３７，３８１，３８２・・・Ｐ＋型
外部ベース領域、３９・・・Ｐ＋型インジェクタ領域、
４０，４１１．４１２・・・Ｐ−型活性ベース領域、４
２・・・Ｎ＋型エミッタ領域、４３１．４３２・・・１
２　ＬのＮ＋型コレクタ領域、４４・・・層間絶縁膜、
４５，４６，４７，４８，４９・・・アルミニウム配線
層 出願人代理人　弁理士　鈴江武彦 第２図 第３図 ＪＪＪＩＩＮＩ１１1(A)'-(F) are cross-sectional views for explaining the manufacturing method of a bipolar semiconductor device according to an embodiment of the present invention along the manufacturing process, and FIG. 3A to 3C are cross-sectional views for explaining the main steps in the conventional manufacturing method, and FIG. 4 is a cross-sectional view of a CalNPN transistor.
F) cross-sectional view along line IV-IV, Fig. 5 (A>(B
) is a sectional view for explaining a method of manufacturing a bipolar semiconductor device according to another embodiment of the present invention, and FIG. 6 is a diagram schematically showing a diffusion profile of a transistor portion thereof. 21...P-type silicon substrate, 221.222...N
+ type buried region 23...N type epitaxial silicon layer, 24...P+ type isolation diffusion layer, 25.
...N++ collector extraction area, 26...Field oxide film, 271.272...Isolation oxide film, 28...
Thermal oxide film, 29... Emitter diffusion window, 30... Polycrystalline silicon layer, 31... High melting point metal silicide layer, 3
2... Emitter electrode, 331, 332... I2 L
collector output electrode, 34...121 input wiring, 35
1.352...Jumper wiring, 36t, 362...
・Mask pattern, 37, 381, 382...P+ type external base region, 39...P+ type injector region,
40,411.412...P-type active base region, 4
2...N+ type emitter region, 431.432...1
2 L N+ type collector region, 44... interlayer insulating film,
45, 46, 47, 48, 49... Aluminum wiring layer applicant representative Patent attorney Takehiko Suzue Figure 2 Figure 3 JJJIINI11

Claims (8)

【特許請求の範囲】[Claims] （１）第一導電型の半導体層に選択的にフィールド絶縁
膜を形成することにより該フィールド絶縁膜で囲まれた
第一導電型半導体領域を分離する工程と、前記第一導電
型半導体層領域にコンタクトし、且つ第一導電型不純物
および該第一導電型不純物よりも拡散係数の大きい第二
導電型不純物を含む電極材料層パターンを形成する工程
と、該電極材料層パターンを拡散源として前記第一導電
型半導体層領域内に第一導電型不純物および第二導電型
不純物を拡散することにより、側端が前記フィールド絶
縁膜に接した第二導電型不純物領域を形成すると同時に
、該第二導電型不純物領域内に包含され且つ側端が前記
フィールド絶縁膜に接した第一導電型不純物領域を形成
する工程とを具備したことを特徴とする半導体装置の製
造方法。(1) A step of separating a first conductive type semiconductor region surrounded by the field insulating film by selectively forming a field insulating film on the first conductive type semiconductor layer, and the first conductive type semiconductor layer region. forming an electrode material layer pattern containing a first conductivity type impurity and a second conductivity type impurity having a larger diffusion coefficient than the first conductivity type impurity, and using the electrode material layer pattern as a diffusion source. By diffusing a first conductivity type impurity and a second conductivity type impurity into the first conductivity type semiconductor layer region, a second conductivity type impurity region whose side edge is in contact with the field insulating film is formed, and at the same time, the second conductivity type impurity region is formed. A method of manufacturing a semiconductor device, comprising the step of forming a first conductivity type impurity region included in the conductivity type impurity region and having a side end in contact with the field insulating film. （２）前記第一導電型半導体領域がバーティカルバイポ
ーラトランジスタのコレクタ領域であり、前記第二導電
型不純物領域がバーティカルバイポーラトランジスタの
活性ベース領域であり、前記第一導電型不純物領域がバ
ーティカルバイポーラトランジスタのエミッタ領域であ
ることを特徴とする特許請求の範囲第１項記載の半導体
装置の製造方法。(2) The first conductivity type semiconductor region is a collector region of a vertical bipolar transistor, the second conductivity type impurity region is an active base region of the vertical bipolar transistor, and the first conductivity type impurity region is a collector region of the vertical bipolar transistor. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is an emitter region. （３）前記第一導電型半導体領域がＩ＾２Ｌを構成する
インバータトランジスタのエミッタ領域であり、前記第
二導電型不純物領域がこのインバータトランジスタの活
性ベース領域であり、前記第一導電型不純物領域がこの
インバータトランジスタのコレクタ領域であることを特
徴とする特許請求の範囲第１項記載の半導体装置の製造
方法。(3) The first conductivity type semiconductor region is an emitter region of an inverter transistor constituting I^2L, the second conductivity type impurity region is an active base region of this inverter transistor, and the first conductivity type impurity region 2. The method of manufacturing a semiconductor device according to claim 1, wherein is a collector region of the inverter transistor. （４）前記第一導電型不純物および第二導電型不純物を
含む電極材料層パターンとして、両不純物を含む多結晶
シリコン層、ポリサイド層または両不純物を含む多結晶
シリコン層表面に高融点金属膜を張付けた積層膜を用い
ることを特徴とする特許請求の範囲第１項、第２項また
は第３項記載の半導体装置の製造方法。(4) As the electrode material layer pattern containing the first conductivity type impurity and the second conductivity type impurity, a high melting point metal film is formed on the surface of the polycrystalline silicon layer or polycide layer containing both impurities, or the polycrystalline silicon layer containing both impurities. A method of manufacturing a semiconductor device according to claim 1, 2 or 3, characterized in that a pasted laminated film is used. （５）第一導電型の半導体層に選択的にフィールド絶縁
膜を形成することにより該フィールド絶縁膜で囲まれた
第一導電型半導体領域を分離する工程と、該第一導電型
半導体層領域の表面を覆う絶縁膜を形成する工程と、該
絶縁膜を緩衝膜とし且つ前記フィールド絶縁膜をブロッ
キングマスクとして前記第一導電型半導体層領域内に第
二導電型不純物をイオン注入することにより第二導電型
の活性ベース領域を形成する工程と、前記第一導電型半
導体層領域表面を覆う絶縁膜に対して前記フィールド絶
縁膜の端部が露出するように拡散窓を開孔する工程と、
該拡散窓を介して前記第一導電型半導体層領域にコンタ
クトし、且つ第一導電型不純物および該第一導電型不純
物よりも拡散係数の大きい第二導電型不純物を含む電極
材料層パターンを形成する工程と、該電極材料層パター
ンを拡散源として前記第一導電型半導体層領域内に第一
導電型不純物および第二導電型不純物を拡散することに
より、前記活性ベース領域内に包含され且つ側端が前記
フィールド絶縁膜に接した第一導電型不純物領域を形成
すると共に前記活性ベース領域の拡散プロファイルを是
正する工程とを具備したことを特徴とする半導体装置の
製造方法。(5) selectively forming a field insulating film on the first conductive type semiconductor layer to separate the first conductive type semiconductor region surrounded by the field insulating film; and the first conductive type semiconductor layer region. forming an insulating film covering the surface of the semiconductor layer, and using the insulating film as a buffer film and the field insulating film as a blocking mask to ion-implant a second conductivity type impurity into the first conductivity type semiconductor layer region. forming a biconductivity type active base region; and opening a diffusion window so that an end of the field insulating film is exposed to the insulating film covering the surface of the first conductivity type semiconductor layer region;
Forming an electrode material layer pattern that contacts the first conductivity type semiconductor layer region through the diffusion window and includes a first conductivity type impurity and a second conductivity type impurity having a larger diffusion coefficient than the first conductivity type impurity. and diffusing a first conductivity type impurity and a second conductivity type impurity into the first conductivity type semiconductor layer region using the electrode material layer pattern as a diffusion source, so that the first conductivity type impurity and the second conductivity type impurity are contained in the active base region and on the side. A method of manufacturing a semiconductor device, comprising the steps of: forming a first conductivity type impurity region whose end is in contact with the field insulating film, and correcting a diffusion profile of the active base region. （６）前記第一導電型半導体領域がバーティカルバイポ
ーラトランジスタのコレクタ領域であり、前記第一導電
型不純物領域がバーティカルバイポーラトランジスタの
エミッタ領域であることを特徴とする特許請求の範囲第
５項記載の半導体装置の製造方法。(6) The first conductive type semiconductor region is a collector region of a vertical bipolar transistor, and the first conductive type impurity region is an emitter region of the vertical bipolar transistor. A method for manufacturing a semiconductor device. （７）前記第一導電型半導体領域がＩ＾２Ｌを構成する
インバータトランジスタのエミッタ領域であり、前記第
一導電型不純物領域がこのインバータトランジスタのコ
レクタ領域であることを特徴とする特許請求の範囲第５
項記載の半導体装置の製造方法。(7) Claims characterized in that the first conductivity type semiconductor region is an emitter region of an inverter transistor forming I^2L, and the first conductivity type impurity region is a collector region of this inverter transistor. Fifth
A method for manufacturing a semiconductor device according to section 1. （８）前記第一導電型不純物および第二導電型不純物を
含む電極材料層パターンとして、両不純物を含む多結晶
シリコン層、ポリサイド層または両不純物を含む多結晶
シリコン層表面に高融点金属膜を張付けた積層膜を用い
ることを特徴とする特許請求の範囲第５項、第６項また
は第７項記載の半導体装置の製造方法。(8) As the electrode material layer pattern containing the first conductivity type impurity and the second conductivity type impurity, a high melting point metal film is formed on the surface of the polycrystalline silicon layer or polycide layer containing both impurities, or the polycrystalline silicon layer containing both impurities. A method of manufacturing a semiconductor device according to claim 5, 6, or 7, characterized in that a pasted laminated film is used.
JP60065231A 1985-03-07 1985-03-29 Manufacture of semiconductor device Pending JPS61224448A (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP60065231A JPS61224448A (en) 1985-03-29 1985-03-29 Manufacture of semiconductor device
EP86102856A EP0193934B1 (en) 1985-03-07 1986-03-05 Semiconductor integreated circuit device and method of manufacturing the same
DE86102856T DE3688711T2 (en) 1985-03-07 1986-03-05 Integrated semiconductor circuit arrangement and method for its production.
US07/730,518 US5144408A (en) 1985-03-07 1991-07-12 Semiconductor integrated circuit device and method of manufacturing the same
US07/989,455 US5280188A (en) 1985-03-07 1992-12-08 Method of manufacturing a semiconductor integrated circuit device having at least one bipolar transistor and a plurality of MOS transistors

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60065231A JPS61224448A (en) 1985-03-29 1985-03-29 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS61224448A true JPS61224448A (en) 1986-10-06

Family

ID=13280930

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60065231A Pending JPS61224448A (en) 1985-03-07 1985-03-29 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS61224448A (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5164370A (en) * 1974-08-16 1976-06-03 Siemens Ag
JPS5482981A (en) * 1977-12-14 1979-07-02 Nec Corp Nanufacture of semiconductor device
JPS5685860A (en) * 1979-11-21 1981-07-13 Siemens Ag High speed bipolar transistor and methdo of manufacturing same

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5164370A (en) * 1974-08-16 1976-06-03 Siemens Ag
JPS5482981A (en) * 1977-12-14 1979-07-02 Nec Corp Nanufacture of semiconductor device
JPS5685860A (en) * 1979-11-21 1981-07-13 Siemens Ag High speed bipolar transistor and methdo of manufacturing same

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