BRPI1105638B8 - Mã‰todo de fabricaã‡ãƒo de um dispositivo que possui um circuito integrado - Google Patents

Mã‰todo de fabricaã‡ãƒo de um dispositivo que possui um circuito integrado

Info

Publication number
BRPI1105638B8
BRPI1105638B8 BRPI1105638A BRPI1105638A BRPI1105638B8 BR PI1105638 B8 BRPI1105638 B8 BR PI1105638B8 BR PI1105638 A BRPI1105638 A BR PI1105638A BR PI1105638 A BRPI1105638 A BR PI1105638A BR PI1105638 B8 BRPI1105638 B8 BR PI1105638B8
Authority
BR
Brazil
Prior art keywords
module
cavity
manufacturing
integrated circuit
place
Prior art date
Application number
BRPI1105638A
Other languages
English (en)
Inventor
Olivier Bosquet
Jean-Franã‡Ois Boschet
Original Assignee
Oberthur Technologies
Idemia France
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oberthur Technologies, Idemia France filed Critical Oberthur Technologies
Publication of BRPI1105638A2 publication Critical patent/BRPI1105638A2/pt
Publication of BRPI1105638B1 publication Critical patent/BRPI1105638B1/pt
Publication of BRPI1105638B8 publication Critical patent/BRPI1105638B8/pt

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07745—Mounting details of integrated circuit chips
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Credit Cards Or The Like (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

dispositivo que possui um circuito integrado e seu mã‰todo de fabricaã‡ãƒo. a presente invenã§ã£o se refere a um mã©todo de fabricaã§ã£o de um dispositivo (10) que compreende um corpo (12) que possui uma cavidade (20) de dimensãµes adequadas para receber um mã³dulo (16) que tenha um circuito integrado (14), a cavidade (20) possuindo um fundo (24) e uma parede perifã©rica (26) que envolve o fundo (24), e o mã©todo incluindo uma etapa de colocaã§ã£o do mã³dulo (16) em seu lugar na cavidade (20). mais precisamente, o mã©todo compreende, antes da etapa de colocaã§ã£o do mã³dulo (16) no lugar, uma etapa de depã³sito de uma faixa adesiva (38) ao menos sobre uma superfã­cie (161) do mã³dulo (16) que ã© projetada para ficar voltada para o fundo (24) da cavidade (20) e para limitar um golpe de compressã£o do mã³dulo (16) que possa ocorrer sob o efeito de uma forã§a mecã¢nica de compressã£o que impulsione o mã³dulo (16) contra o fundo (24) da cavidade (20).
BRPI1105638A 2010-12-06 2011-12-06 Mã‰todo de fabricaã‡ãƒo de um dispositivo que possui um circuito integrado BRPI1105638B8 (pt)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR1060110A FR2968431B1 (fr) 2010-12-06 2010-12-06 Procédé de fabrication d'un dispositif a microcircuit

Publications (3)

Publication Number Publication Date
BRPI1105638A2 BRPI1105638A2 (pt) 2013-03-26
BRPI1105638B1 BRPI1105638B1 (pt) 2020-04-22
BRPI1105638B8 true BRPI1105638B8 (pt) 2020-04-22

Family

ID=44201854

Family Applications (1)

Application Number Title Priority Date Filing Date
BRPI1105638A BRPI1105638B8 (pt) 2010-12-06 2011-12-06 Mã‰todo de fabricaã‡ãƒo de um dispositivo que possui um circuito integrado

Country Status (8)

Country Link
US (1) US8864040B2 (pt)
EP (1) EP2461277B1 (pt)
CN (1) CN102663474B (pt)
BR (1) BRPI1105638B8 (pt)
CA (1) CA2761204C (pt)
ES (1) ES2751368T3 (pt)
FR (1) FR2968431B1 (pt)
MX (1) MX2011012991A (pt)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
USD707682S1 (en) * 2012-12-05 2014-06-24 Logomotion, S.R.O. Memory card
FR2999753B1 (fr) * 2012-12-13 2015-02-13 Oberthur Technologies Procede de fabrication par lamination en continu de cartes a microcircuit du type a contact
US9888283B2 (en) 2013-03-13 2018-02-06 Nagrastar Llc Systems and methods for performing transport I/O
US9647997B2 (en) 2013-03-13 2017-05-09 Nagrastar, Llc USB interface for performing transport I/O
USD759022S1 (en) 2013-03-13 2016-06-14 Nagrastar Llc Smart card interface
USD758372S1 (en) * 2013-03-13 2016-06-07 Nagrastar Llc Smart card interface
USD729808S1 (en) 2013-03-13 2015-05-19 Nagrastar Llc Smart card interface
USD780763S1 (en) 2015-03-20 2017-03-07 Nagrastar Llc Smart card interface
USD864968S1 (en) 2015-04-30 2019-10-29 Echostar Technologies L.L.C. Smart card interface
TWI635444B (zh) * 2016-11-03 2018-09-11 動信科技股份有限公司 Touch smart card

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2629236B1 (fr) * 1988-03-22 1991-09-27 Schlumberger Ind Sa Procede de realisation d'une carte a memoire electronique et carte telle qu'obtenue par la mise en oeuvre dudit procede
FR2632100B1 (fr) * 1988-05-25 1992-02-21 Schlumberger Ind Sa Procede de realisation d'une carte a memoire electronique et cartes a memoire electronique obtenue par la mise en oeuvre dudit procede
FR2662000A1 (fr) * 1990-05-11 1991-11-15 Philips Composants Carte a microcircuit.
US6034427A (en) * 1998-01-28 2000-03-07 Prolinx Labs Corporation Ball grid array structure and method for packaging an integrated circuit chip
FR2779851B1 (fr) * 1998-06-12 2002-11-29 Gemplus Card Int Procede de fabrication d'une carte a circuit integre et carte obtenue
FR2794266B1 (fr) * 1999-05-25 2002-01-25 Gemplus Card Int Procede de fabrication de dispositif electronique portable a circuit integre comportant un dielectrique bas cout
US6475327B2 (en) * 2001-04-05 2002-11-05 Phoenix Precision Technology Corporation Attachment of a stiff heat spreader for fabricating a cavity down plastic chip carrier

Also Published As

Publication number Publication date
CA2761204A1 (fr) 2012-06-06
EP2461277A1 (fr) 2012-06-06
EP2461277B1 (fr) 2019-07-24
CA2761204C (fr) 2020-03-10
ES2751368T3 (es) 2020-03-31
BRPI1105638B1 (pt) 2020-04-22
US8864040B2 (en) 2014-10-21
FR2968431B1 (fr) 2012-12-28
BRPI1105638A2 (pt) 2013-03-26
CN102663474A (zh) 2012-09-12
MX2011012991A (es) 2012-06-08
CN102663474B (zh) 2017-08-22
FR2968431A1 (fr) 2012-06-08
US20120138690A1 (en) 2012-06-07

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Legal Events

Date Code Title Description
B03A Publication of a patent application or of a certificate of addition of invention [chapter 3.1 patent gazette]
B06F Objections, documents and/or translations needed after an examination request according [chapter 6.6 patent gazette]
B06U Preliminary requirement: requests with searches performed by other patent offices: procedure suspended [chapter 6.21 patent gazette]
B09A Decision: intention to grant [chapter 9.1 patent gazette]
B16A Patent or certificate of addition of invention granted [chapter 16.1 patent gazette]

Free format text: PRAZO DE VALIDADE: 20 (VINTE) ANOS CONTADOS A PARTIR DE 06/12/2011, OBSERVADAS AS CONDICOES LEGAIS.

B25F Entry of change of name and/or headquarter and transfer of application, patent and certif. of addition of invention: change of name on requirement

Owner name: OBERTHUR TECHNOLOGIES (FR)

Free format text: A FIM DE ATENDER A ALTERACAO DE NOME REQUERIDA ATRAVES DA PETICAO NO 870230021205, DE 13/09/2023, E NECESSARIO APRESENTAR PROCURACAO COM O NOME ATUAL DA EMPRESA. ALEM DISSO, E PRECISO APRESENTAR A GUIA DE CUMPRIMENTO DE EXIGENCIA.

B25E Requested change of name of applicant rejected

Owner name: OBERTHUR TECHNOLOGIES (FR)

Free format text: INDEFERIDO O PEDIDO DE ALTERACAO DE NOME CONTIDO NA PETICAO 870230021205 DE13/03/2023, POR AUSENCIA DE CUMPRIMENTO DA EXIGENCIA PUBLICADA NA RPI NO 2740, DE 11/07/2023.

B25D Requested change of name of applicant approved

Owner name: IDEMIA FRANCE (FR)

B25G Requested change of headquarter approved

Owner name: IDEMIA FRANCE (FR)

B25G Requested change of headquarter approved

Owner name: IDEMIA FRANCE (FR)

B15G Petition not considered as such [chapter 15.7 patent gazette]

Free format text: A PETICAO DE NO 870230086223, APRESENTADA EM 28/09/2023, EM VIRTUDE DO DISPOSTO NOSARTS. 218 OU 219 DA LPI (LEI 9279 / 96) DE 14/05/1996, E CONSIDERADA COMO PETICAO NAOCONHECIDA POR TER SIDO PROTOCOLADA FORA DO PRAZO LEGAL DE ATE 60 DIAS APOS A PUBLICACAO DAEXIGENCIA.