BR9910924A - Processo de sintonizar uma largura de banda de circuito fechado travado em fase a um nìvel desejado, aparelho, e, artigo de manufatura - Google Patents

Processo de sintonizar uma largura de banda de circuito fechado travado em fase a um nìvel desejado, aparelho, e, artigo de manufatura

Info

Publication number
BR9910924A
BR9910924A BR9910924-7A BR9910924A BR9910924A BR 9910924 A BR9910924 A BR 9910924A BR 9910924 A BR9910924 A BR 9910924A BR 9910924 A BR9910924 A BR 9910924A
Authority
BR
Brazil
Prior art keywords
phase
locked loop
bandwidth
loop bandwidth
locked
Prior art date
Application number
BR9910924-7A
Other languages
English (en)
Other versions
BR9910924B1 (pt
Inventor
Leif Magnus Andre Nilsson
Hans Hagberg
Original Assignee
Ericsson Telefon Ab L M
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ericsson Telefon Ab L M filed Critical Ericsson Telefon Ab L M
Publication of BR9910924A publication Critical patent/BR9910924A/pt
Publication of BR9910924B1 publication Critical patent/BR9910924B1/pt

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/183—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
    • H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
    • H03L7/0895—Details of the current generators
    • H03L7/0898—Details of the current generators the source or sink current values being variable
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/095—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using a lock detector
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
    • H03L7/107—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth
    • H03L7/1072—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth by changing characteristics of the charge pump, e.g. changing the gain

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Processing Of Color Television Signals (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Electrotherapy Devices (AREA)

Abstract

''PROCESSO DE SINTONIZAR UMA LARGURA DE BANDA DE CIRCUITO FECHADO TRAVADO EM FASE A UM NìVEL DESEJADO, APARELHO, E, ARTIGO DE MANUFATURA'' Uma largura de banda de um circuito fechado travado em fase é sintonizada a um nível desejado operando o circuito fechado travado em fase numa condição travada em fase a uma primeira freq³ência e aplicar uma resposta de etapa ao circuito fechado travado em fase levando o circuito fechado travado em fase a principiar a travar com uma segunda freq³ência que é diferente da primeira freq³ência. Um parâmetro é então detectado que está relacionado com a resposta de etapa aplicada e que é indicativo do fato da largura de banda do circuito fechado travado em fase estar ao nível desejado. A Largura de banda do circuito fechado travado em fase é ajustada, e as etapas de operar à primeira freq³ência, aplicar a resposta de etapa, detectar o parâmetro e ajustar a largura de banda do circuito fechado travado em fase são repetidas até a largura de banda do circuito fechado travado em fase estar ao nível desejado. Onde o nível de largura de banda desejado para sintonia não é a largura de banda operacional, a largura de banda do circuito fechado travado em fase é adicionalmente ajustada por um valor predeterminado, desse modo sintonizando a largura de banda do circuito fechado travado em fase com um nível operacional. A resposta de etapa pode ser aplicada alterando um valor de divisão de freq³ência em um trajeto de realimentação do circuito fechado travado em fase. O parâmetro detectado pode ser um salto de pulso, que indica a largura de banda do circuito fechado travado em fase ainda não está ao nível da largura de banda desejada.
BRPI9910924-7A 1998-06-05 1999-06-02 processo para sintonizar largura de banda de um pll a um nÍvel desejado, e, respectivo aparelho. BR9910924B1 (pt)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/090,914 US6049255A (en) 1998-06-05 1998-06-05 Tuning the bandwidth of a phase-locked loop
PCT/SE1999/000953 WO1999065146A1 (en) 1998-06-05 1999-06-02 Method for tuning the bandwidth of a phase-locked loop

Publications (2)

Publication Number Publication Date
BR9910924A true BR9910924A (pt) 2001-03-06
BR9910924B1 BR9910924B1 (pt) 2013-02-05

Family

ID=22224938

Family Applications (1)

Application Number Title Priority Date Filing Date
BRPI9910924-7A BR9910924B1 (pt) 1998-06-05 1999-06-02 processo para sintonizar largura de banda de um pll a um nÍvel desejado, e, respectivo aparelho.

Country Status (15)

Country Link
US (1) US6049255A (pt)
EP (1) EP1095457B1 (pt)
JP (1) JP4455757B2 (pt)
KR (1) KR100624599B1 (pt)
CN (1) CN1315080B (pt)
AT (1) ATE315286T1 (pt)
AU (1) AU754639B2 (pt)
BR (1) BR9910924B1 (pt)
DE (1) DE69929339T2 (pt)
EE (1) EE200000708A (pt)
HK (1) HK1040841B (pt)
IL (1) IL140068A0 (pt)
MY (1) MY118898A (pt)
PL (1) PL195271B1 (pt)
WO (1) WO1999065146A1 (pt)

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US6812734B1 (en) 2001-12-11 2004-11-02 Altera Corporation Programmable termination with DC voltage level control
US7109744B1 (en) 2001-12-11 2006-09-19 Altera Corporation Programmable termination with DC voltage level control
US6768955B2 (en) * 2002-05-17 2004-07-27 Sun Microsystems, Inc. Adjustment and calibration system for post-fabrication treatment of phase locked loop charge pump
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US7405633B2 (en) * 2005-07-18 2008-07-29 Tellabs Reston, Inc. Methods and apparatus for loop bandwidth control for a phase-locked loop
US7679397B1 (en) 2005-08-05 2010-03-16 Altera Corporation Techniques for precision biasing output driver for a calibrated on-chip termination circuit
CN100446392C (zh) * 2006-04-27 2008-12-24 电子科技大学 一种脉冲跨周期调制开关稳压电源控制器
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Also Published As

Publication number Publication date
AU754639B2 (en) 2002-11-21
BR9910924B1 (pt) 2013-02-05
KR20010052536A (ko) 2001-06-25
HK1040841B (zh) 2011-02-18
DE69929339D1 (de) 2006-03-30
CN1315080B (zh) 2010-06-23
HK1040841A1 (en) 2002-06-21
DE69929339T2 (de) 2006-09-07
IL140068A0 (en) 2002-02-10
US6049255A (en) 2000-04-11
JP2002518869A (ja) 2002-06-25
EP1095457A1 (en) 2001-05-02
MY118898A (en) 2005-02-28
PL195271B1 (pl) 2007-08-31
WO1999065146A1 (en) 1999-12-16
PL346360A1 (en) 2002-02-11
AU4667899A (en) 1999-12-30
KR100624599B1 (ko) 2006-09-18
ATE315286T1 (de) 2006-02-15
EE200000708A (et) 2002-04-15
EP1095457B1 (en) 2006-01-04
CN1315080A (zh) 2001-09-26
JP4455757B2 (ja) 2010-04-21

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Legal Events

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B06A Patent application procedure suspended [chapter 6.1 patent gazette]
B09A Decision: intention to grant [chapter 9.1 patent gazette]
B09X Republication of the decision to grant [chapter 9.1.3 patent gazette]

Free format text: REPUBLICACAO DA PUBLICACAO DE DEFERIMENTO FEITA NA RPI NO 2176 DE 18/09/2012 POR TER SIDO EFETUADA COM INCORRECAO.

B16A Patent or certificate of addition of invention granted [chapter 16.1 patent gazette]

Free format text: PRAZO DE VALIDADE: 10 (DEZ) ANOS CONTADOS A PARTIR DE 05/02/2013, OBSERVADAS AS CONDICOES LEGAIS.

B21A Patent or certificate of addition expired [chapter 21.1 patent gazette]

Free format text: PATENTE EXTINTA EM 05/02/2023.