AU2020104420A4 - A metallized structure on the back of silicon wafer and its manufacturing methods - Google Patents
A metallized structure on the back of silicon wafer and its manufacturing methods Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/4827—Materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/03—Manufacturing methods
- H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
- H01L2224/03444—Manufacturing methods by blanket deposition of the material of the bonding area in gaseous form
- H01L2224/0345—Physical vapour deposition [PVD], e.g. evaporation, or sputtering
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01072—Hafnium [Hf]
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- Condensed Matter Physics & Semiconductors (AREA)
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- Electrodes Of Semiconductors (AREA)
- Physical Vapour Deposition (AREA)
Abstract
The invention relates to the technical field of semiconductor devices and
integrated circuit technology, and specifically relates to the backside metallization
structure and technology of silicon devices. In the structure, at least a first metal layer
of hafnium is deposited on the surface of the back silicon wafer, and then other layers
are deposited. The process includes process steps such as front protection, backside
thinning, back polishing, cleaning, physical vapor deposition and so on. The invention
utilizes the characteristics of ohmic contact between hafnium and silicon, prepares a
layer of hafnium on the back of the silicon wafer, has lower contact resistance and
better adhesion, and at the same time has good electrical conductivity, thermal
conductivity and suitable thermal expansion coefficient and improves the yield rate in
the manufacturing process of silicon devices and reliability of the devices.
Description
A Metallized Structure on the Back of Silicon Wafer
and Its Manufacturing Methods
The present invention relates to the technical field of semiconductor devices and
integrated circuit technology, and specifically relates to the back metallization
structure and technology of silicon devices.
With the development of large-scale and very large-scale integrated circuits, the
feature size of chips is getting smaller and smaller, and the degree of integration is
getting higher and higher. Electronic systems and complete machines are constantly
developing towards miniaturization, high performance, high density, and high
reliability. This puts forward higher requirements for chip interconnection materials,
component soldering materials and packaging materials.
The backside metallization system is an important part of the transistor. It has
two main functions, one is a larger current path, and the other is a path for transferring
and dissipating the large amount of heat generated by the collector of the transistor.
Therefore, the backside metallization system has a great influence on the performance
and reliability of the transistor.
A good backside metallization system requires low ohmic contact resistance, low
contact thermal resistance and good reliability. In order to form a good ohmic contact
with the silicon substrate, it is usually required to select: 1) a metal material with a
lower Schottky barrier; 2) a heavily doped substrate material; 3) a substrate with a
high density of the efficient recombination centers.
In order to make the backside metallization layer of the transistor have good
thermal conductivity and reliability, it is necessary to minimize the thermal stress
between the silicon chip and the backside metallization layer. When the transistor is in
an intermittent working state, the device undergoes periodic high and low temperature
processes, forming a thermal cycle. Due to the different linear expansion coefficients
among the silicon chip, solder and the materials of the base layers inside the transistor,
thermal stress is generated inside the system during the thermal cycle, and the thermal
resistance increases, causing the transistor to locally overheat and fail. Moreover, the
silicon chip with a thickness of about 200m is a very thin and brittle material. During
ion implantation, the chip has greater stress and is prone to fragmentation. When the
linear expansion coefficients of the materials of each layer are not well matched, the
chip may fail due to warpage and cracking after experiencing multiple thermal cycles.
1. The technical problem to be solved
The structure of the backside metallization system currently used in devices
generally consists of three parts: an ohmic contact layer, a diffusion barrier layer and a
conductive layer. The metal used in the ohmic contact layer is generally titanium or
vanadium or chromium or gold or gold-arsenic alloy. The metal used in the barrier
layer is generally nickel or gold or copper-tin alloy or gold-germanium alloy or
gold-germanium-antimony alloy. The metal used in the conductive layer is generally
gold or silver. The existing structure and process still fail to meet the comprehensive
requirements of low cost, high stability, high reliability, and good coordination with
subsequent packaging processes. There are also poor coordination with subsequent
packaging processes, warpage or fragmentation and relatively low yield rate.
2. Technical solution
The present invention aims to solve the shortcomings of the prior art, provide a
new backside metallization structure of silicon wafer with low contact resistance and
its manufacturing process, have the advantages of high electrical conductivity, high
thermal conductivity, thermal expansion coefficient and good matching with the
medium, and improve the yield rate of products.
In order to achieve the above-mentioned object, the technical solution adopted by
the present invention is that the structure has at least a first metal layer of hafnium
deposited on the surface of the backside silicon wafer in sequence from near to far
away from the silicon wafer. Preferably, a second metal layer can be deposited, and
the material of the second metal layer is any one of gold, nickel or gold-germanium
alloy. Preferably, a third metal layer can be deposited, and the material of the third
metal layer is any one of silver, gold, gold-germanium alloy, and gold-tin alloy.
Preferably, the thickness of the first metal layer is 30nm-300nm
Preferably, the thickness of gold used as the second metal layer is 500 nm to
2000 nm, the thickness of nickel used as the second metal layer is 100 nm to 600 nm,
and the thickness of gold-germanium alloy used as the second metal layer is 100 nm
to 500 nm.
Preferably, the thickness of silver used as the third metal layer is 100 nm to 2000
nm, the thickness of gold used as the third metal layer is 100 nm to 1500 nm, and the
thickness of gold-germanium alloy or gold-tin alloy used as the third metal layer is
300 nm-1500nm.
A processing technology for the metallization structure on the back of a silicon
wafer, which includes the following steps: front protection, backside thinning, back
polishing, cleaning, magnetron sputtering or electron beam evaporation to prepare the
first metal layer, evaporation or sputtering to prepare other metals layer. The front
protection is to paste a protective film on the front of the silicon wafer. The backside
thinning is to thin the back side of the silicon wafer to a desired thickness. The back
polishing is to remove the damaged layer generated by the grinding plate. The
cleaning is to clean the polished silicon wafer. The first metal layer is prepared by
magnetron sputtering or electron beam evaporation, wherein the rate of magnetron
sputtering is 5nm/s-15nm/s, and the rate of electron beam evaporation is
0.5nm/s3nm/s. The second metal layer and the third metal layer are prepared by
evaporation or magnetron sputtering, the evaporation rate is 0.5 nm/s-3 nm/s, and the
magnetron sputtering rate is 5 nm/s-15 nm/s.
The electron beam evaporation method is a kind of vacuum evaporation coating.
It is a method of directly heating the evaporation material under vacuum conditions
by using an electron beam to vaporize the evaporation material and transport it to the
substrate, and condense on the substrate to form a thin film. In the electron beam
heating device, the material to be heated is placed in a water-cooled crucible, which can prevent the evaporation material from reacting with the crucible wall and thus affect the quality of the film. Electron beam evaporation can evaporate high melting point materials. Compared with general resistance heating evaporation, it has higher thermal efficiency, higher beam current density and faster evaporation speed; the produced film has the advantages of high purity, good quality and accurate control of thickness. The magnetron sputtering is a type of physical vapor deposition, and has the advantages of simple equipment, easy control, large coating area and strong adhesion. The technology includes the target, power supply, target working mode and so on, among which the target is the key. Usually, the target is connected to a negative potential of 400V-600V, the substrate is grounded, and the two constitute a discharge field with the target as the cathode and the substrate as the anode. The cathode target is equipped with a magnetic circuit module, which can be a permanent magnet or an electromagnet, to provide a magnetic flux density of 0.03T-0.06T to the target surface. The magnetic field lines are parallel to the target surface and orthogonal to the electric field. The space enclosed by the magnetic field lines and the target surface is the plasma region that produces a binding effect on electrons. Taking argon gas as an example, the Ar positive ions generated by glow discharge are accelerated and bombard the surface of the target continuously, causing the atoms of the target to be sputtered and deposited on the substrate opposite to the target to form a sputtering film. 3. Beneficial Effects The material of the first metal layer of the present invention is hafnium. Compared with the existing titanium or gold or gold-arsenic alloy, the hafnium and the silicon substrate form a better ohmic contact, with lower contact resistance and better adhesion. It also has good electrical conductivity, thermal conductivity and appropriate thermal expansion coefficient, which effectively improves the yield rate in the manufacturing process of silicon devices and reliability of the devices. When the hafnium layer is applied to an n-type silicon substrate, the ohmic contact can be
realized without increasing the surface doping concentration of the substrate. At the
same time, the design of the second metal layer and the third metal layer of the
present invention effectively increases the stability of the silicon device, can be
applied to eutectic welding occasions, and has a wide range of applications. The
processing technology of the present invention ensures the realization of the
above-mentioned backside metallization structure.
Fig.1 is a schematic diagram of the metallization structure on the back of a
silicon wafer of the present invention. Among them: 101 silicon wafer; 102 hafnium,
the first metal layer of the structure; 103 gold, the second metal layer of the structure.
Fig.2 is a schematic diagram of the metallization structure on the back of the
silicon wafer of the present invention. Among them: 201 silicon wafer; 202 hafnium,
the first metal layer of the structure; 203 nickel, the second metal layer of the structure;
204 silver or gold, the third metal layer of the structure.
Fig.3 is a schematic diagram of the metallization structure on the back of the
silicon wafer of the present invention. Among them: 301 silicon wafer; 302 hafnium,
which is the first metal layer of the structure; 303 gold-germanium alloy, is the second
metal layer of the structure; 304 silver or gold, is the third metal layer of the structure.
Fig.4 is a schematic diagram of the metallization structure on the back of the
silicon wafer of the present invention. Among them: 401 silicon wafer; 402 hafnium,
which is the first metal layer of the structure; 403 nickel, which is the second metal
layer of the structure; and 404 gold-germanium alloy or gold-tin alloy, which is the
third metal layer of the structure.
Fig.5 is a schematic diagram of the metallization structure on the back of the
silicon wafer of the present invention. Among them: 501 silicon wafer; 502 hafnium,
the first metal layer of the structure; 503 nickel, the second metal layer of the structure;
504 gold, the third metal layer of the structure.
The best embodiment for implementing the invention
The metallization structure on the back of the silicon wafer is shown in Figure 1.
The first metal layer 102 is hafnium with a thickness of 300 nm, and the second metal
layer 103 is gold with a thickness of 2000 nm. The processing steps are: front
protection, backside thinning, back polishing, cleaning, magnetron sputtering at a rate
of 5 nm/s to prepare a hafnium layer, and evaporation at a rate of 3 nm/s to prepare a
gold layer.
Embodiment 2. The metallization structure on the back of the silicon wafer is
shown in Figure 2. The first metal layer 202 is hafnium with a thickness of 30 nm, the
second metal layer 203 is nickel with a thickness of 600 nm, and the third metal layer
204 is silver or gold with a thickness of 2000 nm. The processing steps are: front
protection; backside thinning; back polishing; cleaning; electron beam evaporation at
a rate of 0.5 nm/s to prepare a hafnium layer; magnetron sputtering at a rate of 15
nm/s to prepare a nickel layer; magnetron sputtering at a rate of 10 nm/s to prepare a
gold layer or magnetron sputtering at a rate of 15 nm/s to prepare a silver layer.
Embodiment 3. The metallization structure on the back of the silicon wafer is
shown in Figure 3. The first metal layer 302 is hafnium with a thickness of 200 nm,
the second metal layer 303 is a gold-germanium alloy with a thickness of 500 nm, and
the third metal layer 304 is silver or gold with a thickness of 100 nm. The processing
steps are: front protection; backside thinning; back polishing; cleaning; magnetron
sputtering at a rate of 15 nm/s to prepare a hafnium layer; evaporation at a rate of 0.5
nm/s to prepare a gold-germanium layer; magnetron sputtering at a rate of 0.5 nm/s to
prepare a gold layer or magnetron sputtering at a rate of 3 nm/s to prepare a silver
layer.
Embodiment 4. The metallization structure on the back of the silicon wafer is
shown in Figure 4. The first metal layer 402 is hafnium with a thickness of 100 nm,
the second metal layer 403 is nickel with a thickness of 100 nm, and the third metal
layer 404 is a gold-germanium alloy or a gold-tin alloy with a thickness of 1500 nm.
The processing steps are: front protection, backside thinning, back polishing, cleaning,
electron beam evaporation at a rate of 3 nm/s to prepare a hafnium layer, magnetron
sputtering at a rate of 8 nm/s to prepare a nickel layer, magnetron sputtering at a rate
of 15 nm/s to prepare a gold-germanium alloy layer or gold-tin alloy layer.
Embodiment 5. The metallization structure on the back of the silicon wafer is
shown in Figure 5. The first metal layer 502 is hafnium with a thickness of 120 nm,
the second metal layer 503 is nickel with a thickness of 150 nm, and the third metal
layer 504 is gold with a thickness of 1500 nm. The processing steps are: front
protection, backside thinning, back polishing, cleaning, magnetron sputtering at a rate
of 8 nm/s to prepare a hafnium layer, magnetron sputtering at a rate of 5 nm/s to
prepare a nickel layer, magnetron sputtering at a rate of 5 nm/s to prepare a gold layer.
Claims (8)
- [Claim 1] A silicon wafer backside metallization structure, characterized in that: the structure has at least a first metal layer of hafnium deposited on the surface of the backside silicon wafer in sequence from near to far away from the silicon wafer.
- [Claim 2] A silicon wafer backside metallization structure according to claim 1, characterized in that: the structure has a first metal layer and a second metal layer sequentially deposited on the surface of the backside silicon wafer in order from near to far away from the silicon wafer; the material of the second metal layer is any one of gold, nickel, or gold-germanium alloy.
- [Claim 3] A silicon wafer backside metallization structure according to claim 1, characterized in that: the structure has a first metal layer, a second metal layer and a third metal layer deposited on the surface of the backside silicon wafer in order from near to far away from the silicon wafer; the material of the third metal layer is any one of silver, gold, gold-germanium alloy and gold-tin alloy.
- [Claim 4] A silicon wafer backside metallization structure according to claim 1, wherein the thickness of the first metal layer is 30 nm to 300 nm.
- [Claim 5] A silicon wafer backside metallization structure according to claim 2, characterized in that the thickness of gold used as the second metal layer is 500nm-2000nm, the thickness of nickel used as the second metal layer is 100nm600nm, and the thickness of the gold-germanium alloy used as the second metal layer is100nm500nm.
- [Claim 6] A silicon wafer backside metallization structure according to claim 3, characterized in that the thickness of silver used as the third metal layer is 100nm-2000nm, and the thickness of gold used as the third metal layer is 100nm~1500nm, the thickness of gold-germanium alloy or gold-tin alloy used as the third metal layer is 300nm~1500nm.
- [Claim 7] A process for preparing the metallization structure on the back of a silicon wafer as claimed in claim 1, wherein the first metal layer is prepared by magnetron sputtering or electron beam evaporation, and the rate of magnetron sputtering is 5nm/s-15nm/s, the rate of electron beam evaporation is 0.5nm/s3nm/s.
- [Claim 8] A process for preparing the metallized structure on the back of asilicon wafer as claimed in claim 2 or 3, characterized in that: the second metal layerand the third metal layer are prepared by evaporation or magnetron sputtering; the rateof evaporation is 0.5nm/s-3nm/s, and the rate of magnetron sputtering isnm/s-15nm/s.
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| CN202010000190.2 | 2020-01-02 | ||
| CN202010000190.2A CN110783292A (en) | 2020-01-02 | 2020-01-02 | Silicon wafer back metallization structure and manufacturing process thereof |
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| WO (1) | WO2021136222A1 (en) |
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| CN113299621A (en) * | 2020-01-02 | 2021-08-24 | 南京市产品质量监督检验院 | Lightly doped n-type silicon wafer back metallization structure and manufacturing process thereof |
| CN113336182B (en) * | 2021-05-19 | 2023-05-26 | 中山大学南昌研究院 | Micro-electromechanical system packaging structure and preparation method thereof |
| CN115558900A (en) * | 2022-05-30 | 2023-01-03 | 滁州钰顺企业管理咨询合伙企业(有限合伙) | Method for preventing metal coating from being abnormal based on wafer back metallization evaporation |
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| CN100454492C (en) * | 2002-06-13 | 2009-01-21 | 衡阳科晶微电子有限公司 | Back side metallization technology for eutectic welding |
| CN100400703C (en) * | 2004-12-23 | 2008-07-09 | 中国科学院半导体研究所 | Method for preparing film material of metal hafnium |
| CN101465305A (en) * | 2008-10-22 | 2009-06-24 | 杭州士兰集成电路有限公司 | Back face metalization technological process and structure for chip low contact resistance |
| JP6089235B2 (en) * | 2012-03-28 | 2017-03-08 | 国立研究開発法人産業技術総合研究所 | Method for manufacturing silicon carbide semiconductor element |
| CN103963375B (en) * | 2013-01-30 | 2016-12-28 | 苏州同冠微电子有限公司 | Silicon chip back side metallization eutectic structure and manufacturing process thereof |
| CN106653718B (en) * | 2015-11-04 | 2019-02-26 | 苏州同冠微电子有限公司 | Silicon chip back side metallization structure and processing technology for eutectic weldering |
| CN108109901A (en) * | 2016-11-25 | 2018-06-01 | 中芯国际集成电路制造(上海)有限公司 | A kind of production method of semiconductor devices |
| CN107195606A (en) * | 2017-06-26 | 2017-09-22 | 昆山昊盛泰纳米科技有限公司 | A kind of silicon chip back side metallized film and preparation method thereof |
| CN113299621A (en) * | 2020-01-02 | 2021-08-24 | 南京市产品质量监督检验院 | Lightly doped n-type silicon wafer back metallization structure and manufacturing process thereof |
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| CN110783292A (en) | 2020-02-11 |
| CN113299621A (en) | 2021-08-24 |
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