CN106653718B - Silicon chip back side metallization structure and processing technology for eutectic weldering - Google Patents
Silicon chip back side metallization structure and processing technology for eutectic weldering Download PDFInfo
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- CN106653718B CN106653718B CN201510740926.9A CN201510740926A CN106653718B CN 106653718 B CN106653718 B CN 106653718B CN 201510740926 A CN201510740926 A CN 201510740926A CN 106653718 B CN106653718 B CN 106653718B
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- back side
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/27—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/27—Manufacturing methods
- H01L2224/274—Manufacturing methods by blanket deposition of the material of the layer connector
- H01L2224/27444—Manufacturing methods by blanket deposition of the material of the layer connector in gaseous form
- H01L2224/2745—Physical vapour deposition [PVD], e.g. evaporation, or sputtering
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/28105—Layer connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. layer connectors on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/2954—Coating
- H01L2224/29575—Plural coating layers
- H01L2224/2958—Plural coating layers being stacked
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
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- Manufacturing & Machinery (AREA)
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Abstract
The invention belongs to technical field of semiconductors, more particularly to a kind of silicon chip back side metallization structure and processing technology for eutectic weldering, the surface of the structure overleaf silicon substrate is by away from silicon wafer, sequence is successively coated with the first metal layer, second metal layer, third metal layer, the 4th metal layer and fifth metal layer from the near to the distant, the material of the first metal layer is any one of titanium, vanadium or chromium, the material of second metal layer is nickel, the material of third metal layer is silver, the material of 4th metal layer is tin copper or tin pewter, and the material of fifth metal layer is silver.Silicon chip back side metallization structure and processing technology for eutectic weldering of the invention reduces cost while not having toxicity, phenomena such as being when packaged not in bad eutectic, rosin joint, while will not occur the problem of excess temperature in wave-soldering, increase reliability, covering surface is big, widely applicable.
Description
Technical field
The invention belongs to technical field of semiconductors, and in particular to it is a kind of for eutectic weldering silicon chip back side metallization structure and
Processing technology.
Background technique
Eutectic weldering is also known as low-melting alloy welding.The fundamental characteristics of eutectic alloy is: two different metals can be remote low
Alloy is formed in constant weight ratio under respective melting temperature.Most common eutectic weldering is silicon core in microelectronic component
Piece is soldered to gold-plated pedestal or lead frame up, i.e. " gold-silicon eutectic weldering ".Current golden arsenic eutectic technology, higher cost and has
Poison.Existing three layers of low temperature tin eutectic, eutectic is bad, empty when being easy to appear tin layers oxidation and later period encapsulation load in keeping
Weldering, residual less, wave-soldering when excess temperature the problems such as making chip fall off.
Summary of the invention
The object of the present invention is to provide a kind of silicon chip back side metallization structures and processing technology for eutectic weldering, are not having
While toxicity, phenomena such as reducing cost, be when packaged not in bad eutectic, rosin joint, while will not in wave-soldering
There is the problem of excess temperature, increases reliability, covering surface is big, widely applicable.
To achieve the above object, the technical scheme adopted by the invention is that: the surface of the structure overleaf silicon substrate
By away from silicon wafer, sequence is successively coated with the first metal layer, second metal layer, third metal layer, the 4th metal layer and the 5th from the near to the distant
Metal layer, the material of the first metal layer are any one of titanium, vanadium or chromium, and the material of second metal layer is nickel, third metal layer
Material be silver, the material of the 4th metal layer is tin copper or tin pewter, and the material of fifth metal layer is silver.
Preferably, the first metal layer with a thickness of
Preferably, the second metal layer with a thickness of
Preferably, the third metal layer with a thickness of
Preferably, the 4th metal layer with a thickness of
Preferably, the fifth metal layer with a thickness of
Preferably, when the material of the 4th metal layer is gun-metal, the weight percent of tin in the gun-metal
It is 55~65%, the weight percent of copper is 35~45%；When the material of 4th metal layer is tin pewter, the tin pewter
The weight percent of middle tin is 90~94%, and the weight percent of antimony is 6~10%.
A kind of processing technology of the silicon chip back side metallization structure for eutectic weldering, the first metal layer, second metal layer, the
Three metal layers, the 4th metal layer and fifth metal layer carry out plated film by way of evaporation, wherein the evaporation of the first metal layer
Rate beThe rate of the evaporation of second metal layer isThe rate of the evaporation of third metal layer isThe rate of the evaporation of 4th metal layer isThe rate of the evaporation of fifth metal layer is
After adopting the above technical scheme, the present invention has the positive effect that:
The silicon chip back side metallization structure and processing technology for eutectic weldering in the present invention, using the side of five layers of plated film
Formula reduces its cost and reduces toxic action, compared to existing three layers of low temperature compared to existing golden arsenic eutectic technology
Tin eutectic technology is easy to appear tin layers problem of oxidation when efficiently solving keeping, and eutectic structure of the invention when packaged will not
There is phenomena such as eutectic is bad, rosin joint, at the same the design of third metal layer and the 4th metal layer of the invention efficiently solve it is low
The wave-soldering phenomenon generated when warm eutectic ensure that be not in excess temperature problem in wave-soldering, and increase eutectic structure can
By property, covering surface is big, widely applicable.
Detailed description of the invention
Fig. 1 is the schematic diagram for the silicon chip back side metallization structure that eutectic of the invention welds.
Wherein: 1, silicon wafer, 2, the first metal layer, 3, second metal layer, 4, third metal layer, the 5, the 4th metal layer, 6,
Five metal layers.
Specific embodiment
Invention is further described in detail with reference to the accompanying drawings and detailed description.
1. metallization structure
As shown in Figure 1, for the silicon chip back side metallization structure that eutectic of the invention welds, including material is in titanium, vanadium or chromium
Any the first metal layer 2, the second metal layer 3 that material is nickel, material be the third metal layer 4 of silver, material is tin copper
The 4th metal layer 5 and material of alloy or tin pewter are the fifth metal layer 6 of silver.The first metal layer 2, second metal layer 3,
Three metal layers 4, the 4th metal layer 5 and fifth metal layer 6 overleaf silicon substrate 1 surface press away from silicon wafer 1 from the near to the distant sequence
Successively it is deposited.
2. processing technology step are as follows:
(1) prepare gun-metal or tin pewter, the weight percent of tin is 55~65% in gun-metal, the weight of copper
Percentage is 35~45%；The weight percent of tin is 90~94% in tin pewter, and the weight percent of antimony is 6~10%；
(2) pad pasting processing is carried out to the front of silicon wafer 1, then edge is carried out to repair film inspection；
(3) reduction processing is carried out to the backing substrate of silicon wafer 1, after processing, pad pasting is removed to front；
(4) silicon wafer 1 is cleaned；
(5) silicon wafer 1 is put into vapourizing furnace after cleaning；
(6) processing is evaporated to the back side: the first metal layer 2 with a thickness ofThe rate of evaporation isSecond metal layer 3 with a thickness ofThe rate of evaporation isThird metal layer 4
With a thickness ofThe rate of evaporation is4th metal layer 5 with a thickness ofIt steams
The rate of hair isFifth metal layer 6 with a thickness ofThe rate of evaporation is
(7) it comes out of the stove detection.
Embodiment 1
1. metallization structure
The silicon chip back side metallization structure of the eutectic weldering of the present embodiment is including the first metal layer 2 that material is titanium, material
Second metal layer 3, the material of nickel are that third metal layer 4, the 4th metal layer 5 that material is gun-metal and the material of silver are silver-colored
Fifth metal layer 6.
2. processing technology step are as follows:
(1) prepare gun-metal, the weight percent of tin is 60% in gun-metal, and the weight percent of copper is 40%；
(2) pad pasting processing is carried out to the front of silicon wafer 1, then edge is carried out to repair film inspection；
(3) reduction processing is carried out to the backing substrate of silicon wafer 1, after processing, pad pasting is removed to front；
(4) silicon wafer 1 is cleaned；
(5) silicon wafer 1 is put into vapourizing furnace after cleaning；
(6) processing is evaporated to the back side: the first metal layer 2 with a thickness ofThe rate of evaporation isThe
Two metal layers 3 with a thickness ofThe rate of evaporation isThird metal layer 4 with a thickness ofEvaporation
Rate is4th metal layer 5 with a thickness ofThe rate of evaporation isThe thickness of fifth metal layer 6
ForThe rate of evaporation is
(7) it comes out of the stove detection.
Embodiment 2
1. metallization structure
The silicon chip back side metallization structure of the eutectic weldering of the present embodiment is including the first metal layer 2 that material is vanadium, material
Second metal layer 3, the material of nickel are the third metal layer 4 of silver, 5 and of the 4th metal layer that material is gun-metal or tin pewter
Material is the fifth metal layer 6 of silver.
2. processing technology step are as follows:
(1) prepare tin pewter, the weight percent of tin is 92% in tin pewter, and the weight percent of antimony is 8%；
(2) pad pasting processing is carried out to the front of silicon wafer 1, then edge is carried out to repair film inspection；
(3) reduction processing is carried out to the backing substrate of silicon wafer 1, after processing, pad pasting is removed to front；
(4) silicon wafer 1 is cleaned；
(5) silicon wafer 1 is put into vapourizing furnace after cleaning；
(6) processing is evaporated to the back side: the first metal layer 2 with a thickness ofThe rate of evaporation isThe
Two metal layers 3 with a thickness ofThe rate of evaporation isThird metal layer 4 with a thickness ofEvaporation
Rate is4th metal layer 5 with a thickness ofThe rate of evaporation isThe thickness of fifth metal layer 6
ForThe rate of evaporation is
(7) it comes out of the stove detection.
Embodiment 3
1. metallization structure
The silicon chip back side metallization structure of the eutectic weldering of the present embodiment is including the first metal layer 2 that material is chromium, material
Second metal layer 3, the material of nickel are that third metal layer 4, the 4th metal layer 5 that material is gun-metal and the material of silver are silver-colored
Fifth metal layer 6.
2. processing technology step are as follows:
(1) prepare gun-metal, the weight percent of tin is 65% in gun-metal, and the weight percent of copper is 35%；
(2) pad pasting processing is carried out to the front of silicon wafer 1, then edge is carried out to repair film inspection；
(3) reduction processing is carried out to the backing substrate of silicon wafer 1, after processing, pad pasting is removed to front；
(4) silicon wafer 1 is cleaned；
(5) silicon wafer 1 is put into vapourizing furnace after cleaning；
(6) processing is evaporated to the back side: the first metal layer 2 with a thickness ofThe rate of evaporation is
Second metal layer 3 with a thickness ofThe rate of evaporation isThird metal layer 4 with a thickness ofEvaporation
Rate be4th metal layer 5 with a thickness ofThe rate of evaporation isThe thickness of fifth metal layer 6
Degree isThe rate of evaporation is
(7) it comes out of the stove detection.
Embodiment 4
1. metallization structure
The silicon chip back side metallization structure of the eutectic weldering of the present embodiment is including the first metal layer 2 that material is chromium, material
Second metal layer 3, the material of nickel are that third metal layer 4, the 4th metal layer 5 that material is gun-metal and the material of silver are silver-colored
Fifth metal layer 6.
2. processing technology step are as follows:
(1) prepare tin pewter, the weight percent of tin is 90% in tin pewter, and the weight percent of antimony is 10%；
(2) pad pasting processing is carried out to the front of silicon wafer 1, then edge is carried out to repair film inspection；
(3) reduction processing is carried out to the backing substrate of silicon wafer 1, after processing, pad pasting is removed to front；
(4) silicon wafer 1 is cleaned；
(5) silicon wafer 1 is put into vapourizing furnace after cleaning；
(6) processing is evaporated to the back side: the first metal layer 2 with a thickness ofThe rate of evaporation isThe
Two metal layers 3 with a thickness ofThe rate of evaporation isThird metal layer 4 with a thickness ofEvaporation
Rate is4th metal layer 5 with a thickness ofThe rate of evaporation isThe thickness of fifth metal layer 6
Degree isThe rate of evaporation is
(7) it comes out of the stove detection.
It will be apparent to those skilled in the art that can make various other according to the above description of the technical scheme and ideas
It is corresponding to change and deformation, and all these change and deformation all should belong to the present invention claims protection scope it
It is interior.
Claims (7)
1. a kind of silicon chip back side metallization structure for eutectic weldering, it is characterised in that: the structure overleaf silicon substrate (1)
Surface press that sequence is successively coated with the first metal layer (2), second metal layer (3), third metal layer from the near to the distant away from silicon wafer (1)
(4), the 4th metal layer (5) and fifth metal layer (6), the material of the first metal layer (2) are any one of titanium, vanadium or chromium, the
The material of two metal layers (3) is nickel, and the material of third metal layer (4) is silver, and the material of the 4th metal layer (5) is tin copper or tin antimony
Alloy, the material of fifth metal layer (6) is silver, when the material of the 4th metal layer (5) is gun-metal, tin in the gun-metal
Weight percent be 55~65%, the weight percent of copper is 35~45%；The material of 4th metal layer (5) is tin pewter
When, the weight percent of tin is 90~94% in the tin pewter, and the weight percent of antimony is 6~10%.
2. the silicon chip back side metallization structure according to claim 1 for eutectic weldering, it is characterised in that: the first metal layer
(2) with a thickness of
3. the silicon chip back side metallization structure according to claim 2 for eutectic weldering, it is characterised in that: second metal layer
(3) with a thickness of
4. the silicon chip back side metallization structure according to claim 3 for eutectic weldering, it is characterised in that: third metal layer
(4) with a thickness of
5. the silicon chip back side metallization structure according to claim 4 for eutectic weldering, it is characterised in that: the 4th metal layer
(5) with a thickness of
6. the silicon chip back side metallization structure according to claim 5 for eutectic weldering, it is characterised in that: fifth metal layer
(6) with a thickness of
7. the processing technology described in a kind of claim 1 for the silicon chip back side metallization structure of eutectic weldering, it is characterised in that: the
One metal layer (2), second metal layer (3), third metal layer (4), the 4th metal layer (5) and fifth metal layer (6) pass through steaming
The mode of hair carries out plated film, and wherein the rate of the evaporation of the first metal layer (2) isThe evaporation of second metal layer (3)
Rate isThe rate of the evaporation of third metal layer (4) isThe rate of the evaporation of 4th metal layer (5)
ForThe rate of the evaporation of fifth metal layer (6) is
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| CN201510740926.9A CN106653718B (en) | 2015-11-04 | 2015-11-04 | Silicon chip back side metallization structure and processing technology for eutectic weldering |
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| CN110783292A (en) * | 2020-01-02 | 2020-02-11 | 南京市产品质量监督检验院 | Silicon wafer back metallization structure and manufacturing process thereof |
| CN114742819B (en) * | 2022-05-10 | 2022-12-09 | 上海晶岳电子有限公司 | Silicon wafer film pasting quality inspection management method and system in MOS tube back gold process |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102956515A (en) * | 2012-09-29 | 2013-03-06 | 北京时代民芯科技有限公司 | Silver-silicon eutectic soldering method of chips |
| CN203456442U (en) * | 2013-08-16 | 2014-02-26 | 江阴新顺微电子有限公司 | Low-cost high-applicability semiconductor chip back face metallization structure for eutectic package |
| CN103963375A (en) * | 2013-01-30 | 2014-08-06 | 苏州同冠微电子有限公司 | Silicon wafer back side metallized eutectic structure and manufacturing process thereof |
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- 2015-11-04 CN CN201510740926.9A patent/CN106653718B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102956515A (en) * | 2012-09-29 | 2013-03-06 | 北京时代民芯科技有限公司 | Silver-silicon eutectic soldering method of chips |
| CN103963375A (en) * | 2013-01-30 | 2014-08-06 | 苏州同冠微电子有限公司 | Silicon wafer back side metallized eutectic structure and manufacturing process thereof |
| CN203456442U (en) * | 2013-08-16 | 2014-02-26 | 江阴新顺微电子有限公司 | Low-cost high-applicability semiconductor chip back face metallization structure for eutectic package |
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