AU2002247566B2 - Differential stress reduction in thin films - Google Patents

Differential stress reduction in thin films Download PDF

Info

Publication number
AU2002247566B2
AU2002247566B2 AU2002247566A AU2002247566A AU2002247566B2 AU 2002247566 B2 AU2002247566 B2 AU 2002247566B2 AU 2002247566 A AU2002247566 A AU 2002247566A AU 2002247566 A AU2002247566 A AU 2002247566A AU 2002247566 B2 AU2002247566 B2 AU 2002247566B2
Authority
AU
Australia
Prior art keywords
crystalline
predominant
thin film
layer
crystalline material
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
AU2002247566A
Other versions
AU2002247566A1 (en
Inventor
Kia Silverbrook
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Silverbrook Research Pty Ltd
Original Assignee
Silverbrook Research Pty Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from AUPR9197A external-priority patent/AUPR919701A0/en
Application filed by Silverbrook Research Pty Ltd filed Critical Silverbrook Research Pty Ltd
Priority to AU2002247566A priority Critical patent/AU2002247566B2/en
Publication of AU2002247566A1 publication Critical patent/AU2002247566A1/en
Application granted granted Critical
Publication of AU2002247566B2 publication Critical patent/AU2002247566B2/en
Priority to AU2005203476A priority patent/AU2005203476B2/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Landscapes

  • Micromachines (AREA)

Description

WO 03/045836 PCT/AU02/00537 -1- DIFFERENTIAL STRESS REDUCTION IN THIN FILMS FIELD OF THE INVENTION The present invention relates to a method of manufacture of crystalline thin film structures having reduced differential stress build up, and to the crystalline thin film structures that result from the application of this method.
The invention has been developed primarily for use in the manufacture of microelectro mechanical systems (MEMS) formed using CMOS semiconductor chip technology from materials suited to this particular manufacturing process, and will be described hereinafter with reference to this preferred application. However, it will be appreciated by those skilled in the art, that the invention may be applied to other thin film structures where it is similarly desirable to reduce differential stress levels within the thin film structure.
BACKGROUND OF THE INVENTION Processes for the construction of micro-electro mechanical systems (MEMS) are characterised by the formation of micro actuator devices and mechanisms in multi layered wafer structures. Often these layers comprise thin films of different materials having different properties. For example, some of the layers may be required to be conductive, such as where the mechanism includes a heating element as may be used with a thermal bend actuator or the like.
Thin film structures of this kind are typically formed as a wafer using a molecular deposition process such as "sputtering" which causes the requisite material to be deposited at a molecular level until the desired layer thickness has been attained. With these deposition processes, the first layer of material typically forms small seed crystals which adhere to and align themselves with the supporting substrate. However, subsequent deposited material tends to self align on top of these seed crystals and because of the restraint placed on the development of the growing crystals by the substrate and adjacent crystals, further deposition of the same material tends to thus form columnar crystals.
Unfortunately, the columnar crystals and the underlayer of small seed crystals have quite different thermal expansion properties and other physical characteristics. With many materials, the growing layer also exhibits progressively expanding crystals during WO 03/045836 PCT/AU02/00537 -2deposition due to the dominant growth of some columnar crystals over others. As a result, certain crystal boundaries exist through the entire thickness of the film, these particular boundaries not only weaken the overall structure, but also representing potential locations for the onset of crack propagation.
As a result of this natural film building process, residual stress is induced into the material during wafer cooling. This can have several undesirable effects. Firstly, the residual stress gradient maybe sufficient to cause a flap beam actuator formed by this process to curl, even though its design is such that it is effectively a clamped or free beam.
This may necessitate a re-design of the structure to include additional stiffening elements to to counteract any inclination to curl and as a result is highly likely during operation to require additional power to operate the actuator to overcome either the residual stress or the additional resistance caused by the need to stiffen the structural design.
A common method of reducing stress in thin films is annealing. However, for many crystalline thin films, this requires high temperatures which may be incompatible with the device structure or previous processing steps. For example, if a crystalline thin film is deposited on an integrated circuit with aluminium wiring, then the temperature must remain below the melting point of aluminium, which is too low to anneal many crystalline materials typically used in integrated circuits made using CMOS techniques.
It is an object of the invention to provide a method and structure to reduce the differential stress formed in thin film structures of this kind so as to overcome or at least ameliorate these disadvantages of the prior art, or at least offer a useful alternative.
SUMMARY OF TILE INVENTION According to a first aspect of the invention there is provided a method of manufacture of a crystalline thin film structure from a predominant first crystalline material, said method including the steps of: depositing said predominant first crystalline material as two or more sub-layers; and depositing between said first crystalline material sub-layers, a layer of second crystalline material, said second material possessing a lattice constant that is different from that of the first crystalline material, so as to disrupt columnar crystal growth in said underlying first crystalline material and thereby form a composite thin film structure having WO 03/045836 PCT/AU02/00537 -3a differential stress profile that is less than the differential stress profile of a comparative film formed solely from said predominant first crystalline material.
While the final total internal stress present in a thin film structure manufactured in accordance with the invention may be higher than may be achieved when annealing can be used, the differential stress is much reduced and the curl tendency of a released layer can be reduced by orders of magnitude.
Preferably, the crystalline thin film structure is a layer of a MEMS structure and more preferably an operational or active layer of a MEIVIS structure.
Desirably, the second material is selected to have appropriately compatible physical properties relevant to the intended application, as well as possessing a lattice constant that is different from that of the predominant first layer. Where the relevant physical properties of the two materials are similar, such as electrical or thermal conductivity, the thickness of the second material layer relative to the first material sub-layers is less significant. However, where the differences are more pronounced, it is preferable to have a very thin intermediate second material layer so as to minimise the impact of the property difference between the two materials on the final composite structure. Naturally, the pairing of the first and second materials must enable production of a thin film structure having relevant key properties or characteristics that are close to that of the selected predominant first crystalline material.
Preferred combinations of first and second crystalline materials, particularly suited for use in MEMS structures incorporating thermal bend actuators are: titanium nitride as a predominant first material with intermediate layers of tantalum nitride; and silicon as a predominant first material with intermediate layers of germanium.
The combinations are particularly suitable for MEMS constructions formed on top of CMOS circuitry.
BRIEF DESCRIPTION OF THE DRAWINGS A preferred embodiment of the invention will now be described, by way of example only, with reference to the accompanying drawings in which: Figure 1 shows an enlarged partial cross-section of a thin film formed in accordance with the prior art techniques; WO 03/045836 PCT/AU02/00537 -4- Figure 2 shows a length of the thin film of Figure 1 deforming under the residual differential stress; Figure 3 shows a series of clamped/free thin film strips formed in accordance with the prior art techniques; Figure 4 shows a partial cross-section through a thin film formed in accordance with the present invention; Figure 5 shows the brystal boundarys between the primary and secondary layers of the film shown in Figure 4; Figure 6 shows a thin film formed in accordance with the present invention where the deposition of the primary material has been re-seeded three times; and Figure 7 shows clamped/free end strips of thin film formed in accordance with the present invention.
DESCRIPTION OF PREFERRED AND OTHER EMBODIMENTS Referring first to figure 1, there is shown a partial cross-section of a titanium nitride layer showing the grain morphology. The layer has been built up from a first side 1 on a substrate composed of silicon with a thin silicon nitrate coating (not shown). As can be seen, the titanium nitride builds up gradually on the silicon nitrate surface commencing with a thin layer 2 of small seed crystals which gradually evolve into larger columnar crystals shown generally at 3. These columnar crystals tend to become progressively larger during deposition due to the dominant growth of some columnar crystals over others. Thus, certain crystal boundaries exist through the entire thickness of the titanium nitride layer. These particular boundaries weaken the titanium nitride layer and would be the likely location for the onset of crack propagation.
The differing thermal conductivity and expansion characteristics of the different portions of the titanium nitride layer induce residual stress in the wafer during cooling. As shown in Figure 2, this residual stress gradient through the layer thickness tends to cause the layer to curl. This can adversely affect the function of MEMS devices formed from the wafer. In particular, thermoelastic actuators in the form of clamped/free end strips are susceptible to a relatively high degree of curl. As shown in Figure 3, a series of clamped/free end beam thin titanium nitride strips are shown. The longer and thinner strips deflect the most however because of the residual compression on the underside of the strips WO 03/045836 PCT/AU02/00537 and residual tension on the upper side each strip will tend to curl about it's longitudinal axis as well as lateral axis. Wider strips will curl about the longitudinal axis to produce a deeper lateral cross-section which gives the strip a greater bending stiffness about the lateral axis.
A proposed solution for alleviating this differential stress problem, is shown in Figures 4 to 7. An extremely thin layer 100 Angstroms) of tantalum nitride is deposited on top of the titanium nitride at certain levels during the deposition of the titanium nitride layer. The tantalum nitride disrupts any predominant titanium nitride columnar crystal growth and provides a new re-seeding layer. The tantalum nitride effectively acts as a crack inhibitor because the maximum titanium nitride grain boundary can only exist between any two tantalum nitride layers.
The presence of the tantalum nitride layers also effectively moderates the range of grain sizes present. Thus, the magnitude of any induced stress gradient related to the grain size is also moderated. This effectively reduces post fabrication curl.
In this particular preferred embodiment, it is important to note that the tantalum layer is thin enough not to affect the mechanical or resistive properties of the actuator. Tantalum nitride has a decomposition temperature of 750 degrees Centigrade which is above that of titanium nitride.
Examples A finite element model of a simple beam suitable for use in a thermal bend actuator was constructed to investigate residual curl of the tantalum nitride/titanium nitride layer structure. The intent of the analysis was to ascertain the relative effect that different morphologies have on residual curl rather than the calculation of absolute values. The beam model has identical dimensions to the heater section of a centreline prototype thermal actuator and was constructed with ten elements through the thickness. A stress gradient was indirectly included by applying a linearly varying temperature field through the entire thickness. The presence of a tantalum nitride layer is modelled by reapplying the gradient from the initial value.
Four different layer combinations were analysed including no tantalum nitride reseeding layer, and one, two and four layers of tantalum nitride. The solutions resulted in deflections at the beam tip of 0.543, 0.0611, 0.0172 and 0.001 micrometres respectively. It should be noted that these values are relative and not absolute.
WO 03/045836 PCT/AU02/00537 -6- The results of the tests show that the inclusion of tantalum nitride layers can significantly reduce the amount of post-fabrication curl by progressive orders of magnitude depending on the desired overall thickness, number of intermediate layers and the thickness of those intermediate layers.
The above described examples relate to a specific conductor layer having titanium nitride as the predominant material with intermediate layers of tantalum nitride. However, the processes can also be applied to other conductor layer combinations and to nonconductor materials such as silicon which can be compared with intermediate layers of germanium.
Accordingly, while the invention has been described with reference to only one use and two preferred combinations, it will be appreciated by those skilled in the art that the invention can be embodied in many other forms.

Claims (16)

1. A method of manufacture of a crystalline thin film structure from a predominant first crystalline material, said method including the steps of: depositing said predominant first crystalline material as two or more sub-layers; and depositing between said first crystalline material sub-layers, a layer of second crystalline material, said second material possessing a lattice constant that is different from that of the first crystalline material, so as to disrupt columnar crystal growth in said underlying first crystalline material and thereby form a composite thin film structure having a differential stress profile that is less than the differential stress profile of a comparative film formed solely from said predominant first crystalline material.
2. A method according to claim 1 wherein the crystalline thin film structure is a layer of a MEMS structure.
3. A method according to claim 2 wherein the crystalline thin film structure is an operational or active layer of a MEMS structure.
4. A method according to any one of the preceding claims wherein the second material is selected to have appropriately compatible physical properties relevant to the intended application.
A method according to any one of claims 1 to 4 wherein the predominant first material is titanium nitride and the second material is tantalum nitride.
6. A method according to any one of claims 1 to 4 wherein the predominant first material is silicon and the second material is germanium.
7. A method according to any one of the preceding claims wherein the intermediate second layer has a thickness of approximately 100 Angstroms.
8. A crystalline thin film structure including a first and second layer of a predominant first crystalline material; and a second crystalline material between the first and second layers wherein, WO 03/045836 PCT/AU02/00537 -8- the lattice constant of the second crystalline material differs from the lattice constant of the predominant first crystalline material so that columnar crystals in the first layer terminate at the layer of the second crystalline material so that the initiation of crystal growth in the second layer of the first predominant material reduces the differential stress profile relative to a comparative crystalline thin film formed solely from the first predominant crystalline material.
9. A crystalline thin film structure according to claim 8 wherein the structure is a layer of a MEMS structure.
A crystalline thin film structure according to claim 9 wherein the structure is an operational arm in a thermo elastic actuator.
11. A crystalline thin film structure according to claim 10 wherein the predominant first material is titanium nitride and the second material is tantalum nitride.
12. A crystalline thin film structure according to claim 10 wherein the predominant first material silicon and the second crystalline material is germanium.
13. A crystalline thin film structure according to claim 8 wherein the film thickness is less than 500 nanometres.
14. A crystalline thin film structure according to claim 8 having more than two layers of predominant first crystalline material wherein a layer of the second crystalline material is interleaved between each adjacent layer of the first predominant crystalline material.
15. A crystalline thin film structure according to claim 14 having four layers of the predominant first crystalline material and three layers of the second crystalline material interleaved between each adjacent layer of the predominant first crystalline material.
16. A crystalline thin film structure according to claim 15 wherein the thickness of the structure is approximately 300 nanometres and the thickness of each of the layers of predominant first crystalline material is approximately 70 nanometres and the thickness of the second crystalline material is approximately 10 nanometres each.
AU2002247566A 2001-11-30 2002-05-02 Differential stress reduction in thin films Ceased AU2002247566B2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
AU2002247566A AU2002247566B2 (en) 2001-11-30 2002-05-02 Differential stress reduction in thin films
AU2005203476A AU2005203476B2 (en) 2001-11-30 2005-08-05 Formation of a crystalline thin film structure

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
AUPR9197A AUPR919701A0 (en) 2001-11-30 2001-11-30 Method and apparatus (mems18)
AUPR9197 2001-11-30
AU2002247566A AU2002247566B2 (en) 2001-11-30 2002-05-02 Differential stress reduction in thin films
PCT/AU2002/000537 WO2003045836A1 (en) 2001-11-30 2002-05-02 Differential stress reduction in thin films

Related Child Applications (1)

Application Number Title Priority Date Filing Date
AU2005203476A Division AU2005203476B2 (en) 2001-11-30 2005-08-05 Formation of a crystalline thin film structure

Publications (2)

Publication Number Publication Date
AU2002247566A1 AU2002247566A1 (en) 2003-06-10
AU2002247566B2 true AU2002247566B2 (en) 2005-05-05

Family

ID=33565572

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2002247566A Ceased AU2002247566B2 (en) 2001-11-30 2002-05-02 Differential stress reduction in thin films

Country Status (1)

Country Link
AU (1) AU2002247566B2 (en)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61225816A (en) * 1985-03-29 1986-10-07 Sharp Corp Manufacture of compound semiconductor device
JPH02266516A (en) * 1989-04-07 1990-10-31 Hitachi Cable Ltd Manufacture of gaalas epitaxial wafer
EP0455526A1 (en) * 1990-04-13 1991-11-06 Thomson-Csf Process for adaptation between two crystallized semiconductor materials, and semiconductor device
EP0735586A2 (en) * 1995-03-28 1996-10-02 Texas Instruments Incorporated Semi-conductor structures
US6087726A (en) * 1999-03-01 2000-07-11 Lsi Logic Corporation Metal interconnect stack for integrated circuit structure
US6114198A (en) * 1999-05-07 2000-09-05 Vanguard International Semiconductor Corporation Method for forming a high surface area capacitor electrode for DRAM applications

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61225816A (en) * 1985-03-29 1986-10-07 Sharp Corp Manufacture of compound semiconductor device
JPH02266516A (en) * 1989-04-07 1990-10-31 Hitachi Cable Ltd Manufacture of gaalas epitaxial wafer
EP0455526A1 (en) * 1990-04-13 1991-11-06 Thomson-Csf Process for adaptation between two crystallized semiconductor materials, and semiconductor device
EP0735586A2 (en) * 1995-03-28 1996-10-02 Texas Instruments Incorporated Semi-conductor structures
US6087726A (en) * 1999-03-01 2000-07-11 Lsi Logic Corporation Metal interconnect stack for integrated circuit structure
US6114198A (en) * 1999-05-07 2000-09-05 Vanguard International Semiconductor Corporation Method for forming a high surface area capacitor electrode for DRAM applications

Also Published As

Publication number Publication date
AU2002247566A1 (en) 2003-06-10

Similar Documents

Publication Publication Date Title
AU718641B2 (en) Forming a crystalline semiconductor film on a glass substrate
US20060204776A1 (en) Structure and method of thermal stress compensation
US6822304B1 (en) Sputtered silicon for microstructures and microcavities
US20090134513A1 (en) Method and structures for fabricating mems devices on compliant layers
JPH07211709A (en) Formation of layer with reduced mechinical stress
US6037249A (en) Method for forming air gaps for advanced interconnect systems
DE102012209891A1 (en) A method for controlled removal of a semiconductor element layer from a base substrate
TW201318238A (en) Memory device and manufacturing method thereof
TWI281951B (en) Methods for the control of flatness and electron mobility of diamond coated silicon and structures formed thereby
WO2020188313A2 (en) Thermally conductive and protective coating for electronic device
JP5623708B2 (en) Method for manufacturing layered electronic device on flexible substrate and thin film electronic structure
AU2002247566B2 (en) Differential stress reduction in thin films
CA2467174C (en) Differential stress reduction in thin films
AU2005203476B2 (en) Formation of a crystalline thin film structure
Riege et al. Modeling of texture evolution in copper interconnects annealed in trenches
KR101288197B1 (en) Manufacturing method for flexible VLSI and flexible VLSI manufactured by the same
US8907433B2 (en) Thin film with improved temperature range
US7470462B2 (en) Method to control residual stress in a film structure and a system thereof
JP2866485B2 (en) Manufacturing method of semiconductor thin film element
Jeon et al. Properties of phosphorus-doped poly-SiGe films for microelectromechanical system applications
Suzuki Hemispherical-grained LPCVD-polysilicon films in use for MEMS applications
Knick Optimization of MEMS Actuator Driven by Shape Memory Alloy Thin Film Phase Change
KR102142042B1 (en) Fabrication method of reliable pressure sensors at higher temperature
EP3039704B1 (en) Rf mems electrodes with limited grain growth
JP2002075705A (en) Resistor substrate

Legal Events

Date Code Title Description
FGA Letters patent sealed or granted (standard patent)
MK14 Patent ceased section 143(a) (annual fees not paid) or expired