AU2001249665A1 - System having a configurable cache/sram memory - Google Patents

System having a configurable cache/sram memory

Info

Publication number
AU2001249665A1
AU2001249665A1 AU2001249665A AU4966501A AU2001249665A1 AU 2001249665 A1 AU2001249665 A1 AU 2001249665A1 AU 2001249665 A AU2001249665 A AU 2001249665A AU 4966501 A AU4966501 A AU 4966501A AU 2001249665 A1 AU2001249665 A1 AU 2001249665A1
Authority
AU
Australia
Prior art keywords
sram memory
configurable cache
configurable
cache
sram
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2001249665A
Other languages
English (en)
Inventor
Michael Allen
William C. Anderson
Lawrence A. Booth Jr.
Ravi Kolagotla
Hebbalalu S. Ramagopal
Moinul Syed
David B. Witt
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of AU2001249665A1 publication Critical patent/AU2001249665A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0855—Overlapped cache accessing, e.g. pipeline
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Multi Processors (AREA)
AU2001249665A 2000-03-31 2001-03-30 System having a configurable cache/sram memory Abandoned AU2001249665A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09541117 2000-03-31
US09/541,117 US6446181B1 (en) 2000-03-31 2000-03-31 System having a configurable cache/SRAM memory
PCT/US2001/010299 WO2001074134A2 (fr) 2000-03-31 2001-03-30 Systeme a memoire sram/cache configurable

Publications (1)

Publication Number Publication Date
AU2001249665A1 true AU2001249665A1 (en) 2001-10-15

Family

ID=24158241

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2001249665A Abandoned AU2001249665A1 (en) 2000-03-31 2001-03-30 System having a configurable cache/sram memory

Country Status (6)

Country Link
US (1) US6446181B1 (fr)
EP (2) EP1269328B1 (fr)
CN (1) CN1220150C (fr)
AU (1) AU2001249665A1 (fr)
TW (1) TWI243989B (fr)
WO (1) WO2001074134A2 (fr)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6868472B1 (en) * 1999-10-01 2005-03-15 Fujitsu Limited Method of Controlling and addressing a cache memory which acts as a random address memory to increase an access speed to a main memory
AU2001243463A1 (en) 2000-03-10 2001-09-24 Arc International Plc Memory interface and method of interfacing between functional entities
US6606684B1 (en) * 2000-03-31 2003-08-12 Intel Corporation Multi-tiered memory bank having different data buffer sizes with a programmable bank select
US7020736B1 (en) * 2000-12-18 2006-03-28 Redback Networks Inc. Method and apparatus for sharing memory space across mutliple processing units
US20040133745A1 (en) * 2002-10-28 2004-07-08 Quicksilver Technology, Inc. Adaptable datapath for a digital processing system
US20030046492A1 (en) * 2001-08-28 2003-03-06 International Business Machines Corporation, Armonk, New York Configurable memory array
US7330954B2 (en) * 2002-04-18 2008-02-12 Intel Corporation Storing information in one of at least two storage devices based on a storage parameter and an attribute of the storage devices
US6934865B2 (en) * 2002-07-09 2005-08-23 University Of Massachusetts Controlling a processor resource based on a compile-time prediction of number of instructions-per-cycle that will be executed across plural cycles by the processor
US7278136B2 (en) * 2002-07-09 2007-10-02 University Of Massachusetts Reducing processor energy consumption using compile-time information
US7493607B2 (en) 2002-07-09 2009-02-17 Bluerisc Inc. Statically speculative compilation and execution
JP4363081B2 (ja) 2003-05-22 2009-11-11 ソニー株式会社 メモリアクセス制御装置およびこれを有する演算システム
US20050114850A1 (en) 2003-10-29 2005-05-26 Saurabh Chheda Energy-focused re-compilation of executables and hardware mechanisms based on compiler-architecture interaction and compiler-inserted control
US7996671B2 (en) 2003-11-17 2011-08-09 Bluerisc Inc. Security of program executables and microprocessors based on compiler-architecture interaction
US8607209B2 (en) 2004-02-04 2013-12-10 Bluerisc Inc. Energy-focused compiler-assisted branch prediction
US7376791B2 (en) * 2005-04-06 2008-05-20 Mediatek Inc. Memory access systems and methods for configuring ways as cache or directly addressable memory
US20080201528A1 (en) * 2005-04-06 2008-08-21 Mediatek Inc. Memory access systems for configuring ways as cache or directly addressable memory
US7653785B2 (en) * 2005-06-22 2010-01-26 Lexmark International, Inc. Reconfigurable cache controller utilizing multiple ASIC SRAMS
US20080126766A1 (en) 2006-11-03 2008-05-29 Saurabh Chheda Securing microprocessors against information leakage and physical tampering
US8108621B2 (en) * 2009-05-27 2012-01-31 Via Technologies, Inc. Data cache with modified bit array
CN102541754A (zh) * 2010-12-27 2012-07-04 北京国睿中数科技股份有限公司 用于对存储器进行配置的***和方法

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4623990A (en) * 1984-10-31 1986-11-18 Advanced Micro Devices, Inc. Dual-port read/write RAM with single array
US5175841A (en) 1987-03-13 1992-12-29 Texas Instruments Incorporated Data processing device with multiple on-chip memory buses
GB2216307B (en) * 1988-03-01 1992-08-26 Ardent Computer Corp Vector register file
US5257359A (en) * 1989-02-08 1993-10-26 Hitachi Microsystems, Inc. Instruction cache buffer with program-flow control
US5539911A (en) * 1991-07-08 1996-07-23 Seiko Epson Corporation High-performance, superscalar-based computer system with out-of-order instruction execution
US5410669A (en) 1993-04-05 1995-04-25 Motorola, Inc. Data processor having a cache memory capable of being used as a linear ram bank
US5537576A (en) * 1993-06-23 1996-07-16 Dsp Semiconductors Ltd. Expandable memory for a digital signal processor including mapped first and second memory banks forming a continuous and contiguous address space
WO1998013763A2 (fr) 1996-09-25 1998-04-02 Philips Electronics N.V. Memoire cache a acces multiples avec detection de conflits d'adresse
US5966143A (en) * 1997-10-14 1999-10-12 Motorola, Inc. Data allocation into multiple memories for concurrent access
US5978889A (en) * 1997-11-05 1999-11-02 Timeplex, Inc. Multiple device data transfer utilizing a multiport memory with opposite oriented memory page rotation for transmission and reception
US6127843A (en) * 1997-12-22 2000-10-03 Vantis Corporation Dual port SRAM memory for run time use in FPGA integrated circuits
US6321318B1 (en) * 1997-12-31 2001-11-20 Texas Instruments Incorporated User-configurable on-chip program memory system
US6334175B1 (en) * 1998-07-22 2001-12-25 Ati Technologies, Inc. Switchable memory system and memory allocation method

Also Published As

Publication number Publication date
US6446181B1 (en) 2002-09-03
CN1429369A (zh) 2003-07-09
EP1269328A2 (fr) 2003-01-02
WO2001074134A3 (fr) 2002-05-23
EP1269328B1 (fr) 2015-06-03
CN1220150C (zh) 2005-09-21
EP2312447A1 (fr) 2011-04-20
WO2001074134A2 (fr) 2001-10-11
TWI243989B (en) 2005-11-21

Similar Documents

Publication Publication Date Title
AU2001249665A1 (en) System having a configurable cache/sram memory
AU2001285277A1 (en) Mechanism for completing messages in memory
AU2001275147A1 (en) Non-volatile cache
AU2002225643A1 (en) Foams having shape memory
EP1564749B8 (fr) Mémoire multiportes basée sur une DRAM
AU2002213123A1 (en) Reticle storage system
AU8210601A (en) Associative memory
AU2002344503A1 (en) A three-dimensional memory
GB2348024B (en) Cache memory systems
AU2001255591A1 (en) Storage shed
GB2365592B (en) L1 cache memory
AU2002215741A1 (en) Semen storage
AU2001240116A1 (en) Three dimensional optical memory storage
AU2120200A (en) Cache memory
AU7431901A (en) Coherence-free cache
AU2001250589A1 (en) Reduced size object headers
AU2001245894A1 (en) Storage efficient minimization logic
AUPR197400A0 (en) Data storage
EP1195719A3 (fr) Mémoire de rendu de volume
AU2001262263A1 (en) Line arrangement
AU2001280465A1 (en) Autocycle
AU2001232862A1 (en) A register having a ferromagnetic memory cells
AU2002239502A1 (en) Boundary addressable memory
AU2001264882A1 (en) Watchdog arrangement
AU2001294427A1 (en) Floating storage system