CN1220150C - 具有可配置的高速缓存/静态随机存取存储器的*** - Google Patents
具有可配置的高速缓存/静态随机存取存储器的*** Download PDFInfo
- Publication number
- CN1220150C CN1220150C CN01807691.2A CN01807691A CN1220150C CN 1220150 C CN1220150 C CN 1220150C CN 01807691 A CN01807691 A CN 01807691A CN 1220150 C CN1220150 C CN 1220150C
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- China
- Prior art keywords
- memory
- data
- core processor
- bus
- coupled
- Prior art date
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- Expired - Lifetime
Links
- 238000013461 design Methods 0.000 claims description 7
- 230000003068 static effect Effects 0.000 claims description 7
- 238000000605 extraction Methods 0.000 claims 1
- 230000008901 benefit Effects 0.000 description 5
- 238000012545 processing Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 238000010276 construction Methods 0.000 description 3
- 239000000284 extract Substances 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000002708 enhancing effect Effects 0.000 description 2
- 238000011156 evaluation Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 102100025682 Dystroglycan 1 Human genes 0.000 description 1
- 101000855983 Homo sapiens Dystroglycan 1 Proteins 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000012937 correction Methods 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000007334 memory performance Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000008520 organization Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 230000008569 process Effects 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
- G06F12/0855—Overlapped cache accessing, e.g. pipeline
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0893—Caches characterised by their organisation or structure
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Memory System Of A Hierarchy Structure (AREA)
- Multi Processors (AREA)
Abstract
Description
存储器配置 | 超级存储块A | 超级存储块B |
0 | 静态随机存储器 | 静态随机存储器 |
1 | 保留 | 保留 |
2 | 高速缓冲存储器 | 静态随机存储器 |
3 | 高速缓冲存储器 | 高速缓冲存储器 |
Claims (17)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/541,117 US6446181B1 (en) | 2000-03-31 | 2000-03-31 | System having a configurable cache/SRAM memory |
US09/541,117 | 2000-03-31 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1429369A CN1429369A (zh) | 2003-07-09 |
CN1220150C true CN1220150C (zh) | 2005-09-21 |
Family
ID=24158241
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN01807691.2A Expired - Lifetime CN1220150C (zh) | 2000-03-31 | 2001-03-30 | 具有可配置的高速缓存/静态随机存取存储器的*** |
Country Status (6)
Country | Link |
---|---|
US (1) | US6446181B1 (zh) |
EP (2) | EP1269328B1 (zh) |
CN (1) | CN1220150C (zh) |
AU (1) | AU2001249665A1 (zh) |
TW (1) | TWI243989B (zh) |
WO (1) | WO2001074134A2 (zh) |
Families Citing this family (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6868472B1 (en) * | 1999-10-01 | 2005-03-15 | Fujitsu Limited | Method of Controlling and addressing a cache memory which acts as a random address memory to increase an access speed to a main memory |
AU2001243463A1 (en) | 2000-03-10 | 2001-09-24 | Arc International Plc | Memory interface and method of interfacing between functional entities |
US6606684B1 (en) * | 2000-03-31 | 2003-08-12 | Intel Corporation | Multi-tiered memory bank having different data buffer sizes with a programmable bank select |
US7020736B1 (en) * | 2000-12-18 | 2006-03-28 | Redback Networks Inc. | Method and apparatus for sharing memory space across mutliple processing units |
US20040133745A1 (en) * | 2002-10-28 | 2004-07-08 | Quicksilver Technology, Inc. | Adaptable datapath for a digital processing system |
US20030046492A1 (en) * | 2001-08-28 | 2003-03-06 | International Business Machines Corporation, Armonk, New York | Configurable memory array |
US7330954B2 (en) * | 2002-04-18 | 2008-02-12 | Intel Corporation | Storing information in one of at least two storage devices based on a storage parameter and an attribute of the storage devices |
US6934865B2 (en) * | 2002-07-09 | 2005-08-23 | University Of Massachusetts | Controlling a processor resource based on a compile-time prediction of number of instructions-per-cycle that will be executed across plural cycles by the processor |
US7278136B2 (en) * | 2002-07-09 | 2007-10-02 | University Of Massachusetts | Reducing processor energy consumption using compile-time information |
US7493607B2 (en) | 2002-07-09 | 2009-02-17 | Bluerisc Inc. | Statically speculative compilation and execution |
JP4363081B2 (ja) | 2003-05-22 | 2009-11-11 | ソニー株式会社 | メモリアクセス制御装置およびこれを有する演算システム |
US20050114850A1 (en) | 2003-10-29 | 2005-05-26 | Saurabh Chheda | Energy-focused re-compilation of executables and hardware mechanisms based on compiler-architecture interaction and compiler-inserted control |
US7996671B2 (en) | 2003-11-17 | 2011-08-09 | Bluerisc Inc. | Security of program executables and microprocessors based on compiler-architecture interaction |
US8607209B2 (en) | 2004-02-04 | 2013-12-10 | Bluerisc Inc. | Energy-focused compiler-assisted branch prediction |
US7376791B2 (en) * | 2005-04-06 | 2008-05-20 | Mediatek Inc. | Memory access systems and methods for configuring ways as cache or directly addressable memory |
US20080201528A1 (en) * | 2005-04-06 | 2008-08-21 | Mediatek Inc. | Memory access systems for configuring ways as cache or directly addressable memory |
US7653785B2 (en) * | 2005-06-22 | 2010-01-26 | Lexmark International, Inc. | Reconfigurable cache controller utilizing multiple ASIC SRAMS |
US20080126766A1 (en) | 2006-11-03 | 2008-05-29 | Saurabh Chheda | Securing microprocessors against information leakage and physical tampering |
US8108621B2 (en) * | 2009-05-27 | 2012-01-31 | Via Technologies, Inc. | Data cache with modified bit array |
CN102541754A (zh) * | 2010-12-27 | 2012-07-04 | 北京国睿中数科技股份有限公司 | 用于对存储器进行配置的***和方法 |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4623990A (en) * | 1984-10-31 | 1986-11-18 | Advanced Micro Devices, Inc. | Dual-port read/write RAM with single array |
US5175841A (en) | 1987-03-13 | 1992-12-29 | Texas Instruments Incorporated | Data processing device with multiple on-chip memory buses |
GB2216307B (en) * | 1988-03-01 | 1992-08-26 | Ardent Computer Corp | Vector register file |
US5257359A (en) * | 1989-02-08 | 1993-10-26 | Hitachi Microsystems, Inc. | Instruction cache buffer with program-flow control |
US5539911A (en) * | 1991-07-08 | 1996-07-23 | Seiko Epson Corporation | High-performance, superscalar-based computer system with out-of-order instruction execution |
US5410669A (en) | 1993-04-05 | 1995-04-25 | Motorola, Inc. | Data processor having a cache memory capable of being used as a linear ram bank |
US5537576A (en) * | 1993-06-23 | 1996-07-16 | Dsp Semiconductors Ltd. | Expandable memory for a digital signal processor including mapped first and second memory banks forming a continuous and contiguous address space |
WO1998013763A2 (en) | 1996-09-25 | 1998-04-02 | Philips Electronics N.V. | Multiport cache memory with address conflict detection |
US5966143A (en) * | 1997-10-14 | 1999-10-12 | Motorola, Inc. | Data allocation into multiple memories for concurrent access |
US5978889A (en) * | 1997-11-05 | 1999-11-02 | Timeplex, Inc. | Multiple device data transfer utilizing a multiport memory with opposite oriented memory page rotation for transmission and reception |
US6127843A (en) * | 1997-12-22 | 2000-10-03 | Vantis Corporation | Dual port SRAM memory for run time use in FPGA integrated circuits |
US6321318B1 (en) * | 1997-12-31 | 2001-11-20 | Texas Instruments Incorporated | User-configurable on-chip program memory system |
US6334175B1 (en) * | 1998-07-22 | 2001-12-25 | Ati Technologies, Inc. | Switchable memory system and memory allocation method |
-
2000
- 2000-03-31 US US09/541,117 patent/US6446181B1/en not_active Expired - Lifetime
-
2001
- 2001-03-30 WO PCT/US2001/010299 patent/WO2001074134A2/en active Application Filing
- 2001-03-30 EP EP01922915.2A patent/EP1269328B1/en not_active Expired - Lifetime
- 2001-03-30 TW TW090107589A patent/TWI243989B/zh not_active IP Right Cessation
- 2001-03-30 AU AU2001249665A patent/AU2001249665A1/en not_active Abandoned
- 2001-03-30 EP EP10184822A patent/EP2312447A1/en not_active Withdrawn
- 2001-03-30 CN CN01807691.2A patent/CN1220150C/zh not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
US6446181B1 (en) | 2002-09-03 |
CN1429369A (zh) | 2003-07-09 |
EP1269328A2 (en) | 2003-01-02 |
WO2001074134A3 (en) | 2002-05-23 |
EP1269328B1 (en) | 2015-06-03 |
EP2312447A1 (en) | 2011-04-20 |
AU2001249665A1 (en) | 2001-10-15 |
WO2001074134A2 (en) | 2001-10-11 |
TWI243989B (en) | 2005-11-21 |
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C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
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C41 | Transfer of patent application or patent right or utility model | ||
TR01 | Transfer of patent right |
Effective date of registration: 20081226 Address after: Massachusetts, USA Patentee after: ANALOG DEVICES, Inc. Address before: California, USA Co-patentee before: ANALOG DEVICES, Inc. Patentee before: INTEL Corp. |
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ASS | Succession or assignment of patent right |
Owner name: ANALOG DEVICES, INC. Free format text: FORMER OWNER: INTEL CORP Effective date: 20081226 |
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CX01 | Expiry of patent term |
Granted publication date: 20050921 |
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CX01 | Expiry of patent term |