ATE80750T1 - Aneinandergefuegte kontaktstruktur mit vermindertem flaechenbedarf. - Google Patents

Aneinandergefuegte kontaktstruktur mit vermindertem flaechenbedarf.

Info

Publication number
ATE80750T1
ATE80750T1 AT87310857T AT87310857T ATE80750T1 AT E80750 T1 ATE80750 T1 AT E80750T1 AT 87310857 T AT87310857 T AT 87310857T AT 87310857 T AT87310857 T AT 87310857T AT E80750 T1 ATE80750 T1 AT E80750T1
Authority
AT
Austria
Prior art keywords
polysilicon
layers
doped silicon
silicon region
etch
Prior art date
Application number
AT87310857T
Other languages
English (en)
Inventor
Craig S Sander
Richard K Klein
Tat C Choi
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Application granted granted Critical
Publication of ATE80750T1 publication Critical patent/ATE80750T1/de

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)
  • Coupling Device And Connection With Printed Circuit (AREA)
  • Air Bags (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Installation Of Indoor Wiring (AREA)
  • Multi-Conductor Connections (AREA)
  • Connector Housings Or Holding Contact Members (AREA)
AT87310857T 1986-12-17 1987-12-10 Aneinandergefuegte kontaktstruktur mit vermindertem flaechenbedarf. ATE80750T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US94415086A 1986-12-17 1986-12-17
EP87310857A EP0272051B1 (de) 1986-12-17 1987-12-10 Aneinandergefügte Kontaktstruktur mit vermindertem Flächenbedarf

Publications (1)

Publication Number Publication Date
ATE80750T1 true ATE80750T1 (de) 1992-10-15

Family

ID=25480890

Family Applications (1)

Application Number Title Priority Date Filing Date
AT87310857T ATE80750T1 (de) 1986-12-17 1987-12-10 Aneinandergefuegte kontaktstruktur mit vermindertem flaechenbedarf.

Country Status (6)

Country Link
EP (1) EP0272051B1 (de)
JP (1) JPH0752751B2 (de)
AT (1) ATE80750T1 (de)
DE (1) DE3781778T2 (de)
ES (1) ES2046209T3 (de)
GR (1) GR3005727T3 (de)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02202054A (ja) * 1989-01-31 1990-08-10 Texas Instr Japan Ltd 半導体装置及びその製造方法
NL9100094A (nl) * 1991-01-21 1992-08-17 Koninkl Philips Electronics Nv Halfgeleiderinrichting en werkwijze ter vervaardiging van een dergelijke halfgeleiderinrichting.
GB9219268D0 (en) * 1992-09-11 1992-10-28 Inmos Ltd Semiconductor device incorporating a contact and manufacture thereof
WO2003023847A2 (en) * 2001-09-13 2003-03-20 Koninklijke Philips Electronics N.V. Integrated circuit, portable device and method for manufacturing an integrated circuit
DE102008045037B4 (de) * 2008-08-29 2010-12-30 Advanced Micro Devices, Inc., Sunnyvale Statischer RAM-Zellenaufbau und Mehrfachkontaktschema zum Anschluss von Doppelkanaltransistoren

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5842257A (ja) * 1981-09-07 1983-03-11 Toshiba Corp 半導体装置
JPS59171140A (ja) * 1983-03-17 1984-09-27 Nec Corp 半導体装置
US4663831A (en) * 1985-10-08 1987-05-12 Motorola, Inc. Method of forming transistors with poly-sidewall contacts utilizing deposition of polycrystalline and insulating layers combined with selective etching and oxidation of said layers

Also Published As

Publication number Publication date
GR3005727T3 (de) 1993-06-07
EP0272051A2 (de) 1988-06-22
JPS63164359A (ja) 1988-07-07
JPH0752751B2 (ja) 1995-06-05
DE3781778D1 (de) 1992-10-22
EP0272051B1 (de) 1992-09-16
EP0272051A3 (en) 1989-02-01
DE3781778T2 (de) 1993-01-28
ES2046209T3 (es) 1995-04-01

Similar Documents

Publication Publication Date Title
JPS6421967A (en) Semiconductor device and manufacture thereof
EP0272453A3 (de) Vereinigte bipolare/CMOS Technologie unter Verwendung eines elektrisch aktiven Grabens
EP0052989A3 (de) Verfahren zum Herstellen eines Halbleiterbauelementes
WO1986003620A3 (en) Process for forming diffusion regions in a semiconductor substrate
JPS5498521A (en) Solidstate pick up element
EP0029552A3 (de) Verfahren zur Herstellung einer Halbleitervorrichtung
ATE80750T1 (de) Aneinandergefuegte kontaktstruktur mit vermindertem flaechenbedarf.
JPS6481262A (en) Active matrix substrate
JPS57201070A (en) Semiconductor device
JPS5691470A (en) Semiconductor
JPS6418253A (en) Semiconductor memory cell and its manufacture
EP0078890A3 (de) Verfahren zur Herstellung einer dielektrisch isolierten CMOS-Halbleiteranordnung mit Isolationsnuten
JPS57211775A (en) Semiconductor device and manufacture thereof
JPS5769778A (en) Semiconductor device
JPS55107229A (en) Method of manufacturing semiconductor device
JPS54143076A (en) Semiconductor device and its manufacture
JPS55162270A (en) Semiconductor device
JPS6419770A (en) Semiconductor device
JPS55132062A (en) Semiconductor memory device
JPS6489370A (en) Semiconductor storage device
JPS56165360A (en) Manufacture of semiconductor device
JPS6449252A (en) Manufacture of groove-shaped capacitor
JPS6421965A (en) Mos transistor
JPS5685835A (en) Manufacture of semiconductor device
JPS5587480A (en) Insulated gate type field effect transistor and manufacture thereof

Legal Events

Date Code Title Description
UEP Publication of translation of european patent specification
REN Ceased due to non-payment of the annual fee