ATE539446T1 - Herstellung von einem abnehmbaren halbleitersubstrat und einem halbleiterelement - Google Patents
Herstellung von einem abnehmbaren halbleitersubstrat und einem halbleiterelementInfo
- Publication number
- ATE539446T1 ATE539446T1 AT03780289T AT03780289T ATE539446T1 AT E539446 T1 ATE539446 T1 AT E539446T1 AT 03780289 T AT03780289 T AT 03780289T AT 03780289 T AT03780289 T AT 03780289T AT E539446 T1 ATE539446 T1 AT E539446T1
- Authority
- AT
- Austria
- Prior art keywords
- substrate
- layer
- face
- semiconductor
- production
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Recrystallisation Techniques (AREA)
- Semiconductor Memories (AREA)
- Bipolar Transistors (AREA)
- Semiconductor Integrated Circuits (AREA)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR0212443A FR2845517B1 (fr) | 2002-10-07 | 2002-10-07 | Realisation d'un substrat semiconducteur demontable et obtention d'un element semiconducteur |
FR0350130A FR2845518B1 (fr) | 2002-10-07 | 2003-04-25 | Realisation d'un substrat semiconducteur demontable et obtention d'un element semiconducteur |
PCT/FR2003/050077 WO2004032183A2 (fr) | 2002-10-07 | 2003-10-03 | Realisation d'un substrat semiconducteur demontable et obtention d'un element semiconducteur. |
Publications (1)
Publication Number | Publication Date |
---|---|
ATE539446T1 true ATE539446T1 (de) | 2012-01-15 |
Family
ID=32031847
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
AT03780289T ATE539446T1 (de) | 2002-10-07 | 2003-10-03 | Herstellung von einem abnehmbaren halbleitersubstrat und einem halbleiterelement |
Country Status (6)
Country | Link |
---|---|
US (1) | US7238598B2 (de) |
EP (1) | EP1550158B1 (de) |
JP (1) | JP4777774B2 (de) |
AT (1) | ATE539446T1 (de) |
FR (1) | FR2845518B1 (de) |
WO (1) | WO2004032183A2 (de) |
Families Citing this family (23)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4277481B2 (ja) * | 2002-05-08 | 2009-06-10 | 日本電気株式会社 | 半導体基板の製造方法、半導体装置の製造方法 |
JP2006270000A (ja) * | 2005-03-25 | 2006-10-05 | Sumco Corp | 歪Si−SOI基板の製造方法および該方法により製造された歪Si−SOI基板 |
FR2898431B1 (fr) * | 2006-03-13 | 2008-07-25 | Soitec Silicon On Insulator | Procede de fabrication de film mince |
FR2913968B1 (fr) * | 2007-03-23 | 2009-06-12 | Soitec Silicon On Insulator | Procede de realisation de membranes autoportees. |
US7856212B2 (en) * | 2007-08-07 | 2010-12-21 | Intel Corporation | Millimeter-wave phase-locked loop with injection-locked frequency divider using quarter-wavelength transmission line and method of calibration |
US7977221B2 (en) * | 2007-10-05 | 2011-07-12 | Sumco Corporation | Method for producing strained Si-SOI substrate and strained Si-SOI substrate produced by the same |
US20090124038A1 (en) * | 2007-11-14 | 2009-05-14 | Mark Ewing Tuttle | Imager device, camera, and method of manufacturing a back side illuminated imager |
US20090212397A1 (en) * | 2008-02-22 | 2009-08-27 | Mark Ewing Tuttle | Ultrathin integrated circuit and method of manufacturing an ultrathin integrated circuit |
JP5347345B2 (ja) * | 2008-06-16 | 2013-11-20 | 旭硝子株式会社 | 導電性マイエナイト型化合物の製造方法 |
US20100102419A1 (en) * | 2008-10-28 | 2010-04-29 | Eric Ting-Shan Pan | Epitaxy-Level Packaging (ELP) System |
US7905197B2 (en) * | 2008-10-28 | 2011-03-15 | Athenaeum, Llc | Apparatus for making epitaxial film |
WO2010062659A1 (en) * | 2008-10-28 | 2010-06-03 | Athenaeum, Llc | Epitaxial film assembly system & method |
US7967936B2 (en) * | 2008-12-15 | 2011-06-28 | Twin Creeks Technologies, Inc. | Methods of transferring a lamina to a receiver element |
US7927975B2 (en) | 2009-02-04 | 2011-04-19 | Micron Technology, Inc. | Semiconductor material manufacture |
JP6053756B2 (ja) * | 2011-04-11 | 2016-12-27 | エヌディーエスユー リサーチ ファウンデーション | レーザで促進される、分離した部品の選択的な転写 |
US9023729B2 (en) * | 2011-12-23 | 2015-05-05 | Athenaeum, Llc | Epitaxy level packaging |
US9184094B1 (en) * | 2012-01-26 | 2015-11-10 | Skorpios Technologies, Inc. | Method and system for forming a membrane over a cavity |
US9481566B2 (en) | 2012-07-31 | 2016-11-01 | Soitec | Methods of forming semiconductor structures including MEMS devices and integrated circuits on opposing sides of substrates, and related structures and devices |
JP6757953B2 (ja) * | 2016-08-09 | 2020-09-23 | 学校法人 名古屋電気学園 | 表面加工方法、構造体の製造方法 |
CN106896410B (zh) * | 2017-03-09 | 2019-08-23 | 成都理工大学 | 利用声波测井资料解释岩石的变形模量和脆性指数的方法 |
FR3073082B1 (fr) * | 2017-10-31 | 2019-10-11 | Soitec | Procede de fabrication d'un film sur un support presentant une surface non plane |
FR3073083B1 (fr) * | 2017-10-31 | 2019-10-11 | Soitec | Procede de fabrication d'un film sur un feuillet flexible |
FR3094559B1 (fr) | 2019-03-29 | 2024-06-21 | Soitec Silicon On Insulator | Procédé de transfert de paves d’un substrat donneur sur un substrat receveur |
Family Cites Families (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2748851B1 (fr) * | 1996-05-15 | 1998-08-07 | Commissariat Energie Atomique | Procede de realisation d'une couche mince de materiau semiconducteur |
US5877070A (en) * | 1997-05-31 | 1999-03-02 | Max-Planck Society | Method for the transfer of thin layers of monocrystalline material to a desirable substrate |
JP3412470B2 (ja) * | 1997-09-04 | 2003-06-03 | 三菱住友シリコン株式会社 | Soi基板の製造方法 |
EP0926709A3 (de) * | 1997-12-26 | 2000-08-30 | Canon Kabushiki Kaisha | Herstellungsmethode einer SOI Struktur |
JPH11233449A (ja) * | 1998-02-13 | 1999-08-27 | Denso Corp | 半導体基板の製造方法 |
JP3697106B2 (ja) * | 1998-05-15 | 2005-09-21 | キヤノン株式会社 | 半導体基板の作製方法及び半導体薄膜の作製方法 |
US6291326B1 (en) * | 1998-06-23 | 2001-09-18 | Silicon Genesis Corporation | Pre-semiconductor process implant and post-process film separation |
FR2784795B1 (fr) * | 1998-10-16 | 2000-12-01 | Commissariat Energie Atomique | Structure comportant une couche mince de materiau composee de zones conductrices et de zones isolantes et procede de fabrication d'une telle structure |
US6255195B1 (en) * | 1999-02-22 | 2001-07-03 | Intersil Corporation | Method for forming a bonded substrate containing a planar intrinsic gettering zone and substrate formed by said method |
US6323108B1 (en) * | 1999-07-27 | 2001-11-27 | The United States Of America As Represented By The Secretary Of The Navy | Fabrication ultra-thin bonded semiconductor layers |
FR2797347B1 (fr) * | 1999-08-04 | 2001-11-23 | Commissariat Energie Atomique | Procede de transfert d'une couche mince comportant une etape de surfragililisation |
JP4450126B2 (ja) * | 2000-01-21 | 2010-04-14 | 日新電機株式会社 | シリコン系結晶薄膜の形成方法 |
TW452866B (en) * | 2000-02-25 | 2001-09-01 | Lee Tien Hsi | Manufacturing method of thin film on a substrate |
FR2809867B1 (fr) * | 2000-05-30 | 2003-10-24 | Commissariat Energie Atomique | Substrat fragilise et procede de fabrication d'un tel substrat |
FR2811807B1 (fr) * | 2000-07-12 | 2003-07-04 | Commissariat Energie Atomique | Procede de decoupage d'un bloc de materiau et de formation d'un film mince |
FR2816445B1 (fr) * | 2000-11-06 | 2003-07-25 | Commissariat Energie Atomique | Procede de fabrication d'une structure empilee comprenant une couche mince adherant a un substrat cible |
US20020187619A1 (en) * | 2001-05-04 | 2002-12-12 | International Business Machines Corporation | Gettering process for bonded SOI wafers |
-
2003
- 2003-04-25 FR FR0350130A patent/FR2845518B1/fr not_active Expired - Fee Related
- 2003-10-03 JP JP2005500039A patent/JP4777774B2/ja not_active Expired - Fee Related
- 2003-10-03 AT AT03780289T patent/ATE539446T1/de active
- 2003-10-03 EP EP03780289A patent/EP1550158B1/de not_active Expired - Lifetime
- 2003-10-03 WO PCT/FR2003/050077 patent/WO2004032183A2/fr active Application Filing
- 2003-10-03 US US10/530,640 patent/US7238598B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JP2006502593A (ja) | 2006-01-19 |
WO2004032183A2 (fr) | 2004-04-15 |
JP4777774B2 (ja) | 2011-09-21 |
EP1550158A2 (de) | 2005-07-06 |
EP1550158B1 (de) | 2011-12-28 |
US7238598B2 (en) | 2007-07-03 |
US20060019476A1 (en) | 2006-01-26 |
WO2004032183A3 (fr) | 2004-07-29 |
FR2845518B1 (fr) | 2005-10-14 |
FR2845518A1 (fr) | 2004-04-09 |
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