ATE504065T1 - Minderung der lesestörungen in nicht-flüchtigen speichern - Google Patents
Minderung der lesestörungen in nicht-flüchtigen speichernInfo
- Publication number
- ATE504065T1 ATE504065T1 AT06844753T AT06844753T ATE504065T1 AT E504065 T1 ATE504065 T1 AT E504065T1 AT 06844753 T AT06844753 T AT 06844753T AT 06844753 T AT06844753 T AT 06844753T AT E504065 T1 ATE504065 T1 AT E504065T1
- Authority
- AT
- Austria
- Prior art keywords
- volatile memory
- read disturb
- reducing reading
- reducing
- source side
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/26—Sensing or reading circuits; Data output circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
- G11C11/5642—Sensing or reading circuits; Data output circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/08—Address circuits; Decoders; Word-line control circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
- G11C16/3427—Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3436—Arrangements for verifying correct programming or erasure
- G11C16/3454—Arrangements for verifying correct programming or for detecting overprogrammed cells
- G11C16/3459—Circuits or methods to verify correct programming of nonvolatile memory cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
- G11C2211/564—Miscellaneous aspects
- G11C2211/5642—Multilevel memory with buffers, latches, registers at input or output
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Read Only Memory (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
- Micro-Organisms Or Cultivation Processes Thereof (AREA)
- Debugging And Monitoring (AREA)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/295,776 US7349258B2 (en) | 2005-12-06 | 2005-12-06 | Reducing read disturb for non-volatile storage |
US11/296,087 US7262994B2 (en) | 2005-12-06 | 2005-12-06 | System for reducing read disturb for non-volatile storage |
PCT/US2006/046126 WO2007067447A1 (en) | 2005-12-06 | 2006-11-30 | Reducing read disturb for non-volatile storage |
Publications (1)
Publication Number | Publication Date |
---|---|
ATE504065T1 true ATE504065T1 (de) | 2011-04-15 |
Family
ID=37836814
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
AT06844753T ATE504065T1 (de) | 2005-12-06 | 2006-11-30 | Minderung der lesestörungen in nicht-flüchtigen speichern |
Country Status (7)
Country | Link |
---|---|
EP (2) | EP1958206B1 (de) |
JP (1) | JP4960378B2 (de) |
KR (1) | KR100948200B1 (de) |
AT (1) | ATE504065T1 (de) |
DE (1) | DE602006021058D1 (de) |
TW (1) | TWI315524B (de) |
WO (1) | WO2007067447A1 (de) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101301140B1 (ko) * | 2007-07-13 | 2013-09-03 | 삼성전자주식회사 | 읽기 디스터브가 방지되는 불휘발성 반도체 메모리 장치 및그것의 읽기 방법 |
KR101001449B1 (ko) * | 2009-04-14 | 2010-12-14 | 주식회사 하이닉스반도체 | 불휘발성 소자의 독출 동작 방법 |
JP5044624B2 (ja) * | 2009-09-25 | 2012-10-10 | 株式会社東芝 | 不揮発性半導体記憶装置 |
WO2012082880A1 (en) * | 2010-12-14 | 2012-06-21 | University Of Massachusetts | Methods and systems for low-power storage |
JP5385435B1 (ja) * | 2012-07-18 | 2014-01-08 | 力晶科技股▲ふん▼有限公司 | 不揮発性半導体記憶装置とその読み出し方法 |
KR102067755B1 (ko) * | 2013-02-12 | 2020-01-17 | 삼성전자주식회사 | 불휘발성 메모리 장치 및 그것의 제어 방법 |
Family Cites Families (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR960002006B1 (ko) | 1991-03-12 | 1996-02-09 | 가부시끼가이샤 도시바 | 2개의 기준 레벨을 사용하는 기록 검증 제어기를 갖는 전기적으로 소거 가능하고 프로그램 가능한 불휘발성 메모리 장치 |
US6222762B1 (en) | 1992-01-14 | 2001-04-24 | Sandisk Corporation | Multi-state memory |
US5555204A (en) | 1993-06-29 | 1996-09-10 | Kabushiki Kaisha Toshiba | Non-volatile semiconductor memory device |
KR0169267B1 (ko) | 1993-09-21 | 1999-02-01 | 사토 후미오 | 불휘발성 반도체 기억장치 |
JPH09251791A (ja) * | 1996-03-18 | 1997-09-22 | Toshiba Corp | 不揮発性半導体記憶装置 |
US5903495A (en) | 1996-03-18 | 1999-05-11 | Kabushiki Kaisha Toshiba | Semiconductor device and memory system |
JP3679970B2 (ja) * | 2000-03-28 | 2005-08-03 | 株式会社東芝 | 不揮発性半導体記憶装置及びその製造方法 |
JP3829088B2 (ja) * | 2001-03-29 | 2006-10-04 | 株式会社東芝 | 半導体記憶装置 |
US6522580B2 (en) | 2001-06-27 | 2003-02-18 | Sandisk Corporation | Operating techniques for reducing effects of coupling between storage elements of a non-volatile memory operated in multiple data states |
US6456528B1 (en) | 2001-09-17 | 2002-09-24 | Sandisk Corporation | Selective operation of a multi-state non-volatile memory system in a binary mode |
US6657891B1 (en) | 2002-11-29 | 2003-12-02 | Kabushiki Kaisha Toshiba | Semiconductor memory device for storing multivalued data |
US6859397B2 (en) | 2003-03-05 | 2005-02-22 | Sandisk Corporation | Source side self boosting technique for non-volatile memory |
JP3913704B2 (ja) | 2003-04-22 | 2007-05-09 | 株式会社東芝 | 不揮発性半導体記憶装置及びこれを用いた電子装置 |
US7237074B2 (en) | 2003-06-13 | 2007-06-26 | Sandisk Corporation | Tracking cells for a memory system |
US6917542B2 (en) | 2003-07-29 | 2005-07-12 | Sandisk Corporation | Detecting over programmed memory |
KR100515060B1 (ko) | 2003-08-13 | 2005-09-14 | 삼성전자주식회사 | 비트 라인의 프리차지 레벨을 일정하게 유지하는 불휘발성반도체 메모리 장치 |
KR100630535B1 (ko) * | 2004-03-23 | 2006-09-29 | 에스티마이크로일렉트로닉스 엔.브이. | 멀티 레벨 낸드 플래시 메모리 셀의 독출 방법 및 회로 |
US7120051B2 (en) | 2004-12-14 | 2006-10-10 | Sandisk Corporation | Pipelined programming of non-volatile memories using early data |
-
2006
- 2006-11-30 EP EP06844753A patent/EP1958206B1/de active Active
- 2006-11-30 DE DE602006021058T patent/DE602006021058D1/de active Active
- 2006-11-30 WO PCT/US2006/046126 patent/WO2007067447A1/en active Application Filing
- 2006-11-30 AT AT06844753T patent/ATE504065T1/de not_active IP Right Cessation
- 2006-11-30 EP EP10007990.4A patent/EP2256748B1/de active Active
- 2006-11-30 JP JP2008544399A patent/JP4960378B2/ja active Active
- 2006-11-30 KR KR1020087016534A patent/KR100948200B1/ko active IP Right Grant
- 2006-12-05 TW TW095145185A patent/TWI315524B/zh not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
JP4960378B2 (ja) | 2012-06-27 |
KR100948200B1 (ko) | 2010-03-17 |
KR20080080621A (ko) | 2008-09-04 |
EP1958206A1 (de) | 2008-08-20 |
EP1958206B1 (de) | 2011-03-30 |
JP2009518774A (ja) | 2009-05-07 |
DE602006021058D1 (de) | 2011-05-12 |
WO2007067447A1 (en) | 2007-06-14 |
TWI315524B (en) | 2009-10-01 |
EP2256748B1 (de) | 2013-09-11 |
TW200741719A (en) | 2007-11-01 |
EP2256748A1 (de) | 2010-12-01 |
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Legal Events
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RER | Ceased as to paragraph 5 lit. 3 law introducing patent treaties |