WO2012082880A1

WO2012082880A1 - Methods and systems for low-power storage

Info

Publication number: WO2012082880A1
Application number: PCT/US2011/064880
Authority: WO
Inventors: Kevin E. Fu; Erik G. Learned-Miller; Mastooreh Salajegheh
Original assignee: University Of Massachusetts
Priority date: 2010-12-14
Filing date: 2011-12-14
Publication date: 2012-06-21

Abstract

Technologies are provided herein for improving the reliability of storage in non-volatile memories at operationally unreliable voltages. A method includes supplying an operating voltage below a recommended minimum voltage to the computing device having an on-chip flash memory, and executing an improved reliability software-based algorithm that repeatedly writes a data value in the on-chip non-volatile memory. According to one aspect, the data value is repeatedly written at a particular memory location in the flash memory up to a predetermined number of writing operations. According to another aspect, the data value is written to a number of predetermined locations in the non-volatile memory. The written data values are then read as corresponding readback values, and a bitwise logical operation is performed on the readback values to determine a final readback value, which is then read as the final readback value.

Description

METHODS AND SYSTEMS FOR LOW-POWER STORAGE

BACKGROUND

These teachings relate to methods for reducing power consumption of energy-limited devices containing non-volatile memory. In one instance, the teachings relate to methods for reducing power consumption of devices whose flash memory shares the same power rail as their central processing unit (CPU),

Recent years have witnessed a proliferation of low-power embedded devices, many of which use on-chip flash memory for storage (as opposed to flash memory elsewhere on a printed circuit board). For example, microcontrollers typically include 128 bytes to 10 Kbytes of on- chip flash memory. However, writing to flash memory is an energy-intensive operation because of the fundamental behavior of floating gate transistors. An ideal microcontroller would consume energy that varies linearly with the number of flash writes within a workload. State of the art, ultra low-power microcontrollers of this variety require the entire chip to operate on a supply voltage that is significantly higher than what the CPU portion of the microcontroller requires— essentially a large safety margin to eliminate all errors with high probability. The large safety margins result in wasted energy. Present-day technology such as low-power hardware or fast error correction codes do not address this energy wasted by safety margins. The wasted energy is a result of a mismatch between the reliability needed by software and the reliability provided by the hardware. That is, software could run on significantly less energy by tuning the safety margins dynamically to avoid over-provisioning power.

Current embedded systems address the voltage limitations of flash memory in one of the following ways:

i) A system can choose a minimum- voltage threshold sufficiently high that flash memory is guaranteed to function reliably. This is the most common choice for embedded systems with on-chip flash memory, but it sacrifices energy for correctness. For example, the TI MSP430F2131 microcontroller consumes up to 50% less power in active mode when operating at 1.8 V instead of its onboard flash memory's specified minimum of 2.2 V.

ii) Because software cannot easily tune its voltage at run-time (most voltage supervisors and regulators are set to a small number of discrete voltages, and microcontrollers of the same part number vary in their tolerance to reduced voltage, necessitating device-specific tuning of components), a system can choose an operating voltage below the flash memory's minimum specified voltage, resulting in a longer lifetime for a fixed amount of energy by avoiding flash memory usage. This choice forces the system to outsource storage (e.g., via a network interface such as wireless radio) if it demands reliable non- volatile memory. Such an approach, however, raises privacy as well as performance concerns. An example of a system that takes this route is the Intel WISP, a batteryless radio frequency identification (RFID) tag that sets its operating voltage to 1.8 V— below its onboard flash memory's 2.2V specified minimum— to save power. The microcontroller documentation states that writes to the flash memory will be unpredictable at this low voltage. As a result, Intel was unable to make the WISP tag write to flash memory at all when the tag relies on harvested energy. Most of the flash error correction codes are designed for NA D flash memories. The previously developed techniques neither consider the asymmetry of errors in low voltage flash memories nor consider the resource limitations of low power embedded devices.

Jiang et al. suggested several error correction codes for Multi-Level Cell flash memory, Zemor and Cohen introduced error correcting codes for flash memory that are able to correct up to one error when the flash memory is given enough voltage. Another conventional application detects and corrects errors in flash memory using hardware modification and targets powerful computing machines.

Yet another conventional application detects (but does not correct) 2-bit errors and can detect and correct 1-bit errors for each 256 bytes and targets NAND flash memory. A further conventional application provides results specific to Multi-Bit per Cell (or multi-level cells).

There is a need for methods and systems that detect and correct errors in flash memories, particularly in on-chip flash memories, due to low voltages. There is also a need for methods and systems that detect and correct errors in flash memories and do not require a change in hardware.

BRIEF SUMMARY

Technologies are provided herein for improving the reliability of storage in non-volatile memories at operationally unreliable voltages. For instance, the technology allows a chip to operate at voltages where the hardware was not designed to guarantee reliability of the nonvolatile memory. In particular, by implementing the methods and systems disclosed herein, the reliability of storage in on-chip flash memories at operationally unreliable voltages, such as voltages below the recommended minimum operational voltage, can be improved by running one or more various software-based algorithms, including but not limited to, algorithms related to in- place writes, multiple-place writes, and slow writes.

In one embodiment of the present disclosure, a method for improving the reliability of storage in non- volatile memories at operationally unreliable voltages includes supplying an operating voltage below a recommended minimum voltage to the computing device having an on-chip memory, and executing an improved reliability algorithm that repeatedly writes a data value in the on-chip memory. In one aspect, the data value is repeatedly written at a particular memory location in the flash memory up to a predetermined number of writing operations. In another aspect, the data value is written to a number of predetermined locations in the memory. The written data values are then read as corresponding readback values, and a bitwise logical operation is performed on the readback values to determine a final readback value, which is then read as the final readback value.

In another embodiment, a system comprises a processor, a non-volatile memory, and a computer readable medium having computer executable instructions stored thereon, which when executed by the processor, cause the processor to repeatedly write a data value in the non- volatile memory.

In yet another embodiment, a computer-readable storage medium having computer- executable instructions, which when executed by a computer, cause the computer to repeatedly write a data value at a particular memory location in a non-volatile memory up to a

predetermined number of writing operations.

It should be noted that the above disclosed embodiments can be used in combination with one another and the resulting embodiments are within the scope of the present disclosure.

Embodiments of the system of these teachings include a processor and a computer usable medium having computer readable code embodied therein that causes the processor to execute the embodiments of the present disclosure.

Also within the scope of the present disclosure are embodiments of articles of manufacture including computer readable media having computer readable code embodied therein that cause the processor to execute embodiments of the present disclosure. For a better understanding of the present disclosure, together with other and further objects thereof, reference is made to the accompanying drawings and detailed description and its scope will be pointed out in the appended claims.

BRIEF DESCRIPTION OF THE DRAWINGS

Fig. 1 is a graphical representation illustrating normal operating voltage requirements for a conventional computing device and reduced voltage requirements of the computing device for reducing the energy consumption by the computing device according to embodiments of the present disclosure;

Fig. 2 is a graphical representation of flash- write error rates as a function of voltage according to embodiments of the present disclosure;

Figs. 3A-3C are graphical representations of voltage versus time during write operations at various operating voltages according to embodiments of the present disclosure;

Fig. 4 is a graphical representation of error rates indicating that as the Hamming weight (number of Is in the binary representation) of a number increases, the error rate of low- voltage flash write diminishes;

Figs. 5A - 5C are flowchart representations illustrating an in-place writes process of improving the reliability of storage in flash memories at low voltages according to embodiments of the present disclosure;

Figs. 6A - 6B are flowchart representations illustrating a multiple-place process of improving the reliability of storage in flash memories at low voltages according to embodiments of the present disclosure;

Figs. 6C - 6D are flowchart representations illustrating the decode method for the process shown in Figs. 6 A - 6B according to embodiments of the present disclosure;

Fig, 7 is a block diagram representation of a system utilizing the process shown in Figs. 5A-C and 6A-D according to embodiments of the present disclosure;

Fig. 8 is a graphical representation illustrating reliability improvement using in-place writes over five different voltages;

Fig. 9 is a graphical representation illustrating reliability improvement using multiple- place writes over five different voltages; Fig. 10 shows the error rate of slow writes based on the voltage level and the speed of the writes; and

Fig. 11 is a graphical representation illustrating ECG data stored in flash memory at 1.89 V improved by using a sign bit.

Figs. 12A - 12B are flowchart representations illustrating the encoding and decoding methods for the slow- write method.

DETAILED DESCRIPTION

Technologies are provided herein for improving the reliability of storage in non- volatile memories at operationally unreliable voltages. For instance, the technology allows a chip to operate at voltages where the hardware was not designed to guarantee reliability of the nonvolatile memory. In particular, by implementing the methods and systems disclosed herein, the reliability of storage in on-chip flash memories at operationally unreliable voltages, such as voltages below the recommended minimum operational voltage, can be improved by running one or more various software-based algorithms, including but not limited to, algorithms related to in- place writes, multiple-place writes, and slow writes.

As described above, one of the major issues with existing computing devices, or more specifically, microcontrollers used in embedded devices is their high energy consumption, which is due to their high operational voltage requirements. By tolerating a lower voltage, an energy- limited embedded device can decrease its power consumption and therefore extend its lifetime on a finite energy supply. The minimum operating voltage of embedded devices that use nonvolatile on-chip storage is usually determined by the requirements of the non- volatile memory, such as flash memory. Therefore, by reducing the minimum voltage requirements of the non-volatile memory, the energy-limited embedded device can reduce its operational voltage requirements, and as a result, its power consumption.

The present disclosure will be more completely understood through the following description, which should be read in conjunction with the drawings. In this description, like numbers refer to similar elements within various embodiments of the present disclosure. Within this description, the claims will be explained with respect to embodiments. The skilled artisan will readily appreciate that the methods, apparatus and systems described herein are merely exemplary and that variations can be made without departing from the spirit and scope of the disclosure.

"Flash memory" as used herein, refers to memory based on memory technologies that utilize a higher voltage than other system components in order for the hardware to perform reliably.

Referring now to the figures, Fig. 1 is a graphical representation illustrating normal operating voltage requirements for a conventional computing device and reduced voltage requirements of the computing device when implementing power consumption reducing algorithms in accordance with embodiments of the present disclosure. In various embodiments, a computing device, including but not limited to, a microprocessor or a microcontroller, such as, a TI MSP430 microcontroller has a nominal minimum voltage of 2.2V for flash writing and erasure. However, the microcontroller may still operate at lower voltages, such as 1.8V.

Increasing the operating voltage from 1.8V to 2.2V causes the CPU to draw about 50% more power without commensurate gain in clock speed because of the voltage squaring effect.

Moreover, lowering the operating voltage below flash memory requirements in order to save power results in the loss of flash memory reliability.

Fig. 2 is a graphical representation of flash- write error rates as a function of voltage according to embodiments of the present disclosure. It has been determined that flash writes may not be error free at low voltages and that there exist voltage levels below the minimum recommended voltage at which flash writes function correctly. However, not all flash writes at voltages lower than the nominal minimum voltage are guaranteed to be successful. Fig. 2 further shows that for different chips of exactly the same type, the error rate can be different even under equivalent voltage.

Referring now to Figs. 3 A-3C, which are graphical representations of voltage versus time during write operations at various operating voltages, show that not all flash writes fail at low voltages. On the contrary, most of the writes (95.24% at 1.9 V and 89.88% at 1.8 V) succeed. In particular, Fig. 3A shows an original ECG signal correctly stored at 2.0V despite operating below the recommended threshold. As the voltage decreases in Fig. 3B and further in Fig. 3C, erroneous writes, represented by light colored spikes of varying heights according to the magnitude of the error become more common. The black line shows the reconstructed signal that includes the errors. Some background information on conventional flash memory is presented below. Each flash memory cell is a floating-gate (FG) transistor made up of a source, drain, control gate, and floating gate. The floating gate is separated from the source and drain by an insulating oxide that makes it difficult for electrons to travel into or out of the gate. Flash cells rely on this oxide to maintain logical state in the absence of power, making the memory non-volatile.

To write a memory cell (which has an erased value of 1), the control circuitry applies a high field to the source. The application of this field greatly increases the probability that electrons in the floating gate will tunnel to the source. If a sufficient number of electrons tunnel to the source, the cell is subsequently read as a 0. To erase a cell (restoring a 1), the control circuitry applies a high field to both the source and drain. This field energizes the electrons currently stored near the source, allowing them to jump the oxide barrier to the floating gate where they are once again trapped.

Not all electrons must transition in order for a write or erase operation to be successful. The operation only needs to change the state of some majority of the electrons so that subsequent read operations detect sufficient charge to discern the intended value. Lowering the applied voltage (and thus the field strength) lowers the probability of state change for each electron but, as noted earlier, electrons that do transition will remain in place.

The reason why conventional flash memories are error prone at lower voltages is important to understand. In a NOR flash memory, all cells are initialized to 1, and writing data to a byte of flash memory means setting an appropriate number of bits to 0 by applying electrical charge to the corresponding flash cells. At low voltage, there may be insufficient charge to effect a transition to 0, and a flash write may store fewer 0 bits than requested. To be specific, an error occurs when a byte of data dl is written in a flash memory address and then data d2, which is not equal to data dl, is read from that flash memory address.

The present disclosure provides techniques for improving the reliability of storage in nonvolatile memory while operating a computing device under operationally unreliable conditions, such as operational voltages lower than recommended minimum operational voltages, to acceptable error rates, while reducing energy consumption by the computing device. In determining the reliability of storage in non- volatile memories, such as flash memories, at operationally unreliable voltages versus voltages within a recommended operating range, several factors are taken into consideration, including but not limited to the increased error rate, the reduced energy consumption of the computing device, and the increased execution time to store the same data at a low voltage compared to a higher voltage. It should be appreciated that the energy consumed to achieve an acceptably low error rate should not exceed the expected energy savings gained by running at a lower voltage. It should further be appreciated that some of the factors that affect error rates are memory location and the Hamming weight of the data to be stored.

In an experimental setup, a test platform was setup to run a program that writes numbers {0, ..., 255} to flash memory, then sends the contents of its flash memory to the monitoring platform via GPIO pins. Table II compares the written data and the intended data for cases in which errors occurred. Table II demonstrates that, when both the written data and the intended data are represented as integers, the absolute value of the stored data is always greater than or equal to the absolute value of the intended data.

Table II - Erroneous flash writes at low voltage. Insufficient electrical charge may result in some bits failing to transition from 1 (the initial state) to 0.

As background and definition for the present disclosure, some of the factors that affect error rates in flash memories are presented herein below. The following potential factors may affect the error rate of setting a bit to 0 in a flash memory at low voltage: voltage level, Hamming weight of the data, memory address, 0-bit location, and bit neighbors.

With reference to Hamming weight of the data, it has been determined that the lower the Hamming weight (number of Is in the binary representation) of a number, the higher the probability of error when writing that number to flash at low voltage. This can be explained by understanding that in an erased (i.e., having value 1) flash cell, writing a 1 is always error free because no change to the cell is necessary. However, setting a cell to 0 might fail if there is not enough charge accumulated in that cell. Based on per-byte Hamming weight, there are nine equivalence classes of integers that can be represented in one byte. The weight-8 equivalence class has only one member, 255, which can always be written to an erased flash cell without error. The other extreme case is the weight-0 equivalence class, containing only 0, that requires all eight bits to transition to 0. Fig. 4 shows the error rate for all nine equivalence classes. To exploit the fact that the Hamming weight of a number affects probability of error when it is written to flash, in one embodiment of the method of these teachings, numbers are transformed into numbers with greater Hamming weights before writing them to flash memory.

5

With respect to wear-out history, flash memory has a limited lifetime (about 10 cycles of erasures) after which the erase operations fail to reset the bits to 1. The more flash memory is erased (worn-out), the lower its error rate of setting bits to 0 would become. Wear-out history affects error rate, so storing data in more than one location might help decrease the error rate, especially if those locations are in different blocks of memory.

In one embodiment of the present disclosure, a method for improving the reliability of storage in flash memories at low voltages includes repeatedly writing data at the same memory location for up to a predetermined number of writing operations. This embodiment, also referred to as in-place writes, makes attempts at write time to store a value correctly in the given memory address. The in-place writes method repeatedly writes data to the same memory address.

One basis for this approach is that repeating a write attempt in a consistent location accumulates the charge in the same place, increasing the chance of storing a bit of information correctly. In addition, since flash writes only change bits in a single direction, a correctly written bit cannot be reversed to produce an error on a second write attempt. Figs. 5 A - 5C are flowchart representations illustrating an in-place writes process of improving the reliability of storage in flash memories at low voltages according to embodiments of the present disclosure.

Referring to Fig. 5 A, the data is written to flash memory at a given location (step 10), the number of write operations (initially set to zero) is incremented (step 20) and compared to a predetermined threshold (step 30). If the number of write operations is less than the

predetermined threshold, the data is written again to flash memory at the given location. If the number of write operations is not less than the predetermined threshold, the method ends. Fig. 5B shows the same method, with more detail, but including the step of reading the flash memory at the given location and comparing to data being written. If the output of the read operation is substantially equal to the data being written, the method ends. Fig. 5C shows the flowchart of the read operation. Since the transition of a 1 to a 0 in a NOR flash memory at low voltage is stochastic rather than guaranteed, the in-place writes method repeats the write of each byte (to the same memory location) more than once if necessary, up to a threshold number of attempts. Algorithm 1 gives the details for ENCODE and DECODE procedures for in- place writes.

The reason in-place writes decrease the error rate is that each write attempt in the same

Algorithm 1 The encoding and decoding algorithms for

in-place writes method to store data to address by repeating the writes up to threshold number of attempts if

necessary,

ENCODE(Arti/, address, threshold)

1 WRITE-TO-FLASH(dfl∞,iii#re5S)

2 result <— READ.FROM_FLASH{a£i£/reji)

3 repeat <— 1

4 while {result data) AND {repeal < threshold)

5 do WRlTE-TO~FLAS^~H(data,address)

6 result «- R E A D -FROM _FL A S H {address)

7 repeat <— repeat + 1

DECODE{addressj

1 result <— REAO -ROM J LASUfaddress}

2 return result memory location increases the accumulated charge and therefore raises the probability of storing the intended bit sequence successfully.

As set forth in the algorithm above, the processor performs the following steps during writing the data value at a particular memory location in the flash memory. First, the processor writes the data value at the particular memory location and then reads the written data value from the same memory location. A write operation count (repeat) is then incremented. The processor determines if the read data value is not equal to the data value to be written and if the write operation count is less than a predetermined number of writing operations (threshold). Upon determining that the write operation count is less than a predetermined number of writing operations and the data value is not equal to the readback value, the steps of writing the data value at the same memory location, reading a corresponding readback value from the same memory location, and incrementing the write operation count are repeated until the processor determines that the write operation count is not less than a predetermined number of writing operations or the data value is equal to the readback value, at which point, the processor ceases to write the data value at the same memory location. It should be appreciated that by determining to see if the readback value is equal to the data value to be written prior to each iteration, and prior to the threshold being reached, the processor may be able to reduce its energy consumption when compared to writing the data value a threshold number of times. This is because the amount of energy consumed in reading a data value and comparing it to the data value to be written is less than the energy consumed in writing the data value. As such, if the data value is written correctly in the first attempt, the processor can prevent itself from consuming additional energy in repeatedly writing the data value a predetermined number of times.

In another embodiment of the present disclosure, the method for improving the reliability of storage in flash memories at low voltages includes writing a value to a number of

predetermined locations in the flash memory, reading the written data from each one of the number of predetermined locations, the results of their reading constituting a number of readback values for a datum, and performing a bitwise logical operation on the number of readback values for the datum, with the result of the bitwise logical operation being the final readback value.

This embodiment, also referred to as multiple-place writes, tries to decrease the probability of error by making attempts at both write time and read time. This embodiment stores data in more than one location hoping that the data, even partially, will be stored correctly in at least one of these locations. The multiple-place writes approach reads data from all of the locations where the data have been stored, and, in one instance, computes the logical AND of all of the read data. Figs. 6a and 6b are flowchart representations illustrating a multiple-place writes process of improving the reliability of storage in flash memories at low voltages according to embodiments of the present disclosure. Referring to Fig. 6a, the address of the location in the flash memory at which data is to be written is initially a predetermined start address and the number of addresses is initially zero. Data is written at the location for which the address is known (step 40), the number of addresses is incremented (step 50) and compared to a

predetermined threshold (step 60). If the number of addresses is less than the predetermined threshold, the address of the location in the flash memory at which data is to be written is set to the next address (step 70) and steps 40 through 60 are repeated again. If the number of addresses is not less than the predetermined threshold, the method stops. Figs 6B and 6D are flowchart representations of the read back or decoding portion of the above described method. Referring to Fig. 6C, the address is initially set to the initial or start address and the address number is set initially to 1. The flash memory is read at the initial address (step 110) and the outcome of reading is set equal to the result (step 120). The address number is incremented (step 130), the address of the location being read is set to the next address (step 140), the flash memory is read at the location corresponding to the address (step 150), the result is obtained by a logical operation between the outcome of the read process (step 160) and the previous value of the result and the address number is compared to a predetermined threshold (step 170). If the address number is less than the predetermined threshold and the result is not equal to the data, steps 130 through 170 are repeated. If the address number is not less than the predetermined threshold or the result is equal to the data, the method ends. Similar to the case of in-place writes method, It should be appreciated that by determining to see if the readback value is equal to the data value to be written prior to each iteration, and prior to the threshold being reached, the processor may be able to reduce its energy consumption when compared to writing the data value to a threshold number of locations. This is because the amount of energy consumed in reading a data value and comparing it to the data value to be written is less than the energy consumed in writing the data value. As such, if the data value is written correctly in the first attempt, the processor can prevent itself from consuming additional energy in repeatedly writing the data value to a predetermined number of locations. Fig. 6D is a more detailed flow chart for the embodiment in which the logical operation is an AND operation.

Algorithm 2 details ENCODE and DECODE procedures of the multiple-place writes method. Writing a value to more than one memory location increases the probability of storing it successfully in the flash memory.

Algorithm 2 The encoding and decoding algorithms for

multiple-place writes method to store data to address by

repeating the writes up to threshold locations if necessary. The distance between each of these associated locations is offset.

ENCODE(i/i«ii, addr, threshold, offset)

1 WRITE TO-FLASU(data_}addr)

2 result «- READ-FROM-FLASH(at/rfr)

3 repeat <— 1

4 while (result Φ data) and {repeat < threshold)

5 do phyjaddr <— addr + (repeat x offset)

6 WHnE-TO-FLASH dala,phyMddr)

7 n-result *~

8 result <— result & n -result

9 repeat <— repeat + 1

DECODEfifcWr. threshold, offset)

1 for ί «- 0 to (threshold - 1 )

2 do phy ·*— «Λ/Γ + (i x offset)

3 n-result <— READ_FROM JFLASH(p/zy)

4 reiw// <— rciit/ί & n .result

5 return re;u/r

The reason the multiple-place writes approach can decrease the error rate is as follows: All cells of flash memory are initially set to 1. An error means that writing a 0 has failed and a bit cell ci has remained untouched (logical 1) although it was intended to be set to 0. If the cell write in one of the locations has not failed, and cell ci is 0 in at least one location, getting the AND of the read values from all locations will make cell ci = 0 in the AND result. The case of writing a 1 to a cell does not cause an error since it means changing a cell from 1 to 1.

In yet another embodiment of the present disclosure, the method for improving the reliability of storage in flash memories at low voltages, includes slowing down the speed of flash writes to allow more charge to be stored in a cell in an attempt to decrease the probability of error. This embodiment is referred to as slow writes and tries to decrease the probability of error by allow more charge to be stored in a cell at the time of writing. Figs 12A and 12B are flowchart representations of the read back or decoding portion of the above described method.

This method is similar to in-place writes in that it tries to accumulate enough charge in a cell to present a zero bit. However, instead of writing a bit multiple times, this method writes a bit once but slowly. The extra time allows for more charge to get stored in a cell. Algorithm 4 details the simple ENCODE and DECODE procedures. One way to improve the slow writes is to choose a frequency level based on the operating voltage as well as the temperature and then try to adjust the frequency based on the error rate. If the error rate is too high, the frequency has to be set to a smaller number to reduce the speed.

Algorithm 4 The encoding and decoding algorithms for the slow writes method to store data to address by slowing the write threshold times than, a normal write.

ENCODE(daia, address, threshold)

1 SLOW_FLASH_CLOCK(i ire5/ioM)

2 WB.lTE TO LASKidata.address) GOOE(address)

1 result READ JFE O M_PL A S H ( « ddress )

2 return, result

Fig. 7 is a block diagram of an embodiment of the system of these teachings. Referring to Fig. 7, the system includes a processor 180, one or more computer usable media having computer readable code embodied therein for implementing an embodiment of the method of these teachings 185 and a non- volatile memory 190, such as a flash memory. It should be appreciated that the teachings disclosed herein may be applied to other types of non- volatile memory, including but not limited to, memsistors, FRAM, spintronic memory, phase-change memory, and the like. The processor 180, the one or more computer readable media 185 and the non- volatile memory 190 are operatively connected by an interconnection component 175.

The embodiments of the method of these teachings are designed with the resource limitations of low-power devices in mind. The suitability of the three embodiments disclosed herein above for low-power devices was evaluated and the results are presented herein below. For a sensor monitoring application that reads 256 data samples from flash memory, aggregates data, and stores the results in flash memory, use of in-place writes reduces the energy consumption up to 35.25% versus running the same application at 2.2V (minimum listed voltage requirement for the flash memory). This sensing application models a common workload for both wireless sensor nodes and RFID-scale devices. Experimental setup:

A consistent experimental mental setup to measure the energy consumption and execution time of each program most utilize. Using an oscilloscope, the voltage of a small resistor in series with an MSP430 microcontroller programmed with a task (e.g., a flash write) was measured. The integration of the current (voltage divided by the resistance) over the execution time of the task multiplied by the operating voltage of the device gives the energy consumption of that task. To facilitate precise identification of the task on the oscilloscope, the microcontroller was directed to toggle a GPIO pin immediately before and after the task. Comparison of the Embodiments

The workload used to measure the performance of each of the embodiments is the storage of accelerometer traces— generated using the Intel WISP 4. l 's 10-bit ADC sensor— to flash memory. The input trace is a series of three-dimensional 16-bit samples containing 10 bits of information. A simple ad-hoc data compression method was utilized to store more data in the available flash memory. The compression method involved reading 4 samples of data, preparing the first byte of each sample to be stored in flash memory, then combining the remaining 2 bits of each sample into one byte of data. Using this compression scheme, every four samples (8 bytes) and were reduced to 5 bytes.

The maximum number of write attempts for both in-place writes and multiple-place writes methods were set to 2. These settings enable both methods to fit their data in 192 Bytes of flash memory. Table 2 shows the energy consumption and time taken for the same workload under each method. Both of these methods are feedback based and repeat writes if they detect errors. Because there is a lower chance of error at 1.9V, fewer rewrites are required than at 1.8V, so less energy and time are required.

The in-place writes method slightly outperforms the multiple-place writes method at both voltage levels because its decoding procedure is less CPU intensive. In-place writes method has a better Error Correction Rate (ECR in Table 2) than multiple-place writes. The multiple-place writes method seems to be the most suitable when there are some memory cells that are hard to program and therefore rewriting in those cells is not helpful. Method Voltage (V) Energy (μΐ) Time (ms) Error correction rate

In-place 1.8 59.18 24.16 96.14%

M-place 1.8 63.34 25.00 84.28%

In-place 1.9 38.3 15.43 100%

M-place 1.9 40.17 16.85 100%

Table 2: Performance comparison of the proposed methods at 1.8V and 1.9V. Error Correction Rate (ECR) is used as a metric of effectiveness of the methods.

Error Correction Rate:

As Table 2 illustrates, both methods incur similar energy consumption. The effectiveness of these two approaches with respect to error correction rate is compared in more detail herein below.

Fig. 8 and Fig. 9 show that flash storage reliability improves as the number of repeated writes/ places at five different voltage levels is increased (all below the nominal minimum voltage for flash writes).

It should be noted that embodiments of the method of these teachings that combine two or more of the above disclosed embodiments are also within the scope of these teachings.

Various embodiments of the present disclosure that combine two or more of the above disclosed embodiments are also within the scope of the present disclosure. Embodiments of articles of manufacture that includes computer usable media having computer readable code that causes the processor to combine two or more of the above disclosed embodiments are also within the scope of the present disclosure. Other embodiments of methods to decrease the energy requirements are disclosed herein below.

Fig. 10 shows the error rate of slow writes based on the voltage level and the speed of the writes. The speed of the writes has been adjusted by tuning the frequency of the flash memory. For an operating voltage as low as 1.8V, the average error rate eventually drops to about zero percent if the speed is slowed down enough (In the case of this particular chip when the frequency is set to 285 KHz). Since low-power embedded devices have a limited amount of energy available, saving power is usually a higher priority than reducing the delay. Slow writes follows this principle and reduces the speed of the writes in order to save the power consumption of the device. Slow writes would be beneficial especially for CPU-intensive applications that their often use of CPU would cost less power while their rare flash memory use will be slower.

Experiment: A TI MSP430F2131 microcontroller runs a program that writes zeros to the data segment of its flash memory (192 bytes). The microcontroller's operating voltage was increased in 10-mV steps and the frequency of flash writes was increased from 260 KHz to 1104 KHz. The monitoring platform was used to compute the byte error rates over 50 runs.

Sign Bits

As discussed herein above, one of the major factors influencing the error rate is the Hamming weight of a number. One way to improve the performance of the low- voltage storage methods is to store numbers with greater Hamming weights (weight > 4) in flash memory. If a number is lightweight (weight < 4), the complement of the number would be stored and a sign bit would be set for future data access. An array of sign bits can be stored separately from the data to avoid disturbing data structure layouts. Similar techniques have been applied to multi- level cell (MLC) flash memories with four levels; those techniques result in a significant decrease of energy consumption. Fig. 11 shows that using the sign bit scheme decreases the error rate at low voltage for the same ECG data used herein above. For this specific example, out of 168 bytes of ECG data, 160 bytes are over- weight and therefore using the sign-bit scheme greatly decreased the error rate. The sign bit approach involves very lightweight computation (counting the number of ones) and increases the number of writes by a factor of one eight.

Therefore, the effect of this improvement on energy consumption, and delay should be comparatively small. Fig. 11 shows ECG data stored in flash memory at 1.89 V improved by using a sign bit. The light-colored bars show the difference between the ECG stored at low voltage and the original ECG data.

Memory mapping table.

Another technique for exploiting the fact that numbers with greater Hamming weights have a lower probability of error is to map the most frequently used numbers in the user's data to the heavier numbers. One embodiment preprocesses the data to sort numbers based on their frequency of use. A simple memory mapping table would map the most frequent numbers to the heaviest numbers. Such a table could be preloaded in flash memory so that storing the table does not consume energy at run time. Use of a memory mapping table would only increase the number of Is and does not increase the number of writes. Therefore, the energy consumption overhead and the delay should be smaller than the sign bit method.

For the purposes of describing and defining the present teachings, it is noted that the term "substantially" is utilized herein to represent the inherent degree of uncertainty that may be attributed to any quantitative comparison, value, measurement, or other representation. The term "substantially" is also utilized herein to represent the degree by which a quantitative

representation may vary from a stated reference without resulting in a change in the basic function of the subject matter at issue.

Although the teachings have been described with respect to various embodiments, it should be realized these teachings are also capable of a wide variety of further and other embodiments within the spirit and scope of the appended claims. For instance, although the present disclosure describes embodiments related to flash memories, the present disclosure may be applied to other types of memory technologies that utilize a higher voltage than other system components in order for the hardware to perform reliably. As non-limiting examples, the teachings disclosed in the present disclosure can be applied to other memory technologies, including but not limited to, memsistors, FRAM, spintronic memory, phase-change memory, and the like.

In addition, the teachings disclosed herein relate to software algorithms for improving the reliability of storage in a computing device with an on-chip memory at voltages below recommended minimum operating voltages. However, it should be appreciated that the scope of the present disclosure is not intended to be limited to such applications, but rather, includes applications that may utilize the software algorithm methods of in-place writes, multiple-place writes, and slow writes, or any combination thereof, to improve the reliability of storage in a computing device with an on-chip memory operating in physically unreliable or operationally unreliable conditions. Such conditions may arise from operating at physically unreliable or operationally unreliable voltages. However, other conditions other than operating at

operationally unreliable voltages may cause the storage in a non- volatile memory to be unreliable.

What is claimed is:

Claims

1. A method of improving the reliability of storage in a computing device with an on-chip flash memory at low voltages comprising:

supplying an operating voltage below a recommended minimum voltage to the computing device having an on-chip flash memory; and

executing an improved reliability processor-executed method that writes a data value in the on-chip flash memory in a manner that improves reliability of storage while operating at a voltage below the recommended minimum voltage. 2. The method of claim 1 , wherein repeatedly writing a data value at one particular memory location in the flash memory comprises repeatedly writing the data value at the same memory location up to a predetermined number of writing operations.

3. The method of claim 2,wherein repeatedly writing the data value at the same memory location up to a predetermined number of writing operations comprises:

initializing a write operation count;

writing the data value at the same memory location;

reading a corresponding readback value from the same memory location in which the data value is written;

incrementing the write operation count;

determining if the write operation count is less than a predetermined number of writing operations and the data value is not equal to the readback value; and

upon determining that the write operation count is less than a predetermined number of writing operations and the data value is not equal to the readback value, repeating the steps of writing the data value at the same memory location, reading a corresponding readback value from the same memory location, and incrementing the write operation count.

4. The method of claim 3, wherein repeatedly writing the data value at the same memory location up to a predetermined number of writing operations further comprises:

upon determining that the write operation count is not less than a predetermined number of writing operations or the data value is equal to the readback value, ceasing to write the data value at the same memory location.

5. The method of claim 1 , wherein executing an improved reliability processor-executed method that repeatedly writes a data value on the on-chip flash memory comprises:

writing the data value to a number of predetermined locations in the flash memory;

reading, as corresponding readback values, the written data values from each one of the number of predetermined locations; and

performing a bitwise logical operation on the readback values to determine a final readback value; and

reading the final readback value.

6. The method of claim 5, wherein performing a bitwise logical operation on the readback values to determine a final readback value comprises computing a logical AND of the readback values. 7. The method of claim 6, further comprising:

setting a predetermined address as a first location in the flash memory;

initializing an address count;

writing the data value to the first location in the flash memory;

incrementing the address count;

determining if the address count has reached a threshold count value; and

upon determining that the address count has not reached the threshold count value, writing the data value to a subsequent location in the flash memory and incrementing the address count.

The method of claim 7, wherein reading the final readback value comprises:

setting a readback address to the first address in the flash memory;

initializing the address count;

reading a written data value at the first address;

setting the read written value to a result;

incrementing the address count; reading a written data value at the subsequent address corresponding to a subsequent address in the flash memory;

performing a logical operation between the read written data value at the subsequent data and the result.

9. The method of claim 8, wherein performing a logical operation between the read written data value at the subsequent data and the result comprises performing a logical AND operation between the read written data value at the subsequent data and the result. 10. The method of claim 1, further comprising reducing a frequency of the flash memory.

11. The method of claim 1 , further comprising writing the data value in the flash memory at a slower write speed relative to a write speed associated with an operating voltage greater than the recommended minimum voltage.

12. The method of claim 1 , further comprising:

determining a number of one bits in the data value to be stored having a value of 1 ;

determining a number of zero bits in the data value to be stored having a value of 0;

determining if the number of zero bits exceed the number of one bits;

upon determining that the number of zero bits exceed the number of one bits, storing a complement of the data value in the flash memory and setting a sign bit indicating that the complement of the data value is stored.

13. A system, comprising:

a processor;

a non- volatile memory; and

a computer readable medium having computer executable instructions stored thereon, which when executed by the processor, cause the processor to:

write a data value in the non- volatile memory in a manner that improves reliability of storage while operating the processor at an operationally unreliable operating voltage.

14. The system of claim 13, wherein writing a data value in the non-volatile memory comprises repeatedly writing the data value at a particular memory location in the non-volatile memory up to a predetermined number of writing operations.

15. The system of claim 14,wherein repeatedly writing the data value at the particular memory location up to a predetermined number of writing operations comprises:

initializing a write operation count;

writing the data value at the same memory location;

incrementing the write operation count;

upon determining that the write operation count is less than a predetermined number of writing operations and the data value is not equal to the readback value, repeating the steps of writing the data value at the same memory location, reading a corresponding readback value from the same memory location, and incrementing the write operation count; and

16. The system of claim 13 , wherein writing a data value on the non-volatile memory comprises:

writing the data value to a number of predetermined locations in the non- volatile memory;

reading the final readback value.

17. The system of claim 16, wherein performing a bitwise logical operation on the readback values to determine a final readback value comprises computing a logical AND of the readback values. 18. The system of claim 13, wherein writing a data value in the non- volatile memory in a manner that improves reliability of storage while operating the processor at an operationally unreliable operating voltage comprises writing a data value in the non- volatile memory in a manner that improves reliability of storage while operating the processor at an operating voltage lower than a recommended minimum voltage.

19. The system of claim 13, wherein the computer readable medium having further computer executable instructions stored thereon, which when executed by the processor, cause the processor to reduce a frequency of the flash memory. 20. The system of claim 13, wherein writing a data value in the flash memory in a manner that improves reliability of storage while operating at a voltage below a recommended minimum voltage of the processor comprises:

determining a number of one bits in the data value to be stored having a value of 1;

determining a number of zero bits in the data value to be stored having a value of 0; determining if the number of zero bits exceed the number of one bits;

upon determining that the number of zero bits exceed the number of one bits, storing a complement of the data value in the flash memory and setting a sign bit indicating that the complement of the data value is stored. 21. A computer-readable storage medium having computer-executable instructions, which when executed by a computer, cause the computer to:

write a data value in a non-volatile memory in a manner that improves reliability of storage while operating a processor at an operationally unreliable operating voltage. 22. The computer-readable storage medium of claim 21, wherein writing a data value in the non-volatile memory in a manner that improves reliability of storage while operating a processor at an operationally unreliable operating voltage comprises writing a data value at a particular memory location in the non- volatile memory up to a predetermined number of writing operations.

23. The computer-readable storage medium of claim 22, wherein repeatedly writing the data value at the particular memory location up to a predetermined number of writing operations comprises:

initializing a write operation count;

writing the data value at the same memory location;

incrementing the write operation count;

24. The computer-readable storage medium of claim 21, wherein writing a data value in the non- volatile memory in a manner that improves reliability of storage while operating a processor at an operationally unreliable operating voltage comprises:

writing the data value to a number of predetermined locations in the flash memory; reading, as corresponding readback values, the written data values from each one of the number of predetermined locations;

reading the final readback value.

25. The computer-readable storage medium of claim 24, wherein performing a bitwise logical operation on the readback values to determine a final readback value comprises computing a logical AND of the readback values. 26. The computer-readable storage medium of claim 21, wherein the computer readable medium having further computer executable instructions stored thereon, which when executed by the processor, cause the processor to reduce a frequency of the non-volatile memory.

27. The computer-readable storage medium of claim 21, wherein the computer readable medium having further computer executable instructions stored thereon, which when executed by the processor, cause the processor to:

determine a number of one bits in the data value to be stored having a value of 1 ;

determine a number of zero bits in the data value to be stored having a value of 0;

determine if the number of zero bits exceed the number of one bits;

upon determining that the number of zero bits exceed the number of one bits, store a complement of the data value in the flash memory and setting a sign bit indicating that the complement of the data value is stored.

28. A method of improving the reliability of storage in a computing device with a non- volatile memory comprising:

supplying an operationally unreliable operating voltage to the computing device coupled to a non-volatile memory, the operating voltage adversely affecting the reliability of storage in the non-volatile memory; and

executing an improved reliability processor-executed method that writes a data value in the non-volatile memory in a manner that improves reliability of storage while operating at the operationally unreliable operating voltage.

29. The method of claim 28, wherein repeatedly writing a data value at one particular memory location in the non-volatile memory comprises repeatedly writing the data value at the same memory location up to a predetermined number of writing operations.

30. The method of claim 29,wherein repeatedly writing the data value at the same memory location up to a predetermined number of writing operations comprises:

initializing a write operation count;

writing the data value at the same memory location;

incrementing the write operation count;