ATE369656T1 - Grob justierbare verzögerungsschaltungen mit flankenunterdrückungsschaltungen in verzögerungsregelschleifen - Google Patents

Grob justierbare verzögerungsschaltungen mit flankenunterdrückungsschaltungen in verzögerungsregelschleifen

Info

Publication number
ATE369656T1
ATE369656T1 AT03775714T AT03775714T ATE369656T1 AT E369656 T1 ATE369656 T1 AT E369656T1 AT 03775714 T AT03775714 T AT 03775714T AT 03775714 T AT03775714 T AT 03775714T AT E369656 T1 ATE369656 T1 AT E369656T1
Authority
AT
Austria
Prior art keywords
circuit
delay
control loop
edge suppression
delay control
Prior art date
Application number
AT03775714T
Other languages
English (en)
Inventor
Sri Easwaran
Original Assignee
Nxp Bv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nxp Bv filed Critical Nxp Bv
Application granted granted Critical
Publication of ATE369656T1 publication Critical patent/ATE369656T1/de

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/125—Discriminating pulses
    • H03K5/1252—Suppression or limitation of noise or interference
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0818—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the controlled phase shifter comprising coarse and fine delay or phase-shifting means
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Pulse Circuits (AREA)
  • Manipulation Of Pulses (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Networks Using Active Elements (AREA)
  • Input Circuits Of Receivers And Coupling Of Receivers And Audio Equipment (AREA)
  • Noise Elimination (AREA)
  • Stereophonic System (AREA)
  • Filters That Use Time-Delay Elements (AREA)
AT03775714T 2002-12-13 2003-12-08 Grob justierbare verzögerungsschaltungen mit flankenunterdrückungsschaltungen in verzögerungsregelschleifen ATE369656T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US43337302P 2002-12-13 2002-12-13

Publications (1)

Publication Number Publication Date
ATE369656T1 true ATE369656T1 (de) 2007-08-15

Family

ID=32595169

Family Applications (1)

Application Number Title Priority Date Filing Date
AT03775714T ATE369656T1 (de) 2002-12-13 2003-12-08 Grob justierbare verzögerungsschaltungen mit flankenunterdrückungsschaltungen in verzögerungsregelschleifen

Country Status (8)

Country Link
US (1) US7248087B2 (de)
EP (1) EP1573912B1 (de)
JP (1) JP2006510297A (de)
CN (1) CN100337401C (de)
AT (1) ATE369656T1 (de)
AU (1) AU2003283733A1 (de)
DE (1) DE60315507T2 (de)
WO (1) WO2004055988A2 (de)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7855584B2 (en) * 2003-12-09 2010-12-21 St-Ericsson Sa Low lock time delay locked loops using time cycle suppressor
US8502593B2 (en) * 2004-10-13 2013-08-06 Broadcom Corporation Balanced debounce circuit with noise filter for digital system
US7737671B2 (en) * 2005-12-05 2010-06-15 Texas Instruments Incorporated System and method for implementing high-resolution delay
TW200742223A (en) * 2006-04-26 2007-11-01 Novatek Microelectronics Corp Logic-keeping apparatus for improving system-level electrostatic discharge robustness
CN108134758B (zh) * 2017-12-15 2020-04-28 清华大学 一种磁谐振耦合无线携能通信***的时频联合同步方法
CN110620569B (zh) * 2018-06-19 2023-09-08 瑞昱半导体股份有限公司 触发器电路

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0857085A4 (de) * 1995-11-06 2001-01-31 Circuit Automation Inc Vorrichtung zur beseitigung von flecken auf einer sieddruckschablone für leiterplatten
US5920221A (en) * 1997-07-14 1999-07-06 Vanguard International Semiconductor Corporation RC delay circuit for integrated circuits
JPH1185308A (ja) * 1997-09-02 1999-03-30 Nippon Steel Corp 内部クロック発生回路
KR100319890B1 (ko) * 1999-01-26 2002-01-10 윤종용 지연동기루프 및 이에 대한 제어방법
JP4397076B2 (ja) * 1999-08-20 2010-01-13 株式会社ルネサステクノロジ 半導体装置
TW548659B (en) * 2000-09-05 2003-08-21 Samsung Electronics Co Ltd Delay locked loop circuit for reducing load of variable delay unit at high-frequency operation and locking external clock signal stably

Also Published As

Publication number Publication date
CN100337401C (zh) 2007-09-12
WO2004055988A2 (en) 2004-07-01
WO2004055988A3 (en) 2004-11-04
JP2006510297A (ja) 2006-03-23
DE60315507D1 (de) 2007-09-20
DE60315507T2 (de) 2008-04-24
CN1726642A (zh) 2006-01-25
US7248087B2 (en) 2007-07-24
EP1573912A2 (de) 2005-09-14
AU2003283733A8 (en) 2004-07-09
AU2003283733A1 (en) 2004-07-09
US20060109038A1 (en) 2006-05-25
EP1573912B1 (de) 2007-08-08

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Legal Events

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RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties