TW200713828A - Delay locked loop circuit - Google Patents

Delay locked loop circuit

Info

Publication number
TW200713828A
TW200713828A TW095123924A TW95123924A TW200713828A TW 200713828 A TW200713828 A TW 200713828A TW 095123924 A TW095123924 A TW 095123924A TW 95123924 A TW95123924 A TW 95123924A TW 200713828 A TW200713828 A TW 200713828A
Authority
TW
Taiwan
Prior art keywords
clock
locked loop
delay locked
delay
phase
Prior art date
Application number
TW095123924A
Other languages
Chinese (zh)
Other versions
TWI322575B (en
Inventor
Kyung-Hoon Kim
Original Assignee
Hynix Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hynix Semiconductor Inc filed Critical Hynix Semiconductor Inc
Publication of TW200713828A publication Critical patent/TW200713828A/en
Application granted granted Critical
Publication of TWI322575B publication Critical patent/TWI322575B/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1057—Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1066—Output synchronization
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/095—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using a lock detector

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Pulse Circuits (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

A delay locked loop increases an operation margin of a delay locked loop by using an output clock having more advanced phase than a DLL output clock. A clock delay compensation block receives an external clock signal to thereby generate a first multi clock and a second multi clock. A phase control block compares the first multi clock with the second multi clock to generate phase control signal controlling a shifting operation. A multi-phase delay control block performs a shifting operation based on the phase control signal to control the clock delay compensation block.
TW095123924A 2005-09-29 2006-06-30 Delay locked loop circuit TWI322575B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR20050090951 2005-09-29
KR1020050117134A KR100733423B1 (en) 2005-09-29 2005-12-02 Delay Locked Loop Circuit

Publications (2)

Publication Number Publication Date
TW200713828A true TW200713828A (en) 2007-04-01
TWI322575B TWI322575B (en) 2010-03-21

Family

ID=37959237

Family Applications (1)

Application Number Title Priority Date Filing Date
TW095123924A TWI322575B (en) 2005-09-29 2006-06-30 Delay locked loop circuit

Country Status (3)

Country Link
KR (1) KR100733423B1 (en)
CN (1) CN100590733C (en)
TW (1) TWI322575B (en)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6621316B1 (en) * 2002-06-20 2003-09-16 Micron Technology, Inc. Synchronous mirror delay (SMD) circuit and method including a counter and reduced size bi-directional delay line
KR100891335B1 (en) 2007-07-02 2009-03-31 삼성전자주식회사 Clock generating apparatus for performing Bit Error Rate measurement
KR100903369B1 (en) 2007-11-02 2009-06-23 주식회사 하이닉스반도체 Semiconductor memory device
KR100910851B1 (en) * 2007-11-05 2009-08-06 주식회사 하이닉스반도체 Semiconductor device and operation method thereof
KR100968447B1 (en) * 2007-11-13 2010-07-07 주식회사 하이닉스반도체 Semiconductor Integrated Circuit
KR101068628B1 (en) * 2008-12-31 2011-09-28 주식회사 하이닉스반도체 Clock signal generator
KR101012678B1 (en) 2009-02-04 2011-02-09 연세대학교 산학협력단 Delay locked loop and electirc device including the same
KR101145316B1 (en) 2009-12-28 2012-05-14 에스케이하이닉스 주식회사 Semiconductor device and operating method thereof
US8482332B2 (en) * 2011-04-18 2013-07-09 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-phase clock generator and data transmission lines
US8836389B2 (en) * 2011-09-28 2014-09-16 Intel Corporation Apparatus, system, and method for controlling temperature and power supply voltage drift in a digital phase locked loop
KR101965397B1 (en) * 2012-05-25 2019-04-03 에스케이하이닉스 주식회사 Semiconductor Apparatus
CN103888132A (en) * 2014-04-02 2014-06-25 广东顺德中山大学卡内基梅隆大学国际联合研究院 Circuit and method for generating two paths of I/Q orthogonal clocks
CN104143975B (en) * 2014-08-01 2017-11-10 西安紫光国芯半导体有限公司 A kind of DLL time delay chains and the method for reducing delay locked loop clock duty cycle distortion
CN114613402A (en) * 2022-03-21 2022-06-10 东芯半导体股份有限公司 Self-alignment control circuit for offset cancellation calibration circuit of input buffer

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100548549B1 (en) * 2001-12-31 2006-02-02 주식회사 하이닉스반도체 A delay locked loop circuit

Also Published As

Publication number Publication date
CN1941171A (en) 2007-04-04
KR100733423B1 (en) 2007-06-29
CN100590733C (en) 2010-02-17
KR20070036549A (en) 2007-04-03
TWI322575B (en) 2010-03-21

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