WO2024120422A1 - 具有转接板功能的新型封装基板及其制作方法 - Google Patents

具有转接板功能的新型封装基板及其制作方法 Download PDF

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Publication number
WO2024120422A1
WO2024120422A1 PCT/CN2023/136679 CN2023136679W WO2024120422A1 WO 2024120422 A1 WO2024120422 A1 WO 2024120422A1 CN 2023136679 W CN2023136679 W CN 2023136679W WO 2024120422 A1 WO2024120422 A1 WO 2024120422A1
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Prior art keywords
packaging substrate
photosensitive
substrate
film
layer
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PCT/CN2023/136679
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English (en)
French (fr)
Inventor
赵勇
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武汉新创元半导体有限公司
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Publication of WO2024120422A1 publication Critical patent/WO2024120422A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers

Definitions

  • the present invention relates to the field of integrated circuit (IC) packaging substrates. Specifically, the present invention relates to combining photosensitive/non-photosensitive insulating materials as dielectric layers and using metal materials such as copper as conductive lines to produce a novel packaging substrate having multiple layers of finer circuits and interposer functions. In addition, the present invention also relates to a method for producing such a novel packaging substrate.
  • IC integrated circuit
  • packaging substrates or carriers
  • chips such as bare chips (or dies) contain nanometer-level circuits.
  • an adapter plate is usually placed between the two to achieve the function of converting connections between circuits of different orders of magnitude in precision.
  • Adapters such as silicon adapters, serve as interposers for interconnecting dies and dies with package substrates, and play an important role in connecting the circuits in the die with the circuits in the package substrate.
  • TSV through silicon vias
  • the base layer of the adapter is also made of silicon wafers (or glass), which makes it expensive.
  • the size of the silicon adapter is also limited, and it cannot be made larger.
  • EMIB Embedded Multi-Die Interconnect Bridge
  • Intel proposed the EMIB (Embedded Multi-Die Interconnect Bridge) technology, which uses a smaller silicon bridge to implement the thinner line width part of the Die-Die bridge and embeds this part in the substrate, as shown in Figure 2.
  • the EMIB silicon bridge has a smaller size, lower cost, and improved yield.
  • this technology adds the process of pre-embedding the EMIB silicon bridge into the substrate, and the semiconductor wafer process is still used to make the silicon bridge, so there are still problems that need to be improved in terms of cost and yield.
  • the present invention proposes a new packaging substrate with adapter function.
  • This substrate does not require a separate adapter board or silicon bridge connection, but can be directly connected to one or more Dies, and push the line width and line spacing of the substrate to the sub-micron level.
  • the present invention is suitable for traditional substrate materials such as BF (such as ABF, NBF, etc.), BT, FR4, etc. It performs the function of a silicon transfer plate or a silicon bridge without the need for a silicon wafer (or glass).
  • a substrate having the signal interconnection performance between chips and substrates and between chips is manufactured by coating insulating material slurry such as polyimide (PI) slurry or laminating insulating material film such as PI film on traditional substrate materials such as BF, BT, FR4, etc., and using a photolithography method or an etching method.
  • insulating material slurry such as polyimide (PI) slurry or laminating insulating material film such as PI film
  • traditional substrate materials such as BF, BT, FR4, etc.
  • This substrate has an ultra-fine line width of even submicron on the line, thereby meeting the IC's demand for high precision, reducing numerous switching lines and solder ball welding, and the process is more mature to achieve, meeting the requirements of the chipset for short signal transmission distance, fast signal transmission between multiple chips, fast signal transmission between the substrate and each chip, and low cost.
  • the present invention proposes a novel method for manufacturing a packaging substrate.
  • a substrate such as BT, BF, FR4, etc., including one or more layers, is provided, and a substrate circuit is provided in each layer of the substrate.
  • a PI slurry is coated or a PI film is pressed on the layer on the substrate that serves the function of connecting the chip to the substrate or interconnecting the chips to provide one or more PI film layers to form a transfer layer portion.
  • the transfer layer portion together with the packaging substrate integrated therewith constitutes a novel packaging substrate of the present invention.
  • the transfer layer portion may be the top layers of the substrate, the bottom layers of the substrate, the middle layers of the substrate, or a combination thereof.
  • a line width that meets the requirements such as a line of more than hundreds of nanometers, and a via for interconnection are formed. Because the line is already very fine, a full additive method or a semi-additive method is used here to complete it, wherein the seed layer of the additive method or the semi-additive method can be completed by chemical copper plating, Sputter or ion implantation plating.
  • the novel packaging substrate of the present invention can be soldered with a chip such as a Die for the final solder ball welding.
  • the present invention improves the wiring capability and performance, and has the function of an adapter board. At the same time, it provides a manufacturing method that is simpler, more reliable and more mature than the existing adapter board process, and replaces expensive silicon wafers.
  • the present invention also provides a novel packaging substrate processing method and structure. Specifically, the processing method of the present invention does not use a traditional silicon substrate, reduces the number of solder ball welding at least once, and reduces the signal transmission channel, thereby further meeting or improving a higher signal transmission speed and less signal loss than the existing chipset.
  • the present invention incorporates the RDL (Re-distributed layer) process and high-precision exposure and etching process by grooving and/or opening holes on the transfer layer portion, and is able to manufacture a substrate with very high line fineness, thereby realizing the direct use of the RDL process to make the transfer board functional layer on an ordinary substrate, and increasing the line width of the packaging substrate industry to the order of hundreds of nanometers, meeting the development direction of the substrate towards finer line widths, and breaking through the bottleneck of the existing packaging substrate stopping at a line width of several microns.
  • the present invention is more economical.
  • a new packaging substrate with a transfer board function comprising: a packaging substrate, the packaging substrate containing a substrate circuit; and a transfer layer portion integrally integrated on the packaging substrate, wherein a fine circuit is provided on and/or in the transfer layer portion; wherein the fine circuit of the transfer layer portion is connected to the substrate of the packaging substrate.
  • the circuit forms an electrical connection so as to conduct the electrical connection between the packaging substrate and the chip components attached to the transfer layer portion.
  • the transfer layer portion includes a photosensitive PI adhesive film or a photosensitive PI slurry.
  • the transfer layer portion includes a non-photosensitive PI adhesive film or a non-photosensitive PI slurry.
  • the packaging substrate is composed of one or more materials selected from BF, BT, and FR4.
  • the transfer layer portion includes grooves and/or openings to make connecting circuits.
  • a method for manufacturing a novel packaging substrate having a transfer board function comprising the following steps:
  • the dry film or photoresist is stripped off from the prefabricated packaging substrate and flash-etched to remove the exposed portion of the conductive seed crystal layer, thereby achieving interconnection between the circuit of the photosensitive PI film layer and the substrate circuit of the packaging substrate.
  • the steps of providing a photosensitive PI film layer to removing the dry film or photoresist and flash etching are repeated one or more times to provide one or more photosensitive PI film layers to form a transfer layer portion of the novel packaging substrate.
  • the transfer layer portion forms a transfer function layer comprising one or more layers of fine circuits.
  • the thickness of the conductive seed layer is 80nm-2000nm.
  • a method for manufacturing a novel packaging substrate having a transfer board function comprising the following steps:
  • the second dry film or photoresist is stripped off from the prefabricated packaging substrate and flash etching is performed to remove the exposed portion of the conductive seed crystal layer, thereby interconnecting the circuit of the non-photosensitive PI film layer with the substrate circuit of the packaging substrate.
  • the steps of providing a non-photosensitive PI film layer to removing the second dry film or photoresist and flash etching are repeated one or more times to provide one or more non-photosensitive PI film layers to form a transfer layer portion of the novel packaging substrate.
  • the transfer layer portion forms a transfer function layer comprising one or more layers of fine circuits.
  • the thickness of the conductive seed layer is 80nm-2000nm.
  • FIG1 is a schematic cross-sectional view of a silicon interposer interconnecting a Die and a packaging substrate according to the prior art
  • FIG. 2 is a schematic cross-sectional view of a die and a package substrate interconnected using EMIB according to the prior art
  • FIG. 3 is a schematic cross-sectional view of a novel packaging substrate having a transfer board function according to an embodiment of the present invention
  • 4 to 10 are schematic cross-sectional views of different steps of manufacturing a novel packaging substrate according to a method of a first embodiment of the present invention
  • 11 to 19 are schematic cross-sectional views of different steps of manufacturing a novel packaging substrate according to a method of a second embodiment of the present invention.
  • FIG. 20 is a flow chart of a novel packaging substrate manufacturing method according to a first exemplary embodiment of the present invention.
  • FIG. 21 is a flow chart of a novel packaging substrate manufacturing method according to a second exemplary embodiment of the present invention.
  • FIG3 shows a schematic cross-sectional view of a new type of packaging substrate with a transfer board function according to an embodiment of the present invention.
  • the new type of packaging substrate mainly includes a packaging substrate 10, and a transfer layer portion 40 integrally integrated on the packaging substrate 10.
  • the packaging substrate 10 is a laminate comprising one or more layers.
  • hole processing, chemical copper plating, electroplating copper, etching and other processing are selectively performed to obtain a single-sided or double-sided substrate circuit.
  • electrical interconnection of substrate circuits between the various layers of the substrate 10 can be formed.
  • the transfer layer portion 40 also includes one or more layers, and fine circuits are provided in each layer of the transfer layer portion 40.
  • the fine circuits in the transfer layer portion 40 are electrically connected to the substrate circuits of the packaging substrate 10 so as to conduct the electrical connection between the packaging substrate 10 and the bare chips attached to the transfer layer portion 40, such as the first Die 1 and the second Die 2.
  • the transfer layer portion 40 serves as an intermediate layer between Die 1, 2 and the package substrate 10, and plays the role of interconnecting Die 1, 2 and the package substrate 10, thereby realizing the function of a transfer board in the conventional sense.
  • the transfer layer portion 40 includes an insulating material substrate.
  • a PI film layer is used as an insulating material substrate to make the transfer layer portion. Compared with other insulating materials, PI material has a certain fluidity and surface flattening function, and thus has the advantage of being able to make the circuit more refined.
  • Die 1 and 2 are connected to the new packaging substrate, especially the transfer layer part 40, respectively, by solder ball welding.
  • the method of solder ball window opening can adopt the PI film window opening mentioned in this article.
  • traditional green oil window opening can also be used for solder ball welding.
  • the connection between Die 1 and 2 and the transfer layer part 40 can also be connected by a conductive film connection method with Au ball, such as a material with ACF characteristics. This method is also widely used to interconnect display module IC or FPC with components.
  • chip Die As shown in the figure, although two chip dies are shown to be interconnected, this is only schematic. In fact, according to the present invention, a single chip Die can be connected to the substrate, or multiple chip Dies can be interconnected. Optionally, multiple chip Dies of different types and sizes can be interconnected. Optionally, both sides of the substrate can be connected to the chip Die. Moreover, in the figure, the chip Die pins and the circuits of the substrate with the transfer function are only schematic, and they can have different densities and different sizes. In addition, although two similar chip Dies are shown in Figure 3, these chip Dies actually have many possibilities. For example, chip Die includes but is not limited to any one of the chips with computing functions such as CPU, GPU, ASIC, etc. When there are other interconnection requirements, other chipsets or circuit boards can be used instead of chip Dies.
  • the new packaging substrate of the present invention does not require a separate adapter plate or silicon bridge connection, but can be directly connected to the die, and can increase the line width and line spacing of the substrate to the sub-micron level. Therefore, the new packaging substrate of the present invention not only improves the wiring capability performance, but also has the function of an adapter plate, and does not need to use expensive silicon wafers.
  • the novel packaging substrate manufacturing method may generally include the following steps:
  • Step S00 providing a packaging substrate 10 including a substrate circuit (not shown);
  • Step S10 providing a photosensitive PI film layer 14 on the surface of the packaging substrate 10;
  • Step S20 forming via holes 42 and line gaps 44 by exposing and developing the photosensitive PI film layer 14, and then curing the film to fix the shape;
  • Step S30 forming a conductive seed crystal layer 46 on the surface of the photosensitive PI film layer 14, in the via hole 42 and in the line gap 44, thereby obtaining a prefabricated packaging substrate;
  • Step S40 applying a dry film or photoresist 48 on the surface of the prefabricated packaging substrate, and forming a pattern by exposure and development, wherein positions where holes and long lines need to be filled are exposed;
  • Step S50 electroplating the developed prefabricated packaging substrate so that the electroplating layer 50 covers the positions where the holes and long lines need to be filled;
  • Step S55 after the electroplating is completed, the dry film or photoresist 48 of the prefabricated packaging substrate is removed, and then a portion of the conductive seed crystal layer 46 is removed by flash etching to realize the interconnection between the circuit in the photosensitive PI film layer 14 and the circuit of the lower substrate;
  • Step S60 Repeat steps S10 to S55 one or more times to provide one or more photosensitive PI film layers 14 to form the transfer layer portion 40, thereby manufacturing a new packaging substrate including a chipset interconnection function.
  • a build-up layer may be performed on the transfer layer portion 40 of the obtained novel package substrate to provide one or more additional layers of substrate circuits.
  • a package substrate 10 including a substrate circuit (not shown) is provided.
  • the package substrate 10 is a laminate, which includes one or more layers. In each layer of the substrate 10, a single-sided or double-sided substrate circuit is selectively printed. As required, electrical interconnection of the substrate circuits between the layers of the substrate 10 can be formed.
  • the package substrate 10 and the substrate circuits prepared thereon are manufactured using an existing substrate production process. For the sake of simplicity, this is not described in detail.
  • a photosensitive PI film layer 14 is provided on the surface of the packaging substrate 10.
  • the surface generally refers to the surface of the packaging substrate 10 to be welded to the chip, such as the upper surface, the lower surface, or both of the packaging substrate.
  • Figure 4 shows a schematic cross-sectional view of a photosensitive PI film layer 14 coated on a completed conventional process packaging substrate according to an embodiment of the present invention.
  • the photosensitive PI film layer refers to a photosensitive insulating material substrate that forms the transfer layer portion 40, which includes but is not limited to a photosensitive PI film layer, such as a PIC adhesive film, a PSPI slurry, etc.
  • the photosensitive PI film layer 14 can be provided by hot pressing (for example, vacuum hot pressing) the photosensitive PI film onto the surface of the packaging substrate 10.
  • the photosensitive PI film is a dry film material that can be heat-bonded, such as a PIC adhesive film.
  • the photosensitive PI film can be attached to the surface of the substrate after exposure, development, and heat drying.
  • the circuit with the required resolution can be produced by adopting the novel packaging substrate manufacturing method according to the second exemplary embodiment of the present invention mentioned below.
  • the photosensitive PI film layer 14 can be provided by directly coating the photosensitive PI slurry onto the surface of the packaging substrate 10.
  • the photosensitive PI slurry such as PSPI slurry, has the property of being coatable and drying.
  • the photosensitive PI slurry can be attached to the surface of the substrate after exposure, development and heat drying.
  • the circuit with the required resolution can be produced by adopting the novel packaging substrate manufacturing method according to the second exemplary embodiment of the present invention mentioned below.
  • a heat baking process can be used to promote the formation of the photosensitive PI film layer 14 as needed.
  • step S20 the photosensitive PI film layer 14 is exposed and developed to form vias 42 and line gaps 44, and is shaped by curing.
  • Figure 5 shows a schematic cross-sectional view of the photosensitive PI film layer 14 on the packaging substrate 10 after exposure, development and curing according to an embodiment of the present invention.
  • the photosensitive PI film layer 14 is directly exposed through a film, a mask or an LDI.
  • the photosensitive PI film layer 14 is developed to form vias 42 with a diameter of more than 1 ⁇ m, and line gaps 44 with a size of more than hundreds of nanometers.
  • the photosensitive PI film layer is also shaped by high-temperature curing.
  • the photosensitive PI film layer 14 is dried and cured, so that the photosensitive PI material undergoes a polymerization reaction, thereby maintaining the stability of the characteristics.
  • a conductive seed layer 46 is formed on the surface of the photosensitive PI film layer 14, in the via 42 and in the line gap 44, thereby obtaining a prefabricated packaging substrate.
  • FIG6 shows a schematic cross-sectional view of forming a conductive seed layer 46 on a packaging substrate 10 according to an embodiment of the present invention.
  • a conductive seed layer 46 is formed on the surface of the photosensitive PI film layer 14, in the via 42 and in the line gap 44 by chemical copper plating, thereby obtaining a prefabricated packaging substrate.
  • a conductive seed layer 46 is formed on the photosensitive PI film layer 14, in the via 42 and in the line gap 44 by sputtering.
  • a conductive seed layer 46 is formed on the photosensitive PI film layer 14, in the via 42 and in the line gap 44 by ion implantation plating.
  • the thickness of the conductive seed layer is in the range of 80nm-2000nm.
  • ion implantation plating can preferably be used.
  • a dry film or photoresist 48 is applied on the surface of the prefabricated packaging substrate, and a pattern is formed by exposure and development, wherein the positions where holes and long lines need to be filled are exposed.
  • FIG. 7 shows a schematic cross-sectional view of applying a dry film or photoresist 48 on the surface of a prefabricated packaging substrate, after exposure and development according to an embodiment of the present invention.
  • a dry film is attached to the surface of the prefabricated packaging substrate to form a circuit pattern by exposure and development.
  • the circuit pattern can be formed by applying a liquid photoresist to the surface of the prefabricated packaging substrate. The circuit pattern thus formed is exposed at the positions where holes and long lines need to be filled for electroplating.
  • the developed prefabricated package substrate is electroplated so that the electroplated layer 50 covers the holes to be filled and The position of the long line.
  • the prefabricated package substrate needs to be pre-treated before electroplating.
  • it may include surface cleaning treatment, for example, wiping the surface of the substrate with gauze soaked in alcohol to remove dirt attached thereto, or placing the substrate in a cleaning solution and cleaning it with ultrasound.
  • Figure 8 shows a schematic cross-sectional view of forming an electroplating layer 50 on a prefabricated package substrate according to an embodiment of the present invention.
  • the prefabricated package substrate revealing the circuit pattern is electroplated, such as copper plating, so that the electroplating layer 50 covers the exposed circuit pattern portion, so that the thickness of the electroplating layer 50 is increased to the required thickness.
  • grinding can be used to polish so that the copper thickness meets the uniformity.
  • the grinding process or step can be arranged after electroplating and before the film stripping step mentioned below.
  • step S55 the dry film or photoresist 48 of the prefabricated packaging substrate is stripped after the electroplating is completed, and then flash etching is performed to remove part of the conductive seed crystal layer 46, so as to realize the circuit in the photosensitive PI film layer 14 and the interconnection with the circuit of the lower substrate.
  • FIG9 shows a schematic cross-sectional view of a prefabricated packaging substrate after film stripping and flash etching according to an embodiment of the present invention.
  • an alkali solution or an organic film stripping solution is used to strip the dry film or photoresist 48 of the electroplated prefabricated packaging substrate.
  • flash etching is used to etch the non-electroplated thickened conductive seed crystal layer 46 to obtain the desired pattern.
  • the circuit of the desired pattern and its interconnection with the lower hole are realized.
  • steps S10 to S55 are repeated one or more times to provide one or more photosensitive PI film layers 14 to form a transfer layer portion 40, thereby obtaining a new packaging substrate including a chipset interconnection function.
  • Figure 10 shows a schematic cross-sectional view of a new packaging substrate according to an embodiment of the present invention.
  • the new packaging substrate includes a packaging substrate 10 and a transfer layer portion 40 integrally integrated thereon.
  • the transfer layer portion 40 includes 2 layers of fine circuits to realize the function of a transfer board.
  • the transfer layer portion 40 may include one or more layers of fine circuits to realize the function of a transfer board.
  • the transfer layer portion 40 serves as an intermediate layer between the Die and the packaging substrate, and plays a role in interconnecting the Die and the packaging substrate, thereby realizing the function of a transfer board in the conventional sense.
  • the thickness of the conductive seed crystal layer is closely related to the pre-treatment, electroplating and flash etching before the post-process electroplating.
  • the thickness of the conductive seed crystal layer of the present invention is in the range of 80nm-2000nm. If the thickness of the conductive seed crystal layer is too thin, it may be etched away by the electroplating pre-treatment or electroplating process, and cannot play the role of conductivity in the electroplating process; if the thickness is too thick, more flash etching will be required in the end, which may cause the line width and line spacing to fail to meet expectations.
  • the thickness of the conductive seed crystal layer is strongly related to the processes of the three steps of electroplating pre-treatment, electroplating and flash etching, its thickness is limited to the range of 80nm-2000nm.
  • the thickness of the conductive seed crystal layer according to the present invention is 800nm.
  • the metal forming the conductive seed crystal layer may be one or more of Cu, Ta, TaN/Ta alloy, TiN, TiW, Cr, Ti, Mo, MoTi alloy, Ni, NiCu, or a combination thereof.
  • the conductive seed crystal layer is formed by chemical copper plating, and preferably metal Cu is used to form a single-layer conductive seed crystal layer.
  • the conductive seed crystal layer is formed by Sputter or other dry plating methods, other metals except Cu can be selected as the bottom metal to form a two-layer structure of the conductive seed layer with Cu.
  • a two-layer structure of the bottom Ni and the upper Cu can be used to form the conductive seed layer, and the total thickness can be 800nm.
  • the cost of the Sputter method it is also possible to deposit a thinner Ni/Cu to a thickness of 150nm, and then electroplating to thicken it to 800nm. This thickness can be adjusted according to production capacity, cost and process window.
  • the novel packaging substrate manufacturing method may generally include the following steps:
  • Step S000 providing a packaging substrate 100 including a substrate circuit (not shown);
  • Step S100 providing a non-photosensitive PI film layer 140 on the surface of the packaging substrate 100;
  • Step S200 applying a dry film or photoresist 480 on the non-photosensitive PI film layer 140 for exposure and development to form via holes 420 and line gaps 440;
  • Step S300 using dry etching to clean the position on the non-photosensitive PI film layer 140 that is not protected by the dry film or the photoresist 480;
  • Step S350 using a film stripping process to remove the dry film or photoresist 480 on the non-photosensitive PI film layer 140;
  • Step S400 forming a conductive seed crystal layer 460 on the surface of the non-photosensitive PI film layer 140, in the via hole 420 and in the line gap 440, thereby obtaining a prefabricated packaging substrate;
  • Step S500 applying a dry film or photoresist 580 on the surface of the prefabricated packaging substrate, and forming a pattern by exposure and development, wherein positions where holes and long lines need to be filled are exposed;
  • Step S600 electroplating the developed prefabricated packaging substrate so that the electroplating layer 500 covers the position where the hole needs to be filled and the long line needs to be filled;
  • Step S650 after the electroplating is completed, the dry film or photoresist 580 of the prefabricated packaging substrate is removed, and then a portion of the conductive seed layer 460 is removed by flash etching to realize the interconnection between the circuit in the non-photosensitive PI film layer 140 and the circuit of the lower substrate; and
  • Step S700 repeating steps S100 to S650 one or more times to provide one or more non-photosensitive PI film layers 140 to form the transfer layer portion 400, thereby manufacturing a new packaging substrate including a chipset interconnection function.
  • a build-up layer may be performed on the transfer layer portion 400 of the obtained novel package substrate to provide one or more additional layers of substrate circuits.
  • step S000 a package substrate 100 including a substrate circuit (not shown) is provided.
  • the package substrate 100 is similar to the package substrate 10 mentioned above. For the sake of simplicity, a detailed description is omitted.
  • a non-photosensitive PI film layer 140 is provided on the surface of the package substrate 100.
  • the surface generally refers to the surface of the package substrate 100 to be soldered to the chip, such as the upper surface, the lower surface, or the lower surface of the package substrate.
  • Figure 11 shows a schematic cross-sectional view of a non-photosensitive PI film layer 140 coated on a completed conventional process packaging substrate according to an embodiment of the present invention.
  • the non-photosensitive PI film layer 140 can be provided by hot pressing (e.g., vacuum hot pressing) the non-photosensitive PI film onto the surface of the packaging substrate 100.
  • the non-photosensitive PI film is a dry film material that can be heat-pressed, such as a non-photosensitive PI material that can be pressed.
  • the non-photosensitive PI film can be attached to the surface of the substrate after heat drying.
  • the non-photosensitive PI film layer 140 can be provided by coating a non-photosensitive coating film on the surface of the packaging substrate 100.
  • the non-photosensitive coating film such as a non-photosensitive PI slurry, has a coating and drying property.
  • the non-photosensitive PI slurry can be attached to the surface of the substrate after heat drying.
  • the PI film layers 14 and 140 are not limited to the PI dry film and PI slurry mentioned in the text, and slurries and dry films of photosensitive or non-photosensitive acrylic materials can also be used. This part of the material is also widely used as a flat layer material in display panels, or it can be other organic materials that can be coated and cured.
  • a dry film or photoresist 480 is applied to the non-photosensitive PI film layer 140 for exposure and development to form vias 420 and line gaps 440.
  • FIG. 12 shows a schematic cross-sectional view of a non-photosensitive PI film layer 140 on a packaging substrate 100 after exposure and development according to an embodiment of the present invention. As an example, exposure is performed after photoresist is coated on the non-photosensitive PI film layer 140 or a dry film is directly attached. After exposure, a development process is performed on the photoresist or dry film, thereby forming a via 420 with a diameter of more than 1 ⁇ m and a line gap 440 with a size of more than hundreds of nanometers.
  • step S300 the non-photosensitive PI film layer 140 that is not protected by the dry film or photoresist 480 is etched clean by dry etching.
  • the etching gas used for dry etching may be carbon tetrafluoride (CF 4 ) and oxygen (O 2 ).
  • FIG. 13 shows a schematic cross-sectional view of the non-photosensitive PI film layer 140 on the packaging substrate 100 after dry etching according to an embodiment of the present invention. As shown in the figure, the position on the non-photosensitive PI film layer 140 that is not protected by the dry film or photoresist has been etched clean, exposing part of the surface of the packaging substrate 100.
  • the via 420 and the line gap 440 are deepened by etching and reach the surface of the packaging substrate 100.
  • PI etching is not limited to dry etching.
  • wet etching can also be used to remove the non-photosensitive PI film layer 140 under conditions where accuracy permits.
  • a film stripping process is used to remove the dry film or photoresist 480 on the non-photosensitive PI film layer 140.
  • NaOH and an organic film stripping solution are selected for the film stripping operation according to the type of dry film or photoresist.
  • Figure 14 shows a schematic cross-sectional view of a non-photosensitive PI film layer 140 covered with a dry film or photoresist 480 after film stripping according to an embodiment of the present invention. As shown in the figure, the dry film or photoresist covering the non-photosensitive PI film layer 140 has been removed. Similar to that shown in Figure 5, a via 420 with a diameter of more than 1 ⁇ m and a line gap 440 with a size of more than hundreds of nanometers are formed in the non-photosensitive PI film layer 140.
  • a conductive seed crystal layer 460 is formed on the surface of the non-photosensitive PI film layer 140, in the via hole 420 and in the line gap 440, thereby obtaining a prefabricated packaging substrate.
  • FIG. 15 shows a schematic cross-sectional view of forming a conductive seed crystal layer 460 in the non-photosensitive PI film layer 140 on the packaging substrate 100 according to an embodiment of the present invention.
  • chemical copper plating is used.
  • a conductive seed crystal layer 460 is formed on the surface of the non-photosensitive PI film layer 140, in the via hole 420, and in the line gap 440 by a sputtering method, thereby obtaining a prefabricated packaging substrate.
  • a conductive seed crystal layer 460 is formed on the non-photosensitive PI film layer 140, in the via hole 420, and in the line gap 440 by a sputtering method. In another embodiment, a conductive seed crystal layer 460 is formed on the non-photosensitive PI film layer 140, in the via hole 420, and in the line gap 440 by an ion implantation plating method. Preferably, the thickness of the conductive seed crystal layer is in the range of 80nm-2000nm.
  • a dry film or photoresist 580 is applied on the surface of the prefabricated packaging substrate, and a pattern is formed by exposure and development, wherein the positions where holes and long lines need to be filled are exposed.
  • FIG. 16 shows a schematic cross-sectional view of applying a dry film or photoresist 480 on the surface of a prefabricated packaging substrate, after exposure and development according to an embodiment of the present invention.
  • a dry film is attached to the surface of a prefabricated packaging substrate to form a circuit pattern by exposure and development.
  • the circuit pattern can be formed by applying a liquid photoresist to the surface of the prefabricated packaging substrate. The circuit pattern thus formed is exposed at the positions where holes and long lines need to be filled for electroplating.
  • step S600 the developed prefabricated package substrate is electroplated so that the electroplating layer 500 covers the position where the holes and long lines need to be filled.
  • the prefabricated package substrate needs to be pre-treated before electroplating.
  • a surface cleaning treatment may be included, for example, wiping the surface of the substrate with a gauze soaked in alcohol to remove the dirt attached thereto, or placing the substrate in a cleaning solution and cleaning it with ultrasound.
  • Figure 17 shows a schematic cross-sectional view of forming an electroplating layer 500 on a prefabricated package substrate according to an embodiment of the present invention.
  • the prefabricated package substrate with a circuit pattern exposed is electroplated, such as copper plating, so that the electroplating layer 500 covers the exposed circuit pattern portion, so that the thickness of the electroplating layer 500 is increased to the required thickness.
  • grinding can be used to polish so that the copper thickness meets the uniformity.
  • the grinding process or step can be arranged after electroplating and before the film stripping step mentioned below.
  • step S650 the dry film or photoresist 580 of the prefabricated packaging substrate is stripped after the electroplating is completed, and then flash etching is performed to remove part of the conductive seed crystal layer 460, so as to realize the circuit in the non-photosensitive PI film layer 140 and the interconnection with the circuit of the lower substrate.
  • FIG18 shows a schematic cross-sectional view of a prefabricated packaging substrate after film stripping and flash etching according to an embodiment of the present invention.
  • an alkali solution or an organic film stripping solution is used to strip the dry film or photoresist 580 of the electroplated prefabricated packaging substrate.
  • flash etching is used to etch the non-electroplated thickened conductive seed crystal layer 460 to obtain the desired pattern.
  • the circuit of the desired pattern and its interconnection with the lower hole are realized.
  • steps S100 to S650 are repeated one or more times to provide one or more non-photosensitive PI film layers 140 to form a transfer layer portion 400, thereby obtaining a new packaging substrate including a chipset interconnection function.
  • FIG. 19 shows a schematic cross-sectional view of a new packaging substrate according to an embodiment of the present invention.
  • the new packaging substrate includes a packaging substrate 100 and a transfer layer portion 400 integrally integrated thereon.
  • the transfer layer portion 400 includes 2 Of course, as required, the transfer layer portion 400 may include one or more layers of fine circuits to realize the function of the transfer board.
  • the transfer layer portion 40 serves as an intermediate layer between the die and the package substrate, interconnecting the die and the package substrate, thereby realizing the function of the transfer board in the conventional sense.
  • the substrate layers with chipset interconnections mentioned in the present invention are not limited to the last few layers of the substrate, but may also be located in the first layers of the substrate, in the middle layers, or in any layers of the substrate as required. In the present invention, only the layers where the conventional adapter board functions are located are used for explanation.
  • the present invention can also bury the circuit in the middle of the PI film by opening the window of the PI film. This has the advantage of reducing the thickness of the product compared with the traditional process. Moreover, because the PI material is used in the present invention, it has a certain fluidity and surface flattening function. Therefore, the present invention has the advantage of making the circuit more refined.
  • the novel packaging substrate of the present invention not only combines the adapter plate and the substrate into one, but also reduces the number of solder ball implants and soldering.
  • the novel packaging substrate of the present invention not only reduces signal loss and signal reflection in signal transmission, but also reduces the influence of potential alpha rays in the solder balls on high-frequency signals, thereby greatly helping the transmission of high-frequency signals.

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Abstract

本发明涉及具有转接板功能的新型封装基板及其制作方法。具体而言，一种具有转接板功能的新型封装基板，包括含有基板线路的封装基板和一体地集成在封装基板上的转接层部分。相应地，在转接层部分上和/或其中也提供有精细线路。根据需要，该精细线路与封装基板的基板线路形成电连接，以便导通封装基板与附接在转接层部分上的裸芯片之间的电连接。由此，转接层部分起到将裸芯片与本发明的新型封装基板直接互连的作用，从而实现了常规意义上的转接板功能。此外，还公开了用于制作具有转接板功能的新型封装基板的方法。

Description

具有转接板功能的新型封装基板及其制作方法 技术领域
本发明涉及集成电路(Integrated Circuit，简称IC)封装基板领域。具体地，本发明涉及结合感光/非感光绝缘材料作为介质层，以铜等金属材料作为导电线，由此制作具有多层更精细线路和转接板(Interposer)功能的新型封装基板。此外，本发明还涉及用于制作此种新型封装基板的方法。
背景技术
当前，现有的封装基板(或称为载板)含有精度为数微米到数十微米的线路，而芯片例如裸芯片(或裸片，Die)所含有的则是纳米级的线路。为了实现封装基板与Die的电性连接，通常需要转接板置于二者之间以实现在精度上属于不同数量级线路之间的转换连接的功能。
转接板，例如硅转接板，作为Die与Die互连以及Die与封装基板互连的中介层，起到将Die中的线路和封装基板中的线路相连接的重要作用。这就要求转接板具有精细线路和连接基板的硅通孔(Through Silicon Via，简称TSV)，如图1所示。然而，TSV工艺不但成本较高，而且转接板基层因由硅片(或玻璃)制成也使得其成本高昂。此外，由于采用了半导体晶圆设备制作，硅转接板尺寸也有限制，无法制作较大尺寸。这些问题都成为转接板进一步应用的阻碍。
为了改善硅转接板的技术限制和高成本的问题，Intel提出了EMIB(嵌入式多裸片互连桥接，Embedded Multi-Die Interconnect Bridge)技术，该技术将Die-Die桥接的较细线宽部分采用一个较小的硅桥实现，并将这部分嵌入在基板内，如图2所示。与硅转接板相比，EMIB硅桥缩小了尺寸，降低了成本，也提升了良率。然而，该技术增加了将EMIB硅桥预埋到基板中的工艺，而且仍采用半导体晶圆工艺制作硅桥，因此不管在成本上还是良率上仍存在亟待改善的问题。
发明内容
为了更好地解决硅转接板和硅桥所存在的问题，使Die与封装基板及Die之间互连的设计更为自由，同时将封装基板的布线推向更为精细的领域以适合未来更精细线路封装的需求，本发明提出了一种具有转接板功能的新型封装基板。此种基板不需要单独的转接板或者硅桥连接，而是可直接与一个或者多个Die连接，并且将基板的线宽线距推向亚微米的量级。具体地，本发明对于传统的基板材料例如BF(例如ABF、NBF等)、BT、FR4等即可 完成硅转接板或硅桥的功能，同时不需要使用硅片(或玻璃)。
在一个实施例中，通过在诸如BF、BT、FR4等的传统基板材料上涂布绝缘材料浆料例如聚酰亚胺(PI)浆料或覆压绝缘材料膜例如PI膜，以光刻的方法或者刻蚀的方法制造出一种具有芯片基板间及芯片间信号互连性能的基板。此种基板在线路上具有甚至亚微米的超精细线宽，从而满足IC对高精细的需求，减少了众多的转接线路和锡球焊接，同时工艺实现起来也更为成熟，满足芯片组的信号传输距离短、多芯片间的快速信号传输、基板与各芯片间快速信号传输、低成本等要求。
一方面，本发明提出了一种新型的封装基板制作方法。首先，提供包含一层或多层的诸如BT、BF、FR4等的基板，在基板的每一层中提供有基板线路。然后，在提供有基板线路的基板上，对于在基板上起到芯片与基板连接或者芯片间互连功能的层涂布PI浆料或者压合PI膜以提供一层或多层PI膜层来形成转接层部分。由此，转接层部分连同与其一体地集成的封装基板共同构成了本发明的新型封装基板。可选地，转接层部分可以是基板的最上数层、基板的最下数层、基板的中间数层，或者它们的组合。在转接层部分中形成有满足需求的线宽例如数百纳米以上的线路以及互连用的过孔。因线路已经非常精细，故在此采用全加成法或半加成法来完成，其中，加成法或半加成法的种子层可采用化学镀铜、Sputter或者离子注入镀膜的方式完成。最后，在完成所需线路层和过孔后，可将本发明的新型封装基板与芯片例如Die进行最终的锡球焊接。在现有基板生产流程不变的前提下，本发明提升了布线能力性能，并且具备转接板的功能，同时在制造方法上提供了比现有转接板的工艺更为简便可靠和成熟的方法，并且取代了昂贵的硅片。
另一方面，本发明还提供了一种新型封装基板加工方法和结构。具体地，本发明的加工方法不使用传统的硅基板，减少了至少一次锡球焊接的次数，并且减少了信号传输通道，从而进一步满足或提升了比现有芯片组更高的信号传输速度和更少的信号损失。此外，本发明通过在转接层部分上开槽和/或开孔，融入了RDL(Re-distributed layer，重布线层)工艺和高精细曝光及蚀刻工艺，能够制造线路精细度非常高的基板，从而实现了在普通基板上直接采用RDL工艺制作转接板功能层，将封装基板行业的线宽线路提升到数百纳米的量级，满足了基板向更精细线宽的发展方向，突破了现有封装基板止步在数微米线宽线路的瓶颈。与现有硅片转接板的工艺相比，本发明更为经济。
根据本发明，提供了一种具有转接板功能的新型封装基板，包括：封装基板，所述封装基板含有基板线路；以及一体地集成在所述封装基板上的转接层部分，在所述转接层部分上和/或其中提供有精细线路；其中，所述转接层部分的精细线路与所述封装基板的基板 线路形成电连接，以便导通所述封装基板与附接在所述转接层部分上的芯片元件之间的电连接。在一个实施例中，所述转接层部分包括感光PI胶膜或者感光PI浆料。在一个实施例中，所述转接层部分包括非感光PI胶膜或者非感光PI浆料。在一个实施例中，所述封装基板由BF、BT、FR4中的一种或多种材料构成。在一个实施例中，所述转接层部分包括开槽和/或开孔以制作连接线路。
根据本发明，还提供了一种制作具有转接板功能的新型封装基板的方法，所述方法包括以下步骤：
提供包含基板线路的封装基板；
在所述封装基板的表面上提供感光PI膜层；
在所述感光PI膜层上通过曝光和显影而形成过孔和线间隙；
在所述感光PI膜层的表面上、所述过孔内及所述线间隙内形成导电籽晶层，由此得到预制封装基板；
在所述预制封装基板的表面上施加干膜或光刻胶以形成线路图案，其中需要填孔和布置线路的位置均被暴露出来；
将所述预制封装基板进行电镀，使得电镀层覆盖所述需要填孔和布置线路的位置；
从所述预制封装基板褪掉所述干膜或光刻胶并且闪蚀以去掉所述导电籽晶层的露出的部分，从而实现所述感光PI膜层的线路和与所述封装基板的基板线路的互连。
在一个实施例中，重复所述提供感光PI膜层的步骤到所述褪掉所述干膜或光刻胶并且闪蚀的步骤一次或多次以提供一个或多个感光PI膜层来形成所述新型封装基板的转接层部分。在一个实施例中，所述转接层部分形成包含一层或多层精细线路的转接功能层。在一个实施例中，所述导电籽晶层的厚度为80nm-2000nm。
根据本发明，还提供了一种制作具有转接板功能的新型封装基板的方法，所述方法包括以下步骤：
提供包含基板线路的封装基板；
在所述封装基板的表面上提供非感光PI膜层；
在所述非感光PI膜层施加第一干膜或光刻胶进行曝光和显影而形成过孔和线间隙；
采用蚀刻将所述非感光PI膜层上未受所述第一干膜或光刻胶保护的位置刻蚀去除；
采用退膜工艺，去除所述非感光PI膜层上的第一干膜或光刻胶；
在所述非感光PI膜层的表面上、过孔内及线间隙内形成导电籽晶层，由此得到预制封装基板；
在所述预制封装基板的表面上施加第二干膜或光刻胶，通过曝光显影方式来形成图案，其中需要填孔和布置线路的位置均被暴露出来；
将所述预制封装基板进行电镀，使得电镀层覆盖所述需要填孔和布置线路的位置；
从所述预制封装基板褪掉所述第二干膜或光刻胶并且闪蚀以去掉所述导电籽晶层的露出的部分，从而实现所述非感光PI膜层的线路与所述封装基板的基板线路的互连。
在一个实施例中，重复所述提供非感光PI膜层的步骤到所述褪掉所述第二干膜或光刻胶并且闪蚀的步骤一次或多次以提供一个或多个非感光PI膜层来形成所述新型封装基板的转接层部分。在一个实施例中，所述转接层部分形成包含一层或多层精细线路的转接功能层。所述导电籽晶层的厚度为80nm-2000nm。
对于上述技术方案的变型和改进在本发明的范围和精神内，且可在本文中进一步描述。
附图说明
下面通过参考附图并结合实例具体地描述本发明，本发明的优点和实现方式将会更加明显，其中附图所示内容仅用于对本发明的解释说明，而不构成对本发明的任何意义上的限制，附图仅是示意性的，并非严格地按比例绘制。在附图中：
图1是根据现有技术的采用硅转接板互连Die和封装基板的示意性截面图；
图2是根据现有技术的采用EMIB互连Die和封装基板的示意性截面图；
图3是根据本发明的一个实施例的具有转接板功能的新型封装基板的示意性截面图；
图4至图10是根据本发明的第一实施例的方法制作新型封装基板在不同步骤的示意性截面图；
图11至图19是根据本发明的第二实施例的方法制作新型封装基板在不同步骤的示意性截面图；
图20是根据本发明的第一示例性实施例的新型封装基板制作方法的流程图；以及
图21是根据本发明的第二示例性实施例的新型封装基板制作方法的流程图。
具体实施方式
现将详细地参照本发明的实施例，其中的一个或多个实例在附图中示出。各实例均是以阐述本发明的方式提供的，而并不限制本发明。实际上，本领域的技术人员很清楚，在不脱离本发明的范围或精神的情况下，可在本发明中作出各种修改和变型。例如，示为或描述为一个实施例的一部分的特征可结合另一实施例来使用，以产生又一个实施例。因此，期望的是，本发明包含归入所附权利要求及其等同方案范围内的这些修改和变型。
图3示出了根据本发明的一个实施例的具有转接板功能的新型封装基板的示意性截面图。新型封装基板主要包括封装基板10，以及一体地集成在封装基板10上的转接层部分40。在一个实施例中，封装基板10是一种层压板，其包含一层或多层。在基板10的每一层中，有选择地进行孔加工、化学镀铜、电镀铜、蚀刻等加工，得到单面或双面的基板线路。根据需要，可形成基板10的各个层之间基板线路的电性互连。相应地，转接层部分40也包含一层或多层，在转接层部分40的每层中提供有精细线路。根据需要，转接层部分40中的精细线路与封装基板10的基板线路形成电连接，以便导通封装基板10与附接在转接层部分40上的裸芯片例如第一Die 1和第二Die 2之间的电连接。由此，转接层部分40作为Die1、2与封装基板10的中介层，起到将Die 1、2与封装基板10互连的作用，从而实现了常规意义上的转接板功能。在一个实施例中，转接层部分40包括绝缘材料基底。优选地，采用PI膜层作为绝缘材料基底来制作转接层部分。相比于其他绝缘材料，PI材料具有一定的流动性和表面的平坦化功能，因而具有可将线路制作得更为精细的优点。
此外，在一个实施例中，Die 1、2分别采用锡球焊接的方式连接到新型封装基板、尤其是转接层部分40。优选地，植锡球开窗所采用的方式可采用本文提到的PI膜开窗。任选地，也可采用传统的绿油开窗来进行锡球焊接。备选地，Die 1、2与转接层部分40的连接还可采用具有Au ball的导电膜连接方式，例如ACF特性的材料。这种方法也广泛地用于显示模组IC或FPC与元器件互连。
如图中所示，尽管示出的是2个芯片Die互连，但这仅是示意性的。实际上，根据本发明，可采用单个芯片Die与基板连接，也可采用多个芯片Die互连。任选地，可采用多个不同种类和不同尺寸的芯片Die互连。任选地，可采用基板的双面均与芯片Die相连。而且，在图中，芯片Die管脚与具有转接功能基板的线路仅是示意性的，其可具有不同密度和不同尺寸。此外，尽管图3中示出的是两个相似的芯片Die，但实际上这些芯片Die具有多种可能性。例如，芯片Die包括但不限于CPU、GPU、ASIC等具有运算功能的芯片中的任何一种。当存在其他互连需求时，对应地可采用其他的芯片组或者线路板，而不采用芯片Die。
相比于现有的基板生产流程，本发明的新型封装基板不需要单独的转接板或者硅桥连接，而是可直接地与Die连接，并且能够将基板的线宽线距提高至亚微米的量级。由此，本发明的新型封装基板不但提升了布线能力性能，而且具备转接板的功能，同时无需采用昂贵的硅片。
接下来，将描述根据本发明的新型封装基板的制作方法的一些实施例。
图20是根据本发明的第一示例性实施例的新型封装基板制作方法的流程图。该新型封装基板制作方法大体可包括以下步骤：
步骤S00：提供包含基板线路(未示出)的封装基板10；
步骤S10：在封装基板10的表面上提供感光PI膜层14；
步骤S20：将感光PI膜层14通过曝光和显影而形成过孔42和线间隙44，并且通过固化定形；
步骤S30：在感光PI膜层14的表面上、过孔42内及线间隙44内形成导电籽晶层46，由此得到预制封装基板；
步骤S40：在预制封装基板的表面上施加干膜或光刻胶48，通过曝光显影方式来形成图案，其中需要填孔和长线的位置均被暴露出来；
步骤S50：将显影后的预制封装基板进行电镀，使得电镀层50覆盖需要填孔和长线的位置；
步骤S55：将预制封装基板在电镀完成后褪掉干膜或光刻胶48，进而闪蚀以去掉部分导电籽晶层46，实现感光PI膜层14中的线路和与下层基板线路的互连；
步骤S60：重复步骤S10到S55一次或多次以提供一个或多个感光PI膜层14来形成转接层部分40，从而制得包含芯片组互连功能的新型封装基板。
任选地，在步骤S60之后，可在所得新型封装基板的转接层部分40上进行增层以提供一层或多层附加的基板线路。
在步骤S00中，提供包含基板线路(未示出)的封装基板10。封装基板10是一种层压板，其包含一层或多层。在基板10的每一层中，有选择地印制有单面或双面的基板线路。根据需要，可形成基板10的各个层之间基板线路的电性互连。封装基板10及制备在其上的基板线路采用现有的基板生产流程进行制作。为简明起见，对此不作详细描述。
在步骤S10中，在封装基板10的表面上提供感光PI膜层14。作为示例，该表面通常是指封装基板10的待与芯片焊接的表面，例如封装基板的上表面、下表面，或者二者。图4示出了根据本发明的一个实施例在完成的常规制程封装基板上涂布有感光PI膜层14的示意性截面图。在文中，感光PI膜层指代的是形成转接层部分40的感光绝缘材料基底，其包括但不限于感光PI膜层，例如PIC胶膜、PSPI浆料等。在一个实施例中，提供感光PI膜层14可采用将感光PI膜热压(例如，真空热压)到封装基板10的表面上。感光PI膜是具有可热压合性的干膜材料，例如PIC胶膜。在一个实施例中，感光PI膜经过曝光显影及热烘干后可附着在基板的表面上。然而，当感光PI膜的解析特性无法满足曝光解析能力时， 则可采用下文提到的根据本发明第二示例性实施例的新型封装基板制作方法而制作出所需解析度的线路。备选地，提供感光PI膜层14可采用将感光PI浆料直接涂布到封装基板10的表面上。感光PI浆料，例如PSPI浆料，具有可涂布烘干特性。在一个实施例中，感光PI浆料经过曝光显影及热烘干后可附着在基板的表面上。然而，当感光PI浆料的解析特性无法满足曝光解析能力时，则可采用下文提到的根据本发明第二示例性实施例的新型封装基板制作方法而制作出所需解析度的线路。优选地，根据需要，可采用热烘工艺来促进形成感光PI膜层14。
在步骤S20中，将感光PI膜层14通过曝光和显影而形成过孔42和线间隙44，并且通过固化定形。图5示出了根据本发明的一个实施例在封装基板10上的感光PI膜层14经曝光显影固化后的示意性截面图。作为示例，感光PI膜层14通过菲林、掩模版或者LDI直接曝光。在曝光之后，感光PI膜层14通过显影来形成直径为1μm以上的过孔42，以及形成尺寸为数百纳米以上的线间隙44。在一个实施例中，感光PI膜层还通过高温固化来定形。例如，在一个实施例中，感光PI膜层14经烘干固化，使得感光PI材料发生聚合反应，从而保持特性的稳定。
在步骤S30中，在感光PI膜层14的表面上、过孔42内及线间隙44内形成导电籽晶层46，由此得到预制封装基板。图6示出了根据本发明的一个实施例在封装基板10上形成导电籽晶层46的示意性截面图。作为示例，以化学镀铜的方式在感光PI膜层14的表面上、过孔42内以及线间隙44内形成导电籽晶层46，由此得到预制封装基板。在另一实施例中，采用溅射(Sputter)的方式在感光PI膜层14上、过孔42内以及线间隙44内形成导电籽晶层46。在又一实施例中，采用离子注入镀膜的方式在感光PI膜层14上、过孔42内以及线间隙44内形成导电籽晶层46。优选地，导电籽晶层的厚度在80nm-2000nm的范围。在本发明中，若由于粗糙度或者材料原因导致结合力不足而无法量产时，优选地可采用离子注入镀膜的方式。
在步骤S40中，在预制封装基板的表面上施加干膜或光刻胶48，通过曝光显影方式来形成图案，其中需要填孔和长线的位置均被暴露出来。图7示出了根据本发明的一个实施例在预制封装基板的表面上施加干膜或光刻胶48、经曝光、显影后的示意性截面图。作为示例，将干膜附贴到预制封装基板的表面上以通过曝光显影方式来形成线路图案。备选地，该线路图案可通过将液态光刻胶涂覆到预制封装基板的表面上来形成。由此形成的线路图案在需要填孔和长线的位置均被显露出来，以便电镀处理。
在步骤S50中，将显影后的预制封装基板进行电镀，使得电镀层50覆盖需要填孔和 长线的位置。优选地，预制封装基板在电镀之前需要进行前处理。作为前处理的方法，可包括表面清洁处理，例如，用浸渍过酒精的纱布擦拭基板的表面以除去上面附着的脏污，或者将基板放入清洁液中并采用超声波进行清洗。图8示出了根据本发明的一个实施例在预制封装基板上形成电镀层50的示意性截面图。作为示例，将显露线路图案的预制封装基板进行电镀例如镀铜，以将电镀层50覆盖露出的线路图案部分，使得电镀层50的厚度增加至所需要的厚度。在本发明的一个实施例中，电镀后的铜厚均匀性如果无法满足产品的要求，则可采用研磨的形式进行打磨，以使铜厚满足均匀性。任选地，该研磨工艺或步骤可安排在电镀之后且在下文提到的退膜步骤之前。
在步骤S55中，将预制封装基板在电镀完成后褪掉干膜或光刻胶48，进而闪蚀以去掉部分导电籽晶层46，实现感光PI膜层14中的线路和与下层基板线路的互连。图9示出了根据本发明的一个实施例在预制封装基板经退膜、闪蚀后的示意性截面图。作为示例，使用碱液或有机退膜液来将经电镀的预制封装基板褪掉干膜或光刻胶48。进一步地，采用闪蚀来蚀刻未电镀增厚的导电籽晶层46，以得到所需图形。由此，实现所需图形的线路及其与下层孔的互连。
在步骤S60中，重复步骤S10到S55一次或多次以提供一个或多个感光PI膜层14来形成转接层部分40，从而制得包含芯片组互连功能的新型封装基板。图10示出了根据本发明的一个实施例的新型封装基板的示意性截面图。如图中所述，新型封装基板包括封装基板10和一体地集成在其上的转接层部分40。作为示例，转接层部分40包含2层精细线路以实现转接板功能。当然，根据需要，转接层部分40可包含一层或多层精细线路以实现转接板功能。进一步地，如图3中所示，转接层部分40作为Die与封装基板的中介层，起到将Die与封装基板互连的作用，从而实现了常规意义上的转接板功能。
注意的是，导电籽晶层的厚度与后制程电镀之前的前处理、电镀以及闪蚀均有较大关系。在一个实施例中，本发明的导电籽晶层的厚度在80nm-2000nm的范围。导电籽晶层的厚度如果太薄则可能被电镀前处理或者电镀工艺刻蚀掉，无法起到电镀过程中导电的作用；如厚度太厚则最终需闪蚀较多而可能导致线宽线距达不到预期。鉴于导电籽晶层的厚度与电镀前处理、电镀以及闪蚀这三个步骤的工艺强相关，因此将其厚度限定在80nm-2000nm的范围。优选地，根据本发明的导电籽晶层的厚度为800nm。形成导电籽晶层的金属可为Cu、Ta、TaN/Ta合金、TiN、TiW、Cr、Ti、Mo、MoTi合金、Ni、NiCu中的一种或多种，或者它们的组合。在一个实施例中，形成导电籽晶层所采用的是化学镀铜的方法，可优选地采用金属Cu形成单层的导电籽晶层。在另一个实施例中，形成导电籽晶层所采用的是 Sputter或其他干式镀膜方式，则可选择除Cu外的其他金属作为底层金属与Cu搭配形成导电籽晶层的两层结构。优选地，在本发明的一个实施例中，可采用底层Ni和上层Cu的两层结构形成导电籽晶层，其总厚度可为800nm。考虑到Sputter方式的成本，也可采用沉积较薄的Ni/Cu达到厚为150nm，然后电镀加厚到800nm。此种厚度可依照产能和成本以及工艺窗口来调配。
图21是根据本发明的第二示例性实施例的新型封装基板制作方法的流程图。该新型封装基板制作方法大体可包括以下步骤：
步骤S000：提供包含基板线路(未示出)的封装基板100；
步骤S100：在封装基板100的表面上提供非感光PI膜层140；
步骤S200：在非感光PI膜层140施加干膜或光刻胶480进行曝光和显影而形成过孔420和线间隙440；
步骤S300：采用干法蚀刻将非感光PI膜层140上未受干膜或光刻胶480保护的位置刻蚀干净；
步骤S350：采用退膜工艺，去除非感光PI膜层140上的干膜或光刻胶480；
步骤S400：在非感光PI膜层140的表面上、过孔420内及线间隙440内形成导电籽晶层460，由此得到预制封装基板；
步骤S500：在预制封装基板的表面上施加干膜或光刻胶580，通过曝光显影方式来形成图案，其中需要填孔和长线的位置均被暴露出来；
步骤S600：将显影后的预制封装基板进行电镀，使得电镀层500覆盖需要填孔和长线的位置；
步骤S650：将预制封装基板在电镀完成后褪掉干膜或光刻胶580，进而闪蚀以去掉部分导电籽晶层460，实现非感光PI膜层140中的线路和与下层基板线路的互连；以及
步骤S700：重复步骤S100到S650一次或多次以提供一个或多个非感光PI膜层140来形成转接层部分400，从而制得包含芯片组互连功能的新型封装基板。
任选地，在步骤S700之后，可在所得新型封装基板的转接层部分400上进行增层以提供一层或多层附加的基板线路。
在步骤S000中，提供包含基板线路(未示出)的封装基板100。在文中，封装基板100类似于上文提到的封装基板10。为简明起见，对此不作详细描述。
在步骤S100中，在封装基板100的表面上提供非感光PI膜层140。作为示例，该表面通常是指封装基板100的待与芯片焊接的表面，例如封装基板的上表面、下表面，或者二 者。图11示出了根据本发明的一个实施例在完成的常规制程封装基板上涂布有非感光PI膜层140的示意性截面图。在一个实施例中，提供非感光PI膜层140可采用将非感光PI膜热压(例如，真空热压)到封装基板100的表面上。非感光PI膜具有可热压合性的干膜材料，例如可压合的非感光PI材料。在一个实施例中，非感光PI膜经热烘干后可附着在基板的表面上。备选地，提供非感光PI膜层140可采用将非感光涂布膜涂布到封装基板100的表面上。非感光涂布膜，例如非感光PI浆料，具有可涂布烘干特性。在一个实施例中，非感光PI浆料经热烘干后可附着在基板的表面上。在本发明中，PI膜层14和140不限于文中所提到的PI干膜和PI浆料，也可采用感光或者非感光亚克力材质的浆料和干膜。此部分材料在显示面板中作为平坦层材料也有大量应用，或者可以是其他可涂布、固化的有机材料。
在步骤S200中，在非感光PI膜层140施加干膜或光刻胶480进行曝光和显影而形成过孔420和线间隙440。图12示出了根据本发明的一个实施例在封装基板100上的非感光PI膜层140经曝光显影后的示意性截面图。作为示例，在非感光PI膜层140上涂布光刻胶或者直接贴附干膜后进行曝光。在曝光之后，对光刻胶或者干膜进行显影工艺，由此形成直径为1μm以上的过孔420，以及形成尺寸为数百纳米以上的线间隙440。
在步骤S300中，采用干法蚀刻将非感光PI膜层140上未受干膜或光刻胶480保护的位置刻蚀干净。在一个实施例中，用于干法蚀刻的刻蚀气体可采用四氟化碳(CF4)和氧气(O2)。图13示出了根据本发明的一个实施例在封装基板100上的非感光PI膜层140经干法蚀刻后的示意性截面图。如图中所示，在非感光PI膜层140上未受干膜或者光刻胶保护的位置已被刻蚀干净，露出封装基板100的部分表面。换言之，过孔420和线间隙440经刻蚀加深而到达封装基板100的表面。在本发明中，PI刻蚀不限于干法蚀刻。备选地，在精度允许的条件下，也可使用湿法刻蚀来去除非感光PI膜层140。
在步骤S350中，采用退膜工艺，去除非感光PI膜层140上的干膜或光刻胶480。在一个实施例中，根据干膜或者光刻胶的种类来选择NaOH和有机退膜液进行退膜操作。图14示出了根据本发明的一个实施例将覆盖有干膜或光刻胶480的非感光PI膜层140经退膜后的示意性截面图。如图中所示，覆盖在非感光PI膜层140上的干膜或者光刻胶已被移除。类似于图5中所示，在非感光PI膜层140中形成有直径为1μm以上的过孔420，以及尺寸为数百纳米以上的线间隙440。
在步骤S400中，在非感光PI膜层140的表面上、过孔420内及线间隙440内形成导电籽晶层460，由此得到预制封装基板。图15示出了根据本发明的一个实施例在封装基板100上的非感光PI膜层140中形成导电籽晶层460的示意性截面图。作为示例，以化学镀铜 的方式在非感光PI膜层140的表面上、过孔420内以及线间隙440内形成导电籽晶层460，由此得到预制封装基板。在另一实施例中，采用溅射(Sputter)的方式在非感光PI膜层140上、过孔420内以及线间隙440内形成导电籽晶层460。在又一实施例中，采用离子注入镀膜的方式在非感光PI膜层140上、过孔420内以及线间隙440内形成导电籽晶层460。优选地，导电籽晶层的厚度在80nm-2000nm的范围。
在步骤S500中，在预制封装基板的表面上施加干膜或光刻胶580，通过曝光显影方式来形成图案，其中需要填孔和长线的位置均被暴露出来。图16示出了根据本发明的一个实施例在预制封装基板的表面上施加干膜或光刻胶480、经曝光、显影后的示意性截面图。作为示例，将干膜附贴到预制封装基板的表面上以通过曝光显影方式来形成线路图案。备选地，该线路图案可通过将液态光刻胶涂覆到预制封装基板的表面上来形成。由此形成的线路图案在需要填孔和长线的位置均被显露出来，以便电镀处理。
在步骤S600中，将显影后的预制封装基板进行电镀，使得电镀层500覆盖需要填孔和长线的位置。优选地，预制封装基板在电镀之前需要进行前处理。作为前处理的方法，可包括表面清洁处理，例如，用浸渍过酒精的纱布擦拭基板的表面以除去上面附着的脏污，或者将基板放入清洁液中并采用超声波进行清洗。图17示出了根据本发明的一个实施例在预制封装基板上形成电镀层500的示意性截面图。作为示例，将显露线路图案的预制封装基板进行电镀例如镀铜，以将电镀层500覆盖露出的线路图案部分，使得电镀层500的厚度增加至所需要的厚度。在本发明的一个实施例中，电镀后的铜厚均匀性如果无法满足产品的要求，则可采用研磨的形式进行打磨，以使铜厚满足均匀性。任选地，该研磨工艺或步骤可安排在电镀之后且在下文提到的退膜步骤之前。
在步骤S650中，将预制封装基板在电镀完成后褪掉干膜或光刻胶580，进而闪蚀以去掉部分导电籽晶层460，实现非感光PI膜层140中的线路和与下层基板线路的互连。图18示出了根据本发明的一个实施例在预制封装基板经退膜、闪蚀后的示意性截面图。作为示例，使用碱液或有机退膜液来将经电镀的预制封装基板褪掉干膜或光刻胶580。进一步地，采用闪蚀来蚀刻未电镀增厚的导电籽晶层460，以得到所需图形。由此，实现所需图形的线路及其与下层孔的互连。
在步骤S700中，重复步骤S100到S650一次或多次以提供一个或多个非感光PI膜层140来形成转接层部分400，从而制得包含芯片组互连功能的新型封装基板。图19示出了根据本发明的一个实施例的新型封装基板的示意性截面图。如图中所述，新型封装基板包括封装基板100和一体地集成在其上的转接层部分400。作为示例，转接层部分400包含2 层精细线路以实现转接板功能。当然，根据需要，转接层部分400可包含一层或多层精细线路以实现转接板功能。进一步地，如图3中所示，转接层部分40作为Die与封装基板的中介层，起到将Die与封装基板互连的作用，从而实现了常规意义上的转接板功能。
注意到的是，本发明中所提到的具有芯片组互连的基板层别，并不限于在基板的最后数层，也可能位于基板刚开始的层别中、中间的层别中，或者根据需要出现在基板的任何层别中。在本发明中，仅是以常规的转接板功能所在的层别进行说明。
相比于常规的方法只能在PI膜上布置线路或者其他介质上布置线路，本发明还可通过PI膜的开窗而将线路埋置在PI膜中间。这对于传统工艺而言具有减小产品厚度的优点。而且，在本发明中因采用的是PI材料，其具有一定的流动性和表面的平坦化功能。由此，本发明具有可将线路制作得更为精细的优点。
本发明的新型封装基板除了将转接板与基板合二为一外，还减少了植入锡球焊接的次数。此外，本发明的新型封装基板不但减少了信号传输中的信号损失和信号反射，而且减少了锡球中潜在的阿尔法射线对高频信号的影响，从而对高频信号的传输也具有较大帮助。
本书面说明使用了包括最佳模式的实例来公开本发明，且还使本领域的技术人员能够实施本发明，包括制作和使用任何装置或***，以及执行任何相结合的方法。本发明可取得专利的范围由权利要求限定，并且可包括本领域技术人员所构思出的其它实例。如果这些其它的实例具有与权利要求的书面语言并无不同的结构元件，或者如果这些其它实例包括与权利要求的书面语言无实质差异的同等结构元件，则认为这些实例处在权利要求的范围之内。

Claims (13)

  1. 一种具有转接板功能的新型封装基板，包括：
    封装基板，所述封装基板含有基板线路；以及
    一体地集成在所述封装基板上的转接层部分，在所述转接层部分上和/或其中提供有精细线路；
    其中，所述转接层部分的精细线路与所述封装基板的基板线路形成电连接，以便导通所述封装基板与附接在所述转接层部分上的芯片元件之间的电连接。
  2. 根据权利要求1所述的新型封装基板，其中，所述转接层部分包括感光PI胶膜或者感光PI浆料。
  3. 根据权利要求1所述的新型封装基板，其中，所述转接层部分包括非感光PI胶膜或者非感光PI浆料。
  4. 根据权利要求1所述的新型封装基板，其中，所述封装基板由BF、BT、FR4中的一种或多种构成。
  5. 根据权利要求1所述的新型封装基板，其中，所述转接层部分包括开槽和/或开孔以制作连接线路。
  6. 一种制作具有转接板功能的新型封装基板的方法，所述方法包括以下步骤：
    提供包含基板线路的封装基板；
    在所述封装基板的表面上提供感光PI膜层；
    在所述感光PI膜层上通过曝光和显影而形成过孔和线间隙；
    在所述感光PI膜层的表面上、所述过孔内及所述线间隙内形成导电籽晶层，由此得到预制封装基板；
    在所述预制封装基板的表面上施加干膜或光刻胶以形成线路图案，其中需要填孔和布置线路的位置均被暴露出来；
    将所述预制封装基板进行电镀，使得电镀层覆盖所述需要填孔和布置线路的位置；
    从所述预制封装基板褪掉所述干膜或光刻胶并且闪蚀以去掉所述导电籽晶层的露出的部分，从而实现所述感光PI膜层的线路和与所述封装基板的基板线路的互连。
  7. 根据权利要求6所述的方法，其中，重复所述提供感光PI膜层的步骤到所述褪掉所述干膜或光刻胶并且闪蚀的步骤一次或多次以提供一个或多个感光PI膜层来形成所述新型封装基板的转接层部分。
  8. 根据权利要求7所述的方法，其中，所述转接层部分形成包含一层或多层精细线路的转接功能层。
  9. 根据权利要求6所述的方法，其中，所述导电籽晶层的厚度为80nm-2000nm。
  10. 一种制作具有转接板功能的新型封装基板的方法，所述方法包括以下步骤：
    提供包含基板线路的封装基板；
    在所述封装基板的表面上提供非感光PI膜层；
    在所述非感光PI膜层施加第一干膜或光刻胶进行曝光和显影而形成过孔和线间隙；
    采用蚀刻将所述非感光PI膜层上未受所述第一干膜或光刻胶保护的位置刻蚀去除；
    采用退膜工艺，去除所述非感光PI膜层上的第一干膜或光刻胶；
    在所述非感光PI膜层的表面上、过孔内及线间隙内形成导电籽晶层，由此得到预制封装基板；
    在所述预制封装基板的表面上施加第二干膜或光刻胶，通过曝光显影方式来形成图案，其中需要填孔和布置线路的位置均被暴露出来；
    将所述预制封装基板进行电镀，使得电镀层覆盖所述需要填孔和布置线路的位置；
    从所述预制封装基板褪掉所述第二干膜或光刻胶并且闪蚀以去掉所述导电籽晶层的露出的部分，从而实现所述非感光PI膜层的线路与所述封装基板的基板线路的互连。
  11. 根据权利要求9所述的方法，其中，重复所述提供非感光PI膜层的步骤到所述褪掉所述第二干膜或光刻胶并且闪蚀的步骤一次或多次以提供一个或多个非感光PI膜层来形成所述新型封装基板的转接层部分。
  12. 根据权利要求9所述的方法，其中，所述转接层部分形成包含一层或多层精细线路的转接功能层。
  13. 根据权利要求9所述的方法，其中，所述导电籽晶层的厚度为80nm-2000nm。
PCT/CN2023/136679 2022-12-06 2023-12-06 具有转接板功能的新型封装基板及其制作方法 WO2024120422A1 (zh)

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