CN101981655B - 用于在c4焊盘之间制造线/间隔布线的方法 - Google Patents
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Abstract
描述了一种用于制造精细的线和间隔布线的方法。所述方法包括提供具有设置于其上的电介质层和晶种层的衬底。之后在所述晶种层之上形成抗反射涂覆层和光致抗蚀剂层。使所述光致抗蚀剂层和抗反射涂覆层图案化,以形成图案化光致抗蚀剂层和图案化抗反射涂覆层,从而露出晶种层的第一部分,并使晶种层的第二部分仍然受到覆盖。之后,在晶种层的第一部分上,在图案化光致抗蚀剂层和图案化抗反射涂覆层的特征之间形成金属层。接下来,去除图案化光致抗蚀剂层和图案化抗反射涂覆层。之后,去除晶种层的第二部分,从而在电介质层之上提供一系列金属线。
Description
技术领域
本发明的实施例属于半导体结构以及具体而言用于制造适用于高密度互连(HDI)衬底的精细线和间隔(FLS)布线的方法的领域。
背景技术
倒装片或者可控塌陷芯片连接(C4)是一种用于诸如集成电路(工C)芯片、MEMS的半导体器件或元件的安装类型,其采用焊料凸点而不是焊线。将焊料凸点沉积在位于衬底封装的顶部一侧上的C4焊盘上。为了将半导体器件安装到衬底上,将其翻转过来,即,将有源的一面朝下置于安装区上。采用焊料凸点将半导体器件直接连接到衬底上。
C4焊球连接已经使用了很多年,用来在半导体器件和衬底之间提供倒装片互连。在绝缘层之上以及在每者通过一个或多个所述绝缘层内的通孔露出的连接器焊盘(又称凸点焊盘)的暴露表面之上形成半球形的C4焊料凸点。接下来,将焊料凸点加热至其熔点以上直至其发生回流并与管芯的Cu接线柱凸点形成连接。可以采用很多种不同的处理技术制造实际的C4焊料凸点,所述处理技术包括蒸发、丝网印刷和电镀。通过电镀实施的制造需要进行一系列的基本操作,通常包括金属晶种层的沉积、(按照C4焊料凸点的图案)成像的光致抗蚀剂的涂覆、焊料的电沉积、光致抗蚀剂的剥离以及为了隔离C4凸点而对金属晶种层实施的下潜蚀刻(sub-etching)。
随着半导体结构变得更为发达,对更高的I/O密度的需求导致了更加紧密的C4凸点间距。这又对线和间隔的制造和尺寸提出了严格的要求。
附图说明
图1是描述根据本发明实施例的用于在有机衬底封装中制造精细的线和间隔布线的方法的操作的流程图。
图2A-2H示出了描绘根据本发明的实施例的用于在有机衬底封装中制造精细的线和间隔布线的方法的操作的截面图。
具体实施方式
将描述用于在有机衬底封装中制造精细的线和间隔布线的方法。在下述说明中,将阐述很多具体细节,例如,集成规划和材料体制,以提供对本发明的实施例的彻底的理解。对于本领域技术人员而言,显然可以在不需要这些具体细节的情况下实践本发明的实施例。在其他情况下,则未具体描述诸如集成电路设计布局的众所周知的特征,以避免对本发明的实施例造成不必要的含糊不清。此外,应当理解,图中所示的各种实施例只是示范性的表示,而未必是按比例绘制的。
文中公开了用于制造精细的线和间隔布线的方法。可以提供具有设置于其上的电介质层和晶种层的衬底。在实施例中,在所述晶种层之上形成抗反射涂覆层和光致抗蚀剂层。之后,使光致抗蚀剂层和抗反射涂覆层图案化,以形成图案化光致抗蚀剂层和图案化抗反射涂覆层,从而露出晶种层的第一部分,并使晶种层的第二部分仍然受到覆盖。在晶种层的第一部分上,在图案化光致抗蚀剂层和图案化抗反射涂覆层的特征之间形成金属层。接下来去除图案化光致抗蚀剂层和图案化抗反射涂覆层。在一个实施例中,接下来去除晶种层的第二部分,从而在电介质层之上提供一系列金属线。
根据本发明的实施例,采用抗反射涂覆层的涂覆在光刻过程中通过吸收反射光来控制来自晶种层的反射量。通过吸收反射光,可以更好地控制经受图案化处理的光致抗蚀剂层的区域的曝光量。例如,在一个实施例中,通过针对光刻处理在晶种层和光致抗蚀剂层之间采用抗反射涂覆层,即使不能消除对光致抗蚀剂层的区域的不期望的曝光,也能使其充分减少。相应地,与不存在抗反射涂覆层时由散射导致的线宽变化相比,可以缓解图案化光致抗蚀剂层中的特征之间的线宽变化。在一个实施例中,通过在制造精细的线和间隔的集成方案中引入抗反射涂覆层,能够提高这样的布线的密度,同时能够降低这样的布线当中各条线的线宽,以实现对这样的布线的缩放,从而始终适应不断提高的I/O密度。根据本发明的实施例,针对光刻处理在晶种层和光致抗蚀剂层之间采用抗反射涂覆层降低了未采用所述抗反射涂覆层的处理所共有的线边缘粗糙(例如,反射性凹口)的程度。
根据本发明的实施例,在用于制造精细的线和间隔布线的方法中采用了抗反射涂覆层。图1是描述根据本发明的实施例的用于在有机衬底封装中制造精细的线和间隔布线的方法的操作的流程图100。图2A-2H示出了描绘根据本发明的实施例的用于在有机衬底封装中制造精细的线和间隔布线的方法的操作的截面图。
参考流程图100的操作102和对应的图2A,提供具有设置于其上的电介质层204的内置层202。根据本发明的实施例,内置层202和电介质层204形成了有机衬底封装中所包含的层叠体200。例如,在一个实施例中,层叠体200可以包括任何需要精细的线和间隔布线的内置层。在实施例中,电介质层204具有粗糙表面206,例如,使电介质层204受到表面沾污去除处理,如图2A所示。
电介质层204可以是适于使内置层202的面上的器件和互连与接下来形成的设置于电介质层204之上或之下的精细线/间隔布线隔离的层。在实施例中,电介质层204由具有硅石填充剂的基于环氧树脂的材料构成。在一个实施例中,电介质层204具有粗糙表面206,其平均表面粗糙度大约处于0.5-0.6微米的范围内,即,粗糙表面206中的V沟槽的平均深度大约处于0.5-0.6微米的范围内。在实施例中,使电介质层204粗糙化,使其具有粗糙表面206,从而与接下来沉积的金属层更好地附着,例如,所述金属层可以是下文所述的无电沉积金属层。在实施例中,通过激光钻孔以及随后的表面沾污去除处理形成电介质层204的粗糙表面206。在一个实施例中,未使电介质层204的表面粗糙化。
内置层202可以由适于半加成工艺(SAP)制造的材料构成。在一个实施例中,内置层202是具有硅石填充剂的基于环氧树脂的电介质材料。在另一实施例中,内置层202包括铜平面。
再次参考流程图100的操作102和对应的图2B,在电介质层204上设置晶种层208。根据本发明的实施例,与电介质层204共形形成晶种层208,例如,晶种层208具有与粗糙表面206相同或者类似的表面形貌,如图2B所示。在实施例中,晶种层208部分或者完全填充了电介质层204的任何顶表面粗糙,从而为晶种层208提供充分平坦的顶表面。在实施例中,晶种层208具有大约处于0.5-1微米的范围内的厚度。在实施例中,晶种层208具有大约0.7微米的厚度。晶种层208可以是适于接下来在其表面上电解镀覆金属膜的层。在实施例中,晶种层208由金属或者含有金属的合金构成,例如但不限于铜、银、镍、铝。在实施例中,通过无电沉积处理在电介质层204上形成晶种层208。金属溅射是一种可以采用的替代金属沉积工艺。
参考流程图100的操作104和对应的图2C,在晶种层208之上形成抗反射涂覆层210。根据本发明的实施例,在晶种层208之上形成抗反射涂覆层210,以吸收在随后的光刻工艺中从金属表面和晶种层208的粗糙表面形貌反射的光,如图2C所示。而且,在一个实施例中,如图2C所示,抗反射涂覆层210填充了晶种层208的表面粗糙,从而为抗反射涂覆层210提供接下来在其上沉积光致抗蚀剂层的平坦表面。在实施例中,抗反射涂覆层210具有从晶种层208的顶表面开始测量的大约处于1-2微米的范围内的厚度。在实施例中,抗反射涂覆层210具有从晶种层208的顶表面开始测量的大约1.5微米的厚度。
抗反射涂覆层210可以由充分吸收光刻过程中产生的散射光的材料构成。根据本发明的实施例,抗反射涂覆层210由有机化合物和染料构成。在一个实施例中,抗反射涂覆层210由诸如但不限于水溶性的聚合物Aquazol、基于有机硅氧烷的膜的材料构成。在实施例中,对抗反射涂覆层210的成分进行选择,使之与接下来形成于抗反射涂覆层210的表面上的光致抗蚀剂层化学相容。
可以通过适于均匀覆盖晶种层208并提供接下来在上面沉积光致抗蚀剂层的平坦表面的技术在晶种层208上形成抗反射涂覆层210。在一个实施例中,可以通过诸如但不限于喷涂或者滚涂的工艺形成抗反射涂覆层210。在另一实施例中,通过旋涂(spin-on)工艺形成抗反射涂覆层210。在实施例中,在将抗反射涂覆层210涂覆到电介质层204的表面上的过程中,采用溶剂加以辅助,在抗反射涂覆层210形成之后为了去除所述溶剂,接下来在大约但不限于150摄氏度的温度下对抗反射涂覆层210实施烘焙处理。
再次参考流程图100的操作104和对应的图2D,在抗反射涂覆层210之上形成光致抗蚀剂层212。光致抗蚀剂层212可以由适于经受光刻处理的材料构成。根据本发明的实施例,光致抗蚀剂层212由干膜抗蚀剂或液体抗蚀剂构成。在实施例中,光致抗蚀剂层212由负性(negative tone)液体光致抗蚀剂构成。在一个实施例中,光致抗蚀剂层212由包括光敏重氮基醌酯(diazoquinone ester DQ)和酚醛清漆树脂(N)的二成分DQN抗蚀剂构成。可以通过适于均匀覆盖抗反射涂覆层210,并提供对其实施光刻处理的平坦顶表面的技术在抗反射涂覆层210上形成光致抗蚀剂层212。在一个实施例中,光致抗蚀剂层212是通过诸如但不限于向抗反射涂覆层210的表面上喷涂或滚涂的工艺形成的液体光致抗蚀剂层。在另一实施例中,光致抗蚀剂层212是通过层压处理形成的,并且是干膜光致抗蚀剂层。在一个实施例中,所述干膜光致抗蚀剂层是基于环化聚(顺式异戊二烯)树脂的。在实施例中,光致抗蚀剂层212具有大约处于10-15微米的范围内的厚度。在实施例中,光致抗蚀剂层212是负性或正性光致抗蚀剂层。在实施例中,对光致抗蚀剂层212的成分加以选择,使之与抗反射涂覆层210化学相容。
参考流程图100的操作106和对应的图2E,使光致抗蚀剂层212和抗反射涂覆层210图案化,从而分别形成图案化光致抗蚀剂层214和图案化抗反射涂覆层216,以暴露晶种层208的第一部分,并使晶种层208的第二部分仍然受到覆盖。根据本发明的实施例,通过掩模光刻工艺使光致抗蚀剂层212和抗反射涂覆层210图案化,以形成图案化光致抗蚀剂层214和图案化抗反射涂覆层216。在该实施例中,通过掩模光刻,使光致抗蚀剂层212和抗反射涂覆层210暴露于光源之下,其使光致抗蚀剂层212和抗反射涂覆层210的部分发生改变。在实施例中,抗反射涂覆层210吸收光刻曝光操作过程中晶种层208散射的光。在一个实施例中,在用来使光致抗蚀剂层212图案化的同一显影处理当中使抗反射涂覆层210图案化,以形成图案化抗反射涂覆层216。在该实施例中,首先对光致抗蚀剂层212实施掩模光刻处理。接下来,在同一处理步骤中,对光致抗蚀剂层212和抗反射涂覆层210显影,从而分别形成图案化光致抗蚀剂层214和图案化抗反射涂覆层216。在实施例中,通过诸如但不限于1%重量的Na2CO3或四甲基氢氧化铵(TMAH)的溶液使光致抗蚀剂层212和抗反射涂覆层210显影。在另一实施例中,在与光致抗蚀剂层212的图案化所采用的处理步骤不同的处理步骤中使抗反射涂覆层210图案化,以形成图案化抗反射涂覆层216。在实施例中,首先对光致抗蚀剂层212实施掩模光刻和显影处理,以形成图案化光致抗蚀剂层214。接下来,采用图案化光致抗蚀剂层214作为掩模,对抗反射涂覆层210进行干法或湿法蚀刻,以形成图案化抗反射涂覆层216。
参考流程图100的操作108和对应的图2F,在晶种层208的露出部分上,在图案化光致抗蚀剂层214和图案化抗反射涂覆层216的特征之间形成金属层218。根据本发明的实施例,通过电解沉积工艺在晶种层208的暴露部分上形成金属层218。金属层218可以由适于与晶种层208强力附着并且适当导电以形成导电线路的金属构成。在实施例中,晶种层208和金属层218二者均由铜构成。
参考流程图100的操作110和对应的图2G,去除图案化光致抗蚀剂层214和图案化抗反射涂覆层216。根据本发明的实施例,通过光致抗蚀剂剥离溶液(stripping solution)去除图案化光致抗蚀剂层214和图案化抗反射涂覆层216。在实施例中,通过基于胺的剥离溶液去除图案化光致抗蚀剂层214和图案化抗反射涂覆层216。在一个实施例中,在同一处理步骤中去除图案化光致抗蚀剂层214和图案化抗反射涂覆层216。在一个实施例中,通过分离的处理步骤去除图案化光致抗蚀剂层214和图案化抗反射涂覆层216。
参考流程图100的操作112和对应的图2H,去除晶种层208先前被图案化光致抗蚀剂层214和图案化抗反射涂覆层216覆盖的部分。根据本发明的实施例,通过去除晶种层208的这一部分而在电介质层204之上提供一系列金属线220。在一个实施例中,所述一系列线220中的每条线的宽度小于大约5微米,所述一系列线220中的每条线之间的间隔小于大约5微米。可以通过全局干法或湿法蚀刻工艺去除晶种层208的需要去除的部分。在实施例中,在基于H2O2/H2SO4的蚀刻溶液中去除晶种层208的部分。在一个实施例中,所述全局蚀刻工艺还降低了所述一系列线220中的每条线的高度,如图2G和图2H所示。
至此,公开了一种用于制造精细的线和间隔布线的方法。根据本发明的实施例,所述方法包括首先提供具有设置于其上的电介质层和晶种层的衬底。之后,在所述晶种层之上形成抗反射涂覆层和光致抗蚀剂层。使所述光致抗蚀剂层和抗反射涂覆层图案化,以形成图案化光致抗蚀剂层和图案化抗反射涂覆层,从而露出晶种层的第一部分,并使晶种层的第二部分仍然受到覆盖。之后,在晶种层的第一部分上,在图案化光致抗蚀剂层和图案化抗反射涂覆层的特征之间形成金属层。之后,去除图案化光致抗蚀剂层和图案化抗反射涂覆层。最后,去除晶种层的第二部分,从而在所述电介质层之上或之下提供一系列金属线。在一个实施例中,通过分离的处理步骤使光致抗蚀剂层和抗反射涂覆层图案化。首先,对光致抗蚀剂层实施掩模光刻和显影处理,以形成图案化光致抗蚀剂层。接下来,对抗反射涂覆层进行蚀刻,以形成图案化抗反射涂覆层。在另一实施例中,在同一处理步骤中使光致抗蚀剂层和抗反射涂覆层图案化。首先对光致抗蚀剂层和抗反射涂覆层实施掩模光刻处理。接下来,对光致抗蚀剂层和抗反射涂覆层二者显影,以形成图案化光致抗蚀剂层和图案化抗反射涂覆层。
Claims (20)
1.一种用于制造精细的线和间隔布线的方法,包括:
在具有电介质层的衬底上形成晶种层;
在所述晶种层之上形成抗反射涂覆层;
在所述抗反射涂覆层之上形成光致抗蚀剂层;
使所述光致抗蚀剂层和所述抗反射涂覆层图案化,以形成图案化光致抗蚀剂层和图案化抗反射涂覆层,从而露出所述晶种层的第一部分,并使所述晶种层的第二部分仍然受到覆盖;
在所述晶种层的所述第一部分上,在所述图案化光致抗蚀剂层和所述图案化抗反射涂覆层的特征之间形成金属层;
去除所述图案化光致抗蚀剂层和所述图案化抗反射涂覆层;以及
去除所述晶种层的所述第二部分,从而在所述电介质层之上提供一系列金属线。
2.根据权利要求1所述的方法,其中,形成所述抗反射涂覆层包括在所述晶种层上喷涂或滚涂所述抗反射涂覆层。
3.根据权利要求2所述的方法,其中,所述光致抗蚀剂层是液体光致抗蚀剂层,并且其中,形成所述光致抗蚀剂层包括在所述抗反射涂覆层上喷涂或滚涂所述光致抗蚀剂层。
4.根据权利要求2所述的方法,其中,形成所述抗反射涂覆层包括采用有机化合物和染料。
5.根据权利要求1所述的方法,其中,形成所述晶种层和所述金属层二者包括采用铜。
6.根据权利要求1所述的方法,其中,去除所述晶种层的所述第二部分以提供所述一系列金属线包括将所述一系列金属线中的每条线形成为具有低于5微米的宽度,并且每条线之间的间隔低于5微米。
7.一种用于制造精细的线和间隔布线的方法,包括:
在具有电介质层的衬底上形成晶种层;
在所述晶种层之上形成抗反射涂覆层;
在所述抗反射涂覆层之上形成光致抗蚀剂层;
对所述光致抗蚀剂层实施掩模光刻和显影处理,以形成图案化光致抗蚀剂层;
对所述抗反射涂覆层进行蚀刻,以形成图案化抗反射涂覆层,从而露出所述晶种层的第一部分,并使所述晶种层的第二部分仍然受到覆盖;
在所述晶种层的所述第一部分上,在所述图案化光致抗蚀剂层和所述图案化抗反射涂覆层的特征之间形成金属层;
去除所述图案化光致抗蚀剂层和所述图案化抗反射涂覆层;以及
去除所述晶种层的所述第二部分,从而在所述电介质层之上提供一系列金属线。
8.根据权利要求7所述的方法,其中,在同一处理步骤中执行所述图案化光致抗蚀剂层和所述图案化抗反射涂覆层的去除。
9.根据权利要求7所述的方法,其中,形成所述抗反射涂覆层包括在所述晶种层上喷涂或滚涂所述抗反射涂覆层。
10.根据权利要求9所述的方法,其中,所述光致抗蚀剂层是液体光致抗蚀剂层,并且其中,形成所述光致抗蚀剂层包括在所述抗反射涂覆层上喷涂或滚涂所述光致抗蚀剂层。
11.根据权利要求9所述的方法,其中,形成所述抗反射涂覆层包括采用有机化合物和染料。
12.根据权利要求7所述的方法,其中,形成所述晶种层和所述金属层二者包括采用铜。
13.根据权利要求7所述的方法,其中,去除所述晶种层的所述第二部分以提供所述一系列金属线包括将所述一系列金属线中的每条线形成为具有小于5微米的宽度,并且每条线之间的间隔小于5微米。
14.一种用于制造精细的线和间隔布线的方法,包括:
在具有电介质层的衬底上形成晶种层;
在所述晶种层之上形成抗反射涂覆层;
在所述抗反射涂覆层之上形成光致抗蚀剂层;
对所述光致抗蚀剂层和所述抗反射涂覆层实施掩模光刻处理;
在同一处理操作当中对所述光致抗蚀剂层和所述抗反射涂覆层显影,以形成图案化光致抗蚀剂层和图案化抗反射涂覆层,从而露出所述晶种层的第一部分,并使所述晶种层的第二部分仍然受到覆盖;
在所述晶种层的所述第一部分上,在所述图案化光致抗蚀剂层和所述图案化抗反射涂覆层的特征之间形成金属层;
去除所述图案化光致抗蚀剂层和所述图案化抗反射涂覆层;以及
去除所述晶种层的所述第二部分,从而在所述电介质层之上提供一系列金属线。
15.根据权利要求14所述的方法,其中,在同一处理步骤中执行所述图案化光致抗蚀剂层和所述图案化抗反射涂覆层的去除。
16.根据权利要求14所述的方法,其中,形成所述抗反射涂覆层包括在所述晶种层上喷涂或滚涂所述抗反射涂覆层。
17.根据权利要求16所述的方法,其中,所述光致抗蚀剂层是液体光致抗蚀剂层,并且其中,形成所述光致抗蚀剂层包括在所述抗反射涂覆层上喷涂或滚涂所述光致抗蚀剂层。
18.根据权利要求16所述的方法,其中,形成所述抗反射涂覆层包括采用有机化合物和染料。
19.根据权利要求14所述的方法,其中,形成所述晶种层和所述金属层二者包括采用铜。
20.根据权利要求14所述的方法,其中,去除所述晶种层的所述第二部分以提供所述一系列金属线包括将所述一系列金属线中的每条线形成为具有小于5微米的宽度,并且每条线之间的间隔小于5微米。
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US12/164,977 | 2008-06-30 | ||
PCT/US2009/048873 WO2010002736A2 (en) | 2008-06-30 | 2009-06-26 | Methods for fabricating line/space routing between c4 pads |
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US7985622B2 (en) * | 2008-08-20 | 2011-07-26 | Intel Corporation | Method of forming collapse chip connection bumps on a semiconductor substrate |
US8835217B2 (en) | 2010-12-22 | 2014-09-16 | Intel Corporation | Device packaging with substrates having embedded lines and metal defined pads |
CN102738073B (zh) * | 2012-05-24 | 2015-07-29 | 日月光半导体制造股份有限公司 | 间隔件及其制造方法 |
US10217644B2 (en) * | 2012-07-24 | 2019-02-26 | Infineon Technologies Ag | Production of adhesion structures in dielectric layers using photoprocess technology and devices incorporating adhesion structures |
US8877554B2 (en) | 2013-03-15 | 2014-11-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packaged semiconductor devices, methods of packaging semiconductor devices, and PoP devices |
CN104051383B (zh) * | 2013-03-15 | 2018-02-27 | 台湾积体电路制造股份有限公司 | 封装的半导体器件、封装半导体器件的方法以及PoP器件 |
CN104282613B (zh) * | 2013-07-02 | 2017-08-25 | 中芯国际集成电路制造(上海)有限公司 | 半导体制造方法 |
CN103441079B (zh) * | 2013-09-12 | 2015-10-28 | 江阴长电先进封装有限公司 | 一种晶圆级高密度布线制备方法 |
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