WO2024120061A1 - 一种基板及其制作方法、显示装置 - Google Patents

一种基板及其制作方法、显示装置 Download PDF

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Publication number
WO2024120061A1
WO2024120061A1 PCT/CN2023/128046 CN2023128046W WO2024120061A1 WO 2024120061 A1 WO2024120061 A1 WO 2024120061A1 CN 2023128046 W CN2023128046 W CN 2023128046W WO 2024120061 A1 WO2024120061 A1 WO 2024120061A1
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WIPO (PCT)
Prior art keywords
substrate
solder
layer
display device
units
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Application number
PCT/CN2023/128046
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English (en)
French (fr)
Inventor
邓红照
Original Assignee
惠州华星光电显示有限公司
Tcl华星光电技术有限公司
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Publication of WO2024120061A1 publication Critical patent/WO2024120061A1/zh

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  • the present application relates to the field of display technology, and in particular to a substrate and a manufacturing method thereof, and a display device.
  • Micro Light-Emitting Diode (Micro LED) or Mini Light-Emitting Diode (Mini LED) direct display technology is a new generation of display technology after Liquid Crystal Display (LCD), Organic Light-Emitting Diode (OLED), and Mini-LED backlight, and is one of the hot spots of future display technology.
  • LCD Liquid Crystal Display
  • OLED Organic Light-Emitting Diode
  • Mini-LED backlight is one of the hot spots of future display technology.
  • the glass substrate has strict requirements on the LED bin (Bin Code range), the device is easy to drift, and the yield of LED mounted on the glass substrate is difficult to guarantee.
  • LEDs are fixed on the glass substrate through the SMT (Surface Mounted Technology) process.
  • SMT Surface Mounted Technology
  • solder paste and flux are usually made separately on the glass substrate using a steel screen printing process. Due to the poor printing accuracy of the steel screen, the printing accuracy of the solder paste and flux is poor, which causes the LED to shift when mounted, and then leads to a decrease in the yield of the SMT process.
  • the self-tinned devices reduce the difficulty of printing during the mounting process and significantly improve the yield of the SMT process, such self-tinned devices need to be packaged with tin bumps, which increases the packaging cost of the devices.
  • Mini-LED or Micro-LED direct display devices are self-luminous displays, the number of LED devices or IC devices required is huge.
  • the packaging cost of the self-tinned devices leads to huge production costs for the direct display devices, which is not conducive to the rapid mass production and promotion of Mini-LED or Micro-LED direct display technology.
  • the present application provides a substrate and a method for manufacturing the same, and a display device. Since the substrate has its own solder layer, the cost can be effectively reduced and the mounting yield can be improved during the process of mounting electronic devices, thereby facilitating the mass production and promotion of direct display technology.
  • the present application provides a substrate for mounting electronic devices, comprising a circuit substrate and a solder layer located on the circuit substrate;
  • the solder layer includes a plurality of solder units distributed in an array, each of the solder units includes two solder portions arranged at intervals, and each of the solder portions is electrically connected to the circuit substrate.
  • the circuit substrate includes a base substrate and a wiring layer located on the base substrate; the solder layer is located on a side of the wiring layer away from the base substrate, and each of the solder portions is electrically connected to the wiring layer.
  • the circuit substrate further comprises a plurality of pad groups located between the solder layer and the wiring layer; the plurality of pad groups are arranged in one-to-one correspondence with the plurality of solder units and are electrically connected to the wiring layer;
  • Each of the pad groups includes two pads that are spaced apart from each other, and the two solder portions in the solder unit are respectively located on the two pads in the corresponding pad group.
  • the solder portion covers a side of the corresponding pad away from the base substrate.
  • the material of the pad includes metal copper.
  • the routing layer includes a plurality of driving circuit units electrically connected to the plurality of solder units in a one-to-one correspondence, and the plurality of pad groups are electrically connected to the plurality of driving circuit units in a one-to-one correspondence.
  • each of the driving circuit units includes at least one thin film transistor and a low-voltage power supply line
  • the thin film transistor in the driving circuit unit is electrically connected to one of the pads in the corresponding pad group
  • the low-voltage power supply line is connected to another pad in the corresponding pad group.
  • the present application also provides a method for manufacturing the above substrate, comprising the following steps:
  • a solder layer is formed on the circuit substrate; wherein the solder layer includes a plurality of solder units distributed in an array, each of the solder units includes two solder portions spaced apart, and each of the solder portions is electrically connected to the circuit substrate.
  • forming a solder layer on the circuit substrate comprises the following steps:
  • the tin metal film is patterned to form a solder layer.
  • the deposition method of the tin metal film includes any one of physical vapor deposition, electroplating and evaporation.
  • the patterning of the tin metal film comprises the following steps:
  • the patterned photoresist layer is removed.
  • forming a patterned photoresist layer on the tin metal film comprises the following steps:
  • a patterned photoresist layer is formed using a mask and a yellow light process.
  • the material of the mask plate includes metal.
  • the present application also provides a display device, comprising the above-mentioned substrate and a plurality of electronic devices located on the substrate; wherein the plurality of electronic devices are fixedly connected to the plurality of solder units in a one-to-one correspondence.
  • the display device further includes a soldering layer located between each of the electronic components and the corresponding solder unit.
  • the electronic device includes any one or more of a light emitting chip, an integrated circuit chip and a resistor.
  • the light-emitting chip includes any one or more of an LED chip, a Mini-LED chip and a Micro-LED chip.
  • the display device further comprises a functional structure located on a side of the electronic device away from the substrate.
  • the display device is a Mini-LED direct display device or a Micro-LED direct display device
  • the functional structure is a color filter layer.
  • the display device is a liquid crystal display device
  • the functional structure is a liquid crystal box.
  • the substrate and its manufacturing method and display device provided by the present application are self-contained tin substrates.
  • electronic devices are mounted on the substrate using the SMT process, there is no need to make additional solder paste. Only a layer of patterned flux needs to be printed. The difficulty of printing flux can be reduced in the SMT process, which is beneficial to improving the yield of the SMT process.
  • the substrate has its own solder layer.
  • the solder unit in the solder layer can act as a pad of the light-emitting chip or IC, so that the light-emitting chip or IC can be mounted on the substrate without separate packaging, which is beneficial to saving huge packaging costs. Therefore, the present application can effectively improve the yield of the SMT process on the basis of saving packaging costs, which is beneficial to the mass production and promotion of direct display technology.
  • FIG. 1 is a schematic diagram of the structure of a substrate provided in an embodiment of the present application.
  • FIG. 2 is a schematic flow chart of a method for manufacturing a substrate provided in an embodiment of the present application.
  • FIG. 3 is a schematic structural diagram of a method for manufacturing a substrate provided in an embodiment of the present application.
  • FIG. 4 is a schematic diagram of the structure of a light-emitting device provided in an embodiment of the present application.
  • FIG. 5 is a schematic diagram of the structure of a display device provided in an embodiment of the present application.
  • the terms “installed”, “connected”, and “connected” should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or mutual communication; it can be a direct connection, or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements.
  • installed should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or mutual communication; it can be a direct connection, or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements.
  • an embodiment of the present application provides a substrate 1 for mounting electronic devices, wherein the substrate 1 includes a circuit substrate 2 and a solder (Sn) layer 3 located on the circuit substrate 2; wherein the solder layer 3 includes a plurality of solder units 4 distributed in an array, each solder unit 4 includes two solder portions 5 arranged at intervals, and each solder portion 5 is electrically connected to the circuit substrate 2.
  • the substrate 1 includes a circuit substrate 2 and a solder (Sn) layer 3 located on the circuit substrate 2; wherein the solder layer 3 includes a plurality of solder units 4 distributed in an array, each solder unit 4 includes two solder portions 5 arranged at intervals, and each solder portion 5 is electrically connected to the circuit substrate 2.
  • the circuit substrate 2 includes a base substrate 6 and a wiring layer 7 located on the base substrate 6 ; wherein the solder layer 3 is located on a side of the wiring layer 7 away from the base substrate 6 , and each solder portion 5 is electrically connected to the wiring layer 7 .
  • the material of the base substrate 6 includes glass, such as alkali-containing glass or alkali-free glass, but is not limited thereto.
  • the circuit substrate 2 further includes a plurality of pad groups 8 located between the solder layer 3 and the wiring layer 7 ; the plurality of pad groups 8 are arranged in one-to-one correspondence with the plurality of solder units 4 , and the plurality of pad groups 8 are electrically connected to the wiring layer 7 .
  • each pad group 8 includes two pads 9 spaced apart, and the two solder portions 5 in the solder unit 4 are respectively located on the two pads 9 in the corresponding pad group 8. It can be understood that the solder portion 5 covers the side of the corresponding pad 9 away from the substrate 6.
  • the material of the pad 9 includes metal copper (Cu), but is not limited thereto.
  • the pads on the substrate in the prior art are all in an exposed state, and the pads are easily oxidized and corroded in the external environment, resulting in the problem that the pads cannot be tinned when mounting electronic devices on the pads, thereby affecting the reliability of the product.
  • the substrate 1 provided in the embodiment of the present application has a solder layer 3, so that each pad 9 is covered with a solder portion 5 with stable performance, so there is no need to tin it again when mounting electronic devices. Therefore, the substrate 1 provided in the embodiment of the present application can effectively prevent the pads 9 from being oxidized and corroded, and can also improve the connection stability between the pads 9 and the solder portion 5, which is beneficial to improving the reliability of the product, such as improving the yield and service life of the product.
  • the routing layer 7 includes a plurality of driving circuit units (not shown in the figure) electrically connected to the plurality of solder units 4 in a one-to-one correspondence; a plurality of pad groups 8 are electrically connected to the plurality of driving circuit units in a one-to-one correspondence. It can be understood that the solder units 4 are electrically connected to the driving circuit units through the pad groups 8.
  • each driving circuit unit includes at least one thin film transistor (TFT) and a low voltage power supply line (VSS).
  • TFT thin film transistor
  • VSS low voltage power supply line
  • the thin film transistor in the driving circuit unit is electrically connected to one of the pads 9 in the corresponding pad group 8, and the low voltage power supply line is connected to another pad 9 in the corresponding pad group 8.
  • the pitch between the traces on the circuit substrate 2 is not limited.
  • the embodiment of the present application does not limit the film structure of the circuit substrate 2.
  • the circuit substrate 2 can be prepared by a 12-pass mask process or a 16-pass mask process, but is not limited thereto.
  • the TFT in the circuit substrate 2 includes any one or more of a top gate TFT, a back channel etched (BCE) TFT, and an etch-stopper layer (ESL) TFT, but is not limited thereto.
  • the circuit substrate 2 can be an IGZO (Indium Gallium Zinc Oxide) substrate or an LTPS (Low Temperature Poly-Silicon) substrate.
  • the circuit substrate 2 can be driven by an active matrix (AM) TFT or an AM Micro IC.
  • AM active matrix
  • the solder layer 3 in the embodiment of the present application can be prepared by combining the physical vapor deposition (PVD) process, the yellow light process and the etching process, so the solder layer 3 has a high degree of matching with the process of some film layers in the array substrate.
  • the process of the solder layer 3 in the embodiment of the present application is highly compatible with the existing equipment for manufacturing array substrates. Since the process precision of the existing array substrate is high, the process precision of the solder layer 3 is also high, so the substrate 1 in the implementation of the present application can be used for mounting electronic devices with smaller sizes, and it is also beneficial to improve the yield of the SMT process.
  • the substrate provided in the embodiment of the present application is suitable for large-scale batch production.
  • the distance between the two solder portions 5 in each solder unit 4 is determined by the size of the electronic device to be mounted, and is not limited here.
  • the size of the electronic device may be 300um*300um, or 1100um*500um, which is not limited here.
  • the number of soldering units 4 is not limited and is determined according to the size of the substrate 1 and the number of electronic components to be mounted.
  • the electronic device includes any one or more of a light emitting chip, an integrated circuit chip (IC), a resistor and a capacitor, and is not limited to the above-mentioned ones.
  • the light emitting chip includes any one or more of an LED chip, a Mini-LED chip and a Micro-LED chip.
  • the electronic device can be mounted on the substrate 1 through the SMT process, and one electronic device corresponds to one solder unit 4.
  • the electronic device is fixedly connected to the solder portion 5 in the corresponding solder unit 4 through a soldering process (such as reflow soldering).
  • the substrate 1 provided in the embodiment of the present application is a self-tinned substrate
  • the self-tinned substrate provided in the embodiment of the present application can reduce the difficulty of printing solder flux in the SMT process, thereby facilitating the improvement of the yield of the SMT process.
  • the substrate 1 provided in the embodiment of the present application has a solder layer 3
  • the solder unit 4 in the solder layer 3 can act as a pad of the light-emitting chip or IC, so that the light-emitting chip or IC can be mounted on the substrate 1 without being packaged separately.
  • the electronic device in the embodiment of the present application can be a bare crystal. Therefore, when using the substrate 1 provided in the embodiment of the present application to make a display product or a light-emitting product, there is no need to package the chip, which is conducive to saving huge packaging costs and getting rid of dependence on device packaging factories.
  • the self-tinned substrate provided in the embodiment of the present application can effectively improve the yield of the SMT process on the basis of saving packaging costs.
  • the substrate 1 provided in the embodiment of the present application has the following advantages: effectively avoiding pad oxidation, effectively improving the yield of the SMT process, being beneficial to improving the resolution of direct display products, being beneficial to large-scale batch production of substrates and direct display products, and greatly saving packaging costs.
  • the embodiment of the present application further provides a method for manufacturing a substrate, which can be used to manufacture the substrate described in the aforementioned embodiment; wherein the manufacturing method includes steps S201 to S202 .
  • the circuit substrate is an array substrate.
  • the circuit substrate 2 includes a base substrate 6 , and a routing layer 7 and a plurality of pad groups 8 sequentially arranged on the base substrate 6 ; each pad group 8 includes two pads 9 arranged at intervals.
  • the material of the pad 9 includes metal copper, but is not limited thereto.
  • the material of the base substrate 6 includes glass, such as alkali-containing glass or alkali-free glass, but is not limited thereto.
  • the wiring layer 7 includes a plurality of driving circuit units electrically connected to the plurality of pad groups 8 in a one-to-one correspondence; each driving circuit unit includes at least one thin film transistor and one low-voltage power wiring.
  • the embodiment of the present application does not limit the film layer structure of the circuit substrate 2, and the details may refer to the description of the above embodiment.
  • the pitch between the traces on the circuit substrate 2 is not limited.
  • the circuit substrate 2 may be other types of substrates, not limited to array substrates.
  • solder layer comprises a plurality of solder units distributed in an array, each solder unit comprises two solder portions spaced apart, and each solder portion is electrically connected to the circuit substrate.
  • the solder layer 3 is located on the circuit substrate 2 and includes a plurality of solder units 4 distributed in an array.
  • Each solder unit 4 includes two solder portions 5 arranged at intervals, and each solder portion 5 is electrically connected to the circuit substrate 2 .
  • the plurality of solder units 4 are arranged in one-to-one correspondence with the plurality of pad groups 8 , and the two solder portions 5 in the solder unit 4 are respectively located on the two pads 9 in the corresponding pad group 8 .
  • multiple solder units 4 are electrically connected to multiple driving circuit units in a one-to-one correspondence; wherein the TFT in the driving circuit unit is electrically connected to one of the solder parts 5 in the corresponding solder unit 4, and the low-voltage power supply line is electrically connected to another solder part 5 in the corresponding solder unit 4.
  • solder unit 4 is electrically connected to the driving circuit unit through the pad group 8 .
  • the pads on the substrate in the prior art are all in an exposed state, and the pads are easily oxidized and corroded in the external environment, resulting in the problem that the pads cannot be tinned when mounting electronic devices on the pads, thereby affecting the reliability of the product.
  • the substrate 1 provided in the embodiment of the present application has a solder layer 3, so that each pad 9 is covered with a solder portion 5 with stable performance, so there is no need to tin it again when mounting electronic devices. Therefore, the substrate 1 provided in the embodiment of the present application can effectively prevent the pads 9 from being oxidized and corroded, and can also improve the connection stability between the pads 9 and the solder portion 5, which is beneficial to improving the reliability of the product, such as improving the yield and service life of the product.
  • step S202 includes the following steps:
  • a tin metal film 10 is deposited on the entire surface of the circuit substrate 2;
  • the tin metal film 10 is patterned to form the solder layer 3 .
  • the deposition method of the tin metal film 10 includes any one of PVD, electroplating and evaporation.
  • the type and model of the metal tin target used in the deposition process are not limited.
  • patterning the tin metal film 10 includes the following steps:
  • the tin metal film 10 is etched to form a solder layer 3;
  • the patterned photoresist layer 11 is removed.
  • a mask plate and a yellow light process are used to form the patterned photoresist layer 11.
  • the material of the mask plate includes metal, but is not limited thereto.
  • the process matching degree of the solder layer 3 in the embodiment of the present application is relatively high with the process of some film layers in the array substrate.
  • the process of the solder layer 3 in the embodiment of the present application is highly compatible with the existing equipment for manufacturing array substrates. Since the process precision of the existing array substrate is high, the process precision of the solder layer 3 is also high, so the substrate 1 in the implementation of the present application can mount smaller electronic devices, and is also conducive to improving the yield rate of the SMT process.
  • the substrate 1 in the embodiment of the present application when the substrate 1 in the embodiment of the present application is applied to a direct display product, a direct display product with high resolution and high yield can be produced.
  • the physical vapor deposition process, yellow light process and etching process are all very mature processes and are highly compatible with the equipment for manufacturing array substrates. Therefore, the substrate provided in the embodiment of the present application is suitable for large-scale batch production.
  • electronic devices can be mounted on the substrate 1 provided in the present application using an SMT process; wherein the SMT process includes any one of patch, die bonding and die pricking.
  • the electronic device includes any one or more of a light emitting chip, an integrated circuit chip (IC), a resistor and a capacitor, and is not limited to the above-mentioned ones.
  • the light emitting chip includes any one or more of an LED chip, a Mini-LED chip and a Micro-LED chip.
  • the substrate 1 provided in the embodiment of the present application is a self-tinned substrate
  • the self-tinned substrate provided in the embodiment of the present application can reduce the difficulty of printing solder flux in the SMT process, thereby facilitating the improvement of the yield of the SMT process.
  • the substrate 1 provided in the embodiment of the present application has a solder layer 3
  • the solder unit 4 in the solder layer 3 can act as a pad of the light-emitting chip or IC, so that the light-emitting chip or IC can be mounted on the substrate 1 without being packaged separately.
  • the electronic device in the embodiment of the present application can be a bare crystal. Therefore, when using the substrate 1 provided in the embodiment of the present application to make a display product or a light-emitting product, there is no need to package the chip, which is conducive to saving huge packaging costs and getting rid of dependence on device packaging factories.
  • the self-tinned substrate provided in the embodiment of the present application can effectively improve the yield of the SMT process on the basis of saving packaging costs.
  • the substrate manufacturing method provided in the embodiment of the present application has the following advantages: effectively avoiding pad oxidation, effectively improving the yield of the SMT process, being beneficial to improving the resolution of direct display products, being beneficial to large-scale batch production of substrates and direct display products, and greatly saving packaging costs.
  • an embodiment of the present application also provides a light-emitting device 12 made using the substrate described in the aforementioned embodiment, the light-emitting device 12 includes the substrate 1 provided in the aforementioned embodiment and a plurality of electronic devices 13 located on the substrate 1; wherein the plurality of electronic devices 13 are fixedly connected to the plurality of solder units 4 in a one-to-one correspondence.
  • the electronic device 13 includes any one or more of a light emitting chip, an integrated circuit chip (IC), a resistor and a capacitor, and is not limited to the above-mentioned ones.
  • the light emitting chip includes any one or more of an LED chip, a Mini-LED chip and a Micro-LED chip.
  • the electronic device 13 is described by taking a light emitting chip as an example.
  • the light emitting chip is a bare die.
  • the electronic device 13 is fixedly connected to the solder portion 5 in the corresponding solder unit 4 through a soldering process (such as reflow soldering).
  • the light emitting device 12 further includes a soldering layer 14 located between each electronic device 13 and the corresponding solder unit 4.
  • the soldering layer 14 can be manufactured by using a steel screen printing method.
  • the substrate 1 in the light-emitting device 12 is a self-tin substrate, on the one hand, the yield of the SMT process can be effectively improved on the basis of greatly saving packaging costs, thereby greatly reducing production costs and improving product yields; on the other hand, it is conducive to large-scale batch production of the light-emitting device 12.
  • an embodiment of the present application also provides a display device 15, which includes a substrate 1 provided by any of the aforementioned embodiments, a plurality of electronic devices 13 located on the substrate 1, and a functional structure 16 located on the side of the electronic devices 13 away from the substrate 1; wherein the plurality of electronic devices 13 are fixedly connected to the plurality of solder units 4 in a one-to-one correspondence.
  • the electronic device 13 includes any one or more of a light emitting chip, an integrated circuit chip (IC), a resistor and a capacitor, and is not limited to the above-mentioned ones.
  • the light emitting chip includes any one or more of an LED chip, a Mini-LED chip and a Micro-LED chip.
  • the electronic device 13 is described by taking a light emitting chip as an example.
  • the light emitting chip is a bare die.
  • the electronic device 13 is fixedly connected to the solder portion 5 in the corresponding solder unit 4 through a soldering process (such as reflow soldering).
  • the display device 15 further includes a soldering layer 14 located between each electronic device 13 and the corresponding solder unit 4.
  • the soldering layer 14 can be manufactured by using stencil printing.
  • the display device 15 is a Mini-LED or Micro-LED direct display device; correspondingly, the functional structure 16 is a color filter layer.
  • the display device 15 is a liquid crystal display device 15; correspondingly, the functional structure 16 is a liquid crystal box. It can be understood that in this case, the substrate 1 and the electronic device 13 are combined to serve as a backlight source to provide light for the liquid crystal box.
  • the substrate 1 in the display device 15 is a self-contained tin substrate, on the one hand, the yield of the SMT process can be effectively improved on the basis of greatly saving the packaging cost, thereby greatly reducing the production cost and improving the product yield; on the other hand, the resolution of the display device 15 can be effectively improved, thereby improving the display effect; on the other hand, it is also conducive to large-scale batch production of the display device 15.

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Abstract

本申请公开了一种基板及其制作方法、显示装置，基板包括电路基板和位于电路基板上的焊锡层；焊锡层包括呈阵列分布的多个焊锡单元，每个焊锡单元包括间隔设置的两个焊锡部，且每个焊锡部与电路基板电连接。本申请提供的基板自带焊锡层，在节省封装成本的基础上有效提高SMT制程的良率，有利于直显技术的量产和推广。

Description

一种基板及其制作方法、显示装置 技术领域
本申请涉及显示技术领域，具体涉及一种基板及其制作方法、显示装置。
 背景技术
微型发光二极管(Micro Light-Emitting Diode，Micro LED)或次毫米发光二极管(Mini Light-Emitting Diode，Mini LED)直显技术是继液晶显示装置(Liquid Crystal Display，LCD)、有机发光二极管(Organic Light‑Emitting Diode，OLED)、以及Mini-LED背光之后新一代的显示技术，是未来显示技术的热点之一。
目前，实现玻璃基Mini-LED或Micro-LED直显装置的量产仍较困难，其原因主要集中在玻璃基板对LED bin档(Bin Code档次范围)要求严格、器件易漂移、以及在玻璃基板上贴装LED的良率难以保证等几个方面。通常，LED通过SMT(Surface Mounted Technology，表面贴装技术)制程固定在玻璃基板上，而现有的SMT制程中，焊锡膏和助焊剂通常采用钢网印刷工艺单独制作到玻璃基板上，由于钢网印刷精度差，导致焊锡膏和助焊剂的印刷精度差，从而导致贴装LED时发生偏移，进而导致SMT制程的良率下降。
为了解决焊锡膏导致的SMT制程的良率差的问题，一种自带锡的器件（LED或IC）被开发出来。由于器件自带锡，在SMT制程中只需要印刷助焊剂，钢网上可以开更大的孔，使得印刷难度下降，从而使得SMT制程的良率明显提升。
虽然自带锡的器件在贴装过程中降低了印刷难度且明显提升了SMT制程的良率，但是这种自带锡的器件需要进行锡bump封装，导致器件的封装成本上升。并且，由于Mini-LED或Micro-LED直显装置为自发光显示，需要的LED器件或IC器件的数量巨大，自带锡器件的封装成本导致直显装置的生产成本巨大，不利于Mini-LED或Micro-LED直显技术的快速量产和推广。
 发明概述
本申请提供一种基板及其制作方法、显示装置，由于基板自带焊锡层，在贴装电子器件的过程中可以有效的降低成本且提高贴装良率，从而有利于直显技术的量产和推广。
本申请提供一种基板，用于贴装电子器件，包括电路基板和位于电路基板上的焊锡层；
其中，所述焊锡层包括呈阵列分布的多个焊锡单元，每个所述焊锡单元包括间隔设置的两个焊锡部，且每个所述焊锡部与所述电路基板电连接。
可选地，所述电路基板包括衬底基板和位于所述衬底基板上的走线层；所述焊锡层位于所述走线层远离所述衬底基板的一侧，且每个所述焊锡部与所述走线层电连接。
可选地，所述电路基板还包括位于所述焊锡层和所述走线层之间的多个焊盘组；所述多个焊盘组与所述多个焊锡单元一一对应设置，且与所述走线层电连接；
每个所述焊盘组包括间隔设置的两个焊盘，所述焊锡单元中的两个所述焊锡部分别位于对应的所述焊盘组中的两个所述焊盘上。
可选地，所述焊锡部覆盖在对应的所述焊盘远离所述衬底基板的一侧。
可选地，所述焊盘的材料包括金属铜。
可选地，所述走线层包括与多个所述焊锡单元一一对应电连接的多个驱动电路单元，多个所述焊盘组与多个所述驱动电路单元一一对应电连接。
可选地，每个所述驱动电路单元至少包括一个薄膜晶体管和一条低压电源走线，所述驱动电路单元中的薄膜晶体管与对应的所述焊盘组中的其中一个焊盘电连接，且所述低压电源走线与对应的所述焊盘组中的另一个焊盘连接。
本申请还提供一种以上所述的基板的制作方法，包括以下步骤：
提供电路基板；以及
在所述电路基板上形成焊锡层；其中，所述焊锡层包括呈阵列分布的多个焊锡单元，每个所述焊锡单元包括间隔设置的两个焊锡部，且每个所述焊锡部与所述电路基板电连接。
可选地，所述在所述电路基板上形成焊锡层，包括以下步骤：
在所述电路基板上整面沉积锡金属膜；
对所述锡金属膜进行图案化处理，形成焊锡层。
可选地，所述锡金属膜的沉积方法包括物理气相沉积、电镀和蒸镀中的任意一种。
可选地，所述对所述锡金属膜进行图案化处理，包括以下步骤：
在所述锡金属膜上形成图案化的光阻层；
以所述图案化的光阻层为掩膜对所述锡金属膜进行刻蚀，以形成焊锡层；以及
移除所述图案化的光阻层。
可选地，所述在所述锡金属膜上形成图案化的光阻层，包括以下步骤：
采用掩膜板和黄光制程形成图案化的光阻层。
可选地，所述掩膜板的材料包括金属。
本申请还提供一种显示装置，包括以上所述的基板和位于所述基板上的多个电子器件；其中，所述多个电子器件与所述多个焊锡单元一一对应固定连接。
可选地，所述显示装置还包括位于每个所述电子器件和对应的所述焊锡单元之间的助焊层。
可选地，所述电子器件包括发光芯片、集成电路芯片和电阻中的任意一种或多种。
可选地，所述发光芯片包括LED芯片、Mini-LED芯片和Micro-LED芯片中的任意一种或多种。
可选地，所述显示装置还包括位于所述电子器件远离所述基板一侧的功能结构。
可选地，所述显示装置为Mini-LED直显装置或Micro-LED直显装置，所述功能结构为彩色滤光层。
可选地，所述显示装置为液晶显示装置，所述功能结构为液晶盒。
有益效果
本申请提供的基板及其制作方法、显示装置，由于基板为自带锡基板，当采用SMT制程在基板上贴装电子器件时，不需要额外的制作焊锡膏，只需要印刷一层图案化的助焊剂即可，可以在SMT制程中降低印刷助焊剂的难度，从而有利于提高SMT制程的良率；另外，基板自带焊锡层，当待贴装的电子器件为发光芯片或IC时，焊锡层中的焊锡单元可以充当发光芯片或IC的焊盘，使得发光芯片或IC不需要单独进行封装就可以与基板进行贴装，有利于节省巨额的封装费用。因此，本申请可以在节省封装成本的基础上有效的提高SMT制程的良率，从而有利于直显技术的量产和推广。
 附图说明
下面结合附图，通过对本申请的具体实施方式详细描述，将使本申请的技术方案及其它有益效果显而易见。
图1为本申请实施例提供的一种基板的结构示意图。
图2为本申请实施例提供的一种基板的制作方法的流程示意图。
图3为本申请实施例提供的一种基板的制作方法的结构示意图。
图4为本申请实施例提供的一种发光装置的结构示意图。
图5为本申请实施例提供的一种显示装置的结构示意图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
在本申请的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接或可以相互通讯；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通或两个元件的相互作用关系。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本申请中的具体含义。
下文的公开提供了许多不同的实施方式或例子用来实现本申请的不同结构。为了简化本申请的公开，下文中对特定例子的部件和设置进行描述。当然，它们仅仅为示例，并且目的不在于限制本申请。此外，本申请可以在不同例子中重复参考数字和/或参考字母，这种重复是为了简化和清楚的目的，其本身不指示所讨论各种实施方式和/或设置之间的关系。此外，本申请提供了的各种特定的工艺和材料的例子，但是本领域普通技术人员可以意识到其他工艺的应用和/或其他材料的使用。
如图1所示，本申请实施例提供了一种用于贴装电子器件的基板1，基板1包括电路基板2和位于电路基板2上的焊锡（Sn）层3；其中，焊锡层3包括呈阵列分布的多个焊锡单元4，每个焊锡单元4包括间隔设置的两个焊锡部5，且每个焊锡部5与电路基板2电连接。
具体的，如图1所示，电路基板2包括衬底基板6和位于衬底基板6上的走线层7；其中，焊锡层3位于走线层7远离衬底基板6的一侧，且每个焊锡部5与走线层7电连接。
具体的，衬底基板6的材料包括玻璃，例如含碱玻璃或无碱玻璃，但不限于此。
具体的，如图1所示，电路基板2还包括位于焊锡层3和走线层7之间的多个焊盘组8；多个焊盘组8与多个焊锡单元4一一对应设置，且多个焊盘组8与走线层7电连接。
具体的，如图1所示，每个焊盘组8包括间隔设置的两个焊盘9，焊锡单元4中的两个焊锡部5分别位于对应的焊盘组8中的两个焊盘9上。可以理解的，焊锡部5覆盖在对应的焊盘9远离衬底基板6的一侧。
具体的，焊盘9的材料包括金属铜（Cu），但不限于此。
通常，现有技术中的基板上的焊盘都处于裸露状态，而焊盘在外界环境下易氧化腐蚀，导致在焊盘上贴装电子器件时，容易出现焊盘无法上锡的问题，从而影响了产品的可靠性。而本申请实施例所提供的基板1自带焊锡层3，使得每个焊盘9上都覆盖有性能稳定的焊锡部5，故在贴装电子器件时不需要再上锡。因此，本申请实施例所提供的基板1可以有效的防止焊盘9被氧化腐蚀，还可以提高焊盘9与焊锡部5的连接稳定性，从而有利于提高产品的可靠性，例如提高产品的良率和使用寿命。
具体的，走线层7包括与多个焊锡单元4一一对应电连接的多个驱动电路单元（图中未示出）；多个焊盘组8与多个驱动电路单元一一对应电连接。可以理解的，焊锡单元4通过焊盘组8与驱动电路单元电连接。
在一具体实施方式中，电路基板2为阵列（Array）基板，对应的，每个驱动电路单元至少包括一个薄膜晶体管（Thin Film Transistor，TFT）和一条低压电源走线（VSS）。其中，驱动电路单元中的薄膜晶体管与对应的焊盘组8中的其中一个焊盘9电连接，且低压电源走线与对应的焊盘组8中的另一个焊盘9连接。
具体的，电路基板2上的走线之间的间距（pitch）不作限制。
具体的，本申请实施例对电路基板2的膜层结构不作限制。根据制程不同，电路基板2可以采用12道光罩（Mask）制程制备得到，也可以采用16道Mask制程的制备得到，但不限于此。根据TFT的类型不同，电路基板2中的TFT包括顶栅（Top gate）型TFT、背沟道蚀刻（Back Channel Etched，BCE）型TFT、以及刻蚀阻挡层（Etched-stopper Layer，ESL）型TFT中的任意一种或多种，但不限于此。根据有源层的材料不同，电路基板2可以是IGZO（Indium Gallium Zinc Oxide，铟镓锌氧化物）基板，也可为LTPS（Low Temperature Poly-Silicon，低温多晶硅）基板。根据驱动方式不同，电路基板2可以采用主动矩阵（AM）式TFT驱动，也可以采用AM Micro IC驱动。
具体的，本申请实施例中的焊锡层3可以结合物理气相沉积（PVD）工艺、黄光制程和刻蚀工艺制备得到，因此，焊锡层3与阵列基板中的部分膜层的制程匹配度较高。也就是说，本申请实施例中的焊锡层3的制程与现有的制作阵列基板的设备兼容性较高。由于现有的阵列基板的制程精度高，使得焊锡层3的制程精度也较高，故本申请实施中的基板1可以用于贴装尺寸较小的电子器件，还有利于提高SMT制程的良率。
因此，当本申请实施例中的基板1应用于直显产品时，可以制作高分辨率且高良率的直显产品。
另外，PVD、黄光制程和刻蚀工艺都是很成熟的工艺，且与制作阵列基板的设备兼容性高，因此，本申请实施例所提供的基板适合大规模批量生产。
具体的，每个焊锡单元4中的两个焊锡部5之间的间距大小由待贴装的电子器件的尺寸决定，此处不做限制。
具体的，电子器件的尺寸可以是300um*300um，也可以是1100um*500um，此处不作限制。
具体的，焊锡单元4的数量不作限制，具体根据基板1的尺寸和待贴装电子器件的数量决定。
具体的，电子器件包括发光芯片、集成电路芯片（IC）、电阻和电容中的任意一种或多种，且不限于以上列举的几种。其中，发光芯片包括LED芯片、Mini-LED芯片和Micro-LED芯片中的任意一种或多种。
具体的，电子器件可以通过SMT制程贴装到基板1上，且一个电子器件对应一个焊锡单元4。电子器件与对应的焊锡单元4中的焊锡部5通过焊接工艺（例如回流焊）固定连接。
可以理解的，由于本申请实施例所提供的基板1为自带锡基板，当采用SMT制程在基板1上贴装电子器件时，不需要额外的制作焊锡膏，只需要印刷一层图案化的助焊剂即可。因此，本申请实施例所提供的自带锡基板和自带锡器件一样，可以在SMT制程中降低印刷助焊剂的难度，从而有利于提高SMT制程的良率。
具体的，由于本申请实施例所提供的基板1自带焊锡层3，当待贴装的电子器件为发光芯片或IC时，焊锡层3中的焊锡单元4可以充当发光芯片或IC的焊盘，使得发光芯片或IC不需要单独进行封装就可以与基板1进行贴装。也就是说，本申请实施例中的电子器件可以为裸晶。因此，使用本申请实施例所提供的基板1制作显示产品或发光产品时，不需要进行芯片封装，有利于节省巨额的封装费用，且可以摆脱对器件封装工厂的依赖。
因此，与自带锡器件相比，本申请实施例所提供的自带锡基板可以在节省封装成本的基础上有效的提高SMT制程的良率。
综上，本申请实施例所提供的基板1具有以下优势：有效的避免焊盘氧化、有效的提高SMT制程的良率、有利于提高直显产品的分辨率、有利于基板和直显产品的大规模批量生产、以及大大的节省封装成本等。
如图2和图3所示，本申请实施例还提供了一种基板的制作方法，可用于制作前述实施例所述的基板；其中，制作方法包括步骤S201至S202。
S201：提供电路基板。
在一具体实施方式中，电路基板为阵列基板。
具体的，如图1所示，电路基板2包括衬底基板6以及依次设置在衬底基板6上的走线层7和多个焊盘组8；每个焊盘组8包括间隔设置的两个焊盘9。
具体的，焊盘9的材料包括金属铜，但不限于此。
具体的，衬底基板6的材料包括玻璃，例如含碱玻璃或无碱玻璃，但不限于此。
具体的，走线层7包括与多个焊盘组8一一对应电连接的多个驱动电路单元；每个驱动电路单元至少包括一个薄膜晶体管和一条低压电源走线。
具体的，本申请实施例对电路基板2的膜层结构不作限制，具体可参考前述实施例的描述。
具体的，电路基板2上的走线之间的间距（pitch）不作限制。
在另一具体实施方式中，电路基板2可以为其他类型的基板，不限于阵列基板。
S202：在电路基板上形成焊锡层；其中，焊锡层包括呈阵列分布的多个焊锡单元，每个焊锡单元包括间隔设置的两个焊锡部，且每个焊锡部与电路基板电连接。
如图1和图3所示，焊锡层3位于电路基板2上，且包括呈阵列分布的多个焊锡单元4，每个焊锡单元4包括间隔设置的两个焊锡部5，且每个焊锡部5与电路基板2电连接。
具体的，多个焊锡单元4与多个焊盘组8一一对应设置，且焊锡单元4中的两个焊锡部5分别位于对应的焊盘组8中的两个焊盘9上。
具体的，多个焊锡单元4与多个驱动电路单元一一对应电连接；其中，驱动电路单元中的TFT与对应的焊锡单元4中的其中一个焊锡部5电连接，且低压电源走线与对应的焊锡单元4中的另一个焊锡部5电连接。
可以理解的，焊锡单元4通过焊盘组8与驱动电路单元电连接。
通常，现有技术中的基板上的焊盘都处于裸露状态，而焊盘在外界环境下易氧化腐蚀，导致在焊盘上贴装电子器件时，容易出现焊盘无法上锡的问题，从而影响了产品的可靠性。而本申请实施例所提供的基板1自带焊锡层3，使得每个焊盘9上都覆盖有性能稳定的焊锡部5，故在贴装电子器件时不需要再上锡。因此，本申请实施例所提供的基板1可以有效的防止焊盘9被氧化腐蚀，还可以提高焊盘9与焊锡部5的连接稳定性，从而有利于提高产品的可靠性，例如提高产品的良率和使用寿命。
如图3所示，步骤S202包括以下步骤：
在电路基板2上整面沉积锡金属膜10；
对锡金属膜10进行图案化处理，形成焊锡层3。
具体的，锡金属膜10的沉积方法包括PVD、电镀和蒸镀中的任意一种。沉积过程中使用的金属锡靶材的种类和型号不做限制。
具体的，如图3所示，对锡金属膜10进行图案化处理，包括以下步骤：
在锡金属膜10上形成图案化的光阻层11；
以图案化的光阻层11为掩膜对锡金属膜10进行刻蚀，以形成焊锡层3；以及
移除图案化的光阻层11。
具体的，采用掩膜板和黄光制程形成图案化的光阻层11。其中，掩膜板的材料包括金属，但不限于此。
可以理解的，本申请实施例中的焊锡层3与阵列基板中的部分膜层的制程匹配度较高。也就是说，本申请实施例中的焊锡层3的制程与现有的制作阵列基板的设备兼容性较高。由于现有的阵列基板的制程精度高，使得焊锡层3的制程精度也较高，故本申请实施中的基板1可以贴装尺寸更小的电子器件，还有利于提高SMT制程的良率。
因此，当本申请实施例中的基板1应用于直显产品时，可以制作高分辨率且高良率的直显产品。另外，物理气相沉积工艺、黄光制程和刻蚀工艺都是很成熟的工艺，且与制作阵列基板的设备兼容性高，因此，本申请实施例所提供的基板适合大规模批量生产。
具体的，可以在本申请所提供的基板1上采用SMT制程贴装电子器件；其中，SMT制程包括贴片、固晶和刺晶中的任意一种。
具体的，电子器件包括发光芯片、集成电路芯片（IC）、电阻和电容中的任意一种或多种，且不限于以上列举的几种。其中，发光芯片包括LED芯片、Mini-LED芯片和Micro-LED芯片中的任意一种或多种。
需要说明的是，由于本申请实施例所提供的基板1为自带锡基板，当采用SMT制程在基板1上贴装电子器件时，不需要额外的制作焊锡膏，只需要印刷一层图案化的助焊剂即可。因此，本申请实施例所提供的自带锡基板和自带锡器件一样，可以在SMT制程中降低印刷助焊剂的难度，从而有利于提高SMT制程的良率。
具体的，由于本申请实施例所提供的基板1自带焊锡层3，当待贴装的电子器件为发光芯片或IC时，焊锡层3中的焊锡单元4可以充当发光芯片或IC的焊盘，使得发光芯片或IC不需要单独进行封装就可以与基板1进行贴装。也就是说，本申请实施例中的电子器件可以为裸晶。因此，使用本申请实施例所提供的基板1制作显示产品或发光产品时，不需要进行芯片封装，有利于节省巨额的封装费用，且可以摆脱对器件封装工厂的依赖。
因此，与自带锡器件相比，本申请实施例所提供的自带锡基板可以在节省封装成本的基础上有效的提高SMT制程的良率。
综上，本申请实施例所提供的基板的制作方法具有以下优势：有效的避免焊盘氧化、有效的提高SMT制程的良率、有利于提高直显产品的分辨率、有利于基板和直显产品的大规模批量生产、以及大大的节省封装成本等。
如图4所示，本申请实施例还提供一种采用前述实施例所述的基板制作得到的发光装置12，发光装置12包括前述实施例提供的基板1以及位于基板1上的多个电子器件13；其中，多个电子器件13与多个焊锡单元4一一对应固定连接。
具体的，电子器件13包括发光芯片、集成电路芯片（IC）、电阻和电容中的任意一种或多种，且不限于以上列举的几种。其中，发光芯片包括LED芯片、Mini-LED芯片和Micro-LED芯片中的任意一种或多种。
在本申请实施例中，以电子器件13为发光芯片为例进行说明。具体的，发光芯片为裸晶。
具体的，电子器件13与对应的焊锡单元4中的焊锡部5通过焊接工艺（例如回流焊）固定连接。
在一具体实施方式中，发光装置12还包括位于每个电子器件13和对应的焊锡单元4之间的助焊层14。具体的，助焊层14可以采用钢网印刷制作得到。
本申请实施例中，由于发光装置12中的基板1为自带锡基板，一方面可以在大幅地节省封装成本的基础上有效的提高SMT制程的良率，从而可以大幅地降低生产成本以及提高产品良率；另一方面有利于发光装置12大规模批量生产。
如图5所示，本申请实施例还提供一种显示装置15，显示装置15包括前述任意一个实施例提供的基板1、位于基板1上的多个电子器件13、以及位于电子器件13远离基板1一侧的功能结构16；其中，多个电子器件13与多个焊锡单元4一一对应固定连接。
具体的，电子器件13包括发光芯片、集成电路芯片（IC）、电阻和电容中的任意一种或多种，且不限于以上列举的几种。其中，发光芯片包括LED芯片、Mini-LED芯片和Micro-LED芯片中的任意一种或多种。
在本申请实施例中，以电子器件13为发光芯片为例进行说明。具体的，发光芯片为裸晶。
具体的，电子器件13与对应的焊锡单元4中的焊锡部5通过焊接工艺（例如回流焊）固定连接。
在一具体实施方式中，显示装置15还包括位于每个电子器件13和对应的焊锡单元4之间的助焊层14。具体的，助焊层14可以采用钢网印刷制作得到。
在一具体实施方式中，显示装置15为Mini-LED或Micro-LED直显装置；对应的，功能结构16为彩色滤光层。
在另一具体实施方式中，显示装置15为液晶显示装置15；对应的，功能结构16为液晶盒。可以理解的，此时基板1和电子器件13组合用作背光源，为液晶盒提供光源。
本申请实施例中，由于显示装置15中的基板1为自带锡基板，一方面可以在大幅地节省封装成本的基础上有效的提高SMT制程的良率，从而可以大幅地降低生产成本以及提高产品良率；另一方面可以有效的提高显示装置15的分辨率，从而提高显示效果；再一方面还有利于显示装置15大规模批量生产。
在上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详述的部分，可以参见其他实施例的相关描述。
以上对本申请实施例所提供的一种基板及其制作方法、显示装置进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的技术方案及其核心思想；本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例的技术方案的范围。

Claims (20)

  1. 一种基板，用于贴装电子器件，其中，包括电路基板和位于电路基板上的焊锡层；
    其中，所述焊锡层包括呈阵列分布的多个焊锡单元，每个所述焊锡单元包括间隔设置的两个焊锡部，且每个所述焊锡部与所述电路基板电连接。
  2. 根据权利要求1所述的基板，其中，所述电路基板包括衬底基板和位于所述衬底基板上的走线层；所述焊锡层位于所述走线层远离所述衬底基板的一侧，且每个所述焊锡部与所述走线层电连接。
  3. 根据权利要求2所述的基板，其中，所述电路基板还包括位于所述焊锡层和所述走线层之间的多个焊盘组；所述多个焊盘组与所述多个焊锡单元一一对应设置，且与所述走线层电连接；
    每个所述焊盘组包括间隔设置的两个焊盘，所述焊锡单元中的两个所述焊锡部分别位于对应的所述焊盘组中的两个所述焊盘上。
  4. 根据权利要求3所述的基板，其中，所述焊锡部覆盖在对应的所述焊盘远离所述衬底基板的一侧。
  5. 根据权利要求3所述的基板，其中，所述焊盘的材料包括金属铜。
  6. 根据权利要求3所述的基板，其中，所述走线层包括与多个所述焊锡单元一一对应电连接的多个驱动电路单元，多个所述焊盘组与多个所述驱动电路单元一一对应电连接。
  7. 根据权利要求6所述的基板，其中，每个所述驱动电路单元至少包括一个薄膜晶体管和一条低压电源走线，所述驱动电路单元中的薄膜晶体管与对应的所述焊盘组中的其中一个焊盘电连接，且所述低压电源走线与对应的所述焊盘组中的另一个焊盘连接。
  8. 一种如权利要求1所述的基板的制作方法，其中，包括以下步骤：
    提供电路基板；
    在所述电路基板上形成焊锡层；其中，所述焊锡层包括呈阵列分布的多个焊锡单元，每个所述焊锡单元包括间隔设置的两个焊锡部，且每个所述焊锡部与所述电路基板电连接。
  9. 根据权利要求8所述的基板的制作方法，其中，所述在所述电路基板上形成焊锡层，包括以下步骤：
    在所述电路基板上整面沉积锡金属膜；
    对所述锡金属膜进行图案化处理，形成焊锡层。
  10. 根据权利要求9所述的基板的制作方法，其中，所述锡金属膜的沉积方法包括物理气相沉积、电镀和蒸镀中的任意一种。
  11. 根据权利要求10所述的基板的制作方法，其中，所述对所述锡金属膜进行图案化处理，包括以下步骤：
    在所述锡金属膜上形成图案化的光阻层；
    以所述图案化的光阻层为掩膜对所述锡金属膜进行刻蚀，以形成焊锡层；以及
    移除所述图案化的光阻层。
  12. 根据权利要求11所述的基板的制作方法，其中，所述在所述锡金属膜上形成图案化的光阻层，包括以下步骤：
    采用掩膜板和黄光制程形成图案化的光阻层。
  13. 根据权利要求12所述的基板的制作方法，其中，所述掩膜板的材料包括金属。
  14. 一种显示装置，包括如权利要求1所述的基板和位于所述基板上的多个电子器件；其中，所述多个电子器件与所述多个焊锡单元一一对应固定连接。
  15. 根据权利要求14所述的显示装置，其中，所述显示装置还包括位于每个所述电子器件和对应的所述焊锡单元之间的助焊层。
  16. 根据权利要求14所述的显示装置，其中，所述电子器件包括发光芯片、集成电路芯片和电阻中的任意一种或多种。
  17. 根据权利要求16所述的显示装置，其中，所述发光芯片包括LED芯片、Mini-LED芯片和Micro-LED芯片中的任意一种或多种。
  18. 根据权利要求14所述的显示装置，其中，所述显示装置还包括位于所述电子器件远离所述基板一侧的功能结构。
  19. 根据权利要求18所述的显示装置，其中，所述显示装置为Mini-LED直显装置或Micro-LED直显装置，所述功能结构为彩色滤光层。
  20. 根据权利要求18所述的显示装置，其中，所述显示装置为液晶显示装置，所述功能结构为液晶盒。
PCT/CN2023/128046 2022-12-07 2023-10-31 一种基板及其制作方法、显示装置 WO2024120061A1 (zh)

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