WO2024114254A1 - 一种肖特基势垒二极管及其制备方法和应用 - Google Patents
一种肖特基势垒二极管及其制备方法和应用 Download PDFInfo
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- 230000004888 barrier function Effects 0.000 title claims abstract description 67
- 238000002360 preparation method Methods 0.000 title claims abstract description 31
- 229910052751 metal Inorganic materials 0.000 claims abstract description 128
- 239000002184 metal Substances 0.000 claims abstract description 128
- 238000002161 passivation Methods 0.000 claims abstract description 88
- 229910002704 AlGaN Inorganic materials 0.000 claims abstract description 24
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 239000000203 mixture Substances 0.000 claims abstract 2
- 238000000206 photolithography Methods 0.000 claims description 20
- 230000008020 evaporation Effects 0.000 claims description 15
- 238000001704 evaporation Methods 0.000 claims description 15
- 230000006911 nucleation Effects 0.000 claims description 14
- 238000010899 nucleation Methods 0.000 claims description 14
- 238000000034 method Methods 0.000 claims description 8
- 229910045601 alloy Inorganic materials 0.000 claims description 6
- 239000000956 alloy Substances 0.000 claims description 6
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 6
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 4
- 229910052782 aluminium Inorganic materials 0.000 claims description 4
- 230000008021 deposition Effects 0.000 claims description 4
- 229910052737 gold Inorganic materials 0.000 claims description 4
- 229910052759 nickel Inorganic materials 0.000 claims description 4
- 229910052709 silver Inorganic materials 0.000 claims description 4
- 229910052718 tin Inorganic materials 0.000 claims description 4
- 229910052719 titanium Inorganic materials 0.000 claims description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims 3
- 229910052681 coesite Inorganic materials 0.000 claims 3
- 229910052906 cristobalite Inorganic materials 0.000 claims 3
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 claims 3
- 229910003465 moissanite Inorganic materials 0.000 claims 3
- 239000000377 silicon dioxide Substances 0.000 claims 3
- 235000012239 silicon dioxide Nutrition 0.000 claims 3
- 229910052682 stishovite Inorganic materials 0.000 claims 3
- 229910052905 tridymite Inorganic materials 0.000 claims 3
- 230000015556 catabolic process Effects 0.000 abstract description 7
- 230000001052 transient effect Effects 0.000 abstract description 5
- 239000010410 layer Substances 0.000 description 109
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 32
- 229910002601 GaN Inorganic materials 0.000 description 31
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 description 18
- 238000005530 etching Methods 0.000 description 12
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 12
- 229910001020 Au alloy Inorganic materials 0.000 description 9
- 229910000990 Ni alloy Inorganic materials 0.000 description 9
- 238000005566 electron beam evaporation Methods 0.000 description 9
- 238000010894 electron beam technology Methods 0.000 description 9
- 230000005684 electric field Effects 0.000 description 8
- 229910004298 SiO 2 Inorganic materials 0.000 description 6
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 4
- -1 Si 3 N 4 Inorganic materials 0.000 description 3
- 238000000137 annealing Methods 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 239000012299 nitrogen atmosphere Substances 0.000 description 3
- 101001121408 Homo sapiens L-amino-acid oxidase Proteins 0.000 description 2
- 102100026388 L-amino-acid oxidase Human genes 0.000 description 2
- 230000000052 comparative effect Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000002401 inhibitory effect Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Definitions
- the present invention relates to the technical field of semiconductor devices, and in particular to a Schottky barrier diode and a preparation method and application thereof.
- Schottky barrier diodes also known as hot carrier diodes, are indispensable devices in most power electronic products. They need to have a low turn-on voltage, a specific on-resistance, a low reverse leakage current, and a high breakdown voltage to reduce power loss during use.
- Gallium nitride (GaN) has a large bandgap and a high electron mobility.
- SBDs AlGaN/GaN Schottky barrier diodes
- SiC silicon carbide
- Si/GaN-based Schottky barrier diodes have both good performance and low cost, and have great commercialization potential, which has attracted widespread attention.
- the existing Si/GaN-based Schottky barrier diodes have problems such as poor transient tolerance, poor withstand voltage and breakdown resistance, and reliability that needs to be improved, which makes it difficult to fully meet the growing practical application needs.
- the purpose of the present invention is to provide a Schottky barrier diode and a preparation method and application thereof.
- a Schottky barrier diode comprising a Si substrate, an AlN nucleation layer, a GaN buffer layer and an AlGaN barrier layer stacked in sequence, and also comprising a first passivation layer, a second passivation layer, a cathode metal electrode, a first anode metal field plate, a third passivation layer, a second anode metal field plate and an anode metal electrode;
- the first passivation layer is arranged on the side of the AlN nucleation layer away from the Si substrate and in contact with the GaN buffer layer;
- the second passivation layer is L-shaped, with one side covering the side of the AlGaN barrier layer away from the GaN buffer layer, and the other side in contact with the GaN buffer layer;
- the cathode metal electrode is arranged on the side of the AlGaN barrier layer away from the GaN buffer layer, and is in contact with both the second passivation layer and the third passivation layer;
- the first anode metal field plate is L-shaped, covers the corner of the second passivation layer, and contacts the GaN buffer layer;
- the third passivation layer is L-shaped, covers the second passivation layer and the first anode metal field plate, and is in contact with both the GaN buffer layer and the first passivation layer;
- the second anode metal field plate is L-shaped, covers the corner of the third passivation layer, and contacts the first passivation layer;
- the anode metal electrode sequentially penetrates the second anode metal field plate, the third passivation layer, the first anode metal field plate, the second passivation layer and the AlGaN barrier layer, and contacts the GaN buffer layer.
- the thickness of the AlN nucleation layer is 1 nm to 5 nm.
- the thickness of the GaN buffer layer is 300 nm to 350 nm.
- the AlGaN barrier layer has a thickness of 15 nm to 25 nm.
- the AlGaN barrier layer comprises Al x GaN, wherein x is 0.2 to 0.3.
- the first passivation layer comprises at least one of SiO 2 , Si 3 N 4 , SiC and HfO 2 .
- the thickness of the first passivation layer is 50 nm to 100 nm.
- the second passivation layer comprises at least one of SiO 2 , Si 3 N 4 , SiC and HfO 2 .
- the thickness of the second passivation layer is 50 nm to 100 nm.
- the cathode metal electrode comprises at least one of Ti, Al, Ni, Au, Ag and TiN.
- the width of the cathode metal electrode is 5 ⁇ m to 10 ⁇ m.
- one side of the first anode metal field plate has a length of 3 ⁇ m to 5 ⁇ m and a thickness of 40 nm to 60 nm, and the other side has a length of 3 ⁇ m to 5 ⁇ m and a thickness of 500 nm to 800 nm.
- the third passivation layer comprises at least one of SiO 2 , Si 3 N 4 , SiC and HfO 2 .
- the thickness of the third passivation layer is 200 nm to 300 nm.
- one side of the second anode metal field plate has a length of 5 ⁇ m to 7 ⁇ m and a thickness of 40 nm to 60 nm, and the other side has a length of 3 ⁇ m to 5 ⁇ m and a thickness of 1.2 ⁇ m to 1.5 ⁇ m.
- the anode metal electrode comprises at least one of Ti, Al, Ni, Au, Ag and TiN.
- the distance between the cathode metal electrode and the anode metal electrode is 15 ⁇ m to 20 ⁇ m.
- a method for preparing the Schottky barrier diode as described above comprises the following steps:
- An electronic device comprises the above-mentioned Schottky barrier diode.
- the present invention reduces the peak electric field strength at the edge of the anode metal electrode through a lateral double anode field plate (the lateral part of the first anode metal field plate and the second anode metal field plate), and introduces the electric field at the channel into the underlying GaN buffer layer through a longitudinal double anode field plate (the longitudinal part of the first anode metal field plate and the second anode metal field plate), thereby reducing the peak electric field at the channel, thereby improving the device's withstand voltage and breakdown resistance and reducing leakage current, and can significantly reduce the peak electric field strength at the edge of the device, thereby inhibiting the current collapse effect and improving the reliability of the device.
- the lateral and longitudinal double-layer field plates make the electric field at the metal edge more uniform, thereby improving the breakdown voltage of the device.
- the Schottky barrier diode of the present invention has the advantages of high transient tolerance, strong withstand voltage and anti-breakdown performance, high reliability, etc., and is suitable for large-scale promotion and application.
- the Schottky barrier diode of the present invention adopts a lateral double field plate design (the lateral part of the first anode metal field plate and the second anode metal field plate), which reduces the peak electric field strength and leakage current at the edge of the anode metal electrode, and can effectively improve the reliability of the device;
- the Schottky barrier diode of the present invention adopts a longitudinal double field plate design (the longitudinal part of the first anode metal field plate and the second anode metal field plate), which introduces the electric field into the GaN buffer layer below, reduces the peak electric field at the channel, and can effectively improve the breakdown voltage of the device.
- FIG1 is a schematic structural diagram of a Schottky barrier diode of the present invention.
- Embodiment 1 is a diagrammatic representation of Embodiment 1:
- a Schottky barrier diode (schematic structure as shown in FIG1 ), comprising a Si substrate 10, an AlN nucleation layer 20, a GaN buffer layer 30 and an AlGaN barrier layer 40 stacked in sequence, and further comprising a first passivation layer 50, a second passivation layer 60, a cathode metal electrode 70, a first anode metal field plate 80, a third passivation layer 90, a second anode metal field plate 100 and an anode metal electrode 110;
- the first passivation layer 50 is disposed on the side of the AlN nucleation layer 20 away from the Si substrate 10 and in contact with the GaN buffer layer 30;
- the second passivation layer 60 is L-shaped, with one side covering the side of the AlGaN barrier layer 40 away from the GaN buffer layer 30 , and the other side in contact with the GaN buffer layer 30 ;
- the cathode metal electrode 70 is disposed on the side of the AlGaN barrier layer 40 away from the GaN buffer layer 30 , and is in contact with both the second passivation layer 60 and the third passivation layer 90 ;
- the first anode metal field plate 80 is L-shaped, covers the corner of the second passivation layer 60 , and contacts the GaN buffer layer 30 ;
- the third passivation layer 90 is L-shaped, covers the second passivation layer 60 and the first anode metal field plate 80 , and is in contact with both the GaN buffer layer 30 and the first passivation layer 50 ;
- the second anode metal field plate 100 is L-shaped, covers the corner of the third passivation layer 90 , and contacts the first passivation layer 50 ;
- the anode metal electrode 110 sequentially penetrates the second anode metal field plate 100 , the third passivation layer 90 , the first anode metal field plate 80 , the second passivation layer 60 and the AlGaN barrier layer 40 , and contacts the GaN buffer layer 30 .
- the method for preparing the Schottky barrier diode comprises the following steps:
- AlN nucleation layer with a thickness of 1 nm, a GaN buffer layer with a thickness of 300 nm, and an AlGaN barrier layer (Al 0.2 GaN) with a thickness of 20 nm on a Si substrate by metal organic chemical vapor deposition (MOCVD) method;
- MOCVD metal organic chemical vapor deposition
- Embodiment 2 is a diagrammatic representation of Embodiment 1:
- a Schottky barrier diode the structure of which is the same as that of the Schottky barrier diode in Example 1, and the preparation method thereof comprises the following steps:
- AlN nucleation layer with a thickness of 1 nm, a GaN buffer layer with a thickness of 300 nm, and an AlGaN barrier layer (Al 0.2 GaN) with a thickness of 20 nm on a Si substrate by metal organic chemical vapor deposition (MOCVD) method;
- MOCVD metal organic chemical vapor deposition
- Embodiment 3 is a diagrammatic representation of Embodiment 3
- a Schottky barrier diode the structure of which is the same as that of the Schottky barrier diode in Example 1, and the preparation method thereof comprises the following steps:
- MOCVD metal organic chemical vapor deposition
- a Schottky barrier diode is the same as the Schottky barrier diode of embodiment 1 except that the first anode metal field plate and the second anode metal field plate have only a transverse portion (no longitudinal portion).
- the Schottky barrier diodes of Examples 1 to 3 After testing, the Schottky barrier diodes of Examples 1 to 3 have the advantages of high transient tolerance, strong voltage resistance and anti-breakdown performance, high reliability, etc., and the performance in the above aspects is significantly better than that of the Schottky barrier diode of the comparative example.
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Abstract
本发明公开了一种肖特基势垒二极管及其制备方法和应用。本发明的肖特基势垒二极管的组成包括依次层叠设置的Si衬底、AlN成核层、GaN缓冲层和AlGaN势垒层,还包括第一钝化层、第二钝化层、阴极金属电极、第一阳极金属场板、第三钝化层、第二阳极金属场板和阳极金属电极。本发明的肖特基势垒二极管具有瞬变耐受性较高、耐压和抗击穿性能强、可靠性高等优点,适合进行大规模推广应用。
Description
本发明涉及半导体器件技术领域,具体涉及一种肖特基势垒二极管及其制备方法和应用。
肖特基势垒二极管,又称热载流子二极管,是大多数电力电子产品中不可或缺的器件,其需要具有较低的开启电压、特定的导通电阻、较低的反向泄漏电流和较高的击穿电压,用以减少使用过程中的功率损失。氮化镓(GaN)具有较大的禁带宽度和较高的电子迁移率,以蓝宝石或碳化硅(SiC)为衬底的AlGaN/GaN肖特基势垒二极管(SBD)的性能要显著优于其他材料体系的肖特基势垒二极管,应用前景更加广阔。Si/GaN基肖特基势垒二极管兼具较好的性能和较低的成本,具有很好的商业化潜力,引起了人们的广泛关注。然而,现有的Si/GaN基肖特基势垒二极管存在瞬变耐受性较差、耐压和抗击穿性能较差、可靠性有待提高等问题,难以完全满足日益增长的实际应用需求。
因此,开发一种具有较高的瞬变耐受性、耐压和抗击穿性能强、可靠性高的肖特基势垒二极管具有十分重要的意义。
发明内容
本发明的目的在于提供一种肖特基势垒二极管及其制备方法和应用。
本发明所采取的技术方案是:
一种肖特基势垒二极管,其组成包括依次层叠设置的Si衬底、AlN成核层、GaN缓冲层和AlGaN势垒层,还包括第一钝化层、第二钝化层、阴极金属电极、第一阳极金属场板、第三钝化层、第二阳极金属场板和阳极金属电极;
所述第一钝化层设置在AlN成核层远离Si衬底的那面,且与GaN缓冲层接触;
所述第二钝化层呈L型,一条边覆盖在AlGaN势垒层远离GaN缓冲层的那面,另一条边与GaN缓冲层接触;
所述阴极金属电极设置在AlGaN势垒层远离GaN缓冲层的那面,且与第二钝化层和第三钝化层均有接触;
所述第一阳极金属场板呈L型,覆盖在第二钝化层的拐角处,且与GaN缓冲层接触;
所述第三钝化层呈L型,覆盖第二钝化层和第一阳极金属场板,且与GaN缓冲层和第一钝化层均有接触;
所述第二阳极金属场板呈L型,覆盖在第三钝化层的拐角处,且与第一钝化层接触;
所述阳极金属电极依次贯穿第二阳极金属场板、第三钝化层、第一阳极金属场板、第二钝化层和AlGaN势垒层,且与GaN缓冲层接触。
优选的,所述AlN成核层的厚度为1nm~5nm。
优选的,所述GaN缓冲层的厚度为300nm~350nm。
优选的,所述AlGaN势垒层的厚度为15nm~25nm。
优选的,所述AlGaN势垒层的组成成分包括AlxGaN,式中,x为0.2~0.3。
优选的,所述第一钝化层的组成成分包括SiO2、Si3N4、SiC、HfO2中的至少一种。
优选的,所述第一钝化层的厚度为50nm~100nm。
优选的,所述第二钝化层的组成成分包括SiO2、Si3N4、SiC、HfO2中的至少一种。
优选的,所述第二钝化层的厚度为50nm~100nm。
优选的,所述阴极金属电极的组成成分包括Ti、Al、Ni、Au、Ag、TiN中的至少一种。
优选的,所述阴极金属电极的宽度为5μm~10μm。
优选的,所述第一阳极金属场板的一条边的长度为3μm~5μm、厚度为40nm~60nm,另一条边的长度为3μm~5μm、厚度为500nm~800nm。
优选的,所述第三钝化层的组成成分包括SiO2、Si3N4、SiC、HfO2中的至少一种。
优选的,所述第三钝化层的厚度为200nm~300nm。
优选的,所述第二阳极金属场板的一条边的长度为5μm~7μm、厚度为40nm~60nm,另一条边的长度为3μm~5μm、厚度为1.2μm~1.5μm。
优选的,所述阳极金属电极的组成成分包括Ti、Al、Ni、Au、Ag、TiN中的至少一种。
优选的,所述阳极金属电极的宽度为5μm~10μm。
优选的,所述阴极金属电极和阳极金属电极之间的距离为15μm~20μm。
一种如上所述的肖特基势垒二极管的制备方法包括以下步骤:
1)在Si衬底上依次外延生长AlN成核层、GaN缓冲层和AlGaN势垒层;
2)进行光刻,暴露出阴极金属电极制备区域,再进行合金蒸镀和剥离,形成阴极金属电极;
3)进行光刻,暴露出第一钝化层和第二钝化层制备区域,再进行沉积形成第一钝化层和第二钝化层;
4)进行光刻,暴露出阳极金属电极制备区域和第一阳极金属场板制备区域,再进行合金蒸镀和剥离,形成阳极金属电极和第一阳极金属场板;
5)进行沉积,形成第三钝化层;
6)进行光刻,暴露出第二阳极金属场板制备区域,再进行合金蒸镀和剥离,形成第二阳极金属场板,即得肖特基势垒二极管。
一种电子设备,其组成包括上述肖特基势垒二极管。
本发明的原理:本发明通过横向双阳极场板(第一阳极金属场板和第二阳极金属场板的横向部分)来降低阳极金属电极边缘处的峰值电场强度,并通过纵向双阳极场板(第一阳极金属场板和第二阳极金属场板的纵向部分)将沟道处的电场引入下方GaN缓冲层从而降低沟道处的峰值电场,进而提高器件的耐压和抗击穿能力以及减少漏电流,可以明显减少器件边缘处的峰值电场强度,从而抑制电流崩塌效应,提高器件的可靠性,且区别于传统的单层场板,横向与纵向双层场板使得金属边缘处电场更加均匀,提高了器件的击穿电压。
本发明的有益效果是:本发明的肖特基势垒二极管具有瞬变耐受性较高、耐压和抗击穿性能强、可靠性高等优点,适合进行大规模推广应用。
具体来说:
1)本发明的肖特基势垒二极管中采用横向双场板(第一阳极金属场板和第二阳极金属场板的横向部分)设计,降低了阳极金属电极边缘处的峰值电场强度和漏电流,可以有效提高器件的可靠性;
2)本发明的肖特基势垒二极管中采用纵向双场板(第一阳极金属场板和第二阳极金属场板的纵向部分)设计,将电场引入下方GaN缓冲层内部,降低了沟道处的峰值电场,可以有效提高器件的击穿电压。
图1为本发明的肖特基势垒二极管的结构示意图。
附图标识说明:10、Si衬底;20、AlN成核层;30、GaN缓冲层;40、AlGaN势垒层;50、第一钝化层;60、第二钝化层;70、阴极金属电极;80、第一阳极金属场板;90、第三钝化层;100、第二阳极金属场板;110、阳极金属电极。
下面结合具体实施例对本发明作进一步的解释和说明。
实施例1:
一种肖特基势垒二极管(结构示意图如图1所示),其组成包括依次层叠设置的Si衬底10、AlN成核层20、GaN缓冲层30和AlGaN势垒层40,还包括第一钝化层50、第二钝化层60、阴极金属电极70、第一阳极金属场板80、第三钝化层90、第二阳极金属场板100和阳极金属电极110;
第一钝化层50设置在AlN成核层20远离Si衬底10的那面,且与GaN缓冲层30接触;
第二钝化层60呈L型,一条边覆盖在AlGaN势垒层40远离GaN缓冲层30的那面,另一条边与GaN缓冲层30接触;
阴极金属电极70设置在AlGaN势垒层40远离GaN缓冲层30的那面,且与第二钝化层60和第三钝化层90均有接触;
第一阳极金属场板80呈L型,覆盖在第二钝化层60的拐角处,且与GaN缓冲层30接触;
第三钝化层90呈L型,覆盖第二钝化层60和第一阳极金属场板80,且与GaN缓冲层30和第一钝化层50均有接触;
第二阳极金属场板100呈L型,覆盖在第三钝化层90的拐角处,且与第一钝化层50接触;
阳极金属电极110依次贯穿第二阳极金属场板100、第三钝化层90、第一阳极金属场板80、第二钝化层60和AlGaN势垒层40,且与GaN缓冲层30接触。
上述肖特基势垒二极管的制备方法包括以下步骤:
1)采用金属有机化学气相沉积(MOCVD)法在Si衬底上依次外延生长厚度为1nm的AlN成核层、厚度为300nm的GaN缓冲层和厚度为20nm的AlGaN势垒层(Al0.2GaN);
2)进行光刻,暴露出阴极金属电极制备区域,再进行Ti/Al/Ni/Au合金蒸镀,采用电子束蒸发,电子束能量为3kV,真空度P≤10-3Pa,再采用丙酮进行剥离,再置于N2氛围中进行退火,形成阴极金属电极,阴极金属电极的宽度为5μm;
3)进行光刻和可控CF4刻蚀源刻蚀,暴露出第一钝化层和第二钝化层制备区域,再采用低压力化学气相沉积法(LPCVD)沉积厚度为60nm的Si3N4,形成第一钝化层和第二钝化层;
4)进行光刻和可控CF4刻蚀源刻蚀,暴露出阳极金属电极制备区域和第一阳极金属场板制备区域,再进行Ni/Au合金蒸镀,采用电子束蒸发,电子束能量为3kV,真空度P≤10-3Pa,再采用丙酮进行剥离,形成阳极金属电极和第一阳极金属场板,阳极金属电极的宽度为5μm,阳极金属电极与阴极金属电极之间的距离为20μm,第一阳极金属场板的横向边的长度为4μm、
厚度为60nm,竖向边的长度为5μm、厚度为500nm;
5)采用低压力化学气相沉积(LPCVD)法沉积厚度为300nm的SiO2,形成第三钝化层;
6)进行光刻,暴露出第二阳极金属场板制备区域,再进行Ni/Au合金蒸镀,采用电子束蒸发,电子束能量为3kV,真空度P≤10-3Pa,再采用丙酮进行剥离,形成第二阳极金属场板,第二阳极金属场板的一条边的长度为6μm、厚度为40nm,另一条边的长度为3μm、厚度为1.2μm,即得肖特基势垒二极管。
实施例2:
一种肖特基势垒二极管,结构与实施例1的肖特基势垒二极管相同,其制备方法包括以下步骤:
1)采用金属有机化学气相沉积(MOCVD)法在Si衬底上依次外延生长厚度为1nm的AlN成核层、厚度为300nm的GaN缓冲层和厚度为20nm的AlGaN势垒层(Al0.2GaN);
2)进行光刻,暴露出阴极金属电极制备区域,再进行Ti/Al/Ni/Au合金蒸镀,采用电子束蒸发,电子束能量为3kV,真空度P≤10-3Pa,再采用丙酮进行剥离,再置于N2氛围中进行退火,形成阴极金属电极,阴极金属电极的宽度为5μm;
3)进行光刻和可控CF4刻蚀源刻蚀,暴露出第一钝化层和第二钝化层制备区域,再采用低压力化学气相沉积法(LPCVD)沉积厚度为60nm的Si3N4,形成第一钝化层和第二钝化层;
4)进行光刻和可控CF4刻蚀源刻蚀,暴露出阳极金属电极制备区域和第一阳极金属场板制备区域,再进行Ni/Au合金蒸镀,采用电子束蒸发,电子束能量为3kV,真空度P≤10-3Pa,再采用丙酮进行剥离,形成阳极金属电极和第一阳极金属场板,阳极金属电极的宽度为5μm,阳极金属电极与阴极金属电极之间的距离为20μm,第一阳极金属场板的横向边的长度为4μm、厚度为60nm,竖向边的长度为5μm、厚度为600nm;
5)采用低压力化学气相沉积(LPCVD)法沉积厚度为300nm的SiO2,形成第三钝化层;
6)进行光刻,暴露出第二阳极金属场板制备区域,再进行Ni/Au合金蒸镀,采用电子束蒸发,电子束能量为3kV,真空度P≤10-3Pa,再采用丙酮进行剥离,形成第二阳极金属场板,第二阳极金属场板的一条边的长度为6μm、厚度为50nm,另一条边的长度为4μm、厚度为1.3μm,即得肖特基势垒二极管。
实施例3:
一种肖特基势垒二极管,结构与实施例1的肖特基势垒二极管相同,其制备方法包括以下步骤:
1)采用金属有机化学气相沉积(MOCVD)法在Si衬底上依次外延生长厚度为1nm的
AlN成核层、厚度为300nm的GaN缓冲层和厚度为20nm的AlGaN势垒层(Al0.2GaN);
2)进行光刻,暴露出阴极金属电极制备区域,再进行Ti/Al/Ni/Au合金蒸镀,采用电子束蒸发,电子束能量为3kV,真空度P≤10-3Pa,再采用丙酮进行剥离,再置于N2氛围中进行退火,形成阴极金属电极,阴极金属电极的宽度为5μm;
3)进行光刻和可控CF4刻蚀源刻蚀,暴露出第一钝化层和第二钝化层制备区域,再采用低压力化学气相沉积法(LPCVD)沉积厚度为60nm的Si3N4,形成第一钝化层和第二钝化层;
4)进行光刻和可控CF4刻蚀源刻蚀,暴露出阳极金属电极制备区域和第一阳极金属场板制备区域,再进行Ni/Au合金蒸镀,采用电子束蒸发,电子束能量为3kV,真空度P≤10-3Pa,再采用丙酮进行剥离,形成阳极金属电极和第一阳极金属场板,阳极金属电极的宽度为5μm,阳极金属电极与阴极金属电极之间的距离为20μm,第一阳极金属场板的横向边的长度为4μm、厚度为60nm,竖向边的长度为5μm、厚度为700nm;
5)采用低压力化学气相沉积(LPCVD)法沉积厚度为300nm的SiO2,形成第三钝化层;
6)进行光刻,暴露出第二阳极金属场板制备区域,再进行Ni/Au合金蒸镀,采用电子束蒸发,电子束能量为3kV,真空度P≤10-3Pa,再采用丙酮进行剥离,形成第二阳极金属场板,第二阳极金属场板的一条边的长度为6μm、厚度为60nm,另一条边的长度为5μm、厚度为1.4μm,即得肖特基势垒二极管。
对比例:
一种肖特基势垒二极管,除了第一阳极金属场板和第二阳极金属场板仅有横向部分(无纵向部分)以外,其余与实施例1的肖特基势垒二极管相同。
经测试,实施例1~3的肖特基势垒二极管具有瞬变耐受性较高、耐压和抗击穿性能强、可靠性高等优点,且上述几个方面的性能均要显著优于对比例的肖特基势垒二极管。
上述实施例为本发明较佳的实施方式,但本发明的实施方式并不受上述实施例的限制,其他的任何未背离本发明的精神实质与原理下所作的改变、修饰、替代、组合、简化,均应为等效的置换方式,都包含在本发明的保护范围之内。
Claims (10)
- 一种肖特基势垒二极管,其特征在于,组成包括依次层叠设置的Si衬底、AlN成核层、GaN缓冲层和AlGaN势垒层,还包括第一钝化层、第二钝化层、阴极金属电极、第一阳极金属场板、第三钝化层、第二阳极金属场板和阳极金属电极;所述第一钝化层设置在AlN成核层远离Si衬底的那面,且与GaN缓冲层接触;所述第二钝化层呈L型,一条边覆盖在AlGaN势垒层远离GaN缓冲层的那面,另一条边与GaN缓冲层接触;所述阴极金属电极设置在AlGaN势垒层远离GaN缓冲层的那面,且与第二钝化层和第三钝化层均有接触;所述第一阳极金属场板呈L型,覆盖在第二钝化层的拐角处,且与GaN缓冲层接触;所述第三钝化层呈L型,覆盖第二钝化层和第一阳极金属场板,且与GaN缓冲层和第一钝化层均有接触;所述第二阳极金属场板呈L型,覆盖在第三钝化层的拐角处,且与第一钝化层接触;所述阳极金属电极依次贯穿第二阳极金属场板、第三钝化层、第一阳极金属场板、第二钝化层和AlGaN势垒层,且与GaN缓冲层接触。
- 根据权利要求1所述的肖特基势垒二极管,其特征在于:所述AlN成核层的厚度为1nm~5nm。
- 根据权利要求1所述的肖特基势垒二极管,其特征在于:所述GaN缓冲层的厚度为300nm~350nm。
- 根据权利要求1所述的肖特基势垒二极管,其特征在于:所述AlGaN势垒层的厚度为15nm~25nm;所述AlGaN势垒层的组成成分包括AlxGaN,式中,x为0.2~0.3。
- 根据权利要求1~4中任意一项所述的肖特基势垒二极管,其特征在于:所述第一钝化层的组成成分包括SiO2、Si3N4、SiC、HfO2中的至少一种;所述第一钝化层的厚度为50nm~100nm;所述第二钝化层的组成成分包括SiO2、Si3N4、SiC、HfO2中的至少一种;所述第二钝化层的厚度为50nm~100nm;所述第三钝化层的组成成分包括SiO2、Si3N4、SiC、HfO2中的至少一种;所述第三钝化层的厚度为200nm~300nm。
- 根据权利要求1~4中任意一项所述的肖特基势垒二极管,其特征在于:所述第一阳极金属场板的一条边的长度为3μm~5μm、厚度为40nm~60nm,另一条边的长度为3μm~5μm、厚度为500nm~800nm;所述第二阳极金属场板的一条边的长度为5μm~7μm、厚度为40nm~60nm,另一条边的长度为3μm~5μm、厚度为1.2μm~1.5μm。
- 根据权利要求1~4中任意一项所述的肖特基势垒二极管,其特征在于:所述阴极金属电极的组成成分包括Ti、Al、Ni、Au、Ag、TiN中的至少一种;所述阴极金属电极的宽度为5μm~10μm;所述阳极金属电极的组成成分包括Ti、Al、Ni、Au、Ag、TiN中的至少一种;所述阳极金属电极的宽度为5μm~10μm。
- 根据权利要求1~4中任意一项所述的肖特基势垒二极管,其特征在于:所述阴极金属电极和阳极金属电极之间的距离为15μm~20μm。
- 一种如权利要求1~8中任意一项所述的肖特基势垒二极管的制备方法,其特征在于,包括以下步骤:1)在Si衬底上依次外延生长AlN成核层、GaN缓冲层和AlGaN势垒层;2)进行光刻,暴露出阴极金属电极制备区域,再进行合金蒸镀和剥离,形成阴极金属电极;3)进行光刻,暴露出第一钝化层和第二钝化层制备区域,再进行沉积形成第一钝化层和第二钝化层;4)进行光刻,暴露出阳极金属电极制备区域和第一阳极金属场板制备区域,再进行合金蒸镀和剥离,形成阳极金属电极和第一阳极金属场板;5)进行沉积,形成第三钝化层;6)进行光刻,暴露出第二阳极金属场板制备区域,再进行合金蒸镀和剥离,形成第二阳极金属场板,即得肖特基势垒二极管。
- 一种电子设备,其特征在于,组成包括权利要求1~8中任意一项所述的肖特基势垒二极管。
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