WO2024082348A1 - 一种半导体封装结构及制备方法 - Google Patents

一种半导体封装结构及制备方法 Download PDF

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Publication number
WO2024082348A1
WO2024082348A1 PCT/CN2022/129962 CN2022129962W WO2024082348A1 WO 2024082348 A1 WO2024082348 A1 WO 2024082348A1 CN 2022129962 W CN2022129962 W CN 2022129962W WO 2024082348 A1 WO2024082348 A1 WO 2024082348A1
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substrate
layer
interposer
lead pad
packaging structure
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PCT/CN2022/129962
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English (en)
French (fr)
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唐燕菲
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长鑫存储技术有限公司
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Publication of WO2024082348A1 publication Critical patent/WO2024082348A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/49—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions wire-like arrangements or pins or rods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/492—Bases or plates or solder therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H01L2021/60007—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving a soldering or an alloying process
    • H01L2021/60015—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving a soldering or an alloying process using plate connectors, e.g. layer, film
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H01L2021/60007—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving a soldering or an alloying process
    • H01L2021/60022—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving a soldering or an alloying process using bump connectors, e.g. for flip chip mounting

Definitions

  • the present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor packaging structure and a preparation method thereof.
  • embodiments of the present disclosure provide a semiconductor packaging structure and a manufacturing method thereof.
  • a semiconductor package structure including:
  • a first packaging structure comprising a substrate and an interposer, wherein the interposer comprises a first surface and a second surface arranged opposite to each other, a first lead pad is arranged on at least one side of the second surface, and the first lead pad protrudes from the second surface; wherein the interposer is connected to the substrate through the first lead pad;
  • the second packaging structure is located on the first surface of the interposer and is connected to the interposer.
  • an area of a portion of the first lead pad protruding from the second surface is larger than an area of a portion covered by the second surface.
  • an area of a portion of the first lead pad protruding from the second surface is 3 to 4 times an area of a portion covered by the second surface.
  • the interposer includes an interposer substrate and a first dielectric layer and a second dielectric layer respectively disposed on the upper surface and the lower surface of the interposer substrate, wherein the first dielectric layer is located on the first surface side of the interposer and the second dielectric layer is located on the second surface side of the interposer.
  • a first lead pad is disposed on at least one side of the second surface, and the first lead pad protrudes from the second surface, comprising:
  • the first lead pad is located in the second dielectric layer, and the interposer substrate exposes a portion of the first lead pad.
  • a first connecting pad is disposed in the first dielectric layer
  • a second connecting pad is disposed in the second dielectric layer
  • a first signal channel is disposed in the intermediate substrate, wherein the first signal channel connects the first connecting pad and the second connecting pad.
  • it also includes:
  • first lead pad is connected to the substrate via the first lead
  • One end of the first lead is located on a surface of the first lead pad that is away from the substrate, and the other end is located on a surface of the substrate that is adjacent to the interposer.
  • it also includes:
  • a chip stack is disposed on the substrate, wherein the chip stack comprises a plurality of chips stacked in sequence in a direction perpendicular to the substrate;
  • the interposer is disposed on the chip stack.
  • it also includes:
  • each of the chips is connected to the substrate via the second leads.
  • the first packaging structure further includes: a molding compound, wherein the molding compound wraps the interposer and is coplanar with the first connecting pad.
  • the substrate includes an upper surface and a lower surface that are opposite to each other, and a first conductive pattern and a second conductive pattern are respectively disposed on the upper surface and the lower surface;
  • the substrate further includes a second signal channel located between the upper surface and the lower surface, the second signal channel connecting the first conductive pattern and the second conductive pattern.
  • it also includes:
  • a filling layer is provided to fill up the gap.
  • a method for preparing a semiconductor package structure comprising:
  • a first packaging structure includes a substrate and an interposer, wherein the interposer includes a first surface and a second surface that are arranged opposite to each other, a first lead pad is arranged on at least one side of the second surface, and the first lead pad protrudes from the second surface; wherein the interposer is connected to the substrate through the first lead pad;
  • a second packaging structure is provided, wherein the second packaging structure is located on the first surface of the interposer and is connected to the interposer.
  • providing a first lead pad on at least one side of the second surface includes:
  • the first lead pad pre-layer is cut off from the through hole to form a first lead pad, wherein a portion of the surface of the first lead pad is exposed.
  • the method further includes:
  • a first dielectric layer is formed to wrap the first conductive layer, and a second dielectric layer is formed to wrap the second conductive layer and the first lead pad pre-layer.
  • the method further includes:
  • a metal layer is formed on the first conductive layer, the third conductive layer, and the first lead pad pre-layer.
  • a first lead pad is formed on at least one side of the second surface of the interposer, the second surface is a surface close to the substrate, and the first lead pad protrudes from the second surface, that is, the first lead pad exposes a portion of the surface, so that the substrate can be connected by bonding on the exposed surface of the first lead pad, and the height of the bonding is lower than the height of the interposer, and no additional bonding part is required during packaging, thereby reducing the packaging height of the semiconductor packaging structure.
  • the first packaging structure and the second packaging structure are independently packaged, the first packaging structure and the second packaging structure can be tested separately, so that failure analysis can be performed more quickly, and thus after the semiconductor packaging structure is formed, the overall structure can be tested.
  • FIG1 is a schematic structural diagram of a semiconductor packaging structure provided by an embodiment of the present disclosure.
  • FIG2 is a schematic diagram of the structure of an interposer provided in an embodiment of the present disclosure.
  • FIG3 is a schematic structural diagram of a semiconductor packaging structure provided by another embodiment of the present disclosure.
  • FIG4 is a schematic diagram of a process of manufacturing a semiconductor packaging structure according to an embodiment of the present disclosure.
  • 5a to 5h are schematic structural diagrams of a semiconductor packaging structure provided by an embodiment of the present disclosure during the preparation process
  • 6a to 6g are schematic structural diagrams of the first lead pad during the preparation process.
  • 30-intermediary layer 300-through hole; 31-first lead pad; 31'-first lead pad pre-layer; 32-first connection pad; 33-second connection pad; 34-first signal channel; 35-first conductive layer; 36-second conductive layer; 37-third conductive layer; 38-metal layer; 310-first surface; 320-second surface; 301-intermediary substrate; 302-first dielectric layer; 303-second dielectric layer;
  • 70 - second packaging structure 71 - first solder ball; 72 - first substrate;
  • 80-filling layer 801-second filler
  • first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part. And when the second element, component, region, layer or part is discussed, it does not mean that the present disclosure necessarily has the first element, component, region, layer or part.
  • FIG1 is a schematic diagram of the structure of a semiconductor packaging structure provided by an embodiment of the present disclosure.
  • the semiconductor package structure includes:
  • a first packaging structure includes a substrate 10 and an interposer 30, wherein the interposer 30 includes a first surface 310 and a second surface 320 that are opposite to each other, a first lead pad 31 is provided on at least one side of the second surface 320, and the first lead pad 31 protrudes from the second surface 320; wherein the interposer 30 is connected to the substrate 10 through the first lead pad 31;
  • the second packaging structure 70 is located on the first surface 310 of the interposer 30 and is connected to the interposer 30 .
  • a first lead pad is formed on at least one side of the second surface of the interposer, the second surface is a surface close to the substrate, and the first lead pad protrudes from the second surface, that is, the first lead pad exposes a portion of the surface, so that the substrate can be connected by bonding on the exposed surface of the first lead pad, and the height of the bonding is lower than the height of the interposer, and no additional bonding part is required during packaging, thereby reducing the packaging height of the semiconductor packaging structure.
  • the first packaging structure and the second packaging structure are independently packaged, the first packaging structure and the second packaging structure can be tested separately, so that failure analysis can be performed more quickly, and thus after the semiconductor packaging structure is formed, the overall structure can be tested.
  • the substrate 10 may be a printed circuit board (PCB) or a redistribution substrate.
  • PCB printed circuit board
  • the substrate 10 includes a substrate substrate 11 and an upper substrate insulating dielectric layer 12 and a lower substrate insulating dielectric layer 13 respectively disposed on the upper surface and the lower surface of the substrate substrate 11 .
  • the base substrate 11 can be a silicon substrate, a germanium substrate, a silicon germanium substrate, a silicon carbide substrate, an SOI (Silicon On Insulator) substrate or a GOI (Germanium On Insulator) substrate, etc. It can also be a substrate including other element semiconductors or compound semiconductors, such as a glass substrate or a III-V compound substrate (such as a gallium nitride substrate or a gallium arsenide substrate, etc.), and can also be a stacked structure, such as Si/SiGe, etc., and can also be other epitaxial structures, such as SGOI (Silicon Germanium on Insulator), etc.
  • the insulating dielectric layer 12 on the substrate and the insulating dielectric layer 13 under the substrate may be solder resist layers.
  • the material of the insulating dielectric layer 12 on the substrate and the insulating dielectric layer 13 under the substrate may be green paint.
  • the substrate 10 includes an upper surface and a lower surface arranged opposite to each other, and a first conductive pattern 14 and a second conductive pattern 15 are respectively arranged on the upper surface and the lower surface; the substrate 10 also includes a second signal channel 16 located between the upper surface and the lower surface, and the second signal channel 16 connects the first conductive pattern 14 and the second conductive pattern 15.
  • the first conductive pattern 14 is located in the insulating dielectric layer 12 on the substrate, the second conductive pattern 15 is located in the insulating dielectric layer 13 under the substrate, and the signal channel 16 is located in the substrate base 11 and penetrates the substrate base 11 .
  • the first conductive pattern 14 and the second conductive pattern 15 may be connection pads, and the material of the first conductive pattern 14 and the second conductive pattern 15 may include at least one of aluminum, copper, nickel, tungsten, platinum and gold.
  • the signal channel 16 may be a through silicon via (TSV).
  • the first conductive pattern 14 and the second conductive pattern 15 are connected through the signal channel 16, so that the signal can be transmitted.
  • two adjacent first conductive patterns 14 can also be connected through a redistribution layer, so that the signal can be transmitted on the substrate.
  • the substrate 10 also includes a substrate connection bump 17, which can electrically connect the semiconductor package structure to an external device, and can receive at least one of a control signal, a power signal, and a ground signal for operating the chip from the external device, or can receive a data signal to be stored in the chip from the external device, and can also provide data in the chip to an external device.
  • a substrate connection bump 17 can electrically connect the semiconductor package structure to an external device, and can receive at least one of a control signal, a power signal, and a ground signal for operating the chip from the external device, or can receive a data signal to be stored in the chip from the external device, and can also provide data in the chip to an external device.
  • the substrate connection bump 17 includes a conductive material.
  • the substrate connection bump 17 is a solder ball. It can be understood that the shape of the substrate connection bump provided in the embodiment of the present disclosure is only a lower-level, feasible specific implementation in the embodiment of the present disclosure, and does not constitute a limitation of the present disclosure.
  • the substrate connection bump may also be other shapes and structures. The number, spacing and position of the substrate connection bumps are not limited to any specific arrangement, and various modifications can be made.
  • the semiconductor packaging structure further includes: a chip stack 20 disposed on the substrate 10 , the chip stack 20 including a plurality of chips 21 stacked in sequence along a direction perpendicular to the substrate 10 ; and the interposer 30 disposed on the chip stack 20 .
  • the chip 21 can be a dynamic random access memory (DRAM) chip, a static random access memory (SRAM) chip, a flash memory chip, an electrically erasable programmable read-only memory (EEPROM) chip, a phase change random access memory (PRAM) chip, a magnetic random access memory (MRAM) chip or a resistive random access memory (RRAM) chip.
  • DRAM dynamic random access memory
  • SRAM static random access memory
  • EEPROM electrically erasable programmable read-only memory
  • PRAM phase change random access memory
  • MRAM magnetic random access memory
  • RRAM resistive random access memory
  • the chip stack 20 is disposed on the substrate 10 via an adhesive layer 60 .
  • the substrate 10 further includes a dummy channel 18 .
  • the adhesive layer 60 is located on the dummy channel 18 , and the thermal conductivity of the dummy channel 18 is greater than the thermal conductivity of the adhesive layer 60 .
  • the thermal conductivity of the virtual channel is greater than the thermal conductivity of the bonding layer, so that the heat generated by the chip during operation can be dissipated through the virtual channel, thereby reducing the impact on device performance.
  • the virtual channel 18 is composed of the first conductive pattern 14, the second conductive pattern 15 and the second signal channel 16, but no substrate connection bump 17 is formed under the virtual channel 18, so signal transmission cannot be achieved and it is only used for heat dissipation.
  • the thermal conductivity of the virtual channel is greater than that of the structure consisting of the first conductive pattern 14, the second conductive pattern 15 and the second signal channel 16 used for signal transmission, which can reduce the influence of heat on signal transmission.
  • the adhesive layer 60 may be a DAF film.
  • the adhesive layer may include a first adhesive layer and a second adhesive layer (not shown) located on the first adhesive layer, and the elastic modulus of the second adhesive layer is greater than the elastic modulus of the first adhesive layer.
  • the second adhesive layer mainly plays a role in preventing chip warping. Since the second adhesive layer has a higher elastic modulus, no warping will occur during the cutting process. The first adhesive layer has a lower elastic modulus and will not affect the bonding force between the substrate and the chip in subsequent processes.
  • Adjacent chips 21 , as well as the interposer 30 and the chip stack 20 are also connected via the adhesive layer 60 .
  • the semiconductor package structure further includes: a second lead 52 , and each of the chips 21 is connected to the substrate 10 via the second lead 52 .
  • the upper layer of chips in the chip stack 20 are offset and arranged on the lower layer of chips, and the second leads 52 are located on the same side of the chip stack 20. Since adjacent chips are offset and arranged, wire bonding is more convenient.
  • the second leads 52 of each layer of chips are connected to the same first conductive pattern 14 .
  • FIG. 2 is a schematic diagram of the structure of an interposer provided in an embodiment of the present disclosure.
  • the interposer 30 includes an interposer substrate 301 and a first dielectric layer 302 and a second dielectric layer 303 respectively disposed on the upper surface and the lower surface of the interposer substrate 301 , wherein the first dielectric layer 302 is located on the first surface 310 side of the interposer 30 , and the second dielectric layer 303 is located on the second surface 320 side of the interposer 30 .
  • the intermediate substrate 301 can be a silicon substrate, a germanium substrate, a silicon germanium substrate, a silicon carbide substrate, an SOI (Silicon On Insulator) substrate or a GOI (Germanium On Insulator) substrate, etc. It can also be a substrate including other element semiconductors or compound semiconductors, such as a glass substrate or a III-V compound substrate (such as a gallium nitride substrate or a gallium arsenide substrate, etc.), and can also be a stacked structure, such as Si/SiGe, etc., and can also be other epitaxial structures, such as SGOI (Silicon Germanium on Insulator), etc.
  • the first dielectric layer 302 and the second dielectric layer 303 may be solder resist layers.
  • the materials of the first dielectric layer 302 and the second dielectric layer 303 may be green paint.
  • a first connecting pad 32 is disposed in the first dielectric layer 302
  • a second connecting pad 33 is disposed in the second dielectric layer 303
  • a first signal channel 34 is disposed in the intermediate substrate 301 , wherein the first signal channel 34 connects the first connecting pad 32 and the second connecting pad 33 .
  • the first lead pad 31 is connected to the first connection pad 32 and the second connection pad 33 via a redistribution layer.
  • a first lead pad 31 is provided on at least one side of the second surface 320, and the first lead pad 31 protrudes from the second surface 320, including: the first lead pad 31 is located in the second dielectric layer 303, and the intermediate substrate 301 exposes a portion of the first lead pad 31.
  • the first lead pad 31 protrudes from the intermediate base 301, that is, the intermediate base 301 does not completely cover the first lead pad 31.
  • wire bonding can be performed on the first lead pad on the second surface side, avoiding wire bonding on the first surface side, thereby making the height of the wire bonding lower than the height of the intermediate layer, thereby reducing the overall height of the semiconductor packaging structure.
  • the plastic encapsulation material can completely wrap the wire bonding, and the height does not need to exceed the height of the intermediate layer, so the plastic encapsulation material and the intermediate layer can be coplanar, so that in the process of forming the plastic encapsulation material, there is no need to use a special-shaped mold, only a mold with a normal shape, and the mold with a normal shape has a simple shape, so the manufacturing process is simple and the cost is low.
  • the area of the portion of the first lead pad 31 protruding from the second surface 320 is larger than the area of the portion covered by the second surface 320 .
  • the area of the portion of the first lead pad 31 protruding from the second surface 320 is 3 to 4 times the area of the portion covered by the second surface 320 .
  • the area of the first lead pad used for wiring can be increased.
  • the semiconductor packaging structure also includes: a first lead 51, and the first lead pad 31 is connected to the substrate 10 through the first lead 51; wherein, one end of the first lead 51 is located on the surface of the first lead pad 31 away from the substrate 10, and the other end is located on the surface of the substrate 10 adjacent to the interposer 30.
  • the first packaging structure further includes: a molding compound 40 , wherein the molding compound 40 wraps the interposer 30 and is coplanar with the first connecting pad 32 .
  • the plastic encapsulation material 40 is coplanar with the first connecting pad 32, so that after the second packaging structure is subsequently connected to the first packaging structure, a larger gap can be provided between the first packaging structure and the second packaging structure, thereby ensuring the heat dissipation efficiency of the second packaging structure.
  • the molding compound 40 also wraps the chip stack 20 .
  • the second packaging structure 70 is connected to the interposer 30 through the first connecting pad 32 .
  • the second packaging structure is connected to the first lead pad via the first connection pad, and further connected to the substrate via the first lead pad, and the substrate provides a signal for the second packaging structure.
  • the second packaging structure 70 includes a first solder ball 71 , and the first solder ball 71 is electrically connected to the first connection pad 31 on the interposer 30 .
  • the second packaging structure 70 further includes a first substrate 72 .
  • the structure of the first substrate 72 is the same as that of the substrate 10 , and will not be described in detail herein.
  • the first solder ball 71 is located on the first substrate 72 .
  • the second packaging structure 70 can be a universal flash storage (Universal File Store, UFS).
  • UFS Universal File Store
  • Fig. 3 is a schematic diagram of a semiconductor package structure provided by another embodiment of the present disclosure. As shown in Fig. 3, the semiconductor package structure further includes: a filling layer 80, and the filling layer 80 fills the gap.
  • the thermal conductivity of the filling layer 80 is greater than the thermal conductivity of the molding compound 40 .
  • the filling layer By setting the filling layer, not only can a sealed interface be provided between the first packaging structure and the second packaging structure, reducing the contact between the metal structure of the first packaging structure and the second packaging structure and the outside air or other materials, but also it can play a role in heat conduction. And because the thermal conductivity of the filling layer is large, more heat can be dissipated from the filling layer, reducing the impact of heat on the first packaging structure. Although the thermal conductivity of the filling layer is large, because the thermal expansion coefficient of the filling layer matches the thermal expansion coefficient of the first packaging structure and the second packaging structure, the volume change of the filling layer is small, and no outward pressure will be generated on the first packaging structure and the second packaging structure, which can ensure the stability of the structure.
  • carbon nanotube fillers are filled in the filling layer 80 , so as to help absorb more heat from the second packaging structure and reduce the impact of heat on the first packaging structure.
  • the volume of the filler in the filling layer 80 is smaller than the volume of the filler in the molding compound 40 .
  • the filler in the molding compound 40 is a first filler 401
  • the filler in the filling layer 80 is a second filler 801 .
  • the volume of the second filler 801 is smaller than that of the first filler 401 .
  • the main materials of the molding compound 40 and the filling layer 80 may be epoxy resin, and the filler may be silicon dioxide.
  • the gap filled by the molding compound is larger and the gap between the first packaging structure and the second packaging structure is smaller, a filling layer with greater fluidity is selected, the filler volume in the filling layer is small, and the fluidity of the main material is greater.
  • the semiconductor packaging structure provided by the embodiments of the present disclosure can be applied to a multi-process packaged chip (UFS Multi Chip Package, UMCP) with a package on package (PoP) structure.
  • UFS Multi Chip Package UMCP
  • PoP package on package
  • the present disclosure also provides a method for preparing a semiconductor packaging structure. Please refer to FIG. 4 for details. As shown in the figure, the method includes the following steps:
  • Step 401 providing a first package structure, wherein the first package structure includes a substrate and an interposer, wherein the interposer includes a first surface and a second surface that are arranged opposite to each other, and a first lead pad is arranged on at least one side of the second surface, and the first lead pad protrudes from the second surface; wherein the interposer is connected to the substrate through the first lead pad;
  • Step 402 Provide a second packaging structure, where the second packaging structure is located on the first surface of the interposer and connected to the interposer.
  • 5a to 6g are schematic structural diagrams of the semiconductor packaging structure provided by an embodiment of the present disclosure during the preparation process.
  • step 401 is performed to provide a first packaging structure, wherein the first packaging structure includes a substrate 10 and an interposer 30, wherein the interposer 30 includes a first surface 310 and a second surface 320 that are relatively arranged, and a first lead pad 31 is arranged on at least one side of the second surface 320, and a portion of the surface of the first lead pad 31 is exposed; wherein the interposer 30 is connected to the substrate 10 through the first lead pad 31.
  • a substrate 10 is provided.
  • the substrate 10 may be a printed circuit board (PCB) or a redistribution substrate.
  • PCB printed circuit board
  • the substrate 10 includes a substrate substrate 11 and an upper substrate insulating dielectric layer 12 and a lower substrate insulating dielectric layer 13 respectively disposed on the upper surface and the lower surface of the substrate substrate 11 .
  • the base substrate 11 can be a silicon substrate, a germanium substrate, a silicon germanium substrate, a silicon carbide substrate, an SOI (Silicon On Insulator) substrate or a GOI (Germanium On Insulator) substrate, etc. It can also be a substrate including other element semiconductors or compound semiconductors, such as a glass substrate or a III-V compound substrate (such as a gallium nitride substrate or a gallium arsenide substrate, etc.), it can also be a stacked structure, such as Si/SiGe, etc., and it can also be other epitaxial structures, such as SGOI (Silicon Germanium On Insulator), etc.
  • the insulating dielectric layer 12 on the substrate and the insulating dielectric layer 13 under the substrate may be solder resist layers.
  • the material of the insulating dielectric layer 12 on the substrate and the insulating dielectric layer 13 under the substrate may be green paint.
  • the substrate 10 includes an upper surface and a lower surface arranged opposite to each other, and a first conductive pattern 14 and a second conductive pattern 15 are respectively arranged on the upper surface and the lower surface; the substrate 10 also includes a second signal channel 16 located between the upper surface and the lower surface, and the second signal channel 16 connects the first conductive pattern 14 and the second conductive pattern 15.
  • the first conductive pattern 14 is located in the insulating dielectric layer 12 on the substrate, the second conductive pattern 15 is located in the insulating dielectric layer 13 under the substrate, and the signal channel 16 is located in the substrate base 11 and penetrates the substrate base 11 .
  • the first conductive pattern 14 and the second conductive pattern 15 may be connection pads, and the material of the first conductive pattern 14 and the second conductive pattern 15 may include at least one of aluminum, copper, nickel, tungsten, platinum and gold.
  • the signal channel 16 may be a through silicon via (TSV).
  • the first conductive pattern 14 and the second conductive pattern 15 are connected through the signal channel 16, so that the signal can be transmitted.
  • two adjacent first conductive patterns 14 can also be connected through a redistribution layer, so that the signal can be transmitted on the substrate.
  • the substrate 10 further includes a dummy channel 18.
  • the dummy channel 18 is composed of the first conductive pattern 14, the second conductive pattern 15 and the signal channel 16, but no substrate connection bump is subsequently formed below the dummy channel 18, so signal transmission cannot be achieved and the dummy channel 18 is only used for heat dissipation.
  • the thermal conductivity of the virtual channel is greater than that of other structures composed of the first conductive pattern 14, the second conductive pattern 15 and the signal channel 16 that function as signal transmission, which can reduce the influence of heat on signal transmission.
  • a chip stack 20 is formed on the substrate 10 .
  • the adhesive layer 60 is first formed on the substrate 10 , and then the chip stack 20 is formed on the adhesive layer 60 .
  • the adhesive layer 60 may be a DAF film.
  • the adhesive layer may include a first adhesive layer and a second adhesive layer (not shown) located on the first adhesive layer, and the elastic modulus of the second adhesive layer is greater than the elastic modulus of the first adhesive layer.
  • the second adhesive layer mainly plays a role in preventing chip warping. Since the second adhesive layer has a higher elastic modulus, no warping will occur during the cutting process. The first adhesive layer has a lower elastic modulus and will not affect the bonding force between the substrate and the chip in subsequent processes.
  • the bonding layer 60 is located on the virtual channel 18 , and the thermal conductivity of the virtual channel 18 is greater than the thermal conductivity of the bonding layer 60 .
  • the thermal conductivity of the virtual channel is greater than that of the bonding layer, so that more heat generated by the chip during operation can be dissipated through the virtual channel, thereby improving the heat dissipation capacity and reducing the impact on device performance.
  • Adjacent chips 21 are also connected via the adhesive layer 60 .
  • an interposer 30 is formed on the chip stack 20 .
  • the carrier tape 2 is pasted on the ring 1 , and then the intermediate layer 30 is pasted on the carrier tape 2 .
  • the intermediate layer 30 is in the shape of a whole strip.
  • the intermediate layer 30 is cut to form units one by one as shown in FIG. 5c .
  • the interposer 30 is flip-mounted on the chip stack 20 .
  • the intermediary layer 30 includes an intermediary substrate 301 and a first dielectric layer 302 and a second dielectric layer 303 respectively arranged on the upper surface and the lower surface of the intermediary substrate 301, wherein the first dielectric layer 302 is located on the first surface 310 side of the intermediary layer 30, and the second dielectric layer 303 is located on the second surface 320 side of the intermediary layer 30.
  • the intermediate substrate 301 can be a silicon substrate, a germanium substrate, a silicon germanium substrate, a silicon carbide substrate, an SOI (Silicon On Insulator) substrate or a GOI (Germanium On Insulator) substrate, etc. It can also be a substrate including other element semiconductors or compound semiconductors, such as a glass substrate or a III-V compound substrate (such as a gallium nitride substrate or a gallium arsenide substrate, etc.), and can also be a stacked structure, such as Si/SiGe, etc., and can also be other epitaxial structures, such as SGOI (Silicon Germanium on Insulator), etc.
  • the first dielectric layer 302 and the second dielectric layer 303 may be solder resist layers.
  • the materials of the first dielectric layer 302 and the second dielectric layer 303 may be green paint.
  • a first connecting pad 32 is disposed in the first dielectric layer 302
  • a second connecting pad 33 is disposed in the second dielectric layer 303
  • a first signal channel 34 is disposed in the intermediate substrate 301 , wherein the first signal channel 34 connects the first connecting pad 32 and the second connecting pad 33 .
  • the first lead pad 31 is connected to the first connection pad 32 and the second connection pad 33 via a redistribution layer.
  • Figures 6a to 6g are schematic diagrams of the structure of the first lead pad during the preparation process.
  • the first lead pad 31 is provided on at least one side of the second surface 320, including:
  • a first conductive layer 35 and a second conductive layer 36 are respectively disposed;
  • the first lead pad pre-layer 31' is cut off from the through hole 300 to form the first lead pad 31, and a portion of the surface of the first lead pad 31 is exposed.
  • a first conductive layer 35 and a second conductive layer 36 are formed on the upper surface and the lower surface of the interposer substrate 301 , respectively.
  • the material of the first conductive layer 35 and the second conductive layer 36 includes, but is not limited to, Cu.
  • a through hole 300 penetrating the first conductive layer 35 and the intermediate substrate 301 may be formed by laser drilling.
  • a third conductive layer 37 is formed on the sidewall of the through hole 300 .
  • the material of the third conductive layer 37 includes but is not limited to Cu.
  • a third conductive layer 37 is formed in the through hole, which can serve as a conductive path between the circuits of each layer to connect the circuits of each layer.
  • the second conductive layer 36 is etched to disconnect the second conductive layer 36 below the through hole 300 from the second conductive layer 36 on both sides, so as to form a first lead pad pre-layer 31′.
  • a photoresist layer (not shown) can be formed on the second conductive layer, and then the photoresist layer is patterned. According to the patterned photoresist layer, part of the second conductive layer is removed to disconnect the second conductive layer under the through hole from the second conductive layers on both sides.
  • the first conductive layer 35 is designed with circuits so that the first conductive layer 35 is divided into a plurality of independent parts.
  • the method further includes:
  • a first dielectric layer 302 is formed to wrap the first conductive layer 35, and a second dielectric layer 303 is formed to wrap the second conductive layer 36 and the first lead pad pre-layer 31'.
  • the first dielectric layer 302 is coplanar with the first conductive layer 35 to expose the surface of the first conductive layer 35 .
  • the method further comprises: forming a metal layer 38 on the first conductive layer 35, the third conductive layer 37 and the first lead pad pre-layer 31′.
  • the material of the metal layer 38 includes but is not limited to Ni or Au.
  • the metal layer 38 may also serve as a part of the first conductive layer 35, the third conductive layer 37 and the first lead pad 31'.
  • the first lead pad pre-layer 31' is cut off from the through hole 300 to form the first lead pad 31, and the first lead pad 31 partially exposes the surface.
  • the first lead pad 31 exposes the surface, that is, the first lead pad 31 protrudes from the interposer substrate 301.
  • the first conductive layer and the second conductive layer may be further arranged to form the first connecting pad and the second connecting pad, respectively.
  • the area of the portion of the first lead pad 31 protruding from the second surface 320 is larger than the area of the portion covered by the second surface 320 .
  • the area of the portion of the first lead pad 31 protruding from the second surface 320 is 3 to 4 times the area of the portion covered by the second surface 320 .
  • the area of the first lead pad used for wiring can be increased.
  • the method further includes: forming a first lead 51 , wherein the first lead pad 31 is connected to the substrate 10 via the first lead 51 ;
  • a second lead 52 is formed, and each chip 21 is connected to the substrate 10 via the second lead 52 .
  • one end of the first lead 51 is located on a surface of the first lead pad 31 away from the substrate 10 , and the other end is located on a surface of the substrate 10 adjacent to the interposer 30 .
  • the second leads 52 of each layer of chips are connected to the same first conductive pattern 14 .
  • a molding compound 40 is formed.
  • the molding compound 40 wraps the chip stack 20 and the interposer 30 and is coplanar with the first connection pad 32 .
  • the plastic encapsulation material 40 is coplanar with the first connection pad 32 , so that after the second packaging structure is subsequently connected to the first packaging structure, a larger gap can be provided between the first packaging structure and the second packaging structure, thereby ensuring the heat dissipation efficiency of the second packaging structure.
  • a packaging mold 90 is formed.
  • the packaging mold 90 includes two parts, which are respectively located above the interposer 30 and below the substrate 10 .
  • the surface of the packaging mold 90 is parallel to the surface of the substrate 10 .
  • a molding compound 40 is formed using the packaging mold 90 as a mask.
  • first lead pad is located on one side of the second surface of the interposer
  • wire bonding can be performed on the first lead pad on the second surface side, avoiding wire bonding on the first surface side, thereby making the height of the wire bonding lower than the height of the interposer, thereby reducing the overall height of the semiconductor packaging structure.
  • the plastic encapsulation material can completely wrap the wire bonding without exceeding the height of the interposer, so the plastic encapsulation material and the interposer can be coplanar, so that in the process of forming the plastic encapsulation material, no special-shaped mold is needed, only a mold with a normal shape needs to be used, and the mold with a normal shape has a simple shape, so the manufacturing process is simple and the cost is low.
  • a substrate connection bump 17 is formed on the second conductive pattern 15 of the substrate 10 , and the substrate connection bump 17 includes a conductive material.
  • step 402 is performed to provide a second packaging structure 70 .
  • the second packaging structure 70 is located on the first surface 310 of the interposer 30 and is connected to the interposer 30 .
  • a first solder ball 71 is formed on the second packaging structure 70 , and the first solder ball 71 is electrically connected to the first connecting pad 32 .
  • the second packaging structure 70 further includes a first substrate 72 .
  • the structure of the first substrate 72 is the same as that of the substrate 10 , and will not be described in detail herein.
  • the first solder ball 71 is located on the first substrate 72 .
  • the second packaging structure 70 can be a universal flash storage (Universal File Store, UFS).
  • UFS Universal File Store
  • a filling layer 80 is formed in the gap between the first encapsulation structure and the second encapsulation 70 .
  • the thermal conductivity of the filling layer 80 is greater than the thermal conductivity of the molding compound 40 .
  • the filling layer By setting the filling layer, not only can a sealed interface be provided between the first packaging structure and the second packaging structure, reducing the contact between the metal structure of the first packaging structure and the second packaging structure and the outside air or other materials, but also it can play a role in heat conduction. And because the thermal conductivity of the filling layer is relatively large, more heat can be dissipated from the filling layer, reducing the impact of heat on the first packaging structure. Although the thermal conductivity of the filling layer is relatively large, because the thermal expansion coefficient of the filling layer matches the thermal expansion coefficient of the first packaging structure and the second packaging structure, the volume change of the filling layer is relatively small, and no outward pressure will be generated on the first packaging structure and the second packaging structure, which can ensure the stability of the structure.
  • carbon nanotube fillers are filled in the filling layer 80 , so as to help absorb more heat from the second packaging structure and reduce the impact of heat on the first packaging structure.
  • the volume of the filler in the filling layer 80 is smaller than the volume of the filler in the molding compound 40 .
  • the filler in the molding compound 40 is a first filler 401
  • the filler in the filling layer 80 is a second filler 801 .
  • the volume of the second filler 801 is smaller than that of the first filler 401 .
  • the main materials of the molding compound 40 and the filling layer 80 may be epoxy resin, and the filler may be silicon dioxide.
  • the gap filled by the molding compound is relatively large, and the gap between the first packaging structure and the second packaging structure is relatively small, a filling layer with relatively large fluidity is selected, the filler volume in the filling layer is small, and the fluidity of the main body material is relatively large.
  • a first lead pad is formed on at least one side of the second surface of the interposer, the second surface is a surface close to the substrate, and the first lead pad protrudes from the second surface, that is, the first lead pad exposes a portion of the surface, so that the substrate can be connected by bonding on the exposed surface of the first lead pad, and the height of the bonding is lower than the height of the interposer, and no additional bonding part is required during packaging, thereby reducing the packaging height of the semiconductor packaging structure.
  • the first packaging structure and the second packaging structure are independently packaged, the first packaging structure and the second packaging structure can be tested separately, so that failure analysis can be performed more quickly, and thus after the semiconductor packaging structure is formed, the overall structure can be tested.

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Abstract

本公开实施例公开了一种半导体封装结构及制备方法，其中，所述半导体封装结构包括：第一封装结构，包括基板和中介层，所述中介层包括相对设置的第一表面和第二表面，所述第二表面的至少一侧设置有第一引线焊盘，且所述第一引线焊盘突出于所述第二表面；其中，所述中介层通过所述第一引线焊盘与所述基板连接；第二封装结构，位于所述中介层的第一表面上，与所述中介层连接。

Description

一种半导体封装结构及制备方法
相关申请的交叉引用
本公开基于申请号为202211291034.1、申请日为2022年10月21日、发明名称为“一种半导体封装结构及制备方法”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开涉及半导体技术领域，尤其涉及一种半导体封装结构及制备方法。
背景技术
在所有部门，行业和地区，电子行业都在不断要求提供更轻、更快、更小、多功能、更可靠和更具成本效益的产品。为了满足众多不同消费者的这些不断增长的需求，需要集成更多的电路来提供所需的功能。在几乎所有应用中，对减小尺寸，提高性能和改善集成电路功能的需求不断增长。
发明内容
有鉴于此，本公开实施例提供一种半导体封装结构及制备方法。
根据本公开实施例的第一方面，提供了一种半导体封装结构，包括：
第一封装结构，包括基板和中介层，所述中介层包括相对设置的第一表面和第二表面，所述第二表面的至少一侧设置有第一引线焊盘，且所述第一引线焊盘突出于所述第二表面；其中，所述中介层通过所述第一引线焊盘与所述基板连接；
第二封装结构，位于所述中介层的第一表面上，与所述中介层连接。
在一些实施例中，所述第一引线焊盘突出于所述第二表面的部分的面积大于被所述第二表面覆盖的部分的面积。
在一些实施例中，所述第一引线焊盘突出于所述第二表面的部分的面积是被所述第二表面覆盖的部分的面积的3倍-4倍。
在一些实施例中，所述中介层包括中介基底和分别设置于所述中介基底的上表面和下表面上的第一介质层和第二介质层，其中，所述第一介质层位于所述中介层的第一表面一侧，所述第二介质层位于所述中介层的第二表面一侧。
在一些实施例中，所述第二表面的至少一侧设置有第一引线焊盘，且 所述第一引线焊盘突出于所述第二表面，包括：
所述第一引线焊盘位于所述第二介质层内，且所述中介基底暴露部分所述第一引线焊盘。
在一些实施例中，所述第一介质层内设置有第一连接焊盘，所述第二介质层内设置有第二连接焊盘，所述中介基底内设置有第一信号通道，其中，所述第一信号通道连接所述第一连接焊盘和所述第二连接焊盘。
在一些实施例中，还包括：
第一引线，所述第一引线焊盘通过所述第一引线连接所述基板；
其中，所述第一引线的一端位于所述第一引线焊盘的远离所述基板一侧的表面上，另一端位于所述基板邻近所述中介层一侧的表面上。
在一些实施例中，还包括：
芯片堆叠体，设置在所述基板上，所述芯片堆叠体包括多个沿垂直于所述基板的方向依次堆叠的芯片；
所述中介层设置在所述芯片堆叠体上。
在一些实施例中，还包括：
第二引线，每个所述芯片通过所述第二引线连接所述基板。
在一些实施例中，所述第一封装结构还包括：塑封料，所述塑封料包裹所述中介层，并与所述第一连接焊盘共面。
在一些实施例中，所述基板包括相对设置的上表面和下表面，所述上表面和所述下表面上分别设置有第一导电图案和第二导电图案；
所述基板还包括位于所述上表面和所述下表面之间的第二信号通道，所述第二信号通道连接所述第一导电图案和所述第二导电图案。
在一些实施例中，所述第一封装结构与所述第二封装结构之间存在空隙。
在一些实施例中，还包括：
填充层，所述填充层填满所述空隙。
根据本公开实施例的第二方面，提供一种半导体封装结构的制备方法，包括：
提供第一封装结构，所述第一封装结构包括基板和中介层，所述中介层包括相对设置的第一表面和第二表面，在所述第二表面的至少一侧设置第一引线焊盘，且所述第一引线焊盘突出于所述第二表面；其中，所述中介层通过所述第一引线焊盘与所述基板连接；
提供第二封装结构，所述第二封装结构位于所述中介层的第一表面上，与所述中介层连接。
在一些实施例中，所述在所述第二表面的至少一侧设置第一引线焊盘，包括：
提供中介基底，所述中介基底的上表面和下表面上分别设置有第一导电层和第二导电层；
形成贯穿所述第一导电层和所述中介基底的通孔，并暴露所述第二导电层；
在所述通孔的侧壁上形成第三导电层；
刻蚀所述第二导电层，使所述通孔下方的所述第二导电层与两侧的所述第二导电层断开，以形成第一引线焊盘预层；
从通孔内切断所述第一引线焊盘预层，以形成第一引线焊盘，所述第一引线焊盘暴露部分表面。
在一些实施例中，在形成第一引线焊盘预层后，所述方法还包括：
形成包裹所述第一导电层的第一介质层，形成包裹所述第二导电层和所述第一引线焊盘预层的第二介质层。
在一些实施例中，在形成第一介质层和第二介质层后，所述方法还包括：
在所述第一导电层、所述第三导电层和所述第一引线焊盘预层上形成金属层。
本公开实施例中，通过在中介层的第二表面的至少一侧形成第一引线焊盘，第二表面为靠近基板一侧的表面，且第一引线焊盘突出于第二表面，即第一引线焊盘暴露部分表面，如此，可以通过在第一引线焊盘暴露的表面上进行打线与基板连接，并且打线的高度低于中介层的高度，封装时无需多出封装打线的部分，降低了半导体封装结构的封装高度。同时因为第一封装结构和第二封装结构是独立封装的，可以分别对第一封装结构和第二封装结构进行测试，从而可以更加快速的进行失效分析，由此在组成半导体封装结构之后，可以不对整体结构进行测试。
附图说明
为了更清楚地说明本公开实施例或传统技术中的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开实施例提供的半导体封装结构的结构示意图；
图2为本公开实施例提供的中介层的结构示意图；
图3为本公开另一实施例提供的半导体封装结构的结构示意图；
图4为本公开实施例提供的半导体封装结构的制备方法的流程示意图；
图5a至5h为本公开实施例提供的半导体封装结构在制备过程中的结构示意图；
图6a至图6g为第一引线焊盘在制备过程中的结构示意图。
附图标记说明：
1-圆环；2-载带；
10-基板；11-基板衬底；12-基板上绝缘介质层；13-基板下绝缘介质层； 14-第一导电图案；15-第二导电图案；16-第二信号通道；17-基板连接凸块；18-虚拟通道；
20-芯片堆叠体；21-芯片；
30-中介层；300-通孔；31-第一引线焊盘；31’-第一引线焊盘预层；32-第一连接焊盘；33-第二连接焊盘；34-第一信号通道；35-第一导电层；36-第二导电层；37-第三导电层；38-金属层；310-第一表面；320-第二表面；301-中介基底；302-第一介质层；303-第二介质层；
40-塑封料；401-第一填料；
51-第一引线；52-第二引线；
60-粘结层；
70-第二封装结构；71-第一焊球；72-第一基板；
80-填充层；801-第二填料；
90-封装模具。
具体实施方式
下面将参照附图更详细地描述本公开公开的示例性实施方式。虽然附图中显示了本公开的示例性实施方式，然而应当理解，可以以各种形式实现本公开，而不应被这里阐述的具体实施方式所限制。相反，提供这些实施方式是为了能够更透彻地理解本公开，并且能够将本公开公开的范围完整的传达给本领域的技术人员。
在下文的描述中，给出了大量具体的细节以便提供对本公开更为彻底的理解。然而，对于本领域技术人员而言显而易见的是，本公开可以无需一个或多个这些细节而得以实施。在其他的例子中，为了避免与本公开发生混淆，对于本领域公知的一些技术特征未进行描述；即，这里不描述实际实施例的全部特征，不详细描述公知的功能和结构。
在附图中，为了清楚，层、区、元件的尺寸以及其相对尺寸可能被夸大。自始至终相同附图标记表示相同的元件。
应当明白，当元件或层被称为“在……上”、“与……相邻”、“连接到”或“耦合到”其它元件或层时，其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层，或者可以存在居间的元件或层。相反，当元件被称为“直接在……上”、“与……直接相邻”、“直接连接到”或“直接耦合到”其它元件或层时，则不存在居间的元件或层。应当明白，尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层和/或部分，这些元件、部件、区、层和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层或部分与另一个元件、部件、区、层或部分。因此，在不脱离本公开教导之下，下面讨论的第一元件、部件、区、层或部分可表示为第二元件、部件、区、层或部分。而当讨论的第二元件、部件、区、层或部分时，并不表明本公开必然存在第一元件、部件、区、 层或部分。
空间关系术语例如“在……下”、“在……下面”、“下面的”、“在……之下”、“在……之上”、“上面的”等，在这里可为了方便描述而被使用从而描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白，除了图中所示的取向以外，空间关系术语意图还包括使用和操作中的器件的不同取向。例如，如果附图中的器件翻转，然后，描述为“在其它元件下面”或“在其之下”或“在其下”元件或特征将取向为在其它元件或特征“上”。因此，示例性术语“在……下面”和“在……下”可包括上和下两个取向。器件可以另外地取向(旋转90度或其它取向)并且在此使用的空间描述语相应地被解释。
在此使用的术语的目的仅在于描述具体实施例并且不作为本公开的限制。在此使用时，单数形式的“一”、“一个”和“所述/该”也意图包括复数形式，除非上下文清楚指出另外的方式。还应明白术语“组成”和/或“包括”，当在该说明书中使用时，确定所述特征、整数、步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。
为了彻底理解本公开，将在下列的描述中提出详细的步骤以及详细的结构，以便阐释本公开的技术方案。本公开的较佳实施例详细描述如下，然而除了这些详细描述外，本公开还可以具有其他实施方式。
基于此，本公开实施例提供了一种半导体封装结构。图1为本公开实施例提供的半导体封装结构的结构示意图。
参见图1，所述半导体封装结构，包括：
第一封装结构，包括基板10和中介层30，所述中介层30包括相对设置的第一表面310和第二表面320，所述第二表面320的至少一侧设置有第一引线焊盘31，且所述第一引线焊盘31突出于所述第二表面320；其中，所述中介层30通过所述第一引线焊盘31与所述基板10连接；
第二封装结构70，位于所述中介层30的第一表面310上，与所述中介层30连接。
本公开实施例中，通过在中介层的第二表面的至少一侧形成第一引线焊盘，第二表面为靠近基板一侧的表面，且第一引线焊盘突出于第二表面，即第一引线焊盘暴露部分表面，如此，可以通过在第一引线焊盘暴露的表面上进行打线与基板连接，并且打线的高度低于中介层的高度，封装时无需多出封装打线的部分，降低了半导体封装结构的封装高度。同时因为第一封装结构和第二封装结构是独立封装的，可以分别对第一封装结构和第二封装结构进行测试，从而可以更加快速的进行失效分析，由此在组成半导体封装结构之后，可以不对整体结构进行测试。
在一些实施例中，所述基板10可以是印刷电路板(PCB)或再分布基 板。
所述基板10包括基板衬底11和分别设置在所述基板衬底11的上表面和下表面上的基板上绝缘介质层12和基板下绝缘介质层13。
所述基板衬底11可以为硅衬底、锗衬底、硅锗衬底、碳化硅衬底、SOI(绝缘体上硅，Silicon On Insulator)衬底或GOI(绝缘体上锗，Germanium On Insulator)衬底等，还可以为包括其他元素半导体或化合物半导体的衬底，例如玻璃衬底或III-V族化合物衬底(例如氮化镓衬底或砷化镓衬底等)，还可以为叠层结构，例如Si/SiGe等，还可以其他外延结构，例如SGOI(绝缘体上锗硅)等。
所述基板上绝缘介质层12和所述基板下绝缘介质层13可以为阻焊层，例如所述基板上绝缘介质层12和所述基板下绝缘介质层13的材料可以为绿漆。
在一实施例中，所述基板10包括相对设置的上表面和下表面，所述上表面和所述下表面上分别设置有第一导电图案14和第二导电图案15；所述基板10还包括位于所述上表面和所述下表面之间的第二信号通道16，所述第二信号通道16连接所述第一导电图案14和所述第二导电图案15。
所述第一导电图案14位于所述基板上绝缘介质层12内，所述第二导电图案15位于所述基板下绝缘介质层13内，所述信号通道16位于所述基板衬底11内，并贯穿所述基板衬底11。
所述第一导电图案14和所述第二导电图案15可以为连接焊盘，且所述第一导电图案14和所述第二导电图案15的材料可以包括铝、铜、镍、钨、铂和金中的至少一种。所述信号通道16可以为穿硅通孔(TSV)。
第一导电图案14与第二导电图案15通过信号通道16连接，从而能够让信号进行传输。同时，相邻的两个第一导电图案14还可以通过重布线层连接，从而能够完成信号在基板上的传输。
所述基板10还包括基板连接凸块17，所述基板连接凸块17可将半导体封装结构电连接到外部装置上，可以从外部装置接收用于操作芯片的控制信号、功率信号和接地信号中的至少一个，或者可以从外部装置接收将要被存储在芯片内的数据信号，也可将芯片内的数据提供给外部装置。
所述基板连接凸块17包括导电材料。在本公开实施例中，所述基板连接凸块17为焊球，可以理解的是，本公开实施例中提供的基板连接凸块的形状仅作为本公开实施例中的一种下位的、可行的具体实施方式，并不构成对本公开的限制，所述基板连接凸块也可为其他形状结构。基板连接凸块的数量、间隔和位置不限于任何特定布置，可以进行各种修改。
在一实施例中，所述半导体封装结构还包括：芯片堆叠体20，设置在所述基板10上，所述芯片堆叠体20包括多个沿垂直于所述基板10的方向依次堆叠的芯片21；所述中介层30设置在所述芯片堆叠体20上。
所述芯片21可以为动态随机存取存储器(DRAM)芯片、静态随机存 取存储器(SRAM)芯片、闪存芯片、电可擦除可编程只读存储器(EEPROM)芯片、相变随机存取存储器(PRAM)芯片、磁随机存取存储器(MRAM)芯片或电阻随机存取存储器(RRAM)芯片。
所述芯片堆叠体20通过粘结层60设置在所述基板10上，所述基板10还包括虚拟通道18，所述粘结层60位于所述虚拟通道18上，且所述虚拟通道18的导热系数大于所述粘结层60的导热系数。
本公开实施例中，虚拟通道的导热系数大于粘结层的导热系数，能够将芯片工作产生的热量通过虚拟通道散发出去，减少对器件性能的影响。
所述虚拟通道18为第一导电图案14、第二导电图案15和第二信号通道16组成，但是虚拟通道18的下方不形成基板连接凸块17，无法实现信号传输，仅用作散热处理。
在一些实施例中，虚拟通道的导热系数比其他作为信号传输作用的第一导电图案14、第二导电图案15和第二信号通道16组成的结构的导热系数大，能够减少热量对信号传输的影响。
所述粘结层60可以为DAF膜。
在一实施例中，所述粘结层可以包括第一粘结层和位于所述第一粘结层上的第二粘结层(未图示)，所述第二粘结层的弹性模量大于所述第一粘结层的弹性模量。
本公开实施例中，因为第一粘结层主要起到粘结的作用，第二粘结层主要起到防止芯片翘曲的作用，由于第二粘结层的弹性模量较高，在切割过程中不会出现翘曲，第一粘结层具有较低的弹性模量，在后续的工艺中不会影响基板与芯片的结合力。
相邻芯片21之间，以及中介层30和芯片堆叠体20之间也通过所述粘结层60进行连接。
在一实施例中，所述半导体封装结构还包括：第二引线52，每个所述芯片21通过所述第二引线52连接所述基板10。
如图1所示，所述芯片堆叠体20中的上一层芯片偏移地设置在下一层芯片上，并且所述第二引线52位于所述芯片堆叠体20的同侧。由于相邻芯片偏移设置，因此打线更加方便。
在一实施例中，每层芯片的第二引线52连接至同一所述第一导电图案14上。
图2为本公开实施例提供的中介层的结构示意图。
如图2所示，所述中介层30包括中介基底301和分别设置于所述中介基底301的上表面和下表面上的第一介质层302和第二介质层303，其中，所述第一介质层302位于所述中介层30的第一表面310一侧，所述第二介质层303位于所述中介层30的第二表面320一侧。
所述中介基底301可以为硅衬底、锗衬底、硅锗衬底、碳化硅衬底、SOI(绝缘体上硅，Silicon On Insulator)衬底或GOI(绝缘体上锗，Germanium  On Insulator)衬底等，还可以为包括其他元素半导体或化合物半导体的衬底，例如玻璃衬底或III-V族化合物衬底(例如氮化镓衬底或砷化镓衬底等)，还可以为叠层结构，例如Si/SiGe等，还可以其他外延结构，例如SGOI(绝缘体上锗硅)等。
所述第一介质层302和所述第二介质层303可以为阻焊层，例如所述第一介质层302和所述第二介质层303的材料可以为绿漆。
在一实施例中，所述第一介质层302内设置有第一连接焊盘32，所述第二介质层303内设置有第二连接焊盘33，所述中介基底301内设置有第一信号通道34，其中，所述第一信号通道34连接所述第一连接焊盘32和所述第二连接焊盘33。
所述第一引线焊盘31与所述第一连接焊盘32和所述第二连接焊盘33之间通过重布线层连接。
在一实施例中，如图1和图2所示，所述第二表面320的至少一侧设置有第一引线焊盘31，且所述第一引线焊盘31突出于所述第二表面320，包括：所述第一引线焊盘31位于所述第二介质层303内，且所述中介基底301暴露部分所述第一引线焊盘31。
具体地，所述第一引线焊盘31突出于所述中介基底301，即所述中介基底301不全部覆盖所述第一引线焊盘31。如此，可以在第二表面一侧的第一引线焊盘上进行打线，避免在第一表面一侧进行打线，由此可以使打线的高度低于中介层的高度，进而降低半导体封装结构的整体高度。同时由于打线高度低于中介层的高度，如此后续形成塑封料时，塑封料可以在完全包裹打线的基础上，高度又无需超过中介层的高度，因此可以做到塑封料与中介层共面，如此，在形成塑封料的过程中，不需要用到异形模具，只需要使用形状正常的模具，而形状正常的模具因为形状简单，所以制作工艺简单，成本较低。
在一实施例中，所述第一引线焊盘31突出于所述第二表面320的部分的面积大于被所述第二表面320覆盖的部分的面积。
具体地，所述第一引线焊盘31突出于所述第二表面320的部分的面积是被所述第二表面320覆盖的部分的面积的3倍-4倍。
将第一引线焊盘突出于第二表面的面积设置的大一些，可以增加第一引线焊盘用于打线的面积。
在一实施例中，所述半导体封装结构还包括：第一引线51，所述第一引线焊盘31通过所述第一引线51连接所述基板10；其中，所述第一引线51的一端位于所述第一引线焊盘31的远离所述基板10一侧的表面上，另一端位于所述基板10邻近所述中介层30一侧的表面上。
如图1所示，所述第一封装结构还包括：塑封料40，所述塑封料40包裹所述中介层30，并与所述第一连接焊盘32共面。
所述塑封料40与所述第一连接焊盘32共面，这样后续第二封装结构 与第一封装结构连接后，使得第一封装结构和第二封装结构之间能够具有较大的空隙，保证了第二封装结构的散热效率。
如图1所示，所述塑封料40还包裹所述芯片堆叠体20。
在一实施例中，所述第二封装结构70通过所述第一连接焊盘32与所述中介层30连接。
具体地，所述第二封装结构通过第一连接焊盘与第一引线焊盘连接，进而通过第一引线焊盘与基板连接，通过基板为第二封装结构提供信号。
在一实施例中，所述第一封装结构与所述第二封装结构70之间存在空隙。
本公开实施例中，第二封装结构与第一封装结构之间存在空隙，由此增加了二者之间的间距，从而能提高第二封装结构的散热效率，减少热量对芯片的影响。
所述第二封装结构70包括第一焊球71，所述第一焊球71与所述中介层30上的第一连接焊盘31电连接。
所述第二封装结构70还包括第一基板72，所述第一基板72的结构与所述基板10的结构相同，这里不再赘述。
所述第一焊球71位于所述第一基板72上。
所述第二封装结构70可以为通用闪存存储(Universal File Store，UFS)。
图3为本公开另一实施例提供的半导体封装结构的结构示意图。如图3所示，所述半导体封装结构还包括：填充层80，所述填充层80填满所述空隙。
所述填充层80的导热系数大于所述塑封料40的导热系数。
通过设置填充层，不仅可以使第一封装结构和第二封装结构之间具有密封的界面，减少第一封装结构和第二封装结构的金属结构与外界空气或其他材料的接触，而且可以起到导热作用。并且由于填充层的导热系数较大，这样更多的热量能够从填充层散失掉，减少热量对第一封装结构的影响。虽然填充层的导热系数较大，但是由于填充层的热膨胀系数与第一封装结构和第二封装结构的热膨胀系数相匹配，这样填充层的体积变化较小，不会对第一封装结构和第二封装结构产生向外的压力，能够保证结构的稳定性。
在一些实施例中，例如在填充层80内填充碳纳米管填料，从而有利于从第二封装结构中吸收更多的热量，减少热量对第一封装结构的影响。
所述填充层80中的填料体积小于所述塑封料40中的填料体积。
如图3所示，所述塑封料40中的填料为第一填料401，所述填充层80中的填料为第二填料801，第二填料801的体积小于第一填料401的体积。
所述塑封料40和所述填充层80的主体材料可以为环氧树脂，填料可以为二氧化硅。
在此实施例中，由于塑封料填充的空隙较大，而第一封装结构和第二 封装结构之间的空隙较小，由此选择流动性较大的填充层，填充层中的填料体积小，主体材料的流动性大。
本公开实施例提供的半导体封装结构可应用于叠层封装(Package on Package，PoP)结构的多制程封装芯片(UFS Multi Chip Package，UMCP)。
本公开实施例还提供了一种半导体封装结构的制备方法，具体请参见附图4，如图所示，所述方法包括以下步骤：
步骤401：提供第一封装结构，所述第一封装结构包括基板和中介层，所述中介层包括相对设置的第一表面和第二表面，在所述第二表面的至少一侧设置第一引线焊盘，且所述第一引线焊盘突出于所述第二表面；其中，所述中介层通过所述第一引线焊盘与所述基板连接；
步骤402：提供第二封装结构，所述第二封装结构位于所述中介层的第一表面上，与所述中介层连接。
下面结合具体实施例对本公开实施例提供的半导体封装结构的制备方法再作进一步详细的说明。
图5a至6g为本公开实施例提供的半导体封装结构在制备过程中的结构示意图。
首先，参见图5a至图5f，执行步骤401，提供第一封装结构，所述第一封装结构包括基板10和中介层30，所述中介层30包括相对设置的第一表面310和第二表面320，在所述第二表面320的至少一侧设置第一引线焊盘31，且所述第一引线焊盘31暴露部分表面；其中，所述中介层30通过所述第一引线焊盘31与所述基板10连接。
具体地，先参见图5a，提供基板10。
在一些实施例中，所述基板10可以是印刷电路板(PCB)或再分布基板。
所述基板10包括基板衬底11和分别设置在所述基板衬底11的上表面和下表面上的基板上绝缘介质层12和基板下绝缘介质层13。
所述基板衬底11可以为硅衬底、锗衬底、硅锗衬底、碳化硅衬底、SOI(绝缘体上硅，Silicon On Insulator)衬底或GOI(绝缘体上锗，Germanium On Insulator)衬底等，还可以为包括其他元素半导体或化合物半导体的衬底，例如玻璃衬底或III-V族化合物衬底(例如氮化镓衬底或砷化镓衬底等)，还可以为叠层结构，例如Si/SiGe等，还可以其他外延结构，例如SGOI(绝缘体上锗硅)等。
所述基板上绝缘介质层12和所述基板下绝缘介质层13可以为阻焊层，例如所述基板上绝缘介质层12和所述基板下绝缘介质层13的材料可以为绿漆。
在一实施例中，所述基板10包括相对设置的上表面和下表面，所述上表面和所述下表面上分别设置有第一导电图案14和第二导电图案15；所述基板10还包括位于所述上表面和所述下表面之间的第二信号通道16，所述 第二信号通道16连接所述第一导电图案14和所述第二导电图案15。
所述第一导电图案14位于所述基板上绝缘介质层12内，所述第二导电图案15位于所述基板下绝缘介质层13内，所述信号通道16位于所述基板衬底11内，并贯穿所述基板衬底11。
所述第一导电图案14和所述第二导电图案15可以为连接焊盘，且所述第一导电图案14和所述第二导电图案15的材料可以包括铝、铜、镍、钨、铂和金中的至少一种。所述信号通道16可以为穿硅通孔(TSV)。
第一导电图案14与第二导电图案15通过信号通道16连接，从而能够让信号进行传输。同时，相邻的两个第一导电图案14还可以通过重布线层连接，从而能够完成信号在基板上的传输。
所述基板10还包括虚拟通道18。所述虚拟通道18为第一导电图案14、第二导电图案15和信号通道16组成，但是虚拟通道18的下方后续不形成基板连接凸块，无法实现信号传输，仅用作散热处理。
在一些实施例中，虚拟通道的导热系数比其他作为信号传输作用的第一导电图案14、第二导电图案15和信号通道16组成的结构的导热系数大，能够减少热量对信号传输的影响。
接着，参见图5b，在所述基板10上形成芯片堆叠体20。
具体地，先在所述基板10上形成粘结层60，然后在所述粘结层60上形成芯片堆叠体20。
所述粘结层60可以为DAF膜。
在一实施例中，所述粘结层可以包括第一粘结层和位于所述第一粘结层上的第二粘结层(未图示)，所述第二粘结层的弹性模量大于所述第一粘结层的弹性模量。
本公开实施例中，因为第一粘结层主要起到粘结的作用，第二粘结层主要起到防止芯片翘曲的作用，由于第二粘结层的弹性模量较高，在切割过程中不会出现翘曲，第一粘结层具有较低的弹性模量，在后续的工艺中不会影响基板与芯片的结合力。
所述粘结层60位于所述虚拟通道18上，所述虚拟通道18的导热系数大于所述粘结层60的导热系数。
本公开实施例中，虚拟通道的导热系数大于粘结层的导热系数，能够将芯片工作产生的热量更多的通过虚拟通道散发出去，提高散热能力，减少对器件性能的影响。
相邻芯片21之间也通过所述粘结层60进行连接。
接着，参见图5c和图5d，在所述芯片堆叠体20上形成中介层30。
具体地，先参见图5c，在圆环1上粘贴载带2，然后将中介层30粘贴在载带2上，此时的中介层30为整片的条状，对中介层30进行切割，形成如图5c所示的一个一个的单元。
接着，参见图5d，将所述中介层30倒装在所述芯片堆叠体20上。
具体地，参见图2，所述中介层30包括中介基底301和分别设置于所述中介基底301的上表面和下表面上的第一介质层302和第二介质层303，其中，所述第一介质层302位于所述中介层30的第一表面310一侧，所述第二介质层303位于所述中介层30的第二表面320一侧。
所述中介基底301可以为硅衬底、锗衬底、硅锗衬底、碳化硅衬底、SOI(绝缘体上硅，Silicon On Insulator)衬底或GOI(绝缘体上锗，Germanium On Insulator)衬底等，还可以为包括其他元素半导体或化合物半导体的衬底，例如玻璃衬底或III-V族化合物衬底(例如氮化镓衬底或砷化镓衬底等)，还可以为叠层结构，例如Si/SiGe等，还可以其他外延结构，例如SGOI(绝缘体上锗硅)等。
所述第一介质层302和所述第二介质层303可以为阻焊层，例如所述第一介质层302和所述第二介质层303的材料可以为绿漆。
在一实施例中，所述第一介质层302内设置有第一连接焊盘32，所述第二介质层303内设置有第二连接焊盘33，所述中介基底301内设置有第一信号通道34，其中，所述第一信号通道34连接所述第一连接焊盘32和所述第二连接焊盘33。
所述第一引线焊盘31与所述第一连接焊盘32和所述第二连接焊盘33之间通过重布线层连接。
下面对本公开实施例提供的第一引线焊盘的制备过程进行详细描述。图6a至图6g为第一引线焊盘在制备过程中的结构示意图。
如图6a至图6g所示，所述在所述第二表面320的至少一侧设置第一引线焊盘31，包括：
提供中介基底301，在所述中介基底301的上表面和下表面上分别设置第一导电层35和第二导电层36；
形成贯穿所述第一导电层35和所述中介基底301的通孔300，并暴露所述第二导电层36；
在所述通孔300的侧壁上形成第三导电层37；
刻蚀所述第二导电层36，使所述通孔300下方的所述第二导电层36与两侧的所述第二导电层36断开，以形成第一引线焊盘预层31’；
从通孔300内切断所述第一引线焊盘预层31’，以形成第一引线焊盘31，所述第一引线焊盘31暴露部分表面。
具体地，先参见图6a，在中介基底301的上表面和下表面上分别形成第一导电层35和第二导电层36。
所述第一导电层35和所述第二导电层36的材料包括但不限于Cu。
接着，参见图6b，可以通过激光钻孔(Laser drilling)的方式形成贯穿所述第一导电层35和所述中介基底301的通孔300。
接着，参见图6c，在所述通孔300的侧壁上形成第三导电层37。
所述第三导电层37的材料包括但不限于Cu。
在通孔内形成第三导电层37，可作为各层线路间的导通路径，将各层线路进行连通。
接着，参见图6d，刻蚀所述第二导电层36，使所述通孔300下方的所述第二导电层36与两侧的所述第二导电层36断开，以形成第一引线焊盘预层31’。
具体地，可以在所述第二导电层上形成光刻胶层(未图示)，然后图案化所述光刻胶层，根据图案化后的光刻胶层，去除部分第二导电层，使通孔下方的所述第二导电层与两侧的所述第二导电层断开。
继续参见图6d，对所述第一导电层35进行线路设计，使所述第一导电层35分为多个独立的部分。
接着，参见图6e，在形成第一引线焊盘预层31’后，所述方法还包括：
形成包裹所述第一导电层35的第一介质层302，形成包裹所述第二导电层36和所述第一引线焊盘预层31’的第二介质层303。
所述第一介质层302与所述第一导电层35共面，以暴露出所述第一导电层35的表面。
接着，参见图6f，在形成第一介质层302和第二介质层303后，所述方法还包括：在所述第一导电层35、所述第三导电层37和所述第一引线焊盘预层31’上形成金属层38。
所述金属层38的材料包括但不限于Ni或Au。
在一实施例中，所述金属层38也可作为第一导电层35、第三导电层37和第一引线焊盘31’的一部分。
接着，参见图6g，从通孔300内切断所述第一引线焊盘预层31’，以形成第一引线焊盘31，所述第一引线焊盘31暴露部分表面。第一引线焊盘31暴露部分表面也就是说第一引线焊盘31突出于中介基底301。
在形成第一引线焊盘后，可以继续对第一导电层和第二导电层进行设置，以分别形成第一连接焊盘和所述第二连接焊盘。
在一实施例中，所述第一引线焊盘31突出于所述第二表面320的部分的面积大于被所述第二表面320覆盖的部分的面积。
具体地，所述第一引线焊盘31突出于所述第二表面320的部分的面积是被所述第二表面320覆盖的部分的面积的3倍-4倍。
将第一引线焊盘突出于第二表面的面积设置的大一些，可以增加第一引线焊盘用于打线的面积。
接着，继续参见图5d，所述方法还包括：形成第一引线51，所述第一引线焊盘31通过所述第一引线51连接所述基板10；
形成第二引线52，每个所述芯片21通过所述第二引线52连接所述基板10。
在一实施例中，所述第一引线51的一端位于所述第一引线焊盘31的远离所述基板10一侧的表面上，另一端位于所述基板10邻近所述中介层 30一侧的表面上。
在一实施例中，每层芯片的第二引线52连接至同一所述第一导电图案14上。
接着，参见图5e和图5f，形成塑封料40，所述塑封料40包裹所述芯片堆叠体20和所述中介层30，并与所述第一连接焊盘32共面。
所述塑封料40与所述第一连接焊盘32共面，这样后续第二封装结构与第一封装结构连接后，使得第一封装结构和第二封装结构之间能够具有较大的空隙，保证了第二封装结构的散热效率。
具体地，先参见图5e，形成封装模具90，所述封装模具90包括两部分，分别位于所述中介层30的上方，和所述基板10的下方；所述封装模具90的表面平行于所述基板10的表面。
接着，参见图5f，以封装模具90为掩膜，形成塑封料40。
本公开实施例中，因为第一引线焊盘位于中介层的第二表面的一侧，因此可以在第二表面一侧的第一引线焊盘上进行打线，避免在第一表面一侧进行打线，由此可以使打线的高度低于中介层的高度，进而降低半导体封装结构的整体高度。同时由于打线高度低于中介层的高度，如此形成塑封料时，塑封料可以在完全包裹打线的基础上，高度又无需超过中介层的高度，因此可以做到塑封料与中介层共面，如此，在形成塑封料的过程中，不需要用到异形模具，只需要使用形状正常的模具，而形状正常的模具因为形状简单，所以制作工艺简单，成本较低。
继续参见图5f，在形成塑封料40后，在所述基板10的第二导电图案15上形成基板连接凸块17，所述基板连接凸块17包括导电材料。
接着，参见图5g，执行步骤402，提供第二封装结构70，所述第二封装结构70位于所述中介层30的第一表面310上，与所述中介层30连接。
具体地，在所述第二封装结构70上形成第一焊球71，所述第一焊球71与所述第一连接焊盘32电连接。
在一实施例中，所述第一封装结构与所述第二封装结构70之间存在空隙。
所述第二封装结构70还包括第一基板72，所述第一基板72的结构与所述基板10的结构相同，这里不再赘述。
所述第一焊球71位于所述第一基板72上。
所述第二封装结构70可以为通用闪存存储(Universal File Store，UFS)。
接着，参见图5h，在所述第一封装结构和所述第二封装70之间的空隙内形成填充层80。
所述填充层80的导热系数大于所述塑封料40的导热系数。
通过设置填充层，不仅可以使第一封装结构和第二封装结构之间具有密封的界面，减少第一封装结构和第二封装结构的金属结构与外界空气或其他材料的接触，而且可以起到导热作用。并且由于填充层的导热系数较 大，这样更多的热量能够从填充层散失掉，减少热量对第一封装结构的影响。虽然填充层的导热系数较大，但是由于填充层的热膨胀系数与第一封装结构和第二封装结构的热膨胀系数相匹配，这样填充层的体积变化较小，不会对第一封装结构和第二封装结构产生向外的压力，能够保证结构的稳定性。
在一些实施例中，例如在填充层80内填充碳纳米管填料，从而有利于从第二封装结构中吸收更多的热量，减少热量对第一封装结构的影响。
所述填充层80中的填料体积小于所述塑封料40中的填料体积。
如图5h所示，所述塑封料40中的填料为第一填料401，所述填充层80中的填料为第二填料801，第二填料801的体积小于第一填料401的体积。
所述塑封料40和所述填充层80的主体材料可以为环氧树脂，填料可以为二氧化硅。
在此实施例中，由于塑封料填充的空隙较大，而第一封装结构和第二封装结构之间的空隙较小，由此选择流动性较大的填充层，填充层中的填料体积小，主体材料的流动性大。
以上所述，仅为本公开的较佳实施例而已，并非用于限定本公开的保护范围，凡在本公开的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本公开的保护范围之内。
工业实用性
本公开实施例中，通过在中介层的第二表面的至少一侧形成第一引线焊盘，第二表面为靠近基板一侧的表面，且第一引线焊盘突出于第二表面，即第一引线焊盘暴露部分表面，如此，可以通过在第一引线焊盘暴露的表面上进行打线与基板连接，并且打线的高度低于中介层的高度，封装时无需多出封装打线的部分，降低了半导体封装结构的封装高度。同时因为第一封装结构和第二封装结构是独立封装的，可以分别对第一封装结构和第二封装结构进行测试，从而可以更加快速的进行失效分析，由此在组成半导体封装结构之后，可以不对整体结构进行测试。

Claims (17)

  1. 一种半导体封装结构，包括：
    第一封装结构，包括基板和中介层，所述中介层包括相对设置的第一表面和第二表面，所述第二表面的至少一侧设置有第一引线焊盘，且所述第一引线焊盘突出于所述第二表面；其中，所述中介层通过所述第一引线焊盘与所述基板连接；
    第二封装结构，位于所述中介层的第一表面上，与所述中介层连接。
  2. 根据权利要求1所述的半导体封装结构，其中，
    所述第一引线焊盘突出于所述第二表面的部分的面积大于被所述第二表面覆盖的部分的面积。
  3. 根据权利要求2所述的半导体封装结构，其中，
    所述第一引线焊盘突出于所述第二表面的部分的面积是被所述第二表面覆盖的部分的面积的3倍-4倍。
  4. 根据权利要求1所述的半导体封装结构，其中，
    所述中介层包括中介基底和分别设置于所述中介基底的上表面和下表面上的第一介质层和第二介质层，其中，所述第一介质层位于所述中介层的第一表面一侧，所述第二介质层位于所述中介层的第二表面一侧。
  5. 根据权利要求4所述的半导体封装结构，其中，
    所述第二表面的至少一侧设置有第一引线焊盘，且所述第一引线焊盘突出于所述第二表面，包括：
    所述第一引线焊盘位于所述第二介质层内，且所述中介基底暴露部分所述第一引线焊盘。
  6. 根据权利要求4所述的半导体封装结构，其中，
    所述第一介质层内设置有第一连接焊盘，所述第二介质层内设置有第二连接焊盘，所述中介基底内设置有第一信号通道，其中，所述第一信号通道连接所述第一连接焊盘和所述第二连接焊盘。
  7. 根据权利要求1所述的半导体封装结构，其中，还包括：
    第一引线，所述第一引线焊盘通过所述第一引线连接所述基板；
    其中，所述第一引线的一端位于所述第一引线焊盘的远离所述基板一侧的表面上，另一端位于所述基板邻近所述中介层一侧的表面上。
  8. 根据权利要求1所述的半导体封装结构，其中，还包括：
    芯片堆叠体，设置在所述基板上，所述芯片堆叠体包括多个沿垂直于所述基板的方向依次堆叠的芯片；
    所述中介层设置在所述芯片堆叠体上。
  9. 根据权利要求8所述的半导体封装结构，其中，还包括：
    第二引线，每个所述芯片通过所述第二引线连接所述基板。
  10. 根据权利要求6所述的半导体封装结构，其中，
    所述第一封装结构还包括：塑封料，所述塑封料包裹所述中介层，并与所述第一连接焊盘共面。
  11. 根据权利要求1所述的半导体封装结构，其中，
    所述基板包括相对设置的上表面和下表面，所述上表面和所述下表面上分别设置有第一导电图案和第二导电图案；
    所述基板还包括位于所述上表面和所述下表面之间的第二信号通道，所述第二信号通道连接所述第一导电图案和所述第二导电图案。
  12. 根据权利要求1所述的半导体封装结构，其中，
    所述第一封装结构与所述第二封装结构之间存在空隙。
  13. 根据权利要求12所述的半导体封装结构，其中，还包括：
    填充层，所述填充层填满所述空隙。
  14. 一种半导体封装结构的制备方法，包括：
    提供第一封装结构，所述第一封装结构包括基板和中介层，所述中介层包括相对设置的第一表面和第二表面，在所述第二表面的至少一侧设置第一引线焊盘，且所述第一引线焊盘突出于所述第二表面；其中，所述中介层通过所述第一引线焊盘与所述基板连接；
    提供第二封装结构，所述第二封装结构位于所述中介层的第一表面上，与所述中介层连接。
  15. 根据权利要求14所述的方法，其中，
    所述在所述第二表面的至少一侧设置第一引线焊盘，包括：
    提供中介基底，所述中介基底的上表面和下表面上分别设置有第一导电层和第二导电层；
    形成贯穿所述第一导电层和所述中介基底的通孔，并暴露所述第二导电层；
    在所述通孔的侧壁上形成第三导电层；
    刻蚀所述第二导电层，使所述通孔下方的所述第二导电层与两侧的所述第二导电层断开，以形成第一引线焊盘预层；
    从通孔内切断所述第一引线焊盘预层，以形成第一引线焊盘，所述第一引线焊盘暴露部分表面。
  16. 根据权利要求15所述的方法，其中，
    在形成第一引线焊盘预层后，所述方法还包括：
    形成包裹所述第一导电层的第一介质层，形成包裹所述第二导电层和所述第一引线焊盘预层的第二介质层。
  17. 根据权利要求16所述的方法，其中，
    在形成第一介质层和第二介质层后，所述方法还包括：
    在所述第一导电层、所述第三导电层和所述第一引线焊盘预层上形成金属层。
PCT/CN2022/129962 2022-10-21 2022-11-04 一种半导体封装结构及制备方法 WO2024082348A1 (zh)

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