WO2024066713A1 - Multi-band gain-adjustable low noise amplifier - Google Patents

Multi-band gain-adjustable low noise amplifier Download PDF

Info

Publication number
WO2024066713A1
WO2024066713A1 PCT/CN2023/109886 CN2023109886W WO2024066713A1 WO 2024066713 A1 WO2024066713 A1 WO 2024066713A1 CN 2023109886 W CN2023109886 W CN 2023109886W WO 2024066713 A1 WO2024066713 A1 WO 2024066713A1
Authority
WO
WIPO (PCT)
Prior art keywords
capacitor
resistor
branches
transistor
type transistor
Prior art date
Application number
PCT/CN2023/109886
Other languages
French (fr)
Chinese (zh)
Inventor
苏俊华
郭嘉帅
Original Assignee
深圳飞骧科技股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳飞骧科技股份有限公司 filed Critical 深圳飞骧科技股份有限公司
Publication of WO2024066713A1 publication Critical patent/WO2024066713A1/en

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
    • H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
    • H03F1/0277—Selecting one or more amplifiers from a plurality of amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/08—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements
    • H03F1/12—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements by use of attenuating means
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/26—Modifications of amplifiers to reduce influence of noise generated by amplifying elements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/42—Modifications of amplifiers to extend the bandwidth
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/56—Modifications of input or output impedances, not otherwise provided for
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/68—Combinations of amplifiers, e.g. multi-channel amplifiers for stereophonics

Definitions

  • the invention relates to the field of electronic technology, and in particular to a multi-band gain-adjustable low-noise amplifier.
  • the low noise amplifier largely determines the performance of the receiver in terms of noise, linearity and sensitivity.
  • the demand for a single wireless RF transceiver to be compatible with as many communication frequency bands as possible has greatly increased, so RF receivers compatible with multiple frequency bands have become a research hotspot in the field of communication.
  • existing RF receivers are generally implemented using multiple separate low noise amplifiers, that is, multiple separate low noise amplifiers are connected in parallel, and these low noise amplifiers work in different frequency bands respectively, and then the low noise amplifier of the required frequency band is selected by a switch.
  • the embodiment of the present invention provides a multi-band adjustable gain low noise amplifier, which can realize the multi-band of the low noise amplifier while reducing the area occupied by the low noise amplifier, and can realize adjustable gain to meet a large dynamic range.
  • the present invention provides a multi-band adjustable gain low-noise amplifier, comprising a signal input terminal, an input matching network, a plurality of common source stage amplification units, a negative gain attenuation network, a source stage negative feedback unit, a common gate drive amplification unit, a choke inductor unit, an output matching network with adjustable impedance, an output resistance attenuation network and a signal output terminal;
  • Each of the common-source amplifier units includes a first N-type transistor and a second N-type transistor connected correspondingly, the common-gate drive amplifier unit includes a third N-type transistor and a voltage-stabilizing capacitor, the choke inductor unit includes a first P-type transistor, a second P-type transistor, a first choke inductor and a second choke inductor, and the negative gain attenuation network includes an input resistance attenuation network, a fourth N-type transistor and a fifth N-type transistor;
  • the input end of the input matching network is connected to the signal input end, and all the first N-type crystals
  • the gate of the body tube and the first end of the input resistance attenuation network are connected to the output end of the input matching network
  • the sources of all the first N-type transistors, the second end of the input resistance attenuation network and the source of the fourth N-type transistor are connected to the first end of the source negative feedback unit, the second end of the source negative feedback unit is grounded or connected to the first power supply voltage
  • the drain of each of the first N-type transistors is connected to the source of the corresponding second N-type transistor
  • the gate of each of the second N-type transistors is respectively used to input a first control signal
  • the drain of all the second N-type transistors and the drain of the fifth N-type transistor are connected to the source of the third N-type transistor
  • the gate of the third N-type transistor is grounded through the voltage stabilizing capacitor
  • the gate of the fourth N-type transistor is connected to the third end of the input resistance atten
  • the source of the first P-type transistor and the source of the second P-type transistor are both connected to a second power supply voltage, the gate of the first P-type transistor and the gate of the second P-type transistor are respectively used to input a third control signal, the drain of the first P-type transistor is connected to the first end of the first choke inductor, the second end of the first choke inductor is connected to the drain of the second P-type transistor and the first end of the second choke inductor, the second end of the second choke inductor is connected to the drain of the third N-type transistor and the input end of the output matching network, the output end of the output matching network is connected to the input end of the output resistance attenuation network, and the output end of the output resistance attenuation network is connected to the signal output end.
  • the output matching network includes a first variable capacitor
  • the first end of the first variable capacitor is the input end of the output matching network, connected to the drain of the third N-type transistor, and the second end of the first variable capacitor is the output end of the output matching network, connected to the input end of the output resistance attenuation network.
  • the first variable capacitor includes a first capacitance group, a second capacitance group and a third capacitance group;
  • the first capacitor group includes one or a plurality of first capacitor branches connected in parallel, each of the first capacitor branches includes a first capacitor connected to each other and a first capacitor switching switch;
  • the second capacitor group includes one or a plurality of second capacitor branches connected in parallel, each of the second capacitor branches includes a second capacitor connected to each other and a second capacitor switching switch;
  • the third capacitor group includes one or a plurality of third capacitor branches connected in parallel, each of the third capacitor branches includes a third capacitor connected to each other and a third capacitor switching switch;
  • first ends of all the first capacitor branches and the first ends of all the second capacitor branches are connected to the first ends of all the third capacitor branches to serve as the second end of the first variable capacitor, and the second ends of all the second capacitor branches and the second ends of all the third capacitor branches are grounded.
  • the input matching network includes a first inductor, a DC blocking capacitor and a second variable capacitor;
  • the first end of the first inductor is connected to the signal input end
  • the second end of the first inductor is connected to the first end of the DC blocking capacitor
  • the second end of the DC blocking capacitor is connected to the first end of the second variable capacitor
  • the gate of the first N-type transistor and the first end of the input resistance attenuation network
  • the second end of the second variable capacitor is connected to the source of the first N-type transistor.
  • the second variable capacitor includes a plurality of fourth capacitance branches connected in parallel, and each of the fourth capacitance branches includes a fourth capacitor and a fourth capacitance switching switch connected thereto;
  • a first end of the plurality of fourth capacitor branches connected in parallel is connected to the gate of the first N-type transistor, and a second end of the plurality of fourth capacitor branches connected in parallel is connected to the source of the first N-type transistor.
  • the output resistance attenuation network includes a first switch and a first variable resistor
  • the first end of the first switch and the first end of the first variable resistor are connected to serve as the input end of the output resistance attenuation network, and are connected to the output end of the output matching network.
  • the second end of the first switch and the second end of the first variable resistor are connected to serve as the output end of the output resistance attenuation network, and are connected to the signal output end.
  • the first variable resistor includes a first resistor group, a second resistor group and a third resistor group;
  • the first resistor group includes one or a plurality of first resistor branches connected in parallel, each of the first resistor branches includes a first resistor connected to each other and a first resistor switching switch;
  • the second resistor group includes one or a plurality of second resistor branches connected in parallel, each of the second resistor branches includes a second resistor connected to each other and a second resistor switching switch;
  • the third resistor group includes one or a plurality of third resistor branches connected in parallel, each of the third resistor branches includes a third resistor connected to each other and a third resistor switching switch;
  • the first ends of all the first resistance branches are connected to the first ends of all the second resistance branches to serve as the first end of the first variable resistor
  • the second ends of all the first resistance branches are connected to the first ends of all the third resistance branches to serve as the second end of the first variable resistor
  • the second ends of all the second resistance branches and the second ends of all the third resistance branches are grounded.
  • the input resistance attenuation network includes a second switch, a fifth capacitor and a second variable resistor
  • the first end of the second switch and the first ends of all the fourth resistance branches are connected to the output end of the input matching network, the second end of the second switch and the second ends of all the fourth resistance branches and the first end of the fifth capacitor are connected to the gate of the fourth N-type transistor, the second end of the fifth capacitor is connected to the first end of all the fifth resistance branches, and the second ends of all the fifth resistance branches are connected to the first end of the source negative feedback unit.
  • the source negative feedback unit includes a first feedback inductor, a second feedback inductor, a sixth transistor and a seventh transistor;
  • the first end of the first feedback inductor serves as the first end of the source negative feedback unit, connected to the sources of all the first N-type transistors and the second end of the input resistance attenuation network, and the second end of the first feedback inductor is connected to the first end of the second feedback inductor;
  • the drain of the sixth transistor is connected to the second end of the first feedback inductor
  • the drain of the seventh transistor is connected to the second end of the second feedback inductor
  • the gate of the sixth transistor and the gate of the seventh transistor are respectively used to input a fourth control signal
  • the source of the sixth transistor and the source of the seventh transistor are grounded as the second end of the source negative feedback unit;
  • the drain of the sixth transistor is connected to the second end of the first feedback inductor
  • the drain of the seventh transistor is connected to the second end of the second feedback inductor
  • the gate of the sixth transistor and the gate of the seventh transistor are respectively used to input a fourth control signal
  • the source of the sixth transistor and the source of the seventh transistor are connected to the first supply voltage as the second end of the source negative feedback unit.
  • first feedback inductor and the second feedback inductor are connected in series by way of an inductor tap.
  • the multi-band adjustable gain low noise amplifier of the present invention by setting parallel A plurality of common-source amplifier units are provided, and one or more common-source amplifier units can be selectively controlled to amplify the signal through a first control signal, thereby achieving gain adjustment to meet the requirement of a large dynamic range; and, by controlling the conduction or disconnection of a first P-type transistor and a second P-type transistor in a choke inductor unit, whether the first choke inductor is connected to the circuit is controlled, thereby achieving adjustment of the working frequency band.
  • the choke inductor unit through further cooperation between the choke inductor unit and an output matching network with adjustable impedance, adjustment of a wider frequency band can be achieved.
  • the present invention can reduce the occupied area.
  • FIG. 1 is a schematic structural diagram of a multi-band adjustable gain low noise amplifier according to an embodiment of the present invention
  • FIG2 is a specific implementation circuit diagram of an output matching network provided by an embodiment of the present invention.
  • FIG. 3 is a specific implementation circuit diagram of a second variable capacitor provided by an embodiment of the present invention.
  • FIG4 is a circuit diagram of a specific implementation of an output resistance attenuation network provided by an embodiment of the present invention.
  • FIG. 5 is a specific implementation circuit diagram of an input resistance attenuation network provided in an embodiment of the present invention.
  • FIG6 is a schematic diagram of the structure of the source negative feedback unit shown in FIG1 ;
  • FIG. 8 is a schematic structural diagram of the source negative feedback unit shown in FIG. 7 .
  • a multi-band adjustable gain low noise amplifier 100 provided in an embodiment of the present invention includes a signal input terminal RFin, an input matching network 101, a plurality of common source stage amplification units 1021 to 102n, a negative gain attenuation network 103, a source stage negative feedback unit 104, a common gate drive amplification unit, a choke inductor unit, an output matching network 105 with adjustable impedance, an output resistance attenuation network 106, and a signal output terminal RFout.
  • each of the common source amplifier units 102n includes a first N-type transistor Q11 and a second N-type transistor Q12 connected to each other, the common gate drive amplifier unit includes a third N-type transistor Q13 and a voltage stabilizing capacitor CCG, and the choke inductor unit includes a first P-type transistor M11, a third N-type transistor Q12 and a third P-type transistor Q13.
  • the negative gain attenuation network 103 includes an input resistance attenuation network 1031, a fourth N-type transistor Q14 and a fifth N-type transistor Q15.
  • the input end of the input matching network 101 is connected to the signal input end RFin, the gates of all the first N-type transistors Q11 and the first end of the input resistance attenuation network 1031 are connected to the output end of the input matching network 101, the sources of all the first N-type transistors Q11, the second end of the input resistance attenuation network 1031 and the source of the fourth N-type transistor Q14 are connected to the first end of the source negative feedback unit 104, the second end of the source negative feedback unit 104 is grounded or connected to the first power supply voltage, the drain of each of the first N-type transistors Q11 is connected to the corresponding second N-type transistor Q14.
  • the source of the second N-type transistor Q12 is connected, the gate of each of the second N-type transistors Q12 is respectively used to input the first control signal, the drains of all the second N-type transistors Q12 and the drain of the fifth N-type transistor Q15 are connected to the source of the third N-type transistor Q13, the gate of the third N-type transistor Q13 is grounded through the voltage-stabilizing capacitor CCG, the gate of the fourth N-type transistor Q14 is connected to the third end of the input resistor attenuation network 1031, the drain of the fourth N-type transistor Q14 is connected to the source of the fifth N-type transistor Q15, and the gate of the fifth N-type transistor Q15 is used to input the second control signal.
  • the source of the first P-type transistor M11 and the source of the second P-type transistor M12 are both connected to the second power supply voltage VDD2, the gate of the first P-type transistor M11 and the gate of the second P-type transistor M12 are respectively used to input a third control signal, the drain of the first P-type transistor M11 is connected to the first end of the first choke inductor LD1, the second end of the first choke inductor LD1 is connected to the drain of the second P-type transistor M12 and the first end of the second choke inductor LD2, the second end of the second choke inductor LD2 is connected to the drain of the third N-type transistor Q13 and the input end of the output matching network 105, the output end of the output matching network 105 is connected to the input end of the output resistance attenuation network 106, and the output end of the output resistance attenuation network 106 is connected to the signal output end RFout.
  • the first control signal, the second control signal and the third control signal all include high level and low level, thereby the first control signal, the second control signal and the third control signal can respectively control the corresponding transistor to be in the on state or the off state.
  • the first control signal is a high level signal
  • the second N-type transistor Q12 can be controlled to be turned on, and if it is a low level, the second N-type The transistor Q12 is turned off.
  • the gates of the second N-type transistors Q12 are not connected to each other, and the first control signal input to the gate of each second N-type transistor Q12 can be individually controlled to be high or low.
  • the first control signal of one of the second N-type transistors Q12 can be high, while the first control signal of the other second N-type transistors Q12 can be low, or the first control signal of two or three of the second N-type transistors Q12 can be high, while the first control signal of the other second N-type transistors Q12 can be low, so that one or more of the second N-type transistors Q12 can be selectively turned on or off.
  • the third control signal input to the gate of the first P-type transistor M11 and the second P-type transistor M12 can be controlled separately to be high or low.
  • the third control signal input to the gate of the first P-type transistor M11 can be high, while the third control signal input to the gate of the second P-type transistor M12 can be low.
  • the third control signals input to the gates of the two P-type transistors can be high or low, so that one or both of the P-type transistors can be selectively turned on or off.
  • the switching between the positive gain gear and the negative gain gear can be achieved through the action of the fifth N-type transistor Q15.
  • the input resistance attenuation network 1031, the fourth N-type transistor Q14 and the fifth N-type transistor Q15 form a negative gain unit 103, which can provide a negative gain gear for the low noise amplifier 100.
  • the low noise amplifier 100 needs to be in a negative gain gear, all the second N-type transistors Q12 are turned off by the first control signal, that is, the first control signal input to the gate of all the second N-type transistors Q12 is low, and the fifth N-type transistor Q15 is turned on by the second control signal, that is, the second control signal is high.
  • the RF signal is input from the signal input terminal RFin, enters the input resistance attenuation network 1031 after passing through the input matching network 101, and is amplified by the fourth N-type transistor Q14 after being attenuated by the input resistance attenuation network 1031, thereby improving the linearity of the low noise amplifier 100 in the negative gain gear.
  • the signal amplified by the fourth N-type transistor Q14 passes through the fifth N-type transistor Q15, the third N-type transistor Q13, the output matching network 105 and the output resistance attenuation network 106 in sequence, and is output from the signal output terminal RFout.
  • the fifth N-type transistor Q15 is turned off by the second control signal, and part or all of the second N-type transistors Q12 are turned on by the first control signal, so that the radio frequency signal is input from the signal input terminal RFin, passes through the input matching network 101, enters the turned-on common source stage amplification unit for amplification, passes through the third N-type transistor Q13, the output matching network 105 and the output resistor attenuation network 106 in sequence, and then outputs from the signal output terminal RFin. Terminal RFout output.
  • a plurality of common source amplifier units 1021-102n can provide most of the gain for the low noise amplifier 100, wherein by controlling the conduction and shutdown of the second N-type transistor Q12, it is possible to control whether the corresponding first N-type transistor Q11 provides gain, thereby achieving partial gain adjustment.
  • all the second N-type transistors Q12 are in the on state, that is, the first control signals input to the gates of all the second N-type transistors Q12 are at a high level, all the first N-type transistors Q11 can provide gain at this time, so that the plurality of common source amplifier units 1021-102n provide the maximum gain for the low noise amplifier 100; in actual use, part or all of the second N-type transistors Q12 can be selected to be turned on according to the required gain, so that part or all of the first N-type transistors Q11 provide gain, achieving gain adjustment, thereby meeting the requirements of a large dynamic range.
  • the switchable choke inductor composed of the first choke inductor LD1, the second choke inductor LD2, the first P-type transistor M11, and the second P-type transistor M12 provides a DC voltage for the active amplifier part, and its inductive impedance and the output matching network 105 with adjustable impedance together form an impedance conversion circuit, which converts the impedance at the drain of the third N-type transistor Q13 into the conjugate impedance of the subsequent circuit, ensuring that the power generated by the low-noise amplifier can be transmitted to the subsequent circuit to the maximum extent, and the resonant frequency can be freely adjusted by switching the choke inductor LD1 and/or adjusting the impedance of the output matching network 105, thereby achieving output that meets multi-band requirements.
  • the first P-type transistor M11 and the second P-type transistor M12 are turned on or off by the third control signal to control whether the first choke inductor LD1 is connected to the circuit, so that the working frequency band of the low-noise amplifier 100 can be adjusted, and the output matching network 105 with adjustable impedance can make the adjustment range of the working frequency band wider.
  • the first P-type transistor M11 can be controlled to be turned on and the second P-type transistor M12 can be turned off.
  • the first choke inductor LD1 and the second choke inductor LD2 are both connected to the circuit; when it is necessary to operate in a narrower operating frequency band, the first P-type transistor M11 can be controlled to be turned off and the second P-type transistor M12 can be turned on. At this time, only the second choke inductor LD2 is connected to the circuit; and by adjusting the impedance of the output matching network 105, the operating frequency band can be further adjusted, so that the low-noise amplifier 100 can adapt to a wider operating frequency band.
  • the low noise amplifier 100 may further include a first bias resistor R1 and a second bias resistor R2, wherein one end of the first bias resistor R1 is connected to the gate of the first N-type transistor Q11, and the other end of the first bias resistor R1 is connected to the first bias signal BIAS1; One end is connected to the gate of the third N-type transistor Q13, and the other end is connected to the second bias signal BIAS2.
  • the first bias resistor R1 and the second bias resistor R2 provide bias voltage and isolate the RF signal at the same time.
  • the output matching network 105 includes a first variable capacitor.
  • the first end of the first variable capacitor is the input end of the output matching network 105, connected to the drain of the third N-type transistor Q13, and the second end of the first variable capacitor is the output end of the output matching network 105, connected to the input end of the output resistance attenuation network 106.
  • the impedance of the output matching network 105 can be adjusted.
  • the output matching network 105 can also be implemented with other structures, such as an adjustable resistor, or a combination of a capacitor and an inductor with adjustable capacitance, etc.
  • the first variable capacitor includes a first capacitor group 21 , a second capacitor group 22 and a third capacitor group 23 .
  • the first capacitor group 21 includes one or more first capacitor branches connected in parallel, each of which includes a first capacitor C21 and a first capacitor switching switch S21 connected thereto;
  • the second capacitor group 22 includes one or more second capacitor branches connected in parallel, each of which includes a second capacitor C22 and a second capacitor switching switch S22 connected thereto;
  • the third capacitor group 23 includes one or more third capacitor branches connected in parallel, each of which includes a third capacitor C23 and a third capacitor switching switch S23 connected thereto.
  • the first end of all the first capacitor branches is connected to the first end of all the second capacitor branches as the first end of the first variable capacitor, thereby being connected to the drain of the third N-type transistor Q13; the second end of all the first capacitor branches is connected to the first end of all the third capacitor branches as the second end of the first variable capacitor, thereby being connected to the input end of the output resistance attenuation network 106; the second end of all the second capacitor branches and the second end of all the third capacitor branches are grounded.
  • the capacitance of the first variable capacitor can be changed, thereby achieving a change in the impedance of the output matching network 105. Therefore, the impedance of the output matching network 105 can be adjusted according to the required working frequency band.
  • the input matching network 101 includes a first inductor LG, a DC blocking capacitor CB, and a second variable capacitor CGS.
  • the first end of the first inductor LG is connected to the signal input terminal RFin
  • the second end of the first inductor LG is connected to the first end of the DC blocking capacitor CB
  • the second end of the DC blocking capacitor CB is connected to the first end of the second variable capacitor CGS
  • the The gate of the first N-type transistor Q11 and the first end of the input resistance attenuation network 1031 are connected
  • the second end of the second variable capacitor CGS is connected to the source of the first N-type transistor Q11.
  • the first end of the first inductor LG corresponds to the input end of the input matching network 101, connected to the signal input end RFin
  • the connection node of the second end of the DC blocking capacitor CB and the first end of the second variable capacitor CGS corresponds to the output end of the input matching network 101, connected to the gates of all the first N-type transistors Q11 and the first end of the input resistance attenuation network 1031.
  • the second variable capacitor CGS is a switchable gate-source capacitor, which resonates together with the first inductor LG and the DC blocking capacitor CB in the operating frequency band, thereby achieving tunable input impedance matching.
  • the second variable capacitor CGS includes a plurality of fourth capacitor branches connected in parallel, each of which includes a fourth capacitor C24 and a fourth capacitor switching switch S24 connected thereto.
  • the first end of the plurality of fourth capacitor branches connected in parallel is connected to the gate of the first N-type transistor Q11, and the first end of the parallel connection is also the first end of the second variable capacitor CGS;
  • the second end of the plurality of fourth capacitor branches connected in parallel is connected to the source of the first N-type transistor Q11, and the second end of the parallel connection is also the second end of the second variable capacitor CGS.
  • the output resistance attenuation network 106 includes a first switch S30 and a first variable resistor.
  • the first end of the first switch S30 is connected to the first end of the first variable resistor as the input end of the output resistance attenuation network 106, and is connected to the output end of the output matching network 105.
  • the second end of the first switch S30 is connected to the second end of the first variable resistor as the output end of the output resistance attenuation network 106, and is connected to the signal output end RFout.
  • the signal amplified by the third N-type transistor Q13 is not attenuated after passing through the output matching network 105, but is directly transmitted to the signal output end RFout through the first switch S30 for output; when the first switch S30 is disconnected, the amplified signal passes through the output matching network 105, and is further attenuated by the first variable resistor of the output resistance attenuation network 106, and then output through the signal output end RFout.
  • the first variable resistor includes a first resistor group 31 , a second resistor group 32 and a third resistor group 33 .
  • the first resistor group 31 includes one or more first resistor branches in parallel, each of which includes a first resistor R31 and a first resistor switch S31 connected to each other
  • the second resistor group 32 includes one or more second resistor branches in parallel, each of which includes a second resistor R32 and a second resistor switch S32 connected to each other
  • the third resistor group 33 includes one or more third resistor branches in parallel, each of which includes a third resistor R33 and a third resistor switch S33 connected to each other.
  • the first end of all the first resistor branches is connected to the first end of all the second resistor branches as the first end of the first variable resistor
  • the second end of all the first resistor branches is connected to the first end of all the third resistor branches as the second end of the first variable resistor
  • the second end of all the second resistor branches and the second end of all the third resistor branches are grounded.
  • the input resistance attenuation network 1031 includes a second switch S40 , a fifth capacitor C25 , and a second variable resistor.
  • the second variable resistor includes a fourth resistor group 41 and a fifth resistor group 42
  • the fourth resistor group 41 includes one or more fourth resistor branches connected in parallel
  • each of the fourth resistor branches includes a fourth resistor R41 and a fourth resistor switching switch S41 connected thereto
  • the fifth resistor group 42 includes one or more fifth resistor branches connected in parallel
  • each of the fifth resistor branches includes a fifth resistor R42 and a fifth resistor switching switch S42 connected thereto.
  • the first end of the second switch S40 and the first ends of all the fourth resistance branches are connected to the output end of the input matching network 101, the second end of the second switch S40 and the second ends of all the fourth resistance branches and the first end of the fifth capacitor C25 are connected to the gate of the fourth N-type transistor Q14, the second end of the fifth capacitor C25 is connected to the first ends of all the fifth resistance branches, and the second ends of all the fifth resistance branches are connected to the first end of the source negative feedback unit 104.
  • the second switch S40 By controlling the on or off of the second switch S40, it is possible to control whether the input resistance attenuation network 1031 attenuates the signal.
  • the second switch S40 When the second switch S40 is closed, the signal is not attenuated by the input resistance attenuation network 1031. The signal is not attenuated by the network 1031, but is directly transmitted to the gate of the fourth N-type transistor Q14 through the second switch S40.
  • the second switch S40 When the second switch S40 is disconnected, the signal is transmitted to the gate of the fourth N-type transistor Q14 through the second variable resistor.
  • the input signal of the fourth N-type transistor Q14 (i.e., the gate-source voltage of the fourth N-type transistor) is the signal after the second variable resistor divides the voltage, thereby achieving signal attenuation.
  • the resistance value of the second variable resistor can be changed by controlling the conduction or disconnection of the resistance switching switches in each fourth resistance branch and each fifth resistance branch, thereby achieving different degrees of signal attenuation.
  • the source negative feedback unit 104 includes a first feedback inductor LS1 , a second feedback inductor LS2 , a sixth transistor Q16 , and a seventh transistor Q17 .
  • the first end of the first feedback inductor LS1 serves as the first end of the source negative feedback unit 104 and is connected to the sources of all the first N-type transistors Q11 and the second end of the input resistance attenuation network 1031 .
  • the second end of the first feedback inductor LS1 is connected to the first end of the second feedback inductor LS2 .
  • the sixth transistor Q16 and the seventh transistor Q17 are both N-type transistors, the drain of the sixth transistor Q16 is connected to the second end of the first feedback inductor LS1, the drain of the seventh transistor Q17 is connected to the second end of the second feedback inductor LS2, the gate of the sixth transistor Q16 and the gate of the seventh transistor Q17 are respectively used to input the fourth control signal, and the source of the sixth transistor Q16 and the source of the seventh transistor Q17 are grounded as the second end of the source negative feedback unit 104.
  • the source negative feedback unit 104 of this embodiment can provide two different gains.
  • the fourth control signal includes a high level and a low level.
  • the fourth control signal can control the conduction or disconnection of the sixth transistor Q16 and the seventh transistor Q17 respectively to control whether the second feedback inductor LS2 is connected to the circuit, thereby achieving gain adjustment.
  • the seventh transistor Q17 can be controlled to be disconnected and the sixth transistor Q16 can be turned on.
  • the second feedback inductor LS2 is not connected to the circuit, and only the first feedback inductor LS1 is connected to the circuit, so that a larger gain can be obtained.
  • the seventh transistor Q17 can be controlled to be turned on and the sixth transistor Q16 can be turned off.
  • the first feedback inductor LS1 and the second feedback inductor LS2 are both connected to the circuit, and a relatively small gain can be obtained.
  • the source negative feedback unit 104 together with the total transconductance of the common-source stage amplifier unit and the second variable capacitor CGS, constitute the real part of the input impedance.
  • arrow A in the figure indicates that a signal is input from a first end of the first feedback inductor LS1 , and the first feedback inductor LS1 and the second feedback inductor LS2 are connected in series by way of an inductor tap, thereby reducing the layout area.
  • the sixth transistor Q16 and the seventh transistor Q17 may also be P-type transistors, in which case the drain of the sixth transistor Q16 is connected to the second end of the first feedback inductor LS, the drain of the seventh transistor Q17 is connected to the second end of the second feedback inductor LS2, the gate of the sixth transistor Q16 and the gate of the seventh transistor Q17 are respectively used to input the fourth control signal, and the source of the sixth transistor Q16 and the source of the seventh transistor Q17 are connected to the first power supply voltage VDD1 as the second end of the source negative feedback unit 104.
  • the first feedback inductor LS1 and the second feedback inductor LS2 may also be connected in series by means of an inductor tap.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Amplifiers (AREA)

Abstract

Disclosed in embodiments of the present invention is a multi-band gain-adjustable low noise amplifier, comprising a signal input end, an input matching network, a plurality of common-source amplification units, a negative gain attenuation network, a source negative feedback unit, a common-gate driving amplification unit, a choke inductor unit, an impedance-adjustable output matching network, an output resistance attenuation network, and a signal output end. By means of a first control signal, one or more common-source amplification units can be selectively controlled to amplify a signal, so that gain adjustment can be achieved, thereby satisfying the requirement of a large dynamic range; moreover, whether a first choke inductor is connected to a circuit is controlled by controlling the on or off of a first P-type transistor and a second P-type transistor in the choke inductor unit, so that the adjustment of a working frequency band can be achieved; in addition, by means of further cooperation between the choke inductor unit and the impedance-adjustable output matching network, the adjustment of a wider frequency band can be achieved, and the occupied area can be reduced.

Description

多频段可调增益的低噪声放大器Multi-band adjustable gain low noise amplifier 技术领域Technical Field
本发明涉及电子技术领域，尤其涉及一种多频段可调增益的低噪声放大器。The invention relates to the field of electronic technology, and in particular to a multi-band gain-adjustable low-noise amplifier.
背景技术Background technique
低噪声放大器作为接收机的第一个模块，很大程度上决定了接收机在噪声、线性度和灵敏度等方面的性能。随着通信技术的发展，单个无线射频收发机兼容尽可能多的通信频带的需求大大增加，因而兼容多频段的射频接收机成为了通信领域的研究热点。为了实现多频段功能，现有的射频接收机一般是采用多个单独的低噪声放大器来实现，即多个单独的低噪声放大器并联，这些低噪声放大器分别工作在不同的频段，然后通过开关来选择所需频段的低噪声放大器。然而，上述方式中，由于需要设置多个并行的低噪声放大器，会大大增加低噪声放大器所占用的面积，不利于芯片小型化；此外，现有的传统低噪声放大器一般为固定增益模式，无法满足接收机大的动态范围的要求。As the first module of the receiver, the low noise amplifier largely determines the performance of the receiver in terms of noise, linearity and sensitivity. With the development of communication technology, the demand for a single wireless RF transceiver to be compatible with as many communication frequency bands as possible has greatly increased, so RF receivers compatible with multiple frequency bands have become a research hotspot in the field of communication. In order to achieve multi-band functions, existing RF receivers are generally implemented using multiple separate low noise amplifiers, that is, multiple separate low noise amplifiers are connected in parallel, and these low noise amplifiers work in different frequency bands respectively, and then the low noise amplifier of the required frequency band is selected by a switch. However, in the above method, since multiple parallel low noise amplifiers need to be set, the area occupied by the low noise amplifier will be greatly increased, which is not conducive to chip miniaturization; in addition, the existing traditional low noise amplifiers are generally fixed gain mode, which cannot meet the requirements of the large dynamic range of the receiver.
发明内容Summary of the invention
本发明实施例提供一种多频段可调增益的低噪声放大器，能够实现低噪声放大器的多频段的同时，减小低噪声放大器所占用的面积，且能够实现增益可调，满足大的动态范围。The embodiment of the present invention provides a multi-band adjustable gain low noise amplifier, which can realize the multi-band of the low noise amplifier while reducing the area occupied by the low noise amplifier, and can realize adjustable gain to meet a large dynamic range.
为了解决上述技术问题，第一方面，本发明提供一种多频段可调增益的低噪声放大器，包括信号输入端、输入匹配网络、多个共源级放大单元、负增益衰减网络、源级负反馈单元、共栅极驱动放大单元、扼流电感单元、阻抗可调的输出匹配网络、输出电阻衰减网络以及信号输出端；In order to solve the above technical problems, in a first aspect, the present invention provides a multi-band adjustable gain low-noise amplifier, comprising a signal input terminal, an input matching network, a plurality of common source stage amplification units, a negative gain attenuation network, a source stage negative feedback unit, a common gate drive amplification unit, a choke inductor unit, an output matching network with adjustable impedance, an output resistance attenuation network and a signal output terminal;
每个所述共源级放大单元包括对应连接的第一N型晶体管和第二N型晶体管，所述共栅极驱动放大单元包括第三N型晶体管和稳压电容，所述扼流电感单元包括第一P型晶体管、第二P型晶体管、第一扼流电感和第二扼流电感，所述负增益衰减网络包括输入电阻衰减网络、第四N型晶体管和第五N型晶体管；Each of the common-source amplifier units includes a first N-type transistor and a second N-type transistor connected correspondingly, the common-gate drive amplifier unit includes a third N-type transistor and a voltage-stabilizing capacitor, the choke inductor unit includes a first P-type transistor, a second P-type transistor, a first choke inductor and a second choke inductor, and the negative gain attenuation network includes an input resistance attenuation network, a fourth N-type transistor and a fifth N-type transistor;
所述输入匹配网络的输入端连接至所述信号输入端，所有所述第一N型晶 体管的栅极和所述输入电阻衰减网络的第一端均连接至所述输入匹配网络的输出端，所有所述第一N型晶体管的源极、所述输入电阻衰减网络的第二端以及所述第四N型晶体管的源极均连接至所述源极负反馈单元的第一端，所述源极负反馈单元的第二端接地或连接第一供电电压，各所述第一N型晶体管的漏极与对应的所述第二N型晶体管的源极连接，各所述第二N型晶体管的栅极分别用于输入第一控制信号，所有所述第二N型晶体管的漏极和所述第五N型晶体管的漏极均连接至所述第三N型晶体管的源极，所述第三N型晶体管的栅极通过所述稳压电容接地，所述第四N型晶体管的栅极与所述输入电阻衰减网络的第三端连接，所述第四N型晶体管的漏极与所述第五N型晶体管的源极连接，所述第五N型晶体管的栅极用于输入第二控制信号；The input end of the input matching network is connected to the signal input end, and all the first N-type crystals The gate of the body tube and the first end of the input resistance attenuation network are connected to the output end of the input matching network, the sources of all the first N-type transistors, the second end of the input resistance attenuation network and the source of the fourth N-type transistor are connected to the first end of the source negative feedback unit, the second end of the source negative feedback unit is grounded or connected to the first power supply voltage, the drain of each of the first N-type transistors is connected to the source of the corresponding second N-type transistor, the gate of each of the second N-type transistors is respectively used to input a first control signal, the drain of all the second N-type transistors and the drain of the fifth N-type transistor are connected to the source of the third N-type transistor, the gate of the third N-type transistor is grounded through the voltage stabilizing capacitor, the gate of the fourth N-type transistor is connected to the third end of the input resistance attenuation network, the drain of the fourth N-type transistor is connected to the source of the fifth N-type transistor, and the gate of the fifth N-type transistor is used to input a second control signal;
所述第一P型晶体管的源极和所述第二P型晶体管的源极均连接第二供电电压，所述第一P型晶体管的栅极和所述第二P型晶体管的栅极分别用于输入第三控制信号，所述第一P型晶体管的漏极与所述第一扼流电感的第一端连接，所述第一扼流电感的第二端与所述第二P型晶体管的漏极、所述第二扼流电感的第一端连接，所述第二扼流电感的第二端与所述第三N型晶体管的漏极、所述输出匹配网络的输入端连接，所述输出匹配网络的输出端与所述输出电阻衰减网络的输入端连接，所述输出电阻衰减网络的输出端与所述信号输出端连接。The source of the first P-type transistor and the source of the second P-type transistor are both connected to a second power supply voltage, the gate of the first P-type transistor and the gate of the second P-type transistor are respectively used to input a third control signal, the drain of the first P-type transistor is connected to the first end of the first choke inductor, the second end of the first choke inductor is connected to the drain of the second P-type transistor and the first end of the second choke inductor, the second end of the second choke inductor is connected to the drain of the third N-type transistor and the input end of the output matching network, the output end of the output matching network is connected to the input end of the output resistance attenuation network, and the output end of the output resistance attenuation network is connected to the signal output end.
进一步地，所述输出匹配网络包括第一可变电容器；Further, the output matching network includes a first variable capacitor;
所述第一可变电容器的第一端为所述输出匹配网络的输入端，与所述第三N型晶体管的漏极连接，所述第一可变电容器的第二端为所述输出匹配网络的输出端，与所述输出电阻衰减网络的输入端连接。The first end of the first variable capacitor is the input end of the output matching network, connected to the drain of the third N-type transistor, and the second end of the first variable capacitor is the output end of the output matching network, connected to the input end of the output resistance attenuation network.
进一步地，所述第一可变电容器包括第一电容组、第二电容组以及第三电容组；Further, the first variable capacitor includes a first capacitance group, a second capacitance group and a third capacitance group;
所述第一电容组包括一个或并联的多个第一电容支路，每个所述第一电容支路包括相连接的第一电容和第一电容切换开关，所述第二电容组包括一个或并联的多个第二电容支路，每个所述第二电容支路包括相连接的第二电容和第二电容切换开关，所述第三电容组包括一个或并联的多个第三电容支路，每个所述第三电容支路包括相连接的第三电容和第三电容切换开关；The first capacitor group includes one or a plurality of first capacitor branches connected in parallel, each of the first capacitor branches includes a first capacitor connected to each other and a first capacitor switching switch; the second capacitor group includes one or a plurality of second capacitor branches connected in parallel, each of the second capacitor branches includes a second capacitor connected to each other and a second capacitor switching switch; the third capacitor group includes one or a plurality of third capacitor branches connected in parallel, each of the third capacitor branches includes a third capacitor connected to each other and a third capacitor switching switch;
其中，所有所述第一电容支路的第一端与所有所述第二电容支路的第一端 相连接以作为所述第一可变电容器的第一端，所有所述第一电容支路的第二端与所有所述第三电容支路的第一端相连接以作为所述第一可变电容器的第二端，所有所述第二电容支路的第二端和所有所述第三电容支路的第二端均接地。Wherein, the first ends of all the first capacitor branches and the first ends of all the second capacitor branches The second ends of all the first capacitor branches are connected to the first ends of all the third capacitor branches to serve as the second end of the first variable capacitor, and the second ends of all the second capacitor branches and the second ends of all the third capacitor branches are grounded.
进一步地，所述输入匹配网络包括第一电感、隔直电容以及第二可变电容器；Further, the input matching network includes a first inductor, a DC blocking capacitor and a second variable capacitor;
所述第一电感的第一端连接至所述信号输入端，所述第一电感的第二端与所述隔直电容的第一端连接，所述隔直电容的第二端与所述第二可变电容的第一端、所述第一N型晶体管的栅极、所述输入电阻衰减网络的第一端连接，所述第二可变电容器的第二端连接至所述第一N型晶体管的源极。The first end of the first inductor is connected to the signal input end, the second end of the first inductor is connected to the first end of the DC blocking capacitor, the second end of the DC blocking capacitor is connected to the first end of the second variable capacitor, the gate of the first N-type transistor, and the first end of the input resistance attenuation network, and the second end of the second variable capacitor is connected to the source of the first N-type transistor.
进一步地，所述第二可变电容器包括多个并联的第四电容支路，每个所述第四电容支路包括相连接的第四电容和第四电容切换开关；Further, the second variable capacitor includes a plurality of fourth capacitance branches connected in parallel, and each of the fourth capacitance branches includes a fourth capacitor and a fourth capacitance switching switch connected thereto;
多个所述第四电容支路并联的第一端与所述第一N型晶体管的栅极连接，多个所述第四电容支路并联的第二端与所述第一N型晶体管的源极连接。A first end of the plurality of fourth capacitor branches connected in parallel is connected to the gate of the first N-type transistor, and a second end of the plurality of fourth capacitor branches connected in parallel is connected to the source of the first N-type transistor.
进一步地，所述输出电阻衰减网络包括第一开关和第一可变电阻器；Further, the output resistance attenuation network includes a first switch and a first variable resistor;
所述第一开关的第一端和所述第一可变电阻器的第一端相连接以作为所述输出电阻衰减网络的输入端，与所述输出匹配网络的输出端连接，所述第一开关的第二端和所述第一可变电阻器的第二端相连接以作为所述输出电阻衰减网络的输出端，与所述信号输出端连接。The first end of the first switch and the first end of the first variable resistor are connected to serve as the input end of the output resistance attenuation network, and are connected to the output end of the output matching network. The second end of the first switch and the second end of the first variable resistor are connected to serve as the output end of the output resistance attenuation network, and are connected to the signal output end.
进一步地，所述第一可变电阻器包括第一电阻组、第二电阻组以及第三电阻组；Further, the first variable resistor includes a first resistor group, a second resistor group and a third resistor group;
所述第一电阻组包括一个或并联的多个第一电阻支路，每个所述第一电阻支路包括相连接的第一电阻和第一电阻切换开关，所述第二电阻组包括一个或并联的多个第二电阻支路，每个所述第二电阻支路包括相连接的第二电阻和第二电阻切换开关，所述第三电阻组包括一个或并联的多个第三电阻支路，每个所述第三电阻支路包括相连接的第三电阻和第三电阻切换开关；The first resistor group includes one or a plurality of first resistor branches connected in parallel, each of the first resistor branches includes a first resistor connected to each other and a first resistor switching switch; the second resistor group includes one or a plurality of second resistor branches connected in parallel, each of the second resistor branches includes a second resistor connected to each other and a second resistor switching switch; the third resistor group includes one or a plurality of third resistor branches connected in parallel, each of the third resistor branches includes a third resistor connected to each other and a third resistor switching switch;
其中，所有所述第一电阻支路的第一端与所有所述第二电阻支路的第一端相连接以作为所述第一可变电阻器的第一端，所有所述第一电阻支路的第二端与所有所述第三电阻支路的第一端相连接以作为所述第一可变电阻器的第二端，所有所述第二电阻支路的第二端和所有所述第三电阻支路的第二端均接地。 Among them, the first ends of all the first resistance branches are connected to the first ends of all the second resistance branches to serve as the first end of the first variable resistor, the second ends of all the first resistance branches are connected to the first ends of all the third resistance branches to serve as the second end of the first variable resistor, and the second ends of all the second resistance branches and the second ends of all the third resistance branches are grounded.
进一步地，所述输入电阻衰减网络包括第二开关、第五电容以及第二可变电阻器；Further, the input resistance attenuation network includes a second switch, a fifth capacitor and a second variable resistor;
所述第二可变电阻器包括第四电阻组和第五电阻组，所述第四电阻组包括一个或多个并联的第四电阻支路，每个所述第四电阻支路包括相连接的第四电阻和第四电阻切换开关，所述第五电阻组包括一个或多个并联的第五电阻支路，每个所述第五电阻支路包括相连接的第五电阻和第五电阻切换开关；The second variable resistor includes a fourth resistor group and a fifth resistor group, the fourth resistor group includes one or more fourth resistor branches connected in parallel, each of the fourth resistor branches includes a fourth resistor and a fourth resistor switch connected thereto, the fifth resistor group includes one or more fifth resistor branches connected in parallel, each of the fifth resistor branches includes a fifth resistor and a fifth resistor switch connected thereto;
所述第二开关的第一端与所有所述第四电阻支路的第一端均连接至所述输入匹配网络的输出端，所述第二开关的第二端与所有所述第四电阻支路的第二端、所述第五电容的第一端均连接至所述第四N型晶体管的栅极，所述第五电容的第二端与所有所述第五电阻支路的第一端连接，所有所述第五电阻支路的第二端均连接至所述源极负反馈单元的第一端。The first end of the second switch and the first ends of all the fourth resistance branches are connected to the output end of the input matching network, the second end of the second switch and the second ends of all the fourth resistance branches and the first end of the fifth capacitor are connected to the gate of the fourth N-type transistor, the second end of the fifth capacitor is connected to the first end of all the fifth resistance branches, and the second ends of all the fifth resistance branches are connected to the first end of the source negative feedback unit.
进一步地，所述源极负反馈单元包括第一反馈电感、第二反馈电感、第六晶体管以及第七晶体管；Further, the source negative feedback unit includes a first feedback inductor, a second feedback inductor, a sixth transistor and a seventh transistor;
所述第一反馈电感的第一端作为所述源极负反馈单元的第一端，与所有所述第一N型晶体管的源极和所述输入电阻衰减网络的第二端连接，所述第一反馈电感的第二端与所述第二反馈电感的第一端连接；The first end of the first feedback inductor serves as the first end of the source negative feedback unit, connected to the sources of all the first N-type transistors and the second end of the input resistance attenuation network, and the second end of the first feedback inductor is connected to the first end of the second feedback inductor;
当所述第六晶体管和所述第七晶体管均为N型晶体管时，所述第六晶体管的漏极与所述第一反馈电感的第二端连接，所述第七晶体管的漏极与所述第二反馈电感的第二端连接，所述第六晶体管的栅极和所述第七晶体管的栅极分别用于输入第四控制信号，所述第六晶体管的源极和所述第七晶体管的源极作为所述源极负反馈单元的第二端接地；When the sixth transistor and the seventh transistor are both N-type transistors, the drain of the sixth transistor is connected to the second end of the first feedback inductor, the drain of the seventh transistor is connected to the second end of the second feedback inductor, the gate of the sixth transistor and the gate of the seventh transistor are respectively used to input a fourth control signal, and the source of the sixth transistor and the source of the seventh transistor are grounded as the second end of the source negative feedback unit;
当所述第六晶体管和所述第七晶体管均为P型晶体管时，所述第六晶体管的漏极与所述第一反馈电感的第二端连接，所述第七晶体管的漏极与所述第二反馈电感的第二端连接，所述第六晶体管的栅极和所述第七晶体管的栅极分别用于输入第四控制信号，所述第六晶体管的源极和所述第七晶体管的源极作为所述源极负反馈单元的第二端连接第一供电电压。When the sixth transistor and the seventh transistor are both P-type transistors, the drain of the sixth transistor is connected to the second end of the first feedback inductor, the drain of the seventh transistor is connected to the second end of the second feedback inductor, the gate of the sixth transistor and the gate of the seventh transistor are respectively used to input a fourth control signal, and the source of the sixth transistor and the source of the seventh transistor are connected to the first supply voltage as the second end of the source negative feedback unit.
进一步地，所述第一反馈电感和所述第二反馈电感通过电感抽头的方式串联。Furthermore, the first feedback inductor and the second feedback inductor are connected in series by way of an inductor tap.
有益效果：本发明的多频段可调增益的低噪声放大器中，通过设置并行的 多个共源级放大单元，并通过第一控制信号可以选择性控制一个或多个共源级放大单元对信号进行放大，由此可实现增益的调节，满足大动态范围的要求；并且，通过控制扼流电感单元中的第一P型晶体管和第二P型晶体管的导通或关断，以控制第一扼流电感是否接入电路，从而可实现工作频段的调节，此外通过扼流电感单元和阻抗可调的输出匹配网络的进一步配合，可以实现更宽频段的调节，与传统的通过多个低噪声放大器实现多频段功能的方式相比，本发明可以减小所占用的面积。Beneficial effect: In the multi-band adjustable gain low noise amplifier of the present invention, by setting parallel A plurality of common-source amplifier units are provided, and one or more common-source amplifier units can be selectively controlled to amplify the signal through a first control signal, thereby achieving gain adjustment to meet the requirement of a large dynamic range; and, by controlling the conduction or disconnection of a first P-type transistor and a second P-type transistor in a choke inductor unit, whether the first choke inductor is connected to the circuit is controlled, thereby achieving adjustment of the working frequency band. In addition, through further cooperation between the choke inductor unit and an output matching network with adjustable impedance, adjustment of a wider frequency band can be achieved. Compared with the traditional method of achieving multi-band functions through multiple low-noise amplifiers, the present invention can reduce the occupied area.
附图说明BRIEF DESCRIPTION OF THE DRAWINGS
下面结合附图，通过对本发明的具体实施方式详细描述，将使本发明的技术方案及其有益效果显而易见。The technical solutions and beneficial effects of the present invention will be made apparent by describing in detail the specific embodiments of the present invention in conjunction with the accompanying drawings.
图1是本发明实施例的多频段可调增益的低噪声放大器的结构示意图；1 is a schematic structural diagram of a multi-band adjustable gain low noise amplifier according to an embodiment of the present invention;
图2是本发明实施例提供的输出匹配网络的具体实现电路图；FIG2 is a specific implementation circuit diagram of an output matching network provided by an embodiment of the present invention;
图3是本发明实施例提供的第二可变电容器的具体实现电路图；3 is a specific implementation circuit diagram of a second variable capacitor provided by an embodiment of the present invention;
图4是本发明实施例提供的输出电阻衰减网络的具体实现电路图；FIG4 is a circuit diagram of a specific implementation of an output resistance attenuation network provided by an embodiment of the present invention;
图5是本发明实施例提供的输入电阻衰减网络的具体实现电路图；5 is a specific implementation circuit diagram of an input resistance attenuation network provided in an embodiment of the present invention;
图6是图1所示的源极负反馈单元的结构示意图；FIG6 is a schematic diagram of the structure of the source negative feedback unit shown in FIG1 ;
图7是本发明实施例提供的源极负反馈单元的另一具体实现电路图；7 is another specific implementation circuit diagram of the source negative feedback unit provided by an embodiment of the present invention;
图8是图7所示的源极负反馈单元的结构示意图。FIG. 8 is a schematic structural diagram of the source negative feedback unit shown in FIG. 7 .
具体实施方式Detailed ways
请参照图式，其中相同的组件符号代表相同的组件，本发明的原理是以实施在一适当的运算环境中来举例说明。以下的说明是基于所例示的本发明具体实施例，其不应被视为限制本发明未在此详述的其它具体实施例。Please refer to the drawings, in which the same component symbols represent the same components, and the principle of the present invention is illustrated by implementing it in an appropriate computing environment. The following description is based on the illustrated specific embodiment of the present invention, which should not be considered as limiting other specific embodiments of the present invention that are not described in detail herein.
参阅图1，本发明实施例提供的多频段可调增益的低噪声放大器100包括信号输入端RFin、输入匹配网络101、多个共源级放大单元1021～102n、负增益衰减网络103、源级负反馈单元104、共栅极驱动放大单元、扼流电感单元、阻抗可调的输出匹配网络105、输出电阻衰减网络106以及信号输出端RFout。1 , a multi-band adjustable gain low noise amplifier 100 provided in an embodiment of the present invention includes a signal input terminal RFin, an input matching network 101, a plurality of common source stage amplification units 1021 to 102n, a negative gain attenuation network 103, a source stage negative feedback unit 104, a common gate drive amplification unit, a choke inductor unit, an output matching network 105 with adjustable impedance, an output resistance attenuation network 106, and a signal output terminal RFout.
如图1所示，每个所述共源级放大单元102n包括对应连接的第一N型晶体管Q11和第二N型晶体管Q12，所述共栅极驱动放大单元包括第三N型晶体管Q13和稳压电容CCG，所述扼流电感单元包括第一P型晶体管M11、第 二P型晶体管M12、第一扼流电感LD1和第二扼流电感LD2，所述负增益衰减网络103包括输入电阻衰减网络1031、第四N型晶体管Q14和第五N型晶体管Q15。As shown in FIG1 , each of the common source amplifier units 102n includes a first N-type transistor Q11 and a second N-type transistor Q12 connected to each other, the common gate drive amplifier unit includes a third N-type transistor Q13 and a voltage stabilizing capacitor CCG, and the choke inductor unit includes a first P-type transistor M11, a third N-type transistor Q12 and a third P-type transistor Q13. Two P-type transistors M12, a first choke inductor LD1 and a second choke inductor LD2, the negative gain attenuation network 103 includes an input resistance attenuation network 1031, a fourth N-type transistor Q14 and a fifth N-type transistor Q15.
所述输入匹配网络101的输入端连接至所述信号输入端RFin，所有所述第一N型晶体管Q11的栅极和所述输入电阻衰减网络1031的第一端均连接至所述输入匹配网络101的输出端，所有所述第一N型晶体管Q11的源极、所述输入电阻衰减网络1031的第二端以及所述第四N型晶体管Q14的源极均连接至所述源极负反馈单元104的第一端，所述源极负反馈单元104的第二端接地或连接第一供电电压，各所述第一N型晶体管Q11的漏极与对应的所述第二N型晶体管Q12的源极连接，各所述第二N型晶体管Q12的栅极分别用于输入第一控制信号，所有所述第二N型晶体管Q12的漏极和所述第五N型晶体管Q15的漏极均连接至所述第三N型晶体管Q13的源极，所述第三N型晶体管Q13的栅极通过所述稳压电容CCG接地，所述第四N型晶体管Q14的栅极与所述输入电阻衰减网络1031的第三端连接，所述第四N型晶体管Q14的漏极与所述第五N型晶体管Q15的源极连接，所述第五N型晶体管Q15的栅极用于输入第二控制信号。The input end of the input matching network 101 is connected to the signal input end RFin, the gates of all the first N-type transistors Q11 and the first end of the input resistance attenuation network 1031 are connected to the output end of the input matching network 101, the sources of all the first N-type transistors Q11, the second end of the input resistance attenuation network 1031 and the source of the fourth N-type transistor Q14 are connected to the first end of the source negative feedback unit 104, the second end of the source negative feedback unit 104 is grounded or connected to the first power supply voltage, the drain of each of the first N-type transistors Q11 is connected to the corresponding second N-type transistor Q14. The source of the second N-type transistor Q12 is connected, the gate of each of the second N-type transistors Q12 is respectively used to input the first control signal, the drains of all the second N-type transistors Q12 and the drain of the fifth N-type transistor Q15 are connected to the source of the third N-type transistor Q13, the gate of the third N-type transistor Q13 is grounded through the voltage-stabilizing capacitor CCG, the gate of the fourth N-type transistor Q14 is connected to the third end of the input resistor attenuation network 1031, the drain of the fourth N-type transistor Q14 is connected to the source of the fifth N-type transistor Q15, and the gate of the fifth N-type transistor Q15 is used to input the second control signal.
所述第一P型晶体管M11的源极和所述第二P型晶体管M12的源极均连接第二供电电压VDD2，所述第一P型晶体管M11的栅极和所述第二P型晶体管M12的栅极分别用于输入第三控制信号，所述第一P型晶体管M11的漏极与所述第一扼流电感LD1的第一端连接，所述第一扼流电感LD1的第二端与所述第二P型晶体管M12的漏极、所述第二扼流电感LD2的第一端连接，所述第二扼流电感LD2的第二端与所述第三N型晶体管Q13的漏极、所述输出匹配网络105的输入端连接，所述输出匹配网络105的输出端与所述输出电阻衰减网络106的输入端连接，所述输出电阻衰减网络106的输出端与所述信号输出端RFout连接。The source of the first P-type transistor M11 and the source of the second P-type transistor M12 are both connected to the second power supply voltage VDD2, the gate of the first P-type transistor M11 and the gate of the second P-type transistor M12 are respectively used to input a third control signal, the drain of the first P-type transistor M11 is connected to the first end of the first choke inductor LD1, the second end of the first choke inductor LD1 is connected to the drain of the second P-type transistor M12 and the first end of the second choke inductor LD2, the second end of the second choke inductor LD2 is connected to the drain of the third N-type transistor Q13 and the input end of the output matching network 105, the output end of the output matching network 105 is connected to the input end of the output resistance attenuation network 106, and the output end of the output resistance attenuation network 106 is connected to the signal output end RFout.
其中，第一控制信号、第二控制信号和第三控制信号均包括高电平和低电平，由此通过第一控制信号、第二控制信号和第三控制信号的作用可以分别控制相应的晶体管处于导通状态或断开状态，例如当第一控制信号为高电平信号时，可以控制第二N型晶体管Q12导通，若为低电平，则可以控制第二N型 晶体管Q12关断。可以理解的是，各个第二N型晶体管Q12的栅极互不相连，可以单独控制各个第二N型晶体管Q12的栅极所输入的第一控制信号为高电平或低电平，例如可以使其中一个第二N型晶体管Q12的第一控制信号为高电平，而其他第二N型晶体管Q12的第一控制信号为低电平，或者可以使其中的两个或三个第二N型晶体管Q12的第一控制信号为高电平，而其他第二N型晶体管Q12的第一控制信号为低电平，从而可以选择性地使其中一个或多个第二N型晶体管Q12为导通状态或关断状态。同理地，可以分别单独控制第一P型晶体管M11和第二P型晶体管M12的栅极所输入的第三控制信号为高电平或低电平，例如可以使第一P型晶体管M11的栅极输入的第三控制信号为高电平，而第二P型晶体管M12的栅极输入的第三控制信号为低电平，或者可以使两个P型晶体管的栅极输入的第三控制信号均为高电平或低电平，从而可以选择性地使其中一个或两个P型晶体管为导通状态或断开状态。Among them, the first control signal, the second control signal and the third control signal all include high level and low level, thereby the first control signal, the second control signal and the third control signal can respectively control the corresponding transistor to be in the on state or the off state. For example, when the first control signal is a high level signal, the second N-type transistor Q12 can be controlled to be turned on, and if it is a low level, the second N-type The transistor Q12 is turned off. It can be understood that the gates of the second N-type transistors Q12 are not connected to each other, and the first control signal input to the gate of each second N-type transistor Q12 can be individually controlled to be high or low. For example, the first control signal of one of the second N-type transistors Q12 can be high, while the first control signal of the other second N-type transistors Q12 can be low, or the first control signal of two or three of the second N-type transistors Q12 can be high, while the first control signal of the other second N-type transistors Q12 can be low, so that one or more of the second N-type transistors Q12 can be selectively turned on or off. Similarly, the third control signal input to the gate of the first P-type transistor M11 and the second P-type transistor M12 can be controlled separately to be high or low. For example, the third control signal input to the gate of the first P-type transistor M11 can be high, while the third control signal input to the gate of the second P-type transistor M12 can be low. Alternatively, the third control signals input to the gates of the two P-type transistors can be high or low, so that one or both of the P-type transistors can be selectively turned on or off.
本发明实施例中，通过第五N型晶体管Q15的作用可以实现正增益档位和负增益档位的切换。In the embodiment of the present invention, the switching between the positive gain gear and the negative gain gear can be achieved through the action of the fifth N-type transistor Q15.
更具体地，输入电阻衰减网络1031、第四N型晶体管Q14和第五N型晶体管Q15组成负增益单元103，能够为低噪声放大器100提供负增益档位。其中，当低噪声放大器100需要处于负增益档位时，通过第一控制信号控制所有的第二N型晶体管Q12关断，即所有第二N晶体管Q12的栅极输入的第一控制信号均为低电平，并通过第二控制信号控制第五N型晶体管Q15导通，即第二控制信号为高电平，此时射频信号从信号输入端RFin输入，经过输入匹配网络101后进入输入电阻衰减网络1031，经过输入电阻衰减网络1031的衰减后再被第四N型晶体管Q14放大，由此可以提高低噪声放大器100在负增益档位下的线性度。之后，经第四N型晶体管Q14放大后的信号依次经过第五N型晶体管Q15、第三N型晶体管Q13、输出匹配网络105和输出电阻衰减网络106后，从信号输出端RFout输出。当低噪声放大器100处于正增益档位时，通过第二控制信号控制第五N型晶体管Q15关断，通过第一控制信号控制部分或全部的第二N型晶体管Q12导通，从而射频信号从信号输入端RFin输入，经过输入匹配网络101后进入导通的共源级放大单元进行放大后，依次经过第三N型晶体管Q13、输出匹配网络105和输出电阻衰减网络106，然后从信号输出 端RFout输出。More specifically, the input resistance attenuation network 1031, the fourth N-type transistor Q14 and the fifth N-type transistor Q15 form a negative gain unit 103, which can provide a negative gain gear for the low noise amplifier 100. When the low noise amplifier 100 needs to be in a negative gain gear, all the second N-type transistors Q12 are turned off by the first control signal, that is, the first control signal input to the gate of all the second N-type transistors Q12 is low, and the fifth N-type transistor Q15 is turned on by the second control signal, that is, the second control signal is high. At this time, the RF signal is input from the signal input terminal RFin, enters the input resistance attenuation network 1031 after passing through the input matching network 101, and is amplified by the fourth N-type transistor Q14 after being attenuated by the input resistance attenuation network 1031, thereby improving the linearity of the low noise amplifier 100 in the negative gain gear. Afterwards, the signal amplified by the fourth N-type transistor Q14 passes through the fifth N-type transistor Q15, the third N-type transistor Q13, the output matching network 105 and the output resistance attenuation network 106 in sequence, and is output from the signal output terminal RFout. When the low noise amplifier 100 is in the positive gain gear, the fifth N-type transistor Q15 is turned off by the second control signal, and part or all of the second N-type transistors Q12 are turned on by the first control signal, so that the radio frequency signal is input from the signal input terminal RFin, passes through the input matching network 101, enters the turned-on common source stage amplification unit for amplification, passes through the third N-type transistor Q13, the output matching network 105 and the output resistor attenuation network 106 in sequence, and then outputs from the signal output terminal RFin. Terminal RFout output.
其中，在正增益档位时，通过多个共源级放大单元1021～102n可以为低噪声放大器100提供大部分增益，其中通过控制第二N型晶体管Q12的导通和关断，可以控制相应的第一N型晶体管Q11是否提供增益，由此实现部分增益可调。其中，当所有第二N型晶体管Q12均为导通状态，即所有第二N型晶体管Q12的栅极所输入的第一控制信号均为高电平，此时可以使得所有第一N型晶体管Q11均提供增益，从而多个共源级放大单元1021～102n对低噪声放大器100提供最大的增益；在实际使用中，可以根据所需增益选择部分或全部第二N型晶体管Q12导通，以使得部分或全部第一N型晶体管Q11提供增益，实现增益可调，从而满足大动态范围的要求。In the positive gain gear, a plurality of common source amplifier units 1021-102n can provide most of the gain for the low noise amplifier 100, wherein by controlling the conduction and shutdown of the second N-type transistor Q12, it is possible to control whether the corresponding first N-type transistor Q11 provides gain, thereby achieving partial gain adjustment. In the case where all the second N-type transistors Q12 are in the on state, that is, the first control signals input to the gates of all the second N-type transistors Q12 are at a high level, all the first N-type transistors Q11 can provide gain at this time, so that the plurality of common source amplifier units 1021-102n provide the maximum gain for the low noise amplifier 100; in actual use, part or all of the second N-type transistors Q12 can be selected to be turned on according to the required gain, so that part or all of the first N-type transistors Q11 provide gain, achieving gain adjustment, thereby meeting the requirements of a large dynamic range.
此外，本发明实施例中，由第一扼流电感LD1、第二扼流电感LD2、第一P型晶体管M11、第二P型晶体管M12组成的可切换扼流电感为有源放大部分提供直流电压，同时其感性阻抗与阻抗可调的输出匹配网络105共同组成阻抗变换电路，将第三N型晶体管Q13的漏极处的阻抗转换成后级电路的共轭阻抗，保证由低噪声放大器产生的功率能最大限度的传输给后级电路，通过切换扼流电感LD1和/或调节输出匹配网络105的阻抗可以自由地调整谐振频点，由此实现输出满足多频段需求。更具体而言，通过第三控制信号控制第一P型晶体管M11和第二P型晶体管M12的导通或关断，以控制第一扼流电感LD1是否接入电路，从而可调节低噪声放大器100的工作频段，而配合阻抗可调的输出匹配网络105，可以使得工作频段的调节范围更宽。例如，若需要低噪声放大器100工作在较宽的工作频段，可以控制第一P型晶体管M11导通，第二P型晶体管M12断开，此时第一扼流电感LD1和第二扼流电感LD2均接入电路；当需要工作在较窄的工作频段时，可以控制第一P型晶体管M11关断，第二P型晶体管M12导通，此时只有第二扼流电感LD2接入电路；并且，通过调节输出匹配网络105的阻抗，可以进一步调节工作频段，使得低噪声放大器100能够适应更宽的工作频段。In addition, in the embodiment of the present invention, the switchable choke inductor composed of the first choke inductor LD1, the second choke inductor LD2, the first P-type transistor M11, and the second P-type transistor M12 provides a DC voltage for the active amplifier part, and its inductive impedance and the output matching network 105 with adjustable impedance together form an impedance conversion circuit, which converts the impedance at the drain of the third N-type transistor Q13 into the conjugate impedance of the subsequent circuit, ensuring that the power generated by the low-noise amplifier can be transmitted to the subsequent circuit to the maximum extent, and the resonant frequency can be freely adjusted by switching the choke inductor LD1 and/or adjusting the impedance of the output matching network 105, thereby achieving output that meets multi-band requirements. More specifically, the first P-type transistor M11 and the second P-type transistor M12 are turned on or off by the third control signal to control whether the first choke inductor LD1 is connected to the circuit, so that the working frequency band of the low-noise amplifier 100 can be adjusted, and the output matching network 105 with adjustable impedance can make the adjustment range of the working frequency band wider. For example, if the low-noise amplifier 100 is required to operate in a wider operating frequency band, the first P-type transistor M11 can be controlled to be turned on and the second P-type transistor M12 can be turned off. At this time, the first choke inductor LD1 and the second choke inductor LD2 are both connected to the circuit; when it is necessary to operate in a narrower operating frequency band, the first P-type transistor M11 can be controlled to be turned off and the second P-type transistor M12 can be turned on. At this time, only the second choke inductor LD2 is connected to the circuit; and by adjusting the impedance of the output matching network 105, the operating frequency band can be further adjusted, so that the low-noise amplifier 100 can adapt to a wider operating frequency band.
如图1所示，低噪声放大器100进一步还可以包括第一偏置电阻R1和第二偏置电阻R2，其中第一偏置电阻R1的一端连接至第一N型晶体管Q11的栅极，第一偏置电阻R1的另一端连接第一偏置信号BIAS1；第二偏置电阻R2的 一端连接至第三N型晶体管Q13的栅极，另一端连接第二偏置信号BIAS2。第一偏置电阻R1和第二偏置电阻R2提供偏置电压的同时隔绝射频信号。As shown in FIG1 , the low noise amplifier 100 may further include a first bias resistor R1 and a second bias resistor R2, wherein one end of the first bias resistor R1 is connected to the gate of the first N-type transistor Q11, and the other end of the first bias resistor R1 is connected to the first bias signal BIAS1; One end is connected to the gate of the third N-type transistor Q13, and the other end is connected to the second bias signal BIAS2. The first bias resistor R1 and the second bias resistor R2 provide bias voltage and isolate the RF signal at the same time.
本发明实施例中，所述输出匹配网络105包括第一可变电容器。所述第一可变电容器的第一端为所述输出匹配网络105的输入端，与所述第三N型晶体管Q13的漏极连接，所述第一可变电容器的第二端为所述输出匹配网络105的输出端，与所述输出电阻衰减网络106的输入端连接。通过设置容值可变的第一可变电容器，从而实现输出匹配网络105的阻抗可调。当然，在其他实施方式中，输出匹配网络105也可以采用其他结构实现，例如可调的电阻器，或者容值可调的电容和电感的组合，等等。In the embodiment of the present invention, the output matching network 105 includes a first variable capacitor. The first end of the first variable capacitor is the input end of the output matching network 105, connected to the drain of the third N-type transistor Q13, and the second end of the first variable capacitor is the output end of the output matching network 105, connected to the input end of the output resistance attenuation network 106. By setting the first variable capacitor with variable capacitance, the impedance of the output matching network 105 can be adjusted. Of course, in other implementations, the output matching network 105 can also be implemented with other structures, such as an adjustable resistor, or a combination of a capacitor and an inductor with adjustable capacitance, etc.
参阅图2，进一步地，所述第一可变电容器包括第一电容组21、第二电容组22以及第三电容组23。Referring to FIG. 2 , further, the first variable capacitor includes a first capacitor group 21 , a second capacitor group 22 and a third capacitor group 23 .
所述第一电容组21包括一个或并联的多个第一电容支路，每个所述第一电容支路包括相连接的第一电容C21和第一电容切换开关S21，所述第二电容组22包括一个或并联的多个第二电容支路，每个所述第二电容支路包括相连接的第二电容C22和第二电容切换开关S22，所述第三电容组23包括一个或并联的多个第三电容支路，每个所述第三电容支路包括相连接的第三电容C23和第三电容切换开关S23。其中，所有所述第一电容支路的第一端与所有所述第二电容支路的第一端相连接以作为所述第一可变电容器的第一端，从而与所述第三N型晶体管Q13的漏极连接；所有所述第一电容支路的第二端与所有所述第三电容支路的第一端相连接以作为所述第一可变电容器的第二端，从而与所述输出电阻衰减网络106的输入端连接；所有所述第二电容支路的第二端和所有所述第三电容支路的第二端均接地。The first capacitor group 21 includes one or more first capacitor branches connected in parallel, each of which includes a first capacitor C21 and a first capacitor switching switch S21 connected thereto; the second capacitor group 22 includes one or more second capacitor branches connected in parallel, each of which includes a second capacitor C22 and a second capacitor switching switch S22 connected thereto; the third capacitor group 23 includes one or more third capacitor branches connected in parallel, each of which includes a third capacitor C23 and a third capacitor switching switch S23 connected thereto. The first end of all the first capacitor branches is connected to the first end of all the second capacitor branches as the first end of the first variable capacitor, thereby being connected to the drain of the third N-type transistor Q13; the second end of all the first capacitor branches is connected to the first end of all the third capacitor branches as the second end of the first variable capacitor, thereby being connected to the input end of the output resistance attenuation network 106; the second end of all the second capacitor branches and the second end of all the third capacitor branches are grounded.
由此，通过控制各个电容支路中的电容切换开关的导通或关断，可以使得第一可变电容器的容值产生变化，进而实现输出匹配网络105的阻抗变化。因此，可以根据所需要的工作频段调节输出匹配网络105的阻抗。Thus, by controlling the on or off of the capacitance switching switches in each capacitance branch, the capacitance of the first variable capacitor can be changed, thereby achieving a change in the impedance of the output matching network 105. Therefore, the impedance of the output matching network 105 can be adjusted according to the required working frequency band.
继续参阅图1，本发明实施例中，所述输入匹配网络101包括第一电感LG、隔直电容CB以及第二可变电容器CGS。所述第一电感LG的第一端连接至所述信号输入端RFin，所述第一电感LG的第二端与所述隔直电容CB的第一端连接，所述隔直电容CB的第二端与所述第二可变电容器CGS的第一端、所述 第一N型晶体管Q11的栅极、所述输入电阻衰减网络1031的第一端连接，所述第二可变电容器CGS的第二端连接至所述第一N型晶体管Q11的源极。可以理解的是，第一电感LG的第一端对应为输入匹配网络101的输入端，与信号输入端RFin连接，隔直电容CB的第二端和第二可变电容器CGS的第一端的连接节点对应为输入匹配网络101的输出端，与所有所述第一N型晶体管Q11的栅极和所述输入电阻衰减网络1031的第一端连接。Continuing to refer to FIG. 1 , in the embodiment of the present invention, the input matching network 101 includes a first inductor LG, a DC blocking capacitor CB, and a second variable capacitor CGS. The first end of the first inductor LG is connected to the signal input terminal RFin, the second end of the first inductor LG is connected to the first end of the DC blocking capacitor CB, the second end of the DC blocking capacitor CB is connected to the first end of the second variable capacitor CGS, the The gate of the first N-type transistor Q11 and the first end of the input resistance attenuation network 1031 are connected, and the second end of the second variable capacitor CGS is connected to the source of the first N-type transistor Q11. It can be understood that the first end of the first inductor LG corresponds to the input end of the input matching network 101, connected to the signal input end RFin, and the connection node of the second end of the DC blocking capacitor CB and the first end of the second variable capacitor CGS corresponds to the output end of the input matching network 101, connected to the gates of all the first N-type transistors Q11 and the first end of the input resistance attenuation network 1031.
第二可变电容器CGS为可切换的栅源电容，其与第一电感LG和隔直电容CB共同谐振在工作频段，由此可以实现输入阻抗匹配的可调谐。The second variable capacitor CGS is a switchable gate-source capacitor, which resonates together with the first inductor LG and the DC blocking capacitor CB in the operating frequency band, thereby achieving tunable input impedance matching.
进一步地，如图3所示，所述第二可变电容器CGS包括多个并联的第四电容支路，每个所述第四电容支路包括相连接的第四电容C24和第四电容切换开关S24。多个所述第四电容支路并联的第一端与所述第一N型晶体管Q11的栅极连接，该并联的第一端也即第二可变电容器CGS的第一端；多个所述第四电容支路并联的第二端与所述第一N型晶体管Q11的源极连接，该并联的第二端也即第二可变电容器CGS的第二端。由此，通过控制各个第四电容支路的电容切换开关S24的导通或关断，可以使得第二可变电容器CGS的容值产生变化，实现输入阻抗匹配的调谐。Further, as shown in FIG3 , the second variable capacitor CGS includes a plurality of fourth capacitor branches connected in parallel, each of which includes a fourth capacitor C24 and a fourth capacitor switching switch S24 connected thereto. The first end of the plurality of fourth capacitor branches connected in parallel is connected to the gate of the first N-type transistor Q11, and the first end of the parallel connection is also the first end of the second variable capacitor CGS; the second end of the plurality of fourth capacitor branches connected in parallel is connected to the source of the first N-type transistor Q11, and the second end of the parallel connection is also the second end of the second variable capacitor CGS. Thus, by controlling the on or off of the capacitor switching switches S24 of each fourth capacitor branch, the capacitance of the second variable capacitor CGS can be changed, and the input impedance matching tuning can be achieved.
参阅图4，本发明实施例中，所述输出电阻衰减网络106包括第一开关S30和第一可变电阻器。Referring to FIG. 4 , in the embodiment of the present invention, the output resistance attenuation network 106 includes a first switch S30 and a first variable resistor.
所述第一开关S30的第一端和所述第一可变电阻器的第一端相连接以作为所述输出电阻衰减网络106的输入端，与所述输出匹配网络105的输出端连接，所述第一开关S30的第二端和所述第一可变电阻器的第二端相连接以作为所述输出电阻衰减网络106的输出端，与所述信号输出端RFout连接。通过调节第一可变电阻器的阻值，可以实现增益衰减程度的调节，从而可提供多档位的增益衰减，且对整体噪声的影响较小。此外，可以通过控制第一开关S30的导通或断开来控制对放大后的信号是否进行衰减，当第一开关S30闭合时，此时经过第三N型晶体管Q13放大后的信号在经过输出匹配网络105后，未进行衰减而是经由第一开关S30直接传输至信号输出端RFout进行输出；当第一开关S30断开时，放大后的信号在经过输出匹配网络105后，经过输出电阻衰减网络106的第一可变电阻器进一步衰减后经信号输出端RFout输出。 The first end of the first switch S30 is connected to the first end of the first variable resistor as the input end of the output resistance attenuation network 106, and is connected to the output end of the output matching network 105. The second end of the first switch S30 is connected to the second end of the first variable resistor as the output end of the output resistance attenuation network 106, and is connected to the signal output end RFout. By adjusting the resistance value of the first variable resistor, the gain attenuation degree can be adjusted, so that multi-level gain attenuation can be provided, and the overall noise has little impact. In addition, whether the amplified signal is attenuated can be controlled by controlling the conduction or disconnection of the first switch S30. When the first switch S30 is closed, the signal amplified by the third N-type transistor Q13 is not attenuated after passing through the output matching network 105, but is directly transmitted to the signal output end RFout through the first switch S30 for output; when the first switch S30 is disconnected, the amplified signal passes through the output matching network 105, and is further attenuated by the first variable resistor of the output resistance attenuation network 106, and then output through the signal output end RFout.
进一步地，所述第一可变电阻器包括第一电阻组31、第二电阻组32以及第三电阻组33。Furthermore, the first variable resistor includes a first resistor group 31 , a second resistor group 32 and a third resistor group 33 .
所述第一电阻组31包括一个或并联的多个第一电阻支路，每个所述第一电阻支路包括相连接的第一电阻R31和第一电阻切换开关S31，所述第二电阻组32包括一个或并联的多个第二电阻支路，每个所述第二电阻支路包括相连接的第二电阻R32和第二电阻切换开关S32，所述第三电阻组33包括一个或并联的多个第三电阻支路，每个所述第三电阻支路包括相连接的第三电阻R33和第三电阻切换开关S33。其中，所有所述第一电阻支路的第一端与所有所述第二电阻支路的第一端相连接以作为所述第一可变电阻器的第一端，所有所述第一电阻支路的第二端与所有所述第三电阻支路的第一端相连接以作为所述第一可变电阻器的第二端，所有所述第二电阻支路的第二端和所有所述第三电阻支路的第二端均接地。由此，通过控制各个电阻支路中的电阻切换开关的导通或关断，可以使得第一可变电阻器的阻值产生变化，进而可以得到不同的***损耗，也即衰减程度。The first resistor group 31 includes one or more first resistor branches in parallel, each of which includes a first resistor R31 and a first resistor switch S31 connected to each other, the second resistor group 32 includes one or more second resistor branches in parallel, each of which includes a second resistor R32 and a second resistor switch S32 connected to each other, and the third resistor group 33 includes one or more third resistor branches in parallel, each of which includes a third resistor R33 and a third resistor switch S33 connected to each other. Wherein, the first end of all the first resistor branches is connected to the first end of all the second resistor branches as the first end of the first variable resistor, the second end of all the first resistor branches is connected to the first end of all the third resistor branches as the second end of the first variable resistor, and the second end of all the second resistor branches and the second end of all the third resistor branches are grounded. Thus, by controlling the conduction or disconnection of the resistor switch in each resistor branch, the resistance value of the first variable resistor can be changed, and then different insertion losses, that is, attenuation degrees, can be obtained.
参阅图5，本发明实施例中，所述输入电阻衰减网络1031包括第二开关S40、第五电容C25以及第二可变电阻器。5 , in the embodiment of the present invention, the input resistance attenuation network 1031 includes a second switch S40 , a fifth capacitor C25 , and a second variable resistor.
所述第二可变电阻器包括第四电阻组41和第五电阻组42，所述第四电阻组41包括一个或多个并联的第四电阻支路，每个所述第四电阻支路包括相连接的第四电阻R41和第四电阻切换开关S41，所述第五电阻组42包括一个或多个并联的第五电阻支路，每个所述第五电阻支路包括相连接的第五电阻R42和第五电阻切换开关S42。The second variable resistor includes a fourth resistor group 41 and a fifth resistor group 42, the fourth resistor group 41 includes one or more fourth resistor branches connected in parallel, each of the fourth resistor branches includes a fourth resistor R41 and a fourth resistor switching switch S41 connected thereto, the fifth resistor group 42 includes one or more fifth resistor branches connected in parallel, each of the fifth resistor branches includes a fifth resistor R42 and a fifth resistor switching switch S42 connected thereto.
所述第二开关S40的第一端与所有所述第四电阻支路的第一端均连接至所述输入匹配网络101的输出端，所述第二开关S40的第二端与所有所述第四电阻支路的第二端、所述第五电容C25的第一端均连接至所述第四N型晶体管Q14的栅极，所述第五电容C25的第二端与所有所述第五电阻支路的第一端连接，所有所述第五电阻支路的第二端均连接至所述源极负反馈单元104的第一端。The first end of the second switch S40 and the first ends of all the fourth resistance branches are connected to the output end of the input matching network 101, the second end of the second switch S40 and the second ends of all the fourth resistance branches and the first end of the fifth capacitor C25 are connected to the gate of the fourth N-type transistor Q14, the second end of the fifth capacitor C25 is connected to the first ends of all the fifth resistance branches, and the second ends of all the fifth resistance branches are connected to the first end of the source negative feedback unit 104.
其中，通过控制第二开关S40的导通或断开可以控制输入电阻衰减网络1031对信号是否进行衰减，当第二开关S40闭合时，信号未被输入电阻衰减网 络1031衰减，而是经过第二开关S40直接传输至第四N型晶体管Q14的栅极，当第二开关S40断开时，信号经过第二可变电阻器时传输至第四N型晶体管Q14的栅极，此时第四N型晶体管Q14的输入信号(即第四N型晶体管的栅源电压)为第二可变电阻器分压后的信号，由此实现信号衰减。其中，可以通过控制各个第四电阻支路和各个第五电阻支路中的电阻切换开关的导通或断开，从而实现第二可变电阻器的阻值变化，进而可以实现对信号不同程度的衰减。By controlling the on or off of the second switch S40, it is possible to control whether the input resistance attenuation network 1031 attenuates the signal. When the second switch S40 is closed, the signal is not attenuated by the input resistance attenuation network 1031. The signal is not attenuated by the network 1031, but is directly transmitted to the gate of the fourth N-type transistor Q14 through the second switch S40. When the second switch S40 is disconnected, the signal is transmitted to the gate of the fourth N-type transistor Q14 through the second variable resistor. At this time, the input signal of the fourth N-type transistor Q14 (i.e., the gate-source voltage of the fourth N-type transistor) is the signal after the second variable resistor divides the voltage, thereby achieving signal attenuation. Among them, the resistance value of the second variable resistor can be changed by controlling the conduction or disconnection of the resistance switching switches in each fourth resistance branch and each fifth resistance branch, thereby achieving different degrees of signal attenuation.
继续参阅图1，本发明实施例中，所述源极负反馈单元104包括第一反馈电感LS1、第二反馈电感LS2、第六晶体管Q16以及第七晶体管Q17。Continuing to refer to FIG. 1 , in the embodiment of the present invention, the source negative feedback unit 104 includes a first feedback inductor LS1 , a second feedback inductor LS2 , a sixth transistor Q16 , and a seventh transistor Q17 .
所述第一反馈电感LS1的第一端作为所述源极负反馈单元104的第一端，与所有所述第一N型晶体管Q11的源极和所述输入电阻衰减网络1031的第二端连接，所述第一反馈电感LS1的第二端与所述第二反馈电感LS2的第一端连接。The first end of the first feedback inductor LS1 serves as the first end of the source negative feedback unit 104 and is connected to the sources of all the first N-type transistors Q11 and the second end of the input resistance attenuation network 1031 . The second end of the first feedback inductor LS1 is connected to the first end of the second feedback inductor LS2 .
本实施例中，所述第六晶体管Q16和所述第七晶体管Q17均为N型晶体管，所述第六晶体管Q16的漏极与所述第一反馈电感LS1的第二端连接，所述第七晶体管Q17的漏极与所述第二反馈电感LS2的第二端连接，所述第六晶体管Q16的栅极和所述第七晶体管Q17的栅极分别用于输入第四控制信号，所述第六晶体管Q16的源极和所述第七晶体管Q17的源极作为所述源极负反馈单元104的第二端接地。In this embodiment, the sixth transistor Q16 and the seventh transistor Q17 are both N-type transistors, the drain of the sixth transistor Q16 is connected to the second end of the first feedback inductor LS1, the drain of the seventh transistor Q17 is connected to the second end of the second feedback inductor LS2, the gate of the sixth transistor Q16 and the gate of the seventh transistor Q17 are respectively used to input the fourth control signal, and the source of the sixth transistor Q16 and the source of the seventh transistor Q17 are grounded as the second end of the source negative feedback unit 104.
本实施例的源极负反馈单元104可以提供两档不同的增益。具体而言，第四控制信号包括高电平和低电平，通过第四控制信号可以分别控制第六晶体管Q16和第七晶体管Q17的导通或断开，以控制第二反馈电感LS2是否接入电路，从而实现增益的调节。其中，当需要低噪声放大器100提供较大增益时，可以控制第七晶体管Q17断开，第六晶体管Q16导通，此时第二反馈电感LS2未接入电路，只有第一反馈电感LS1接入电路，从而可获得较大的增益。当需要低噪声放大器100提供较小增益时，可以控制第七晶体管Q17导通，第六晶体管Q16断开，此时第一反馈电感LS1和第二反馈电感LS2均接入电路，可得的相对较小的增益。此外，源极负反馈单元104同时与共源级放大单元的总跨导以及第二可变电容器CGS共同组成输入阻抗的实部，在调整共源级放大单元和 第二可变电容器CGS时能保证输入阻抗的实部基本保持不变且不随输入匹配的谐振频率的变化而变化。The source negative feedback unit 104 of this embodiment can provide two different gains. Specifically, the fourth control signal includes a high level and a low level. The fourth control signal can control the conduction or disconnection of the sixth transistor Q16 and the seventh transistor Q17 respectively to control whether the second feedback inductor LS2 is connected to the circuit, thereby achieving gain adjustment. Among them, when the low-noise amplifier 100 is required to provide a larger gain, the seventh transistor Q17 can be controlled to be disconnected and the sixth transistor Q16 can be turned on. At this time, the second feedback inductor LS2 is not connected to the circuit, and only the first feedback inductor LS1 is connected to the circuit, so that a larger gain can be obtained. When the low-noise amplifier 100 is required to provide a smaller gain, the seventh transistor Q17 can be controlled to be turned on and the sixth transistor Q16 can be turned off. At this time, the first feedback inductor LS1 and the second feedback inductor LS2 are both connected to the circuit, and a relatively small gain can be obtained. In addition, the source negative feedback unit 104, together with the total transconductance of the common-source stage amplifier unit and the second variable capacitor CGS, constitute the real part of the input impedance. When adjusting the common-source stage amplifier unit and The second variable capacitor CGS can ensure that the real part of the input impedance remains substantially unchanged and does not change with the change of the resonant frequency of the input matching.
进一步地，如图6所示，其中图中的箭头A表示信号从第一反馈电感LS1的第一端输入，所述第一反馈电感LS1和所述第二反馈电感LS2通过电感抽头的方式串联，由此可以减少版图面积。Further, as shown in FIG6 , arrow A in the figure indicates that a signal is input from a first end of the first feedback inductor LS1 , and the first feedback inductor LS1 and the second feedback inductor LS2 are connected in series by way of an inductor tap, thereby reducing the layout area.
在本发明的其他实施例中，如图7所示，所述第六晶体管Q16和所述第七晶体管Q17也可以是P型晶体管，此时所述第六晶体管Q16的漏极与所述第一反馈电感LS的第二端连接，所述第七晶体管Q17的漏极与所述第二反馈电感LS2的第二端连接，所述第六晶体管Q16的栅极和所述第七晶体管Q17的栅极分别用于输入第四控制信号，所述第六晶体管Q16的源极和所述第七晶体管Q17的源极作为所述源极负反馈单元104的第二端连接第一供电电压VDD1。其中，如图8所示，所述第一反馈电感LS1和所述第二反馈电感LS2也可以通过电感抽头的方式串联。In other embodiments of the present invention, as shown in FIG7 , the sixth transistor Q16 and the seventh transistor Q17 may also be P-type transistors, in which case the drain of the sixth transistor Q16 is connected to the second end of the first feedback inductor LS, the drain of the seventh transistor Q17 is connected to the second end of the second feedback inductor LS2, the gate of the sixth transistor Q16 and the gate of the seventh transistor Q17 are respectively used to input the fourth control signal, and the source of the sixth transistor Q16 and the source of the seventh transistor Q17 are connected to the first power supply voltage VDD1 as the second end of the source negative feedback unit 104. As shown in FIG8 , the first feedback inductor LS1 and the second feedback inductor LS2 may also be connected in series by means of an inductor tap.
本文中应用了具体个例对本发明的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本发明的方法及其核心思想；同时，对于本领域的技术人员，依据本发明的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本发明的限制。 Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of the present invention, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as limiting the present invention.

Claims (10)

  1. 一种多频段可调增益的低噪声放大器，其特征在于，包括信号输入端、输入匹配网络、多个共源级放大单元、负增益衰减网络、源级负反馈单元、共栅极驱动放大单元、扼流电感单元、阻抗可调的输出匹配网络、输出电阻衰减网络以及信号输出端；A multi-band adjustable gain low noise amplifier, characterized in that it includes a signal input terminal, an input matching network, a plurality of common source stage amplification units, a negative gain attenuation network, a source stage negative feedback unit, a common gate drive amplification unit, a choke inductor unit, an output matching network with adjustable impedance, an output resistance attenuation network and a signal output terminal;
    每个所述共源级放大单元包括对应连接的第一N型晶体管和第二N型晶体管，所述共栅极驱动放大单元包括第三N型晶体管和稳压电容，所述扼流电感单元包括第一P型晶体管、第二P型晶体管、第一扼流电感和第二扼流电感，所述负增益衰减网络包括输入电阻衰减网络、第四N型晶体管和第五N型晶体管；Each of the common-source amplifier units includes a first N-type transistor and a second N-type transistor connected correspondingly, the common-gate drive amplifier unit includes a third N-type transistor and a voltage-stabilizing capacitor, the choke inductor unit includes a first P-type transistor, a second P-type transistor, a first choke inductor and a second choke inductor, and the negative gain attenuation network includes an input resistance attenuation network, a fourth N-type transistor and a fifth N-type transistor;
    所述输入匹配网络的输入端连接至所述信号输入端，所有所述第一N型晶体管的栅极和所述输入电阻衰减网络的第一端均连接至所述输入匹配网络的输出端，所有所述第一N型晶体管的源极、所述输入电阻衰减网络的第二端以及所述第四N型晶体管的源极均连接至所述源极负反馈单元的第一端，所述源极负反馈单元的第二端接地或连接第一供电电压，各所述第一N型晶体管的漏极与对应的所述第二N型晶体管的源极连接，各所述第二N型晶体管的栅极分别用于输入第一控制信号，所有所述第二N型晶体管的漏极和所述第五N型晶体管的漏极均连接至所述第三N型晶体管的源极，所述第三N型晶体管的栅极通过所述稳压电容接地，所述第四N型晶体管的栅极与所述输入电阻衰减网络的第三端连接，所述第四N型晶体管的漏极与所述第五N型晶体管的源极连接，所述第五N型晶体管的栅极用于输入第二控制信号；The input end of the input matching network is connected to the signal input end, the gates of all the first N-type transistors and the first end of the input resistance attenuation network are connected to the output end of the input matching network, the sources of all the first N-type transistors, the second end of the input resistance attenuation network and the source of the fourth N-type transistor are connected to the first end of the source negative feedback unit, the second end of the source negative feedback unit is grounded or connected to a first power supply voltage, the drain of each of the first N-type transistors is connected to the source of the corresponding second N-type transistor, the gate of each of the second N-type transistors is respectively used to input a first control signal, the drains of all the second N-type transistors and the drain of the fifth N-type transistor are connected to the source of the third N-type transistor, the gate of the third N-type transistor is grounded through the voltage stabilizing capacitor, the gate of the fourth N-type transistor is connected to the third end of the input resistance attenuation network, the drain of the fourth N-type transistor is connected to the source of the fifth N-type transistor, and the gate of the fifth N-type transistor is used to input a second control signal;
    所述第一P型晶体管的源极和所述第二P型晶体管的源极均连接第二供电电压，所述第一P型晶体管的栅极和所述第二P型晶体管的栅极分别用于输入第三控制信号，所述第一P型晶体管的漏极与所述第一扼流电感的第一端连接，所述第一扼流电感的第二端与所述第二P型晶体管的漏极、所述第二扼流电感的第一端连接，所述第二扼流电感的第二端与所述第三N型晶体管的漏极、所述输出匹配网络的输入端连接，所述输出匹配网络的输出端与所述输出电阻衰减网络的输入端连接，所述输出电阻衰减网络的输出端与所述信号输出端连接。The source of the first P-type transistor and the source of the second P-type transistor are both connected to a second power supply voltage, the gate of the first P-type transistor and the gate of the second P-type transistor are respectively used to input a third control signal, the drain of the first P-type transistor is connected to the first end of the first choke inductor, the second end of the first choke inductor is connected to the drain of the second P-type transistor and the first end of the second choke inductor, the second end of the second choke inductor is connected to the drain of the third N-type transistor and the input end of the output matching network, the output end of the output matching network is connected to the input end of the output resistance attenuation network, and the output end of the output resistance attenuation network is connected to the signal output end.
  2. 根据权利要求1所述的低噪声放大器，其特征在于，所述输出匹配网络 包括第一可变电容器；The low noise amplifier according to claim 1, characterized in that the output matching network including a first variable capacitor;
    所述第一可变电容器的第一端为所述输出匹配网络的输入端，与所述第三N型晶体管的漏极连接，所述第一可变电容器的第二端为所述输出匹配网络的输出端，与所述输出电阻衰减网络的输入端连接。The first end of the first variable capacitor is the input end of the output matching network, connected to the drain of the third N-type transistor, and the second end of the first variable capacitor is the output end of the output matching network, connected to the input end of the output resistance attenuation network.
  3. 根据权利要求2所述的低噪声放大器，其特征在于，所述第一可变电容器包括第一电容组、第二电容组以及第三电容组；The low noise amplifier according to claim 2, characterized in that the first variable capacitor includes a first capacitor group, a second capacitor group and a third capacitor group;
    所述第一电容组包括一个或并联的多个第一电容支路，每个所述第一电容支路包括相连接的第一电容和第一电容切换开关，所述第二电容组包括一个或并联的多个第二电容支路，每个所述第二电容支路包括相连接的第二电容和第二电容切换开关，所述第三电容组包括一个或并联的多个第三电容支路，每个所述第三电容支路包括相连接的第三电容和第三电容切换开关；The first capacitor group includes one or a plurality of first capacitor branches connected in parallel, each of the first capacitor branches includes a first capacitor connected to each other and a first capacitor switching switch; the second capacitor group includes one or a plurality of second capacitor branches connected in parallel, each of the second capacitor branches includes a second capacitor connected to each other and a second capacitor switching switch; the third capacitor group includes one or a plurality of third capacitor branches connected in parallel, each of the third capacitor branches includes a third capacitor connected to each other and a third capacitor switching switch;
    其中，所有所述第一电容支路的第一端与所有所述第二电容支路的第一端相连接以作为所述第一可变电容器的第一端，所有所述第一电容支路的第二端与所有所述第三电容支路的第一端相连接以作为所述第一可变电容器的第二端，所有所述第二电容支路的第二端和所有所述第三电容支路的第二端均接地。Among them, the first ends of all the first capacitor branches are connected to the first ends of all the second capacitor branches to serve as the first end of the first variable capacitor, the second ends of all the first capacitor branches are connected to the first ends of all the third capacitor branches to serve as the second end of the first variable capacitor, and the second ends of all the second capacitor branches and the second ends of all the third capacitor branches are grounded.
  4. 根据权利要求1所述的低噪声放大器，其特征在于，所述输入匹配网络包括第一电感、隔直电容以及第二可变电容器；The low noise amplifier according to claim 1, characterized in that the input matching network comprises a first inductor, a DC blocking capacitor and a second variable capacitor;
    所述第一电感的第一端连接至所述信号输入端，所述第一电感的第二端与所述隔直电容的第一端连接，所述隔直电容的第二端与所述第二可变电容的第一端、所述第一N型晶体管的栅极、所述输入电阻衰减网络的第一端连接，所述第二可变电容器的第二端连接至所述第一N型晶体管的源极。The first end of the first inductor is connected to the signal input end, the second end of the first inductor is connected to the first end of the DC blocking capacitor, the second end of the DC blocking capacitor is connected to the first end of the second variable capacitor, the gate of the first N-type transistor, and the first end of the input resistance attenuation network, and the second end of the second variable capacitor is connected to the source of the first N-type transistor.
  5. 根据权利要求4所述的低噪声放大器，其特征在于，所述第二可变电容器包括多个并联的第四电容支路，每个所述第四电容支路包括相连接的第四电容和第四电容切换开关；The low noise amplifier according to claim 4, characterized in that the second variable capacitor comprises a plurality of fourth capacitance branches connected in parallel, and each of the fourth capacitance branches comprises a fourth capacitor and a fourth capacitance switching switch connected thereto;
    多个所述第四电容支路并联的第一端与所述第一N型晶体管的栅极连接，多个所述第四电容支路并联的第二端与所述第一N型晶体管的源极连接。A first end of the plurality of fourth capacitor branches connected in parallel is connected to the gate of the first N-type transistor, and a second end of the plurality of fourth capacitor branches connected in parallel is connected to the source of the first N-type transistor.
  6. 根据权利要求1所述的低噪声放大器，其特征在于，所述输出电阻衰减网络包括第一开关和第一可变电阻器；The low noise amplifier according to claim 1, characterized in that the output resistance attenuation network comprises a first switch and a first variable resistor;
    所述第一开关的第一端和所述第一可变电阻器的第一端相连接以作为所述 输出电阻衰减网络的输入端，与所述输出匹配网络的输出端连接，所述第一开关的第二端和所述第一可变电阻器的第二端相连接以作为所述输出电阻衰减网络的输出端，与所述信号输出端连接。The first end of the first switch is connected to the first end of the first variable resistor to serve as the The input end of the output resistance attenuation network is connected to the output end of the output matching network, and the second end of the first switch and the second end of the first variable resistor are connected to serve as the output end of the output resistance attenuation network, which is connected to the signal output end.
  7. 根据权利要求6所述的低噪声放大器，其特征在于，所述第一可变电阻器包括第一电阻组、第二电阻组以及第三电阻组；The low noise amplifier according to claim 6, characterized in that the first variable resistor includes a first resistor group, a second resistor group and a third resistor group;
    所述第一电阻组包括一个或并联的多个第一电阻支路，每个所述第一电阻支路包括相连接的第一电阻和第一电阻切换开关，所述第二电阻组包括一个或并联的多个第二电阻支路，每个所述第二电阻支路包括相连接的第二电阻和第二电阻切换开关，所述第三电阻组包括一个或并联的多个第三电阻支路，每个所述第三电阻支路包括相连接的第三电阻和第三电阻切换开关；The first resistor group includes one or a plurality of first resistor branches connected in parallel, each of the first resistor branches includes a first resistor connected to each other and a first resistor switching switch; the second resistor group includes one or a plurality of second resistor branches connected in parallel, each of the second resistor branches includes a second resistor connected to each other and a second resistor switching switch; the third resistor group includes one or a plurality of third resistor branches connected in parallel, each of the third resistor branches includes a third resistor connected to each other and a third resistor switching switch;
    其中，所有所述第一电阻支路的第一端与所有所述第二电阻支路的第一端相连接以作为所述第一可变电阻器的第一端，所有所述第一电阻支路的第二端与所有所述第三电阻支路的第一端相连接以作为所述第一可变电阻器的第二端，所有所述第二电阻支路的第二端和所有所述第三电阻支路的第二端均接地。Among them, the first ends of all the first resistance branches are connected to the first ends of all the second resistance branches to serve as the first end of the first variable resistor, the second ends of all the first resistance branches are connected to the first ends of all the third resistance branches to serve as the second end of the first variable resistor, and the second ends of all the second resistance branches and the second ends of all the third resistance branches are grounded.
  8. 根据权利要求1所述的低噪声放大器，其特征在于，所述输入电阻衰减网络包括第二开关、第五电容以及第二可变电阻器；The low noise amplifier according to claim 1, characterized in that the input resistance attenuation network comprises a second switch, a fifth capacitor and a second variable resistor;
    所述第二可变电阻器包括第四电阻组和第五电阻组，所述第四电阻组包括一个或多个并联的第四电阻支路，每个所述第四电阻支路包括相连接的第四电阻和第四电阻切换开关，所述第五电阻组包括一个或多个并联的第五电阻支路，每个所述第五电阻支路包括相连接的第五电阻和第五电阻切换开关；The second variable resistor includes a fourth resistor group and a fifth resistor group, the fourth resistor group includes one or more fourth resistor branches connected in parallel, each of the fourth resistor branches includes a fourth resistor and a fourth resistor switch connected thereto, the fifth resistor group includes one or more fifth resistor branches connected in parallel, each of the fifth resistor branches includes a fifth resistor and a fifth resistor switch connected thereto;
    所述第二开关的第一端与所有所述第四电阻支路的第一端均连接至所述输入匹配网络的输出端，所述第二开关的第二端与所有所述第四电阻支路的第二端、所述第五电容的第一端均连接至所述第四N型晶体管的栅极，所述第五电容的第二端与所有所述第五电阻支路的第一端连接，所有所述第五电阻支路的第二端均连接至所述源极负反馈单元的第一端。The first end of the second switch and the first ends of all the fourth resistance branches are connected to the output end of the input matching network, the second end of the second switch and the second ends of all the fourth resistance branches and the first end of the fifth capacitor are connected to the gate of the fourth N-type transistor, the second end of the fifth capacitor is connected to the first end of all the fifth resistance branches, and the second ends of all the fifth resistance branches are connected to the first end of the source negative feedback unit.
  9. 根据权利要求1所述的低噪声放大器，其特征在于，所述源极负反馈单元包括第一反馈电感、第二反馈电感、第六晶体管以及第七晶体管；The low noise amplifier according to claim 1, characterized in that the source negative feedback unit comprises a first feedback inductor, a second feedback inductor, a sixth transistor and a seventh transistor;
    所述第一反馈电感的第一端作为所述源极负反馈单元的第一端，与所有所述第一N型晶体管的源极和所述输入电阻衰减网络的第二端连接，所述第一反 馈电感的第二端与所述第二反馈电感的第一端连接；The first end of the first feedback inductor serves as the first end of the source negative feedback unit, connected to the sources of all the first N-type transistors and the second end of the input resistance attenuation network. The second end of the feeding inductor is connected to the first end of the second feedback inductor;
    当所述第六晶体管和所述第七晶体管均为N型晶体管时，所述第六晶体管的漏极与所述第一反馈电感的第二端连接，所述第七晶体管的漏极与所述第二反馈电感的第二端连接，所述第六晶体管的栅极和所述第七晶体管的栅极分别用于输入第四控制信号，所述第六晶体管的源极和所述第七晶体管的源极作为所述源极负反馈单元的第二端接地；When the sixth transistor and the seventh transistor are both N-type transistors, the drain of the sixth transistor is connected to the second end of the first feedback inductor, the drain of the seventh transistor is connected to the second end of the second feedback inductor, the gate of the sixth transistor and the gate of the seventh transistor are respectively used to input a fourth control signal, and the source of the sixth transistor and the source of the seventh transistor are grounded as the second end of the source negative feedback unit;
    当所述第六晶体管和所述第七晶体管均为P型晶体管时，所述第六晶体管的漏极与所述第一反馈电感的第二端连接，所述第七晶体管的漏极与所述第二反馈电感的第二端连接，所述第六晶体管的栅极和所述第七晶体管的栅极分别用于输入第四控制信号，所述第六晶体管的源极和所述第七晶体管的源极作为所述源极负反馈单元的第二端连接第一供电电压。When the sixth transistor and the seventh transistor are both P-type transistors, the drain of the sixth transistor is connected to the second end of the first feedback inductor, the drain of the seventh transistor is connected to the second end of the second feedback inductor, the gate of the sixth transistor and the gate of the seventh transistor are respectively used to input a fourth control signal, and the source of the sixth transistor and the source of the seventh transistor are connected to the first supply voltage as the second end of the source negative feedback unit.
  10. 根据权利要求9所述的低噪声放大器，其特征在于，所述第一反馈电感和所述第二反馈电感通过电感抽头的方式串联。 The low noise amplifier according to claim 9, characterized in that the first feedback inductor and the second feedback inductor are connected in series by means of an inductor tap.
PCT/CN2023/109886 2022-09-29 2023-07-28 Multi-band gain-adjustable low noise amplifier WO2024066713A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202211196925.9 2022-09-29
CN202211196925.9A CN115296620B (en) 2022-09-29 2022-09-29 Multi-band adjustable gain low-noise amplifier

Publications (1)

Publication Number Publication Date
WO2024066713A1 true WO2024066713A1 (en) 2024-04-04

Family

ID=83833599

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2023/109886 WO2024066713A1 (en) 2022-09-29 2023-07-28 Multi-band gain-adjustable low noise amplifier

Country Status (2)

Country Link
CN (1) CN115296620B (en)
WO (1) WO2024066713A1 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115296620B (en) * 2022-09-29 2022-12-30 深圳飞骧科技股份有限公司 Multi-band adjustable gain low-noise amplifier
CN116505895B (en) * 2023-03-24 2024-03-19 江苏卓胜微电子股份有限公司 Low noise amplifier with adjustable current and gain
CN116094469B (en) * 2023-04-11 2023-06-30 南京米乐为微电子科技有限公司 Common gate amplifying circuit, low noise amplifier and ultra-wideband receiver
CN117559920B (en) * 2024-01-10 2024-04-09 深圳飞骧科技股份有限公司 Low-noise amplifier and radio frequency chip

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105141263A (en) * 2015-09-29 2015-12-09 株洲宏达天成微波有限公司 Multi-band low-noise amplification method and multi-band low-noise amplifier
US9847765B1 (en) * 2016-08-16 2017-12-19 Raytheon Company Amplifier with automatic gain control
CN109845098A (en) * 2016-08-31 2019-06-04 天工方案公司 Multi input amplifier with degenerated switch block and low-loss bypass functionality
CN109891742A (en) * 2016-08-30 2019-06-14 天工方案公司 Multi input amplifier with Programmable Embedded attenuator
CN115296620A (en) * 2022-09-29 2022-11-04 深圳飞骧科技股份有限公司 Multi-band adjustable gain low-noise amplifier

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1142627C (en) * 2000-01-26 2004-03-17 华为技术有限公司 Stepped attenuation controlling circuit in digital current mode
KR100644273B1 (en) * 2004-12-21 2006-11-10 한국전자통신연구원 Low noise amplifier of wide-band tunable matching
US8577325B2 (en) * 2010-08-31 2013-11-05 Korea Advanced Institute Of Science And Technology Low noise amplifier having both ultra-high linearity and low noise characteristic and radio receiver including the same
CN108322191B (en) * 2018-02-06 2022-03-25 广州慧智微电子股份有限公司 Multi-band low-noise amplifier and amplification method
CN110719074B (en) * 2019-09-23 2023-06-20 航天科工微电子***研究院有限公司 Tunable broadband low noise amplifier
CN111130466A (en) * 2020-01-08 2020-05-08 南京米乐为微电子科技有限公司 Frequency-adjustable broadband low-noise amplifier
CN112003575B (en) * 2020-08-25 2023-01-31 广州慧智微电子股份有限公司 Dual-frequency low-noise amplifier circuit
CN112953405A (en) * 2021-02-04 2021-06-11 江苏卓胜微电子股份有限公司 Gain-adjustable low-noise amplifier
CN114172478A (en) * 2021-12-20 2022-03-11 上海迦美信芯通讯技术有限公司 Low-noise amplifier wide-range high-precision gain control circuit

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105141263A (en) * 2015-09-29 2015-12-09 株洲宏达天成微波有限公司 Multi-band low-noise amplification method and multi-band low-noise amplifier
US9847765B1 (en) * 2016-08-16 2017-12-19 Raytheon Company Amplifier with automatic gain control
CN109891742A (en) * 2016-08-30 2019-06-14 天工方案公司 Multi input amplifier with Programmable Embedded attenuator
CN109845098A (en) * 2016-08-31 2019-06-04 天工方案公司 Multi input amplifier with degenerated switch block and low-loss bypass functionality
CN115296620A (en) * 2022-09-29 2022-11-04 深圳飞骧科技股份有限公司 Multi-band adjustable gain low-noise amplifier

Also Published As

Publication number Publication date
CN115296620B (en) 2022-12-30
CN115296620A (en) 2022-11-04

Similar Documents

Publication Publication Date Title
WO2024066713A1 (en) Multi-band gain-adjustable low noise amplifier
US7420425B2 (en) Power amplifier and method thereof
US6351183B1 (en) Switched amplifying device
US7649418B2 (en) Variable-gain amplifier
US7394313B2 (en) Multiple power mode amplifier with bias modulation option and without bypass switches
US7944291B2 (en) Power amplifier having parallel amplification stages and associated impedance matching networks
KR100704568B1 (en) Variable Gain Low Noise Amplifier
US7688133B2 (en) Power amplifier
KR100758854B1 (en) Low noise amplifier and differential amplifier with variable gain mode
CN107248850B (en) Non-inductance low-power-consumption high-gain high-linearity broadband low-noise amplifier
WO2024055759A1 (en) Low-noise amplifier and radio frequency chip
CN108574464B (en) Low-power-consumption high-linearity dual-mode millimeter wave broadband stacked low-noise amplifier
CN1835390B (en) Low noise amplifier
JP2017098892A (en) Power Amplifier Module
CN111600556A (en) Low noise amplifier and radio frequency receiver
WO2024078155A1 (en) Radio frequency low noise amplifier circuit and radio frequency chip
WO2024055761A1 (en) Multi-band low-noise amplifier and communication device
US8378744B2 (en) Multi-mode power amplifier
US8633771B2 (en) Power amplifier
WO2024099059A1 (en) Passive circuit in bypass mode of radio frequency receiving module, and radio frequency receiving module
CN113422583A (en) Low-noise amplification circuit, radio frequency front-end module and control method
JP2009225342A (en) Variable-gain low noise amplifier
CN112968680A (en) Differential output numerical control double-frequency low-noise amplifier circuit
JPWO2006095416A1 (en) High frequency amplifier with attenuator
US9641130B2 (en) Low noise amplifier with noise and linearity improvement

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 23869959

Country of ref document: EP

Kind code of ref document: A1