WO2024066190A1 - 显示装置、栅极驱动电路、移位寄存单元及其驱动方法 - Google Patents

显示装置、栅极驱动电路、移位寄存单元及其驱动方法 Download PDF

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Publication number
WO2024066190A1
WO2024066190A1 PCT/CN2023/078439 CN2023078439W WO2024066190A1 WO 2024066190 A1 WO2024066190 A1 WO 2024066190A1 CN 2023078439 W CN2023078439 W CN 2023078439W WO 2024066190 A1 WO2024066190 A1 WO 2024066190A1
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Prior art keywords
node
transistor
control
signal terminal
electrode
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PCT/CN2023/078439
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English (en)
French (fr)
Inventor
张竞文
郭永林
曹丹
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202380007932.6A priority Critical patent/CN118235206A/zh
Publication of WO2024066190A1 publication Critical patent/WO2024066190A1/zh

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a display device, a gate driving circuit, a shift register unit and a driving method thereof.
  • the gate drive circuit is an important auxiliary circuit in the Active Matrix Organic Light-Emitting Diode (AMOLED) display.
  • the existing gate drive circuit includes a plurality of cascaded shift register units. However, the gate drive circuit needs to be improved.
  • the present disclosure aims to provide a display device, a gate driving circuit, a shift register unit and a driving method thereof.
  • a shift register unit comprising:
  • An input subcircuit connected to the signal input terminal, the first clock signal terminal and the first node, and used for controlling the signal input terminal to be connected to the first node under the control of the potential of the first clock signal terminal;
  • a first control subcircuit connected to a first power signal terminal, the first clock signal terminal, the first node and a second node, and configured to control the first clock signal terminal to be connected to the second node under the control of the potential of the first node, and further configured to control the first power signal terminal to be connected to the second node under the control of the potential of the first clock signal terminal;
  • the second control subcircuit is connected to the second node, the third node, the fourth node and the second timing a clock signal terminal connected to the first node, for controlling the second clock signal terminal to be connected to the third node under the control of the potential of the second node, and for controlling the third node to be connected to the fourth node under the control of the potential of the second clock signal terminal;
  • a third control subcircuit connected to the first node, the second clock signal terminal and the fifth node, and configured to control the potential of the fifth node according to the potentials of the first node and the second clock signal terminal;
  • An output subcircuit is connected to the first power signal terminal, the second power signal terminal, the fourth node, the fifth node and the signal output terminal, and is used to control the connection between the second power signal terminal and the signal output terminal under the control of the potential of the fourth node, and is also used to control the connection between the first power signal terminal and the signal output terminal under the control of the potential of the fifth node.
  • the third control subcircuit is connected to the first node, the second clock signal terminal, the fifth node and the sixth node, and is used to control the connection between the first node and the sixth node under the control of the potential of the second clock signal terminal, and is also used to control the connection between the first node and the fifth node under the control of the potential of the sixth node.
  • the third control subcircuit includes:
  • a control electrode of the first transistor is connected to the second clock signal terminal, a first electrode of the first transistor is connected to the first node, and a second electrode of the first transistor is connected to the sixth node;
  • a second transistor wherein a control electrode of the second transistor is connected to the sixth node, a first electrode of the second transistor is connected to the first node, and a second electrode of the second transistor is connected to the fifth node.
  • the shift register unit further includes a fourth control subcircuit;
  • the fourth control subcircuit includes a third transistor, a fourth transistor and a first capacitor, the control electrode of the third transistor is connected to the second node, the first electrode of the third transistor is connected to the second power signal terminal, the second electrode of the third transistor is connected to the seventh node; the control electrode of the fourth transistor is connected to the The first node is connected, the first electrode of the fourth transistor is connected to the second clock signal terminal, the second electrode of the fourth transistor is connected to the seventh node; the first capacitor is connected between the first node and the seventh node.
  • the shift register unit also includes a fourth control subcircuit;
  • the fourth control subcircuit includes a fourth transistor and a first capacitor, the control electrode of the fourth transistor is connected to the first node, the first electrode of the fourth transistor is connected to the second clock signal end, and the second electrode of the fourth transistor is connected to the seventh node; the first capacitor is connected between the first node and the seventh node.
  • the shift register unit further includes:
  • the fifth control subcircuit is connected to the fourth node, the fifth node, the eighth node, the first power signal terminal and the second power signal terminal, and is used to control the connection between the fifth node and the eighth node under the control of the potential of the first power signal terminal, and is also used to control the connection between the second power signal terminal and the eighth node under the control of the potential of the fourth node.
  • the fifth control subcircuit includes:
  • a sixteenth transistor wherein a control electrode of the sixteenth transistor is connected to the fourth node, a first electrode of the sixteenth transistor is connected to the second power signal terminal, and a second electrode of the sixteenth transistor is connected to the eighth node;
  • a seventeenth transistor wherein the control electrode of the seventeenth transistor is connected to the first power signal terminal, the first electrode of the seventeenth transistor is connected to the eighth node, and the second electrode of the seventeenth transistor is connected to the fifth node.
  • the input subcircuit comprises:
  • a fifth transistor wherein a control electrode of the fifth transistor is connected to the first clock signal terminal, a first electrode of the fifth transistor is connected to the signal input terminal, and a second electrode of the fifth transistor is connected to the first node.
  • the first control subcircuit includes:
  • a control electrode of the sixth transistor is connected to the first clock signal terminal, a first electrode of the sixth transistor is connected to the first power signal terminal, and a second electrode of the sixth transistor is connected to the second node;
  • a seventh transistor wherein a control electrode of the seventh transistor is connected to the first node, a first electrode of the seventh transistor is connected to the first clock signal terminal, and a second electrode of the seventh transistor is connected to the second node.
  • the output subcircuit comprises:
  • an eighth transistor wherein a control electrode of the eighth transistor is connected to the fourth node, a first electrode of the eighth transistor is connected to the second power signal terminal, and a second electrode of the eighth transistor is connected to the signal output terminal;
  • a ninth transistor wherein a control electrode of the ninth transistor is connected to the fifth node, a first electrode of the ninth transistor is connected to the first power signal terminal, and a second electrode of the ninth transistor is connected to the signal output terminal;
  • the second capacitor is connected between the fourth node and the second power signal terminal.
  • the second control subcircuit includes:
  • a control electrode of the tenth transistor is connected to the second node, a first electrode of the tenth transistor is connected to the second clock signal terminal, and a second electrode of the tenth transistor is connected to the third node;
  • an eleventh transistor wherein a control electrode of the eleventh transistor is connected to the second clock signal terminal, a first electrode of the eleventh transistor is connected to the third node, and a second electrode of the eleventh transistor is connected to the fourth node;
  • the third capacitor is connected between the second node and the third node.
  • the shift register unit further includes:
  • a pull-up sub-circuit the pull-up sub-circuit is connected to the fifth node and the second power signal terminal And the fourth node is connected, used to control the second power signal terminal to be connected to the fourth node under the control of the potential of the fifth node; or, the pull-up sub-circuit is connected to the first node, the second power signal terminal and the fourth node, used to control the second power signal terminal to be connected to the fourth node under the control of the potential of the first node.
  • the shift register unit further includes:
  • a pull-up sub-circuit is connected to the first node, the second power signal terminal and the fourth node, and is used to control the second power signal terminal to be connected to the fourth node under the control of the potential of the first node.
  • the shift register unit further includes:
  • the voltage stabilizing sub-circuit is connected to the fifth node.
  • the voltage stabilizing subcircuit comprises:
  • a voltage-stabilizing capacitor is connected between the fifth node and the signal output terminal.
  • the shift register unit further includes:
  • the anti-flash screen sub-circuit is connected to the first node, the fifth node, the second power signal terminal and the control signal terminal, and is used to control the connection between the first node and the second power signal terminal under the control of the potential of the control signal terminal, and is also used to control the connection between the fifth node and the second power signal terminal under the control of the potential of the control signal terminal.
  • a gate driving circuit comprising a plurality of cascaded shift register units as described above.
  • a display device comprising the above-mentioned gate driving circuit.
  • a driving method of a shift register unit wherein the driving method adopts the above-mentioned shift register unit, and the driving method comprises:
  • the input sub-circuit controls the signal under the control of the potential of the first clock signal terminal.
  • the signal input terminal is connected to the first node;
  • the first control subcircuit controls the first clock signal terminal to be connected to the second node under the control of the potential of the first node, and also controls the first power signal terminal to be connected to the second node under the control of the potential of the first clock signal terminal;
  • the second control subcircuit controls the second clock signal terminal to be connected to the third node under the control of the potential of the second node, and also controls the third node to be connected to the fourth node under the control of the potential of the second clock signal terminal;
  • the output subcircuit controls the second power signal terminal to be connected to the signal output terminal under the control of the potential of the fourth node, and also controls the first power signal terminal to be connected to the signal output terminal under the control of the potential of the fifth node.
  • the display device, gate drive circuit, shift register unit and driving method thereof disclosed in the present invention when the input sub-circuit controls the signal input terminal to be connected to the first node under the control of the potential of the first clock signal terminal, the third control sub-circuit controls the first node to be disconnected from the fifth node according to the potential of the second clock signal terminal, so as to prevent the potential of the signal input terminal from being directly written into the fifth node and avoid the step phenomenon; when the input sub-circuit controls the signal input terminal to be disconnected from the first node under the control of the potential of the first clock signal terminal, the third control sub-circuit controls the first node to be connected to the fifth node according to the potential of the second clock signal terminal, so as to enable the signal output terminal to output normally.
  • FIG. 1 is a circuit diagram of a shift register unit in the related art.
  • 2(a), 2(b), 2(c), 2(d), 2(e) and 2(f) are block diagrams of shift register units according to embodiments of the present disclosure.
  • FIG. 3( a ), FIG. 3( b ), FIG. 3( c ) and FIG. 3( d ) are diagrams of a shift register unit according to an embodiment of the present disclosure. Circuit diagram of the .
  • FIG. 4 is a timing diagram of the operation of the shift register unit according to an embodiment of the present disclosure.
  • FIG5(a) is a schematic diagram of voltages at various nodes of the structure shown in FIG3(a).
  • FIG5(b) is a schematic diagram of voltages at each node of the structure shown in FIG3(c).
  • FIG. 6 is another circuit diagram of the shift register unit according to an embodiment of the present disclosure.
  • FIG. 7 is another circuit diagram of the shift register unit according to an embodiment of the present disclosure.
  • the twelfth transistor T13. the thirteenth transistor; T14. the fourteenth transistor; T15. the fifteenth transistor; T16. the input transistor; T17. the output transistor; T18. the sixteenth transistor; T19. the seventeenth transistor; T20. the eighteenth transistor; T21. the nineteenth transistor; 1. the input sub-circuit; 2. the first control sub-circuit; 3. the second control sub-circuit; 4. the third control sub-circuit; 5. the output sub-circuit; 6. the fourth control sub-circuit; 7. the pull-up sub-circuit; 8. the voltage stabilization sub-circuit; 9. the anti-flash screen sub-circuit; 10. the fifth control sub-circuit.
  • Words such as “include” or “include” mean that the elements or objects appearing in front of “include” or “include” include the elements or objects listed after “include” or “include” and their equivalents, and do not exclude other elements or objects. Words such as “connect” or “connected” are not limited to physical or mechanical connections, and can include electrical connections, whether direct or indirect.
  • the singular forms of “one”, “said” and “the” used in this disclosure and the attached claims are also intended to include plural forms unless the context clearly indicates other meanings. It should also be understood that the term “and/or” used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.
  • the transistors used in the present disclosure can be triodes, thin film transistors or field effect transistors or other devices with the same characteristics.
  • one of the electrodes is called the first electrode and the other is called the second electrode.
  • the control electrode when the transistor is a triode, the control electrode may be a base, the first electrode may be a collector, and the second electrode may be an emitter; or, the control electrode may be a base, the first electrode may be an emitter, and the second electrode may be a collector.
  • the control electrode when the transistor is a thin film transistor or a field effect transistor, the control electrode can be a gate, the first electrode can be a drain, and the second electrode can be a source; or, the control electrode can be a gate, the first electrode can be a source, and the second electrode can be a drain.
  • the shift register unit includes an input transistor T16 and an output transistor T26.
  • Transistor T17 The control electrode of the input transistor T16 is connected to the first clock signal terminal ECK, and the first electrode of the input transistor T16 is connected to the signal input terminal ESTV.
  • the control electrode of the output transistor T17 is connected to the second electrode of the input transistor T16, the first electrode of the output transistor T17 is connected to the first power signal terminal V1, and the second electrode of the output transistor T17 is connected to the signal output terminal EOUT.
  • the signal output by the input transistor T16 will be directly written into the control electrode of the output transistor T17, resulting in the potential of the control electrode of the output transistor T17 being unable to drop to a potential lower than the potential of the first power signal terminal V1, thereby causing the output signal of the signal output terminal EOUT to form a step; in addition, in the process of the shift register unit outputting a valid level, the potential of the control electrode of the output transistor T17 will change, resulting in the output of the output transistor T17 being a floating voltage for half of the time, and the output of the output transistor T17 is easily disturbed during the time period when the output transistor T17 outputs the floating voltage.
  • the shift register unit may include an input subcircuit 1, a first control subcircuit 2, a second control subcircuit 3, a third control subcircuit 4 and an output subcircuit 5, wherein:
  • the input subcircuit 1 is connected to the signal input terminal ESTV, the first clock signal terminal ECK and the first node N1, and is used to control the signal input terminal ESTV to be connected to the first node N1 under the control of the potential of the first clock signal terminal ECK.
  • the first control subcircuit 2 is connected to the first power signal terminal V1, the first clock signal terminal ECK, the first node N1 and the second node N2, and is used to control the first clock signal terminal ECK to be connected to the second node N2 under the control of the potential of the first node N1, and is also used to control the first power signal terminal V1 to be connected to the second node N2 under the control of the potential of the first clock signal terminal ECK.
  • the second control subcircuit 3 is connected to the second node N2, the third node N3, the fourth node N4 and the second clock signal terminal ECB, and is used to control the second clock signal terminal ECB to be connected to the third node N3 under the control of the potential of the second node N2, and is also used to control the third node N3 to be connected to the fourth node N4 under the control of the potential of the second clock signal terminal ECB.
  • the third control subcircuit 4 is connected to the first node N1, the second clock signal terminal ECB and the fifth node N5, and is used to control the potential of the fifth node N5 according to the potentials of the first node N1 and the second clock signal terminal ECB.
  • the third control sub-circuit 4 controls the first node N1 to be disconnected from the fifth node N5 according to the potential of the second clock signal terminal ECB, so as to prevent the potential of the signal input terminal ESTV from being directly written into the fifth node N5, thereby avoiding the step phenomenon;
  • the third control sub-circuit 4 controls the first node N1 to be connected to the fifth node N5 according to the potential of the second clock signal terminal ECB, so as to enable the signal output terminal EOUT to output normally.
  • the input subcircuit 1 is connected to the signal input terminal ESTV, the first clock signal terminal ECK and the first node N1, and is used to control the signal input terminal ESTV to be connected to the first node N1 under the control of the potential of the first clock signal terminal ECK.
  • the input subcircuit 1 may include a fifth transistor T5.
  • the control electrode of the fifth transistor T5 is connected to the first clock signal terminal ECK
  • the first electrode of the fifth transistor T5 is connected to the signal input terminal ESTV
  • the second electrode of the fifth transistor T5 is connected to the first node N1.
  • the first control subcircuit 2 is connected to the first power signal terminal V1, the first clock signal terminal ECK, the first node N1 and the second node N2, and is used to control the first clock signal terminal ECK to be connected to the second node N2 under the control of the potential of the first node N1, and is also used to control the first power signal terminal V1 to be connected to the second node N2 under the control of the potential of the first clock signal terminal ECK.
  • the first control subcircuit 2 may include a sixth transistor T6 and a seventh transistor T7.
  • the control electrode of the sixth transistor T6 is connected to the first clock signal terminal ECK, the first electrode of the sixth transistor T6 is connected to the first power signal terminal V1, and the second electrode of the sixth transistor T6 is connected to the second node N2.
  • the control electrode of the seventh transistor T7 is connected to the first node N1, the first electrode of the seventh transistor T7 is connected to the first clock signal terminal ECK, and the second electrode of the seventh transistor T7 is connected to the second node N2.
  • the first power signal terminal V1 can output a constant low voltage.
  • the second control subcircuit 3 is connected to the second node N2, the third node N3, the fourth node N4 and the second clock signal terminal ECB, and is used to control the second clock signal terminal ECB to be connected to the third node N3 under the control of the potential of the second node N2, and is also used to control the third node N3 to be connected to the fourth node N4 under the control of the potential of the second clock signal terminal ECB.
  • the second control subcircuit 3 may include a tenth transistor T10 and an eleventh transistor T11.
  • the control electrode of the tenth transistor T10 is connected to the second node N2, the first electrode of the tenth transistor T10 is connected to the second clock signal terminal ECB, and the second electrode of the tenth transistor T10 is connected to the third node N3.
  • the control electrode of the eleventh transistor T11 is connected to the second clock signal terminal ECB, the first electrode of the eleventh transistor T11 is connected to the third node N3, and the second electrode of the eleventh transistor T11 is connected to the fourth node N4.
  • the third capacitor C3 may be connected between the second node N2 and the third node N3.
  • the third control subcircuit 4 is connected to the first node N1, the second clock signal terminal ECB and the fifth node N5, and is used to control the potential of the fifth node N5 according to the potentials of the first node N1 and the second clock signal terminal ECB. Further, the third control subcircuit 4 is connected to the first node N1, the second clock signal terminal ECB, the fifth node N5 and the sixth node N6, and is used to control the first node N1 to be connected to the sixth node N6 under the control of the potential of the second clock signal terminal ECB, and is also used to control the first node N1 to be connected to the fifth node N5 under the control of the potential of the sixth node N6.
  • the third control subcircuit 4 includes a first transistor T1 and a second transistor T2.
  • the control electrode of the first transistor T1 is connected to the second clock signal terminal ECB, the first electrode of the first transistor T1 is connected to the first node N1, and the second electrode of the first transistor T1 is connected to the sixth node N6.
  • the control electrode of the second transistor T2 is connected to the sixth node N6, the first electrode of the second transistor T2 is connected to the first node N1, and the second electrode of the second transistor T2 is connected to the fifth node N5.
  • the shift register unit of the present disclosure may further include a fourth control subcircuit 6.
  • the fourth control subcircuit 6 may be connected to the first node N1, the second node N2, the second power signal terminal V2,
  • the seventh node N7 is connected to the second clock signal terminal ECB, and is used to control the second power signal terminal V2 to be connected to the seventh node N7 under the control of the potential of the second node N2, and is also used to control the seventh node N7 to be connected to the second clock signal terminal ECB under the control of the potential of the first node N1.
  • the fourth control subcircuit 6 may include a third transistor T3 and a fourth transistor T4.
  • the control electrode of the third transistor T3 is connected to the second node N2, the first electrode of the third transistor T3 is connected to the second power signal terminal V2, and the second electrode of the third transistor T3 is connected to the seventh node N7.
  • the control electrode of the fourth transistor T4 is connected to the first node N1, the first electrode of the fourth transistor T4 is connected to the second clock signal terminal ECB, and the second electrode of the fourth transistor T4 is connected to the seventh node N7.
  • the fourth control subcircuit 6 may also include a first capacitor C1.
  • the first capacitor C1 is connected between the first node N1 and the seventh node N7.
  • the second power signal terminal V2 can output a constant high voltage.
  • the fourth control subcircuit 6 includes a fourth transistor T4 and a first capacitor C1.
  • the control electrode of the fourth transistor T4 is connected to the first node N1
  • the first electrode of the fourth transistor T4 is connected to the second clock signal terminal ECB
  • the second electrode of the fourth transistor T4 is connected to the seventh node N7
  • the first capacitor C1 is connected between the first node N1 and the seventh node N7.
  • the present disclosure can preserve the potential of the first node N1 and also lower the potential of the first node N1.
  • the shift register unit of the present disclosure may further include a fifth control subcircuit 10.
  • the fifth control subcircuit 10 is connected to the fourth node N4, the fifth node N5, the eighth node N8, the first power signal terminal V1 and the second power signal terminal V2, and is used to control the fifth node N5 to be connected to the eighth node N8 under the control of the potential of the first power signal terminal V1, and is also used to control the second power signal terminal V2 to be connected to the eighth node N8 under the control of the potential of the fourth node N4.
  • the fifth control subcircuit 10 may include a sixteenth transistor T18 and a seventeenth transistor T19.
  • the control electrode of the sixteenth transistor T18 is connected to the fourth node N4, the first electrode of the sixteenth transistor T18 is connected to the second power signal terminal V2, and the second electrode of the sixteenth transistor T18 is connected to the eighth node N8.
  • the control electrode of the seventeenth transistor T19 is connected to the first power signal terminal V1, and the second electrode of the sixteenth transistor T19 is connected to the eighth node N8.
  • a first electrode of the seventeenth transistor T19 is connected to the eighth node N8, and a second electrode of the seventeenth transistor T19 is connected to the fifth node N5.
  • the shift register unit of the present disclosure may further include a pull-up sub-circuit 7.
  • the pull-up sub-circuit 7 is connected to the fifth node N5, the second power signal terminal V2 and the fourth node N4, and is used to control the second power signal terminal V2 to be connected to the fourth node N4 under the control of the potential of the fifth node N5.
  • the pull-up sub-circuit 7 may include a twelfth transistor T12.
  • the control electrode of the twelfth transistor T12 is connected to the fifth node N5, the first electrode of the twelfth transistor T12 is connected to the second power signal terminal V2, and the second electrode of the twelfth transistor T12 is connected to the fourth node N4.
  • the pull-up sub-circuit 7 is connected to the first node N1, the second power signal terminal V2 and the fourth node N4, and is used to control the second power signal terminal V2 to be connected to the fourth node N4 under the control of the potential of the first node N1.
  • the control electrode of the above-mentioned twelfth transistor T12 is connected to the first node N1
  • the first electrode of the twelfth transistor T12 is connected to the second power signal terminal V2
  • the second electrode of the twelfth transistor T12 is connected to the fourth node N4.
  • the output subcircuit 5 is connected to the first power signal terminal V1, the second power signal terminal V2, the fourth node N4, the fifth node N5 and the signal output terminal EOUT, and is used to control the second power signal terminal V2 to be connected to the signal output terminal EOUT under the control of the potential of the fourth node N4, and is also used to control the first power signal terminal V1 to be connected to the signal output terminal EOUT under the control of the potential of the fifth node N5.
  • the output subcircuit 5 may include an eighth transistor T8, a ninth transistor T9 and a second capacitor C2.
  • the control electrode of the eighth transistor T8 is connected to the fourth node N4, the first electrode of the eighth transistor T8 is connected to the second power signal terminal V2, and the second electrode of the eighth transistor T8 is connected to the signal output terminal EOUT.
  • the control electrode of the ninth transistor T9 is connected to the fifth node N5, the first electrode of the ninth transistor T9 is connected to the first power signal terminal V1, and the second electrode of the ninth transistor T9 is connected to the signal output terminal EOUT.
  • the second capacitor C2 is connected between the fourth node N4 and the second power signal terminal V2.
  • the signal output terminal EOUT can be connected to the pixel The light emitting control signal terminal (EM) of the circuit.
  • the shift register unit of the embodiment of the present disclosure may further include a voltage stabilizing subcircuit 8.
  • the voltage stabilizing subcircuit 8 is connected to the fifth node N5.
  • the voltage stabilizing subcircuit 8 may include a voltage stabilizing capacitor C4.
  • the voltage stabilizing capacitor C4 may be connected between the fifth node N5 and the signal output terminal EOUT.
  • the shift register unit of the embodiment of the present disclosure may further include a fifteenth transistor T15.
  • the control electrode of the fifteenth transistor T15 may be connected to the first power supply signal terminal V1, the first electrode of the fifteenth transistor may be connected to the first node N1, and the second electrode of the fifteenth transistor may be connected to the control electrode of the fourth transistor T4.
  • the fifteenth transistor T15 may be a normally-on transistor.
  • the shift register unit of the embodiment of the present disclosure may further include an anti-flash screen subcircuit 9.
  • the anti-flash screen subcircuit 9 is connected to the first node N1, the fifth node N5, the second power signal terminal V2 and the control signal terminal ECX, and is used to control the first node N1 to be connected to the second power signal terminal V2 under the control of the control signal terminal ECX, and is also used to control the fifth node N5 to be connected to the second power signal terminal V2 under the control of the control signal terminal ECX.
  • the anti-flash screen subcircuit 9 may include a thirteenth transistor T13 and a fourteenth transistor T14.
  • the control electrode of the thirteenth transistor T13 is connected to the control signal terminal ECX, the first electrode of the thirteenth transistor is connected to the second power signal terminal V2, and the second electrode of the thirteenth transistor is connected to the first node N1.
  • the control electrode of the fourteenth transistor T14 is connected to the control signal terminal ECX, the first electrode of the fourteenth transistor is connected to the second power signal terminal V2, and the second electrode of the fourteenth transistor is connected to the fifth node N5.
  • the control signal terminal ECX controls the thirteenth transistor T13 and the fourteenth transistor T14 to be turned on, and connects the first node N1 and the fifth node N5 to the second power signal terminal V2 respectively, so as to prevent the occurrence of the screen flashing phenomenon when the power is on; when the shift register unit is working normally, the control signal terminal ECX controls the thirteenth transistor T13 and the fourteenth transistor T14 to be turned off, so as to prevent the thirteenth transistor T13 and the fourteenth transistor T14 from affecting the operation of the shift register unit.
  • the shift register unit may further include an eighteenth transistor T20 and a nineteenth transistor T21.
  • the control electrode of the eighteenth transistor T20 is connected to the first power signal terminal V1, the first electrode of the eighteenth transistor T20 is connected to the second node N2, and the second electrode of the eighteenth transistor T20 is connected to the first power signal terminal V1.
  • the gate of the tenth transistor T10 is connected.
  • the control electrode of the nineteenth transistor T21 is connected to the first power signal terminal V1, the first electrode of the nineteenth transistor T21 is connected to the first node N1, and the second electrode of the nineteenth transistor T21 is connected to the gate of the fourth transistor T4.
  • the eighteenth transistor T20 and the nineteenth transistor T21 can be normally open transistors.
  • the eighteenth transistor T20 and the nineteenth transistor T21 can reduce the source-drain voltage of the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7, thereby reducing the load.
  • the signal input terminal ESTV is high, the first clock signal terminal ECK is low, and the second clock signal terminal ECB is high;
  • the fifth transistor T5 is turned on, the fourth transistor T4 is turned off, the first node N1 is written to VGH, the first transistor T1 is turned off, the sixth node N6 (affected by a certain coupling effect) is floating, the second transistor T2 is partially turned on, the fifth node N5 is increased, and the ninth transistor T9 is turned off;
  • the seventh transistor T7 is turned off, the sixth transistor T6 is turned on, the second node N2 is written to [VGL-Vth(sixth transistor T6)],
  • the third transistor T3 is turned on, the seventh node N7 is written to VGH, the tenth transistor T10 is turned on, the third node N3 is written to VGH, the eleventh transistor T11 is turned off, affected by the fifth node N5, the twelfth transistor T12 is also turned off
  • phase B the signal input terminal ESTV is high, the first clock signal terminal ECK is high, the second clock signal terminal ECB is low, the fifth transistor T5 is turned off, the fourth transistor T4 is turned off, the third transistor T3 is turned on, the first node N1 is floating, the first transistor T1 is turned on, the sixth node N6 is written to VGH, the second transistor T2 is turned off, the fifth node N5 is floating, the ninth transistor T9 is turned off; the sixth transistor T6 is turned off, the seventh transistor T7 is turned off, the tenth transistor T10 is turned on, and the third node N3 is written to VGL-Vth (sixth transistor T6)-Vth (tenth transistor T10).
  • the second node N2 is further reduced to exceed VGL, and the third node N3 is completely VGL is written, the eleventh transistor T11 is turned on, [VGL-Vth(eleventh transistor T11)] is written to the fourth node N4, the eighth transistor T8 is turned on, the ninth transistor T9 is turned off, the signal output terminal EOUT outputs VGH, and the fifth node N5 is further increased to exceed VGH due to the coupling effect of Cgs (capacitance between the gate and source or drain of the transistor) of the ninth transistor T9.
  • the signal input terminal ESTV is high, the first clock signal terminal ECK is low, the second clock signal terminal ECB is high, the fifth transistor T5 is turned on, the first node N1 is written to VGH, the fourth transistor T4 is turned off, the first transistor T1 is turned off, the sixth node N6 is floating (VGH), the fifth node N5 is floating, the ninth transistor T9 is turned off; the sixth transistor T6 is turned on, the seventh transistor T7 is turned off, the second node N2 is written to [VGL-Vth (sixth transistor T6)].
  • the tenth transistor T10 is turned on, the third node N3 is written to VGH, the eleventh transistor T11 is turned off, the twelfth transistor T12 is turned off, the fourth node N4 is floating [VGL-Vth (eleventh transistor T11)], the eighth transistor T8 is turned on, and the signal output terminal EOUT outputs VGH.
  • the signal input terminal ESTV is high, the first clock signal terminal ECK is high, and the second clock signal terminal ECB is low; the fifth transistor T5 is turned off, the first node N1 is floating (VGH), the sixth node N6 is written to VGH, the second transistor T2 is turned off, the fifth node N5 is floating, and the ninth transistor T9 is turned off.
  • the third transistor T3 is turned on, and the fourth transistor T4 is turned off; the sixth transistor T6 is turned off, the seventh transistor T7 is turned off, and the tenth transistor T10 is turned on.
  • the third node N3 is written to VGL-Vth (sixth transistor T6)-Vth (tenth transistor T10).
  • the second node N2 is further reduced to exceed VGL, and the third node N3 is completely written to VGL.
  • the eleventh transistor T11 is turned on, and the fourth node N4 is written to [VGL-Vth (eleventh transistor T11)], the eighth transistor T8 is turned on, and the signal output terminal EOUT outputs VGH.
  • the signal input terminal ESTV is low, the first clock signal terminal ECK is low, and the second clock signal terminal ECB is high;
  • the fifth transistor T5 is turned on, the first node N1 is written with [VGL-Vth(fifth transistor T5)], the first transistor T1 is turned off, the sixth node N6 is floating(VGH), the second transistor T2 is turned off, the fifth node N5 is floating(VH), and the ninth transistor T9 is turned off;
  • the sixth transistor T6 is turned on, the seventh transistor T7 is turned on, and the second node N2 is written with [VGL-Vth(sixth transistor T6)],
  • the fourth transistor T4 is turned on, the third transistor T3 is turned on, and the seventh node N7 is written to VGH;
  • the tenth transistor T10 is turned on, the third node N3 is written to VGH, the eleventh transistor T11 is turned off, the twelfth transistor T12 is turned off, the fourth node N4 floating[VGL-
  • the signal output terminal EOUT outputs VGH. Since the first transistor T1 and the second transistor T2 are introduced between the ninth transistor T9 and the fifth transistor T5 of the present disclosure, the second electrode of the fifth transistor T5 is disconnected from the control electrode of the ninth transistor T9, and the potential of the first node N1 is maintained by the first capacitor C1.
  • the signal input terminal ESTV is low, the first clock signal terminal ECK is high, and the second clock signal terminal ECB is low; the fifth transistor T5 is turned off; the seventh transistor T7 is turned on, the second node N2 is written to VGH, the third transistor T3 is turned off, the fourth transistor T4 is turned on, and the seventh node N7 is written to [VGL-Vth(fifth transistor T5)-Vth(fourth transistor T4)], and due to the coupling effect of the first capacitor C1, the voltage of the first node N1 is further pulled down to exceed VGL, and the seventh node N7 can be completely written to VGL; the first transistor T1 is turned on, the sixth node N6 is written to [VGL-Vth(first transistor T1)], and the fifth node N5 is written to [VGL-Vth(first transistor T4)].
  • the sixth node N6 can also be further reduced to below VGL.
  • the signal input terminal ESTV is low, the first clock signal terminal ECK is low, and the second clock signal terminal ECB is high;
  • the first node N1 is written to approximately [VGL-Vth (fifth transistor T5)], the first transistor T1 is turned off, and the sixth node N6 is affected by the coupling effect of Cgs of the second transistor T2 and rises to a level higher than VGL;
  • the second transistor T2 is not turned on, the fifth node N5 floating (VL, maintaining the low level of the F phase), the ninth transistor T9 is turned on, and the signal output terminal EOUT outputs VGL;
  • the sixth transistor T2 is turned off, and the fifth transistor N5 is turned on.
  • Transistor T6 is turned on, the seventh transistor T7 is turned on, a low level is written to the second node N2, the third transistor T3 is turned on, the fourth transistor T4 is turned on, and VGH is written to the seventh node N7; the tenth transistor T10 is turned on, VGH is written to the third node N3, the eleventh transistor T11 is turned off, the twelfth transistor T12 is turned on, VGH is written to the fourth node N4, and the eighth transistor T8 is turned off.
  • the signal input terminal ESTV is low, the first clock signal terminal ECK is high, and the second clock signal terminal ECB is low; the fifth transistor T5 is turned off; the seventh transistor T7 is turned on, the second node N2 is written to VGH, the third transistor T3 is turned off, the fourth transistor T4 is turned on, and the seventh node N7 is written to (VGL-Vth), and due to the coupling effect of the capacitor of C1, the voltage of the first node N1 is further pulled down to exceed VGL, and the seventh node N7 can be completely written to VGL; the first transistor T1 is turned off, the sixth node N6 is affected by the coupling effect of Cgs of the second transistor T2 and is reduced to below VGL, the second transistor T2 is not turned on, the fifth node N5 is floating (VL, maintaining the low level of the G phase), the ninth transistor T9 is turned on, and VGL is output; the tenth transistor T10 is turned off, the third node N3 is floating (V
  • the fifth node N5 in the process of continuously outputting a low level (effective level), the fifth node N5 is always in a floating state, and the ninth transistor T9 remains in an on state, so as to prevent the output signal of the signal output terminal EOUT from being disturbed. It is worth noting that if the fifth node N5 is disturbed and becomes a high level in the case of continuous output of a low level, firstly, the fourth node N4 maintains VGH and the output signal floating is still VGL, and secondly, in the next H phase, the potentials of the first node N1 and the sixth node N6 are both coupled and lower than VGL, so the fifth node N5 can be reset to a voltage lower than VGL.
  • the difference in the working process of the shift register unit shown in FIG. 3( b ) is that in the E phase, the twelfth transistor T12 is turned on, the fourth node N4 is written to VGH, and the eighth transistor T8 is turned off.
  • the signal input terminal ESTV is high, the first clock signal terminal ECK is low, and the second clock signal terminal ECB is high; the fifth transistor T5 is turned on, and VGH is written to the first node N1; the fourth transistor T4 is turned off, and the seventh node N7 (subject to a certain coupling effect) is floating; the first transistor T1 is turned off, the sixth node N6 (subject to a certain coupling effect) is floating, the second transistor T2 is partially turned on, the fifth node N5 is increased, and the ninth transistor T9 is turned off; the seventh transistor T7 is turned off, the sixth transistor T6 is turned on, the second node N2 is written with [VGL-Vth(sixth transistor T6)], the tenth transistor T10 is turned on, and VGH is written to the third node N3, the eleventh transistor T11 is turned off, the twelfth transistor T12 is turned off, the fourth node N4 is
  • phase B the signal input terminal ESTV is high, the first clock signal terminal ECK is high, the second clock signal terminal ECB is low, the fifth transistor T5 is turned off, the fourth transistor T4 is turned off, the first node N1 is floating, and the seventh node N7 is floating; the first transistor T1 is turned on, the sixth node N6 is written with VGH, and the second transistor T2 is turned off; the sixth transistor T6 is turned off, the seventh transistor T7 is turned off, the second node N2 is floating, the tenth transistor T10 is turned on, and the third node N3 is written with VGL-Vth(sixth transistor T6)-Vth(tenth transistor T10), through the coupling effect of the third capacitor C3, the second node N2 is further reduced to exceed VGL, and the third node N3 is completely written with VGL; the eleventh transistor T11 is turned on, and the fourth node N4 is written with [VGL-Vth(eleventh transistor T11)]; the sixteenth transistor T18 is
  • the fifth node N5 is written with VGH to avoid it being in a floating state and will not be affected by the coupling effect of Cgs (capacitance between the gate and source or drain of the transistor) of the ninth transistor T9.
  • the signal input terminal ESTV is high, the first clock signal terminal ECK is low, the second clock signal terminal ECB is high, the fifth transistor T5 is turned on, the first node N1 is written with VGH, the fourth transistor T4 is turned off, the first transistor T1 is turned off, the sixth node N6 floating (VGH); the sixth transistor T6 is turned on, the seventh transistor T7 is turned off, and the second node N2 is written with [VGL-Vth (sixth transistor The tenth transistor T10 is turned on, the third node N3 is written with VGH, the eleventh transistor T11 is turned off, the twelfth transistor T12 is turned off, the fourth node N4 floating[VGL-Vth(eleventh transistor T11)], the eighth transistor T8 is turned on; the sixteenth transistor T18 is turned on, the seventeenth transistor T19 is turned on, the fifth node N5 is written with VGH, the ninth transistor T9 is turned off, and the signal output terminal EOUT outputs VGH.
  • the signal input terminal ESTV is high, the first clock signal terminal ECK is high, and the second clock signal terminal ECB is low; the fifth transistor T5 is turned off, the first node N1 is floating (VGH), the sixth node N6 is written with VGH, and the second transistor T2 is turned off; the sixth transistor T6 is turned off, the seventh transistor T7 is turned off, the tenth transistor T10 is turned on, and the third node N3 is written with VGL-Vth (sixth transistor T6)-Vth (tenth transistor T10), through the coupling effect of the third capacitor C3, the second node N2 is further reduced to exceed VGL, the third node N3 is completely written with VGL, the eleventh transistor T11 is turned on, the fourth node N4 is written with [VGL-Vth (eleventh transistor T11)], and the eighth transistor T8 is turned on; the sixteenth transistor T18 is turned on, the seventeenth transistor T19 is turned on, the fifth node N5 is written with VGH,
  • the signal input terminal ESTV is low, the first clock signal terminal ECK is low, and the second clock signal terminal ECB is high; the fifth transistor T5 is turned on, and the first node N1 is written with [VGL-Vth(fifth transistor T5)]; the fourth transistor T4 is turned on, and the seventh node N7 is written with VGH; the first transistor T1 is turned off, the sixth node N6 is floating (VGH), and the second transistor T2 is turned off; the sixth transistor T6 is turned on, the seventh transistor T7 is turned on, and the second node N2 is written with [VGL-Vth(sixth transistor T6)]; the tenth transistor T10 is turned on, the third node N3 is written with VGH, the eleventh transistor T11 is turned off, the twelfth transistor T12 is turned on, the fourth node N4 is written with VGH, and the eighth transistor T8 is turned off; the sixteenth transistor T18 is turned off, the seventeenth transistor T19 is turned on,
  • the signal input terminal ESTV is low, the first clock signal terminal ECK is high, and the second clock signal terminal ECB is low; the fifth transistor T5 is turned off, the fourth transistor T4 is turned on, and the seventh node N7 is written with [VGL-Vth(fifth transistor T5)-Vth(fourth transistor T4)], and due to the coupling effect of the first capacitor C1, the voltage of the first node N1 is further pulled down to exceed VGL, and the seventh node N7 can be completely written with VGL; the first transistor T1 is turned on, the sixth node N6 is written with [VGL-Vth(first transistor T1)], and the fifth node N5 is written with [VGL-Vth(first transistor T1)-Vth(second transistor T2)]; the seventh transistor T7 is turned on, the second node N2 is written with VGH, and the tenth transistor T10 is turned off; the twelfth transistor T12 is turned on, and the sixth node N6 is written with [VGL-
  • the signal input terminal ESTV is low, the first clock signal terminal ECK is low, and the second clock signal terminal ECB is high; the first node N1 is coupled to approximately VGL by the fourth transistor T4 and the first capacitor C1, the seventh node N7 is written to VGH, the first transistor T1 is turned off, and the sixth node N6 is affected by the coupling effect of Cgs of the second transistor T2 and rises to above VGL; the sixth transistor T6 is turned on, the seventh transistor T7 is turned on, the second node N2 is written to a low level, the tenth transistor T10 is turned on, the third node N3 is written to VGH, the eleventh transistor T11 is turned off, the twelfth transistor T12 is turned on, the fourth node N4 is written to VGH, and the eighth transistor T8 is turned off; the second transistor T2 is not turned on, the fifth node N5 is floating (VL, maintaining the low level of the F phase), the ninth transistor T9 is turned on, and
  • the signal input terminal ESTV is low, the first clock signal terminal ECK is high, and the second clock signal terminal ECB is low; the fifth transistor T5 is turned off; the seventh transistor T7 is turned on, the second node N2 is written to VGH, the tenth transistor T10 is turned off, the twelfth transistor T12 is turned on, the fourth node N4 is written to VGH, the eighth transistor T8 and the sixteenth transistor T16 are turned off, the eleventh transistor T11 is turned on, and the third node N3 is written to VGH; the fourth transistor T4 is turned on, and the seventh node N7 is written to VGH.
  • the voltage of the first node N1 is further pulled down to exceed VGL due to the coupling effect of the capacitor of C1, and the seventh node N7 can be completely written into VGL; the sixth node N6 is affected by the coupling effect of Cgs of the second transistor T2 and is reduced to below VGL. Since the source voltage and the drain voltage of the first transistor T1 are both lower than the gate voltage, the first transistor T1 is not turned on. Similarly, the second transistor T2 is not turned on.
  • the fifth node N5 is floating (VL, maintaining the low level of the G stage), the ninth transistor T9 is turned on, and the signal output terminal EOUT outputs VGL.
  • the fifth node N5 is always in a floating state. It is worth noting that if the fifth node N5 is disturbed and becomes a high level in the case of continuous low output, firstly, since the first node N1 has a first capacitor C1, it is not easy to be disturbed.
  • the capacitance of the first node N1 is at a relatively low level (about VGL in the G stage and lower than VGL in the H stage), the gate potential of the twelfth transistor T12 is in a relatively stable state, the twelfth transistor T12 is continuously turned on, the voltage of the fourth node N4 can be guaranteed to be VGH, and the eighth transistor T8 is guaranteed to be turned off, then even if the signal output terminal EOUT outputs a floating signal, it is still VGL. ; Secondly, when the second clock signal terminal ECB becomes a low level, the fourth transistor T4 is turned on, and the seventh node N7 is written to (VGL-Vth).
  • the voltage of the first node N1 is further pulled down to exceed VGL, and the seventh node N7 can be completely written to VGL; the sixth node N6 is affected by the coupling effect of Cgs of the second transistor T2 and is reduced to a voltage lower than VGL, that is, the sixth node N6 is reset to a voltage lower than VGL, the second transistor T2 is reopened, the first node N1 is connected to the fifth node N5, and the fifth node N5 is reset to a voltage lower than VGL.
  • the difference in the working process of the shift register unit shown in Figure 3(d) is that: in stage A, the third transistor T3 is turned on and VGH is written to the seventh node N7; in stages B, C, D and E, the third transistor T3 remains on and the seventh node N7 remains VGH; in stage F, the third transistor T3 is turned off; in stage G, the third transistor T3 is turned on; in stage H, the third transistor T3 is turned off.
  • the disclosed embodiment further provides a gate driving circuit, which may include a plurality of cascaded shift register units of any of the above embodiments.
  • the present disclosure also provides a display device, which may include the gate driving circuit of the above embodiment.
  • the embodiment of the present disclosure also provides a driving method of a shift register unit.
  • the driving method adopts the shift register unit of the above embodiment.
  • the driving method may include: enabling the input subcircuit 1 to control the signal input terminal ESTV to be connected to the first node N1 under the control of the potential of the first clock signal terminal ECK; enabling the first control subcircuit 2 to control the first clock signal terminal ECK to be connected to the second node N2 under the control of the potential of the first node N1, and also enabling the first control subcircuit 2 to control the first power signal terminal V1 to be connected to the second node N2 under the control of the potential of the first clock signal terminal ECK; enabling the second control subcircuit 3 to control the second clock signal terminal ECB to be connected to the third node N3 under the control of the potential of the second node N2, and also enabling the second control subcircuit 3 to control the third node N3 to be connected to the fourth node N4 under the control of the potential of the second clock signal terminal
  • the display device, gate driving circuit, shift register unit and driving method thereof provided in the embodiments of the present disclosure belong to the same inventive concept, and the descriptions of relevant details and beneficial effects can be referred to each other and will not be repeated here.

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Abstract

一种显示装置、栅极驱动电路、移位寄存单元及其驱动方法。该移位寄存单元包括输入子电路(1)、第一控制子电路(2)、第二控制子电路(3)、第三控制子电路(4)以及输出子电路(5)。该第三控制子电路(4)与第一节点(N1)、第二时钟信号端(ECB)以及第五节点(N5)连接，用于根据第一节点(N1)以及第二时钟信号端(ECB)的电位控制第五节点(N5)的电位。

Description

显示装置、栅极驱动电路、移位寄存单元及其驱动方法 技术领域
本公开涉及显示技术领域，尤其涉及一种显示装置、栅极驱动电路、移位寄存单元及其驱动方法。
背景技术
栅极驱动电路是有源矩阵有机发光二极体(Active Matrix Organic Light-Emitting Diode，AMOLED)显示中一种重要的辅助电路。现有的栅极驱动电路包括多个级联的移位寄存单元。然而，该栅极驱动电路还有待改进。
发明内容
本公开的目的在于提供一种显示装置、栅极驱动电路、移位寄存单元及其驱动方法。
根据本公开的一个方面，提供一种移位寄存单元，包括：
输入子电路，与信号输入端、第一时钟信号端以及第一节点连接，用于在所述第一时钟信号端的电位的控制下控制所述信号输入端与所述第一节点连接；
第一控制子电路，与第一电源信号端、所述第一时钟信号端、所述第一节点以及第二节点连接，用于在所述第一节点的电位的控制下控制所述第一时钟信号端与所述第二节点连接，还用于在所述第一时钟信号端的电位的控制下控制所述第一电源信号端与所述第二节点连接；
第二控制子电路，与所述第二节点、第三节点、第四节点以及第二时 钟信号端连接，用于在所述第二节点的电位的控制下控制所述第二时钟信号端与所述第三节点连接，还用于在所述第二时钟信号端的电位的控制下控制所述第三节点与所述第四节点连接；
第三控制子电路，与所述第一节点、所述第二时钟信号端以及第五节点连接，用于根据所述第一节点以及所述第二时钟信号端的电位控制所述第五节点的电位；
输出子电路，与所述第一电源信号端、第二电源信号端、所述第四节点、所述第五节点以及信号输出端连接，用于在所述第四节点的电位的控制下控制所述第二电源信号端与所述信号输出端连接，还用于在所述第五节点的电位的控制下控制所述第一电源信号端与所述信号输出端连接。
进一步地，所述第三控制子电路与所述第一节点、所述第二时钟信号端、所述第五节点以及第六节点连接，用于在所述第二时钟信号端的电位的控制下控制所述第一节点与所述第六节点连接，还用于在所述第六节点的电位的控制下控制所述第一节点与所述第五节点连接。
进一步地，所述第三控制子电路包括：
第一晶体管，所述第一晶体管的控制极与所述第二时钟信号端连接，所述第一晶体管的第一极与所述第一节点连接，所述第一晶体管的第二极与所述第六节点连接；
第二晶体管，所述第二晶体管的控制极与所述第六节点连接，所述第二晶体管的第一极与所述第一节点连接，所述第二晶体管的第二极与所述第五节点连接。
进一步地，所述移位寄存单元还包括第四控制子电路；所述第四控制子电路包括第三晶体管、第四晶体管以及第一电容，所述第三晶体管的控制极与所述第二节点连接，所述第三晶体管的第一极与所述第二电源信号端连接，所述第三晶体管的第二极与第七节点连接；所述第四晶体管的控制极与 所述第一节点连接，所述第四晶体管的第一极与所述第二时钟信号端连接，所述第四晶体管的第二极与所述第七节点连接；所述第一电容连接于所述第一节点与所述第七节点之间。
进一步地，所述移位寄存单元还包括第四控制子电路；所述第四控制子电路包括第四晶体管以及第一电容，所述第四晶体管的控制极与所述第一节点连接，所述第四晶体管的第一极与所述第二时钟信号端连接，所述第四晶体管的第二极与第七节点连接；所述第一电容连接于所述第一节点与所述第七节点之间。
进一步地，所述移位寄存单元还包括：
第五控制子电路，与所述第四节点、所述第五节点、第八节点、所述第一电源信号端以及所述第二电源信号端连接，用于在所述第一电源信号端的电位的控制下控制所述第五节点与所述第八节点连接，还用于在所述第四节点的电位的控制下控制所述第二电源信号端与所述第八节点连接。
进一步地，所述第五控制子电路包括：
第十六晶体管，所述第十六晶体管的控制极与所述第四节点连接，所述第十六晶体管的第一极与所述第二电源信号端连接，所述第十六晶体管的第二极与所述第八节点连接；
第十七晶体管，所述第十七晶体管的控制极与所述第一电源信号端连接，所述第十七晶体管的第一极与所述第八节点连接，所述第十七晶体管的第二极与所述第五节点连接。
进一步地，所述输入子电路包括：
第五晶体管，所述第五晶体管的控制极与所述第一时钟信号端连接，所述第五晶体管的第一极与所述信号输入端连接，所述第五晶体管的第二极与所述第一节点连接。
进一步地，所述第一控制子电路包括：
第六晶体管，所述第六晶体管的控制极与所述第一时钟信号端连接，所述第六晶体管的第一极与所述第一电源信号端连接，所述第六晶体管的第二极与所述第二节点连接；
第七晶体管，所述第七晶体管的控制极与所述第一节点连接，所述第七晶体管的第一极与所述第一时钟信号端连接，所述第七晶体管的第二极与所述第二节点连接。
进一步地，所述输出子电路包括：
第八晶体管，所述第八晶体管的控制极与所述第四节点连接，所述第八晶体管的第一极与所述第二电源信号端连接，所述第八晶体管的第二极与所述信号输出端连接；
第九晶体管，所述第九晶体管的控制极与所述第五节点连接，所述第九晶体管的第一极与所述第一电源信号端连接，所述第九晶体管的第二极与所述信号输出端连接；
第二电容，连接于所述第四节点与所述第二电源信号端之间。
进一步地，所述第二控制子电路包括：
第十晶体管，所述第十晶体管的控制极与所述第二节点连接，所述第十晶体管的第一极与所述第二时钟信号端连接，所述第十晶体管的第二极与所述第三节点连接；
第十一晶体管，所述第十一晶体管的控制极与所述第二时钟信号端连接，所述第十一晶体管的第一极与所述第三节点连接，所述第十一晶体管的第二极与所述第四节点连接；
第三电容，连接于所述第二节点与所述第三节点之间。
进一步地，所述移位寄存单元还包括：
上拉子电路，所述上拉子电路与所述第五节点、所述第二电源信号端 以及所述第四节点连接，用于在所述第五节点的电位的控制下控制所述第二电源信号端与所述第四节点连接；或者，所述上拉子电路与所述第一节点、所述第二电源信号端以及所述第四节点连接，用于在所述第一节点的电位的控制下控制所述第二电源信号端与所述第四节点连接。
进一步地，所述移位寄存单元还包括：
上拉子电路，所述上拉子电路与所述第一节点、所述第二电源信号端以及所述第四节点连接，用于在所述第一节点的电位的控制下控制所述第二电源信号端与所述第四节点连接。
进一步地，所述移位寄存单元还包括：
稳压子电路，连接于所述第五节点。
进一步地，所述稳压子电路包括：
稳压电容，连接于所述第五节点与所述信号输出端之间。
进一步地，所述移位寄存单元还包括：
防闪屏子电路，与所述第一节点、所述第五节点、所述第二电源信号端以及所述控制信号端连接，用于在所述控制信号端的电位的控制下控制所述第一节点与所述第二电源信号端连接，还用于在所述控制信号端的电位的控制下控制所述第五节点与所述第二电源信号端连接。
根据本公开的一个方面，提供一种栅极驱动电路，包括多个级联的上述的移位寄存单元。
根据本公开的一个方面，提供一种显示装置，包括上述的栅极驱动电路。
根据本公开的一个方面，提供一种移位寄存单元的驱动方法，所述驱动方法采用上述的移位寄存单元，所述驱动方法包括：
使所述输入子电路在所述第一时钟信号端的电位的控制下控制所述信 号输入端与所述第一节点连接；
使所述第一控制子电路在所述第一节点的电位的控制下控制所述第一时钟信号端与所述第二节点连接，还使所述第一控制子电路在所述第一时钟信号端的电位的控制下控制所述第一电源信号端与所述第二节点连接；
使所述第二控制子电路在所述第二节点的电位的控制下控制所述第二时钟信号端与所述第三节点连接，还使所述第二控制子电路在所述第二时钟信号端的电位的控制下控制所述第三节点与所述第四节点连接；
使所述第三控制子电路根据所述第一节点以及所述第二时钟信号端的电位控制所述第五节点的电位；
使所述输出子电路在所述第四节点的电位的控制下控制所述第二电源信号端与所述信号输出端连接，还使所述输出子电路在所述第五节点的电位的控制下控制所述第一电源信号端与所述信号输出端连接。
本公开的显示装置、栅极驱动电路、移位寄存单元及其驱动方法，当输入子电路在第一时钟信号端的电位的控制下控制信号输入端与第一节点连接时，该第三控制子电路根据第二时钟信号端的电位控制第一节点与第五节点断开，防止信号输入端的电位直接写入第五节点，避免出现台阶现象；当输入子电路在第一时钟信号端的电位的控制下控制信号输入端与第一节点断开时，该第三控制子电路根据第二时钟信号端的电位控制第一节点与第五节点连接，以使信号输出端正常输出。
附图说明
图1是相关技术中移位寄存单元的电路图。
图2(a)、图2(b)、图2(c)、图2(d)、图2(e)以及图2(f)是本公开实施方式的移位寄存单元的框图。
图3(a)、图3(b)、图3(c)以及图3(d)是本公开实施方式的移位寄存单元 的电路图。
图4是本公开实施方式的移位寄存单元的工作时序图。
图5(a)是图3(a)所示结构的各节点电压示意图。
图5(b)是图3(c)所示结构的各节点电压示意图。
图6是本公开实施方式的移位寄存单元的另一电路图。
图7是本公开实施方式的移位寄存单元的又一电路图。
附图标记说明：ESTV、信号输入端；ECK、第一时钟信号端；ECB、第二时钟信号端；V1、第一电源信号端；V2、第二电源信号端；EOUT、信号输出端；ECX、控制信号端；C1、第一电容；C2、第二电容；C3、第三电容；C4、稳压电容；N1、第一节点；N2、第二节点；N3、第三节点；N4、第四节点；N5、第五节点；N6、第六节点；N7、第七节点；T1、第一晶体管；T2、第二晶体管；T3、第三晶体管；T4、第四晶体管；T5、第五晶体管；T6、第六晶体管；T7、第七晶体管；T8、第八晶体管；T9、第九晶体管；T10、第十晶体管；T11、第十一晶体管；T12、第十二晶体管；T13、第十三晶体管；T14、第十四晶体管；T15、第十五晶体管；T16、输入晶体管；T17、输出晶体管；T18、第十六晶体管；T19、第十七晶体管；T20、第十八晶体管；T21、第十九晶体管；1、输入子电路；2、第一控制子电路；3、第二控制子电路；4、第三控制子电路；5、输出子电路；6、第四控制子电路；7、上拉子电路；8、稳压子电路；9、防闪屏子电路；10、第五控制子电路。
具体实施方式
这里将详细地对示例性实施方式进行说明，其示例表示在附图中。下面的描述涉及附图时，除非另有表示，不同附图中的相同数字表示相同或相似的要素。以下示例性实施方式中所描述的实施方式并不代表与本公开相一致的所有实施方式。相反，它们仅是与如所附权利要求书中所详述的、本公 开的一些方面相一致的装置的例子。
在本公开使用的术语是仅仅出于描述特定实施方式的目的，而非旨在限制本公开。除非另作定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开说明书以及权利要求书中使用的“第一”“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”或者“一”等类似词语也不表示数量限制，而是表示存在至少一个。“多个”或者“若干”表示两个及两个以上。“包括”或者“包含”等类似词语意指出现在“包括”或者“包含”前面的元件或者物件涵盖出现在“包括”或者“包含”后面列举的元件或者物件及其等同，并不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而且可以包括电性的连接，不管是直接的还是间接的。在本公开说明书和所附权利要求书中所使用的单数形式的“一种”、“所述”和“该”也旨在包括多数形式，除非上下文清楚地表示其他含义。还应当理解，本文中使用的术语“和/或”是指并包含一个或多个相关联的列出项目的任何或所有可能组合。
本公开中采用的晶体管均可以为三极管、薄膜晶体管或场效应管或其他特性相同的器件。在本公开实施例中，为区分晶体管除控制极之外的两极，将其中一极称为第一极，另一极称为第二极。
在实际操作时，当所述晶体管为三极管时，所述控制极可以为基极，所述第一极可以为集电极，所述第二极可以发射极；或者，所述控制极可以为基极，所述第一极可以为发射极，所述第二极可以集电极。
在实际操作时，当所述晶体管为薄膜晶体管或场效应管时，所述控制极可以为栅极，所述第一极可以为漏极，所述第二极可以为源极；或者，所述控制极可以为栅极，所述第一极可以为源极，所述第二极可以为漏极。
相关技术中，如图1所示，移位寄存单元包括输入晶体管T16和输出 晶体管T17。该输入晶体管T16的控制极与第一时钟信号端ECK连接，输入晶体管T16的第一极与信号输入端ESTV连接。该输出晶体管T17的控制极与输入晶体管T16的第二极连接，该输出晶体管T17的第一极与第一电源信号端V1连接，该输出晶体管T17的第二极与信号输出端EOUT连接。在工作过程中，信号输入端ESTV以及第一时钟信号端ECK均为低电平时，输入晶体管T16输出的信号会直接写入输出晶体管T17的控制极，导致输出晶体管T17的控制极的电位无法下降至比第一电源信号端V1的电位更低的电位，进而导致信号输出端EOUT的输出信号形成台阶；此外，在移位寄存单元输出有效电平的过程中，输出晶体管T17的控制极的电位会发生变化，导致输出晶体管T17的输出有一半时间为floating电压，在输出晶体管T17输出floating电压的时间段，其输出容易被扰动。
为了解决上述问题，本公开实施方式提供一种移位寄存单元。如图2(a)所示，该移位寄存单元可以包括输入子电路1、第一控制子电路2、第二控制子电路3、第三控制子电路4以及输出子电路5，其中：
该输入子电路1与信号输入端ESTV、第一时钟信号端ECK以及第一节点N1连接，用于在第一时钟信号端ECK的电位的控制下控制信号输入端ESTV与第一节点N1连接。该第一控制子电路2与第一电源信号端V1、第一时钟信号端ECK、第一节点N1以及第二节点N2连接，用于在第一节点N1的电位的控制下控制第一时钟信号端ECK与第二节点N2连接，还用于在第一时钟信号端ECK的电位的控制下控制第一电源信号端V1与第二节点N2连接。该第二控制子电路3与第二节点N2、第三节点N3、第四节点N4以及第二时钟信号端ECB连接，用于在第二节点N2的电位的控制下控制第二时钟信号端ECB与第三节点N3连接，还用于在第二时钟信号端ECB的电位的控制下控制第三节点N3与第四节点N4连接。该第三控制子电路4与第一节点N1、第二时钟信号端ECB以及第五节点N5连接，用于根据第一节点N1以及第二时钟信号端ECB的电位控制第五节点N5的电位。该输出子电路5 与第一电源信号端V1、第二电源信号端V2、第四节点N4、第五节点N5以及信号输出端EOUT连接，用于在第四节点N4的电位的控制下控制第二电源信号端V2与信号输出端EOUT连接，还用于在第五节点N5的电位的控制下控制第一电源信号端V1与信号输出端EOUT连接。
本公开实施方式的移位寄存单元，当输入子电路1在第一时钟信号端ECK的电位的控制下控制信号输入端ESTV与第一节点N1连接时，该第三控制子电路4根据第二时钟信号端ECB的电位控制第一节点N1与第五节点N5断开，防止信号输入端ESTV的电位会直接写入第五节点N5，避免出现台阶现象；当输入子电路1在第一时钟信号端ECK的电位的控制下控制信号输入端ESTV与第一节点N1断开时，该第三控制子电路4根据第二时钟信号端ECB的电位控制第一节点N1与第五节点N5连接，以使信号输出端EOUT正常输出。
下面对本公开实施方式的移位寄存单元的各部分进行详细说明：
该输入子电路1与信号输入端ESTV、第一时钟信号端ECK以及第一节点N1连接，用于在第一时钟信号端ECK的电位的控制下控制信号输入端ESTV与第一节点N1连接。举例而言，如图3(a)所示，该输入子电路1可以包括第五晶体管T5。该第五晶体管T5的控制极与第一时钟信号端ECK连接，第五晶体管T5的第一极与信号输入端ESTV连接，第五晶体管T5的第二极与第一节点N1连接。
该第一控制子电路2与第一电源信号端V1、第一时钟信号端ECK、第一节点N1以及第二节点N2连接，用于在第一节点N1的电位的控制下控制第一时钟信号端ECK与第二节点N2连接，还用于在第一时钟信号端ECK的电位的控制下控制第一电源信号端V1与第二节点N2连接。举例而言，如图3(a)所示，该第一控制子电路2可以包括第六晶体管T6和第七晶体管T7。该第六晶体管T6的控制极与第一时钟信号端ECK连接，第六晶体管T6的第一极与第一电源信号端V1连接，第六晶体管T6的第二极与第二节点N2连接。 该第七晶体管T7的控制极与第一节点N1连接，第七晶体管T7的第一极与第一时钟信号端ECK连接，第七晶体管T7的第二极与第二节点N2连接。其中，该第一电源信号端V1能够恒定输出低电压。
该第二控制子电路3与第二节点N2、第三节点N3、第四节点N4以及第二时钟信号端ECB连接，用于在第二节点N2的电位的控制下控制第二时钟信号端ECB与第三节点N3连接，还用于在第二时钟信号端ECB的电位的控制下控制第三节点N3与第四节点N4连接。举例而言，如图3(a)所示，该第二控制子电路3可以包括第十晶体管T10和第十一晶体管T11。该第十晶体管T10的控制极与第二节点N2连接，第十晶体管T10的第一极与第二时钟信号端ECB连接，第十晶体管T10的第二极与第三节点N3连接。该第十一晶体管T11的控制极与第二时钟信号端ECB连接，第十一晶体管T11的第一极与第三节点N3连接，第十一晶体管T11的第二极与第四节点N4连接。该第三电容C3可以连接于第二节点N2与第三节点N3之间。
该第三控制子电路4与第一节点N1、第二时钟信号端ECB以及第五节点N5连接，用于根据第一节点N1以及第二时钟信号端ECB的电位控制第五节点N5的电位。进一步地，该第三控制子电路4与第一节点N1、第二时钟信号端ECB、第五节点N5以及第六节点N6连接，用于在第二时钟信号端ECB的电位的控制下控制第一节点N1与第六节点N6连接，还用于在第六节点N6的电位的控制下控制第一节点N1与第五节点N5连接。举例而言，如图3(a)所示，该第三控制子电路4包括第一晶体管T1和第二晶体管T2。该第一晶体管T1的控制极与第二时钟信号端ECB连接，第一晶体管T1的第一极与第一节点N1连接，第一晶体管T1的第二极与第六节点N6连接。该第二晶体管T2的控制极与第六节点N6连接，第二晶体管T2的第一极与第一节点N1连接，第二晶体管T2的第二极与第五节点N5连接。
如图2(b)所示，本公开的移位寄存单元还可以包括第四控制子电路6。该第四控制子电路6可以与第一节点N1、第二节点N2、第二电源信号端V2、 第七节点N7以及第二时钟信号端ECB连接，用于在第二节点N2的电位的控制下控制第二电源信号端V2与第七节点N7连接，还用于在第一节点N1的电位的控制下控制第七节点N7与第二时钟信号端ECB连接。举例而言，如图3(a)、图3(b)以及图3(d)所示，该第四控制子电路6可以包括第三晶体管T3和第四晶体管T4。该第三晶体管T3的控制极与第二节点N2连接，第三晶体管T3的第一极与第二电源信号端V2连接，第三晶体管T3的第二极与第七节点N7连接。该第四晶体管T4的控制极与第一节点N1连接，第四晶体管T4的第一极与第二时钟信号端ECB连接，第四晶体管T4的第二极与第七节点N7连接。该第四控制子电路6还可以包括第一电容C1。该第一电容C1连接于第一节点N1与第七节点N7之间。其中，该第二电源信号端V2能够恒定输出高电压。
在另一实施方式中，如图2(c)和图3(c)所示，该第四控制子电路6包括第四晶体管T4以及第一电容C1。该第四晶体管T4的控制极与第一节点N1连接，第四晶体管T4的第一极与第二时钟信号端ECB连接，第四晶体管T4的第二极与第七节点N7连接；第一电容C1连接于第一节点N1与第七节点N7之间。其中，通过该第四晶体管T4以及第一电容C1，本公开可以对第一节点N1的电位进行保存，同时也可以拉低第一节点N1电位。
如图2(d)、图3(c)以及图3(d)所示，本公开的移位寄存单元还可以包括第五控制子电路10。该第五控制子电路10与第四节点N4、第五节点N5、第八节点N8、第一电源信号端V1以及第二电源信号端V2连接，用于在第一电源信号端V1的电位的控制下控制第五节点N5与第八节点N8连接，还用于在第四节点N4的电位的控制下控制第二电源信号端V2与第八节点N8连接。举例而言，该第五控制子电路10可以包括第十六晶体管T18和第十七晶体管T19。该第十六晶体管T18的控制极与第四节点N4连接，第十六晶体管T18的第一极与第二电源信号端V2连接，第十六晶体管T18的第二极与第八节点N8连接。该第十七晶体管T19的控制极与第一电源信号端V1连接，第 十七晶体管T19的第一极与第八节点N8连接，第十七晶体管T19的第二极与第五节点N5连接。
如图2(e)和图2(f)所示，本公开的移位寄存单元还可以包括上拉子电路7。如图2(e)和图3(a)所示，该上拉子电路7与第五节点N5、第二电源信号端V2以及第四节点N4连接，用于在第五节点N5的电位的控制下控制第二电源信号端V2与第四节点N4连接。举例而言，该上拉子电路7可以包括第十二晶体管T12。该第十二晶体管T12的控制极与第五节点N5连接，第十二晶体管T12的第一极与第二电源信号端V2连接，第十二晶体管T12的第二极与第四节点N4连接。
在另一实施方式中，如图2(f)、图3(b)以及图3(c)所示，该上拉子电路7与第一节点N1、第二电源信号端V2以及第四节点N4连接，用于在第一节点N1的电位的控制下控制第二电源信号端V2与第四节点N4连接，此时，上述的第十二晶体管T12的控制极与第一节点N1连接，第十二晶体管T12的第一极与第二电源信号端V2连接，第十二晶体管T12的第二极与第四节点N4连接。
如图2(a)所示，该输出子电路5与第一电源信号端V1、第二电源信号端V2、第四节点N4、第五节点N5以及信号输出端EOUT连接，用于在第四节点N4的电位的控制下控制第二电源信号端V2与信号输出端EOUT连接，还用于在第五节点N5的电位的控制下控制第一电源信号端V1与信号输出端EOUT连接。举例而言，如图3(a)所示，该输出子电路5可以包括第八晶体管T8、第九晶体管T9以及第二电容C2。该第八晶体管T8的控制极与第四节点N4连接，第八晶体管T8的第一极与第二电源信号端V2连接，第八晶体管T8的第二极与信号输出端EOUT连接。该第九晶体管T9的控制极与第五节点N5连接，第九晶体管T9的第一极与第一电源信号端V1连接，第九晶体管T9的第二极与信号输出端EOUT连接。该第二电容C2连接于第四节点N4与第二电源信号端V2之间。此外，该信号输出端EOUT可以连接于像素 电路的发光控制信号端(EM)。
如图6所示，本公开实施方式的移位寄存单元还可以包括稳压子电路8。该稳压子电路8连接于第五节点N5。举例而言，该稳压子电路8可以包括稳压电容C4。该稳压电容C4可以连接于第五节点N5与信号输出端EOUT之间。本公开实施方式的移位寄存单元还可以包括第十五晶体管T15。该第十五晶体管T15的控制极可以连接于第一电源信号端V1，十五晶体管的第一极可以连接于第一节点N1，十五晶体管的第二极可以连接于第四晶体管T4的控制极。该第十五晶体管T15可以为常开晶体管。
如图6所示，本公开实施方式的移位寄存单元还可以包括防闪屏子电路9。该防闪屏子电路9与第一节点N1、第五节点N5、第二电源信号端V2以及控制信号端ECX连接，用于在控制信号端ECX的控制下控制第一节点N1与第二电源信号端V2连接，还用于在控制信号端ECX的控制下控制第五节点N5与第二电源信号端V2连接。举例而言，该防闪屏子电路9可以包括第十三晶体管T13和第十四晶体管T14。该第十三晶体管T13的控制极连接于控制信号端ECX，十三晶体管的第一极连接于第二电源信号端V2，十三晶体管的第二极连接于第一节点N1。该第十四晶体管T14的控制极连接于控制信号端ECX，十四晶体管的第一极连接于第二电源信号端V2，十四晶体管的第二极连接于第五节点N5。在移位寄存单元上电时，控制信号端ECX控制第十三晶体管T13以及第十四晶体管T14导通，将第一节点N1和第五节点N5分别与第二电源信号端V2连接，可以防止上电闪屏现象的发生；在移位寄存单元正常工作时，控制信号端ECX控制第十三晶体管T13以及第十四晶体管T14断开，防止第十三晶体管T13和第十四晶体管T14对移位寄存单元的工作造成影响。
如图7所示，该移位寄存单元还可以包括第十八晶体管T20和第十九晶体管T21。该第十八晶体管T20的控制极与第一电源信号端V1连接，第十八晶体管T20的第一极与第二节点N2连接，第十八晶体管T20的第二极与 第十晶体管T10的栅极连接。该第十九晶体管T21的控制极与第一电源信号端V1连接，第十九晶体管T21的第一极与第一节点N1连接，第十九晶体管T21的第二极与第四晶体管T4的栅极连接。其中，该第十八晶体管T20和第十九晶体管T21可以为常开晶体管。所设置的第十八晶体管T20和第十九晶体管T21可以降低第五晶体管T5、第六晶体管T6以及第七晶体管T7的源漏电压，降低负载。
下面结合图4所示的移位寄存单元的工作时序图对图3(a)中的移位寄存单元的工作过程加以详细的说明，以上述所有晶体管均为P型薄膜晶体管为例，所有晶体管的导通电平均为低电平。
如图3(a)、图4以及图5(a)所示，在A阶段，信号输入端ESTV为高，第一时钟信号端ECK为低，第二时钟信号端ECB为高；第五晶体管T5开启，第四晶体管T4关闭，第一节点N1写入VGH，第一晶体管T1关闭，第六节点N6(受到一定耦合作用)浮空(floating)，第二晶体管T2部分开启，第五节点N5有所升高，第九晶体管T9关闭；第七晶体管T7关闭，第六晶体管T6开启，第二节点N2写入[VGL-Vth(第六晶体管T6)]，第三晶体管T3开启，第七节点N7写入VGH，第十晶体管T10开启，第三节点N3写入VGH，第十一晶体管T11关闭，受到第五节点N5的影响，第十二晶体管T12也关闭，第四节点N4 floating(VGH)，第八晶体管T8关闭，信号输出端EOUT输出floating(VGL)。
在B阶段，信号输入端ESTV为高，第一时钟信号端ECK为高，第二时钟信号端ECB为低，第五晶体管T5关闭，第四晶体管T4关闭，第三晶体管T3开启，第一节点N1 floating，第一晶体管T1开启，第六节点N6写入VGH，第二晶体管T2关闭，第五节点N5 floating，第九晶体管T9关闭；第六晶体管T6关闭，第七晶体管T7关闭，第十晶体管T10开启，第三节点N3写入VGL-Vth(第六晶体管T6)-Vth(第十晶体管T10)，通过第三电容C3的耦合(coupling)作用，第二节点N2进一步降低超过VGL，第三节点N3完全 写入VGL，第十一晶体管T11开启，第四节点N4写入[VGL-Vth(第十一晶体管T11)]，第八晶体管T8开启，第九晶体管T9关闭，信号输出端EOUT输出VGH，第五节点N5受第九晶体管T9的Cgs(晶体管的栅极与源极或漏极之间的电容)耦合作用进一步升高超过VGH。
在C阶段，信号输入端ESTV为高，第一时钟信号端ECK为低，第二时钟信号端ECB为高，第五晶体管T5开启，第一节点N1写入VGH，第四晶体管T4关闭，第一晶体管T1关闭，第六节点N6 floating(VGH)，第五节点N5 floating，第九晶体管T9关闭；第六晶体管T6开启，第七晶体管T7关闭，第二节点N2写入[VGL-Vth(第六晶体管T6)]。第十晶体管T10开启，第三节点N3写入VGH，第十一晶体管T11关闭，第十二晶体管T12关闭，第四节点N4 floating[VGL-Vth(第十一晶体管T11)]，第八晶体管T8开启，信号输出端EOUT输出VGH。
在D阶段，信号输入端ESTV为高，第一时钟信号端ECK为高，第二时钟信号端ECB为低；第五晶体管T5关闭，第一节点N1 floating(VGH)，第六节点N6写入VGH，第二晶体管T2关闭，第五节点N5 floating，第九晶体管T9关闭。第三晶体管T3开启，第四晶体管T4关闭；第六晶体管T6关闭，第七晶体管T7关闭，第十晶体管T10开启，第三节点N3写入VGL-Vth(第六晶体管T6)-Vth(第十晶体管T10)，通过第三电容C3的耦合作用，第二节点N2进一步降低超过VGL，第三节点N3完全写入VGL，第十一晶体管T11开启，第四节点N4写入[VGL-Vth(第十一晶体管T11)]，第八晶体管T8开启，信号输出端EOUT输出VGH。
在E阶段，信号输入端ESTV为低，第一时钟信号端ECK为低，第二时钟信号端ECB为高；第五晶体管T5开启，第一节点N1写入[VGL-Vth(第五晶体管T5)]，第一晶体管T1关闭，第六节点N6 floating(VGH)，第二晶体管T2关闭，第五节点N5floating(VH)，第九晶体管T9关闭；第六晶体管T6开启，第七晶体管T7开启，第二节点N2写入[VGL-Vth(第六晶体管T6)]， 第四晶体管T4开启，第三晶体管T3开启，第七节点N7写入VGH；第十晶体管T10开启，第三节点N3写入VGH，第十一晶体管T11关闭，第十二晶体管T12关闭，第四节点N4 floating[VGL-Vth(第十一晶体管T11)]，第八晶体管T8开启。信号输出端EOUT输出VGH。由于本公开的第九晶体管T9与第五晶体管T5之间引入了第一晶体管T1以及第二晶体管T2，从而使第五晶体管T5的第二极与第九晶体管T9的控制极断开，并使第一节点N1的电位由第一电容C1保持。
在F阶段，信号输入端ESTV为低，第一时钟信号端ECK为高，第二时钟信号端ECB为低；第五晶体管T5关闭；第七晶体管T7开启，第二节点N2被写入VGH，第三晶体管T3关闭，第四晶体管T4开启，第七节点N7被写入[VGL-Vth(第五晶体管T5)-Vth(第四晶体管T4)]，又因第一电容C1的耦合作用，第一节点N1电压进一步拉低超过VGL，第七节点N7可完全写入VGL；第一晶体管T1开启，第六节点N6被写入[VGL-Vth(第一晶体管T1)]，第五节点N5被写入[VGL-Vth(第一晶体管T1)-Vth(第二晶体管T2)]，第十晶体管T10关闭，第三节点N3floating(VGH)，第十一晶体管T11以及第十二晶体管T12均开启，第四节点N4写入VGH，第八晶体管T8关闭；第九晶体管T9部分开启，信号输出端EOUT输出[VGL-Vth(第一晶体管T1)-Vth(第二晶体管T2)-Vth(第九晶体管T9)]，因第九晶体管T9的Cgs的耦合作用，进一步拉低第五节点N5至低于VGL，第九晶体管T9可完全开启，信号输出端EOUT输出VGL，不会出现相关技术中的台阶现象。此外，通过第二晶体管T2的Cgs的耦合作用，第六节点N6也得以进一步降低至低于VGL。
在G阶段，信号输入端ESTV为低，第一时钟信号端ECK为低，第二时钟信号端ECB为高；第一节点N1被写入至约为[VGL-Vth(第五晶体管T5)]，第一晶体管T1关闭，第六节点N6受第二晶体管T2的Cgs的耦合作用影响升高至高于VGL；第二晶体管T2不开启，第五节点N5 floating(VL，维持F阶段的低电平)，第九晶体管T9开启，信号输出端EOUT输出VGL；第六 晶体管T6开启，第七晶体管T7开启，第二节点N2写入低电平，第三晶体管T3开启，第四晶体管T4开启，第七节点N7写入VGH；第十晶体管T10开启，第三节点N3写入VGH，第十一晶体管T11关闭，第十二晶体管T12开启，第四节点N4写入VGH，第八晶体管T8关闭。
在H阶段，信号输入端ESTV为低，第一时钟信号端ECK为高，第二时钟信号端ECB为低；第五晶体管T5关闭；第七晶体管T7开启，第二节点N2被写入VGH，第三晶体管T3关闭，第四晶体管T4开启，第七节点N7被写入(VGL-Vth)，又因C1的电容的耦合作用，第一节点N1电压进一步拉低超过VGL，第七节点N7可完全写入VGL；第一晶体管T1关闭，第六节点N6受第二晶体管T2的Cgs的耦合作用影响降低至低于VGL，第二晶体管T2不开启，第五节点N5floating(VL，维持G阶段的低电平)，第九晶体管T9开启，输出VGL；第十晶体管T10关闭，第三节点N3floating(VGH)，第十一晶体管T11以及第十二晶体管T12均开启，第四节点N4写入VGH，第八晶体管T8关闭；信号输出端EOUT输出VGL。
可见连续输出低电平(有效电平)的过程中，第五节点N5始终处于floating状态，第九晶体管T9保持开启状态，避免信号输出端EOUT的输出信号受到扰动。值得注意的是，若在持续输出低的情况下第五节点N5受到扰动变为高电平，首先，第四节点N4维持VGH则输出信号floating仍为VGL，其次，在接下来的H阶段，第一节点N1以及第六节点N6电位均会受到耦合作用而低于VGL，因此，可以将第五节点N5重新置为较VGL更低的电压。
与图3(a)所示的移位寄存单元相比，图3(b)所示的移位寄存单元的工作过程的区别在于：在E阶段，第十二晶体管T12开启，第四节点N4写入VGH，第八晶体管T8关闭。
下面结合图4所示的移位寄存单元的工作时序图对图3(c)中的移位寄存单元的工作过程加以详细的说明，以上述所有晶体管均为P型薄膜晶体管为例，所有晶体管的导通电平均为低电平。
如图3(c)、图4以及图5(b)所示，在A阶段，信号输入端ESTV为高，第一时钟信号端ECK为低，第二时钟信号端ECB为高；第五晶体管T5开启，第一节点N1写入VGH；第四晶体管T4关闭，第七节点N7(受到一定耦合作用)floating；第一晶体管T1关闭，第六节点N6(受到一定耦合作用)floating，第二晶体管T2部分开启，第五节点N5有所升高，第九晶体管T9关闭；第七晶体管T7关闭，第六晶体管T6开启，第二节点N2写入[VGL-Vth(第六晶体管T6)]，第十晶体管T10开启，第三节点N3写入VGH，第十一晶体管T11关闭，第十二晶体管T12关闭，第四节点N4 floating(VGH)，第八晶体管T8关闭，信号输出端EOUT输出floating(VGL)。
在B阶段，信号输入端ESTV为高，第一时钟信号端ECK为高，第二时钟信号端ECB为低，第五晶体管T5关闭，第四晶体管T4关闭，第一节点N1 floating，第七节点N7 floating；第一晶体管T1开启，第六节点N6写入VGH，第二晶体管T2关闭；第六晶体管T6关闭，第七晶体管T7关闭，第二节点N2 floating，第十晶体管T10开启，第三节点N3写入VGL-Vth(第六晶体管T6)-Vth(第十晶体管T10)，通过第三电容C3的耦合(coupling)作用，第二节点N2进一步降低超过VGL，第三节点N3完全写入VGL；第十一晶体管T11开启，第四节点N4写入[VGL-Vth(第十一晶体管T11)]；第十六晶体管T18开启，第十七晶体管T19开启，第五节点N5写入VGH；第九晶体管T9关闭，第八晶体管T8开启，信号输出端EOUT输出VGH。可知，在第十六晶体管T18和第十七晶体管T19的作用下，第五节点N5写入VGH，避免其处于floating状态，且不会受到第九晶体管T9的Cgs(晶体管的栅极与源极或漏极之间的电容)耦合作用的影响。
在C阶段，信号输入端ESTV为高，第一时钟信号端ECK为低，第二时钟信号端ECB为高，第五晶体管T5开启，第一节点N1写入VGH，第四晶体管T4关闭，第一晶体管T1关闭，第六节点N6 floating(VGH)；第六晶体管T6开启，第七晶体管T7关闭，第二节点N2写入[VGL-Vth(第六晶体 管T6)]。第十晶体管T10开启，第三节点N3写入VGH，第十一晶体管T11关闭，第十二晶体管T12关闭，第四节点N4 floating[VGL-Vth(第十一晶体管T11)]，第八晶体管T8开启；第十六晶体管T18开启，第十七晶体管T19开启，第五节点N5写入VGH，第九晶体管T9关闭，信号输出端EOUT输出VGH。
在D阶段，信号输入端ESTV为高，第一时钟信号端ECK为高，第二时钟信号端ECB为低；第五晶体管T5关闭，第一节点N1 floating(VGH)，第六节点N6写入VGH，第二晶体管T2关闭；第六晶体管T6关闭，第七晶体管T7关闭，第十晶体管T10开启，第三节点N3写入VGL-Vth(第六晶体管T6)-Vth(第十晶体管T10)，通过第三电容C3的耦合作用，第二节点N2进一步降低超过VGL，第三节点N3完全写入VGL，第十一晶体管T11开启，第四节点N4写入[VGL-Vth(第十一晶体管T11)]，第八晶体管T8开启；第十六晶体管T18开启，第十七晶体管T19开启，第五节点N5写入VGH，第九晶体管T9关闭，信号输出端EOUT输出VGH。
在E阶段，信号输入端ESTV为低，第一时钟信号端ECK为低，第二时钟信号端ECB为高；第五晶体管T5开启，第一节点N1写入[VGL-Vth(第五晶体管T5)]；第四晶体管T4开启，第七节点N7写入VGH；第一晶体管T1关闭，第六节点N6 floating(VGH)，第二晶体管T2关闭；第六晶体管T6开启，第七晶体管T7开启，第二节点N2写入[VGL-Vth(第六晶体管T6)]；第十晶体管T10开启，第三节点N3写入VGH，第十一晶体管T11关闭，第十二晶体管T12开启，第四节点N4写入VGH，第八晶体管T8关闭；第十六晶体管T18关闭，第十七晶体管T19开启，第五节点N5 floating(VGH)，第九晶体管T9关闭，信号输出端EOUT输出floating(VGH)。本公开的第一节点N1的电位可以由第一电容C1保持。
在F阶段，信号输入端ESTV为低，第一时钟信号端ECK为高，第二时钟信号端ECB为低；第五晶体管T5关闭，第四晶体管T4开启，第七节点 N7被写入[VGL-Vth(第五晶体管T5)-Vth(第四晶体管T4)]，又因第一电容C1的耦合作用，第一节点N1电压进一步拉低超过VGL，第七节点N7可完全写入VGL；第一晶体管T1开启，第六节点N6被写入[VGL-Vth(第一晶体管T1)]，第五节点N5被写入[VGL-Vth(第一晶体管T1)-Vth(第二晶体管T2)]；第七晶体管T7开启，第二节点N2被写入VGH，第十晶体管T10关闭；第十二晶体管T12开启，第四节点N4写入VGH，第十一晶体管T11开启，第三节点N3写入VGH；第八晶体管T8以及第十六晶体管T18均关闭；第九晶体管T9部分开启，信号输出端EOUT输出[VGL-Vth(第一晶体管T1)-Vth(第二晶体管T2)-Vth(第九晶体管T9)]，因第九晶体管T9的Cgs的耦合作用，进一步拉低第五节点N5至低于VGL，第九晶体管T9可完全开启，信号输出端EOUT输出VGL，不会出现相关技术中的台阶现象。此外，通过第二晶体管T2的Cgs的耦合作用，第六节点N6也得以进一步降低至低于VGL。
在G阶段，信号输入端ESTV为低，第一时钟信号端ECK为低，第二时钟信号端ECB为高；第一节点N1被第四晶体管T4和第一电容C1耦合至约为VGL，第七节点N7写入VGH，第一晶体管T1关闭，第六节点N6受第二晶体管T2的Cgs的耦合作用影响升高至高于VGL；第六晶体管T6开启，第七晶体管T7开启，第二节点N2写入低电平，第十晶体管T10开启，第三节点N3写入VGH，第十一晶体管T11关闭，第十二晶体管T12开启，第四节点N4写入VGH，第八晶体管T8关闭；第二晶体管T2不开启，第五节点N5 floating(VL，维持F阶段的低电平)，第九晶体管T9开启，信号输出端EOUT输出VGL。
在H阶段，信号输入端ESTV为低，第一时钟信号端ECK为高，第二时钟信号端ECB为低；第五晶体管T5关闭；第七晶体管T7开启，第二节点N2被写入VGH，第十晶体管T10关闭，第十二晶体管T12开启，第四节点N4写入VGH，第八晶体管T8以及第十六晶体管T16关闭，第十一晶体管T11开启，第三节点N3写入VGH；第四晶体管T4开启，第七节点N7被写 入(VGL-Vth)，又因C1的电容的耦合作用，第一节点N1电压进一步拉低超过VGL，第七节点N7可完全写入VGL；第六节点N6受第二晶体管T2的Cgs的耦合作用影响降低至低于VGL，由于第一晶体管T1的源极电压和漏极电压均低于栅极电压，第一晶体管T1不开启，同理，第二晶体管T2不开启，第五节点N5 floating(VL，维持G阶段的低电平)，第九晶体管T9开启，信号输出端EOUT输出VGL。
可见，在图3(c)所示结构的电路在连续输出低电平(有效电平)的过程中，第五节点N5始终处于floating状态。值得注意的是，若在持续输出低的情况下第五节点N5受到扰动变为高电平，首先，由于第一节点N1有第一电容C1，不易被扰动，在输出为VGL的阶段下，第一节点N1电容均为一个较低的水平(G阶段为约VGL，H阶段低于VGL)，第十二晶体管T12的栅极电位处于较稳定的状态，第十二晶体管T12持续开启，第四节点N4电压可保证为VGH，保证第八晶体管T8关闭，则即使信号输出端EOUT输出信号floating仍为VGL；其次，在第二时钟信号端ECB变为低电平时，第四晶体管T4开启，第七节点N7被写入(VGL-Vth)，又因C1的电容的耦合作用，第一节点N1电压进一步拉低超过VGL，第七节点N7可完全写入VGL；第六节点N6受第二晶体管T2的Cgs的耦合作用影响降低至低于VGL，即将第六节点N6重新置为较VGL更低的电压，第二晶体管T2重新开启，第一节点N1与第五节点N5连通，将第五节点N5重新置为较VGL更低的电压。
与图3(c)所示的移位寄存单元相比，图3(d)所示的移位寄存单元的工作过程的区别在于：在A阶段，第三晶体管T3开启，第七节点N7写入VGH；在B阶段、C、阶段、D阶段以及E阶段，第三晶体管T3均保持开启状态，第七节点N7保持VGH；在F阶段，第三晶体管T3关闭；在G阶段，第三晶体管T3开启；在H阶段，第三晶体管T3关闭。
本公开实施方式还提供一种栅极驱动电路。该栅极驱动电路可以包括多个级联的上述任一实施方式的移位寄存单元。
本公开实施方式还提供一种显示装置。该显示装置可以包括上述实施方式的栅极驱动电路。
本公开实施方式还提供一种移位寄存单元的驱动方法。该驱动方法采用上述实施方式的移位寄存单元。该驱动方法可以包括：使输入子电路1在第一时钟信号端ECK的电位的控制下控制信号输入端ESTV与第一节点N1连接；使第一控制子电路2在第一节点N1的电位的控制下控制第一时钟信号端ECK与第二节点N2连接，还使第一控制子电路2在第一时钟信号端ECK的电位的控制下控制第一电源信号端V1与第二节点N2连接；使第二控制子电路3在第二节点N2的电位的控制下控制第二时钟信号端ECB与第三节点N3连接，还使第二控制子电路3在第二时钟信号端ECB的电位的控制下控制第三节点N3与第四节点N4连接；使第三控制子电路4根据第一节点N1以及第二时钟信号端ECB的电位控制第五节点N5的电位；使输出子电路5在第四节点N4的电位的控制下控制第二电源信号端V2与信号输出端EOUT连接，还使输出子电路5在第五节点N5的电位的控制下控制第一电源信号端V1与信号输出端EOUT连接。
本公开实施方式提供的显示装置、栅极驱动电路、移位寄存单元及其驱动方法属于同一发明构思，相关细节及有益效果的描述可互相参见，不再进行赘述。
以上仅是本公开的较佳实施方式而已，并非对本公开做任何形式上的限制，虽然本公开已以较佳实施方式揭露如上，然而并非用以限定本公开，任何熟悉本专业的技术人员，在不脱离本公开技术方案的范围内，当可利用上述揭示的技术内容做出些许更动或修饰为等同变化的等效实施方式，但凡是未脱离本公开技术方案的内容，依据本公开的技术实质对以上实施方式所作的任何简单修改、等同变化与修饰，均仍属于本公开技术方案的范围内。

Claims (19)

  1. 一种移位寄存单元，其特征在于，包括：
    输入子电路，与信号输入端、第一时钟信号端以及第一节点连接，用于在所述第一时钟信号端的电位的控制下控制所述信号输入端与所述第一节点连接；
    第一控制子电路，与第一电源信号端、所述第一时钟信号端、所述第一节点以及第二节点连接，用于在所述第一节点的电位的控制下控制所述第一时钟信号端与所述第二节点连接，还用于在所述第一时钟信号端的电位的控制下控制所述第一电源信号端与所述第二节点连接；
    第二控制子电路，与所述第二节点、第三节点、第四节点以及第二时钟信号端连接，用于在所述第二节点的电位的控制下控制所述第二时钟信号端与所述第三节点连接，还用于在所述第二时钟信号端的电位的控制下控制所述第三节点与所述第四节点连接；
    第三控制子电路，与所述第一节点、所述第二时钟信号端以及第五节点连接，用于根据所述第一节点以及所述第二时钟信号端的电位控制所述第五节点的电位；
    输出子电路，与所述第一电源信号端、第二电源信号端、所述第四节点、所述第五节点以及信号输出端连接，用于在所述第四节点的电位的控制下控制所述第二电源信号端与所述信号输出端连接，还用于在所述第五节点的电位的控制下控制所述第一电源信号端与所述信号输出端连接。
  2. 根据权利要求1所述的移位寄存单元，其特征在于，所述第三控制子电路与所述第一节点、所述第二时钟信号端、所述第五节点以及第六节点连接，用于在所述第二时钟信号端的电位的控制下控制所述第一节点与所述第六节点连接，还用于在所述第六节点的电位的控制下控制所述第一节点与所述第五节点连接。
  3. 根据权利要求2所述的移位寄存单元，其特征在于，所述第三控制子 电路包括：
    第一晶体管，所述第一晶体管的控制极与所述第二时钟信号端连接，所述第一晶体管的第一极与所述第一节点连接，所述第一晶体管的第二极与所述第六节点连接；
    第二晶体管，所述第二晶体管的控制极与所述第六节点连接，所述第二晶体管的第一极与所述第一节点连接，所述第二晶体管的第二极与所述第五节点连接。
  4. 根据权利要求1-3任一项所述的移位寄存单元，其特征在于，所述移位寄存单元还包括第四控制子电路；所述第四控制子电路包括第三晶体管、第四晶体管以及第一电容，所述第三晶体管的控制极与所述第二节点连接，所述第三晶体管的第一极与所述第二电源信号端连接，所述第三晶体管的第二极与第七节点连接；所述第四晶体管的控制极与所述第一节点连接，所述第四晶体管的第一极与所述第二时钟信号端连接，所述第四晶体管的第二极与所述第七节点连接；所述第一电容连接于所述第一节点与所述第七节点之间。
  5. 根据权利要求1-3任一项所述的移位寄存单元，其特征在于，所述移位寄存单元还包括第四控制子电路；所述第四控制子电路包括第四晶体管以及第一电容，所述第四晶体管的控制极与所述第一节点连接，所述第四晶体管的第一极与所述第二时钟信号端连接，所述第四晶体管的第二极与第七节点连接；所述第一电容连接于所述第一节点与所述第七节点之间。
  6. 根据权利要求1所述的移位寄存单元，其特征在于，所述移位寄存单元还包括：
    第五控制子电路，与所述第四节点、所述第五节点、第八节点、所述第一电源信号端以及所述第二电源信号端连接，用于在所述第一电源信号端的电位的控制下控制所述第五节点与所述第八节点连接，还用于在所述第四节点的电位的控制下控制所述第二电源信号端与所述第八节点连接。
  7. 根据权利要求6所述的移位寄存单元，其特征在于，所述第五控制子 电路包括：
    第十六晶体管，所述第十六晶体管的控制极与所述第四节点连接，所述第十六晶体管的第一极与所述第二电源信号端连接，所述第十六晶体管的第二极与所述第八节点连接；
    第十七晶体管，所述第十七晶体管的控制极与所述第一电源信号端连接，所述第十七晶体管的第一极与所述第八节点连接，所述第十七晶体管的第二极与所述第五节点连接。
  8. 根据权利要求1所述的移位寄存单元，其特征在于，所述输入子电路包括：
    第五晶体管，所述第五晶体管的控制极与所述第一时钟信号端连接，所述第五晶体管的第一极与所述信号输入端连接，所述第五晶体管的第二极与所述第一节点连接。
  9. 根据权利要求8所述的移位寄存单元，其特征在于，所述第一控制子电路包括：
    第六晶体管，所述第六晶体管的控制极与所述第一时钟信号端连接，所述第六晶体管的第一极与所述第一电源信号端连接，所述第六晶体管的第二极与所述第二节点连接；
    第七晶体管，所述第七晶体管的控制极与所述第一节点连接，所述第七晶体管的第一极与所述第一时钟信号端连接，所述第七晶体管的第二极与所述第二节点连接。
  10. 根据权利要求9所述的移位寄存单元，其特征在于，所述输出子电路包括：
    第八晶体管，所述第八晶体管的控制极与所述第四节点连接，所述第八晶体管的第一极与所述第二电源信号端连接，所述第八晶体管的第二极与所述信号输出端连接；
    第九晶体管，所述第九晶体管的控制极与所述第五节点连接，所述第九晶体管的第一极与所述第一电源信号端连接，所述第九晶体管的第二极与所 述信号输出端连接；
    第二电容，连接于所述第四节点与所述第二电源信号端之间。
  11. 根据权利要求10所述的移位寄存单元，其特征在于，所述第二控制子电路包括：
    第十晶体管，所述第十晶体管的控制极与所述第二节点连接，所述第十晶体管的第一极与所述第二时钟信号端连接，所述第十晶体管的第二极与所述第三节点连接；
    第十一晶体管，所述第十一晶体管的控制极与所述第二时钟信号端连接，所述第十一晶体管的第一极与所述第三节点连接，所述第十一晶体管的第二极与所述第四节点连接；
    第三电容，连接于所述第二节点与所述第三节点之间。
  12. 根据权利要求1所述的移位寄存单元，其特征在于，所述移位寄存单元还包括：
    上拉子电路，所述上拉子电路与所述第五节点、所述第二电源信号端以及所述第四节点连接，用于在所述第五节点的电位的控制下控制所述第二电源信号端与所述第四节点连接；或者，所述上拉子电路与所述第一节点、所述第二电源信号端以及所述第四节点连接，用于在所述第一节点的电位的控制下控制所述第二电源信号端与所述第四节点连接。
  13. 根据权利要求6所述的移位寄存单元，其特征在于，所述移位寄存单元还包括：
    上拉子电路，所述上拉子电路与所述第一节点、所述第二电源信号端以及所述第四节点连接，用于在所述第一节点的电位的控制下控制所述第二电源信号端与所述第四节点连接。
  14. 根据权利要求1所述的移位寄存单元，其特征在于，所述移位寄存单元还包括：
    稳压子电路，连接于所述第五节点。
  15. 根据权利要求14所述的移位寄存单元，其特征在于，所述稳压子电 路包括：
    稳压电容，连接于所述第五节点与所述信号输出端之间。
  16. 根据权利要求1所述的移位寄存单元，其特征在于，所述移位寄存单元还包括：
    防闪屏子电路，与所述第一节点、所述第五节点、所述第二电源信号端以及所述控制信号端连接，用于在所述控制信号端的电位的控制下控制所述第一节点与所述第二电源信号端连接，还用于在所述控制信号端的电位的控制下控制所述第五节点与所述第二电源信号端连接。
  17. 一种栅极驱动电路，其特征在于，包括多个级联的权利要求1-16任一项所述的移位寄存单元。
  18. 一种显示装置，其特征在于，包括权利要求17所述的栅极驱动电路。
  19. 一种移位寄存单元的驱动方法，其特征在于，所述驱动方法采用权利要求1-16任一项所述的移位寄存单元，所述驱动方法包括：
    使所述输入子电路在所述第一时钟信号端的电位的控制下控制所述信号输入端与所述第一节点连接；
    使所述第一控制子电路在所述第一节点的电位的控制下控制所述第一时钟信号端与所述第二节点连接，还使所述第一控制子电路在所述第一时钟信号端的电位的控制下控制所述第一电源信号端与所述第二节点连接；
    使所述第二控制子电路在所述第二节点的电位的控制下控制所述第二时钟信号端与所述第三节点连接，还使所述第二控制子电路在所述第二时钟信号端的电位的控制下控制所述第三节点与所述第四节点连接；
    使所述第三控制子电路根据所述第一节点以及所述第二时钟信号端的电位控制所述第五节点的电位；
    使所述输出子电路在所述第四节点的电位的控制下控制所述第二电源信号端与所述信号输出端连接，还使所述输出子电路在所述第五节点的电位的控制下控制所述第一电源信号端与所述信号输出端连接。
PCT/CN2023/078439 2022-09-27 2023-02-27 显示装置、栅极驱动电路、移位寄存单元及其驱动方法 WO2024066190A1 (zh)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107154234A (zh) * 2017-07-20 2017-09-12 京东方科技集团股份有限公司 移位寄存器单元、驱动方法、栅极驱动电路和显示装置
CN109616056A (zh) * 2018-08-24 2019-04-12 京东方科技集团股份有限公司 移位寄存器及其驱动方法、栅极驱动电路和显示装置
CN113362768A (zh) * 2021-06-29 2021-09-07 京东方科技集团股份有限公司 显示装置、栅极驱动电路、移位寄存单元及其驱动方法
CN113724770A (zh) * 2020-02-05 2021-11-30 京东方科技集团股份有限公司 一种移位寄存器及其驱动方法

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CN107154234A (zh) * 2017-07-20 2017-09-12 京东方科技集团股份有限公司 移位寄存器单元、驱动方法、栅极驱动电路和显示装置
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