WO2024060614A1 - 对流过目标电阻器的目标电流进行采样的电路 - Google Patents
对流过目标电阻器的目标电流进行采样的电路 Download PDFInfo
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- WO2024060614A1 WO2024060614A1 PCT/CN2023/090712 CN2023090712W WO2024060614A1 WO 2024060614 A1 WO2024060614 A1 WO 2024060614A1 CN 2023090712 W CN2023090712 W CN 2023090712W WO 2024060614 A1 WO2024060614 A1 WO 2024060614A1
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- voltage
- terminal
- coupled
- operational amplifier
- circuit
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- 238000005070 sampling Methods 0.000 title claims abstract description 166
- 238000002347 injection Methods 0.000 claims abstract description 47
- 239000007924 injection Substances 0.000 claims abstract description 47
- 230000000087 stabilizing effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 12
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 239000000243 solution Substances 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 238000010276 construction Methods 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
- H03M1/1245—Details of sampling arrangements or methods
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
- G01R19/0092—Arrangements for measuring currents or voltages or for indicating presence or sign thereof measuring current only
Definitions
- Embodiments of the present disclosure relate to the field of integrated circuit technology, and in particular, to a circuit that samples a target current flowing through a target resistor.
- a current sampling circuit can be used to indirectly detect the target current value.
- the current sampling circuit can sample the target current value and output the sampling current value, or convert the sampling current into a sampling voltage. Determine the size of the target current value by measuring the output sampling current or sampling voltage.
- Current sampling circuits can be used in circuits such as DC-DC converters. When the inductor current flowing through the inductor in the DC-DC converter is too large, the power tube and freewheeling tube can be controlled to stop charging the inductor. The inductor is allowed to charge again when the inductor current drops to the valley current limit. This can realize the function of overcurrent protection.
- Embodiments described herein provide a circuit for sampling a target current flowing through a target resistor, and a DC-DC converter.
- a circuit for sampling a target current flowing through a target resistor includes: a first resistor, a second resistor, a first operational amplifier, a first offset current injection circuit, a first current sampling circuit, and a sampling voltage output circuit.
- the first terminal of the first resistor is coupled to the first terminal of the target resistor.
- the second terminal of the first resistor is coupled to the first input terminal of the first operational amplifier.
- the first terminal of the second resistor is coupled to the second terminal of the target resistor.
- the second terminal of the second resistor is coupled to the second input terminal of the first operational amplifier.
- the first offset current injection circuit is configured to inject a first offset current into the non-inverting input terminal of the first operational amplifier.
- the first current sampling circuit is coupled to the output terminal and the inverting input terminal of the first operational amplifier, and is configured to generate a sampling current according to the target current and the first offset current.
- the sampling voltage output circuit is configured to generate a sampling voltage according to the sampling current and output the sampling voltage via the sampling voltage output terminal.
- the first output of the first op amp One of the input terminal and the second input terminal is a non-inverting input terminal, and the other is an inverting input terminal.
- the first input terminal of the first operational amplifier is an inverting input terminal.
- the second input terminal of the first operational amplifier is a non-inverting input terminal.
- the first current sampling circuit includes: a first transistor. Wherein, the control electrode of the first transistor is coupled to the output terminal of the first operational amplifier. The first pole of the first transistor is coupled to the inverting input terminal of the first operational amplifier. The second pole of the first transistor is coupled to the sampling voltage output terminal.
- the first input terminal of the first operational amplifier is an inverting input terminal.
- the second input terminal of the first operational amplifier is a non-inverting input terminal.
- the first current sampling circuit includes: a first transistor and a voltage regulator diode. Among them, the control electrode of the first transistor is coupled to the output terminal of the first operational amplifier. The first electrode of the first transistor is coupled to the inverting input terminal of the first operational amplifier. The second electrode of the first transistor is coupled to the sampling voltage output terminal. The anode of the voltage regulator diode is coupled to the second voltage terminal. The cathode of the voltage regulator diode is coupled to the second electrode of the first transistor.
- the first input terminal of the first operational amplifier is a non-inverting input terminal.
- the second input terminal of the first operational amplifier is an inverting input terminal.
- the first current sampling circuit includes: a second transistor, a third transistor, and a fourth transistor.
- the control electrode of the second transistor is coupled to the output terminal of the first operational amplifier.
- the first pole of the second transistor is coupled to the inverting input terminal of the first operational amplifier.
- the second electrode of the second transistor is coupled to the control electrode and the second electrode of the third transistor.
- the first pole of the third transistor is coupled to the first voltage terminal.
- the control electrode of the fourth transistor is coupled to the control electrode of the third transistor.
- the first pole of the fourth transistor is coupled to the first voltage terminal.
- the second pole of the fourth transistor is coupled to the sampling voltage output terminal.
- the circuit further includes: a second operational amplifier, a second offset current injection circuit, a second current sampling circuit, a voltage judgment circuit, a first operational amplifier selection circuit, and a second operational amplifier selection circuit.
- the voltage judgment circuit is configured to generate the first selection signal and the second selection signal according to the voltage at one end of the target resistor and the reference voltage from the reference voltage end.
- the first operational amplifier selection circuit is configured to: disconnect the first offset current injection circuit from the first operational amplifier and disconnect the first current sampling circuit from the sampling voltage output when the first selection signal is at an inactive level. Connection of the circuit; when the first selection signal is at a valid level, control the second operational amplifier and the second current sampling circuit to stop working.
- the second operational amplifier selection circuit is configured to: when the second selection signal is at an active level, the second offset current injection circuit is coupled to the non-inverting input terminal of the second operational amplifier, so that the first input of the second operational amplifier The terminal is coupled to the second terminal of the first resistor, so that the second input terminal of the second operational amplifier is coupled to the second terminal of the second resistor.
- the second offset current injection circuit is configured to generate a second offset current.
- the second current sampling circuit is coupled to the output terminal and the inverting input terminal of the second operational amplifier, and is configured to generate a sampling current according to the target current and the second offset current.
- the first input terminal of the second operational amplifier is a non-inverting input terminal.
- the second input terminal of the second operational amplifier is the inverting input terminal.
- the second current sampling circuit includes: a second transistor, a third transistor, and a fourth transistor. That , the control electrode of the second transistor is coupled to the output terminal of the second operational amplifier.
- the first pole of the second transistor is coupled to the inverting input terminal of the second operational amplifier.
- the second electrode of the second transistor is coupled to the control electrode and the second electrode of the third transistor.
- the first pole of the third transistor is coupled to the first voltage terminal.
- the control electrode of the fourth transistor is coupled to the control electrode of the third transistor.
- the first pole of the fourth transistor is coupled to the first voltage terminal.
- the second pole of the fourth transistor is coupled to the sampling voltage output terminal.
- the voltage judgment circuit includes: a voltage comparator and an inverter.
- the first input terminal of the voltage comparator is coupled to one terminal of the target resistor.
- the second input terminal of the voltage comparator is coupled to the reference voltage terminal.
- the output terminal of the voltage comparator is coupled to the input terminal of the inverter.
- the first selection signal is output from the output terminal of the voltage comparator.
- the second selection signal is output from the output terminal of the inverter.
- the first operational amplifier selection circuit includes: first to fifth voltage-controlled switches.
- the controlled terminal of the first voltage-controlled switch is provided with the first selection signal.
- the first terminal of the first voltage-controlled switch is coupled to the second terminal of the second resistor.
- the second terminal of the first voltage-controlled switch is coupled to the output terminal of the first offset current injection circuit.
- the controlled terminal of the second voltage-controlled switch is provided with the first selection signal.
- the first terminal of the second voltage-controlled switch is coupled to the output terminal of the first current sampling circuit.
- the second terminal of the second voltage-controlled switch is coupled to the sampling voltage output terminal.
- the controlled terminal of the third voltage-controlled switch is provided with the first selection signal.
- the first terminal of the third voltage-controlled switch is coupled to the first input terminal of the second operational amplifier.
- the second terminal of the third voltage-controlled switch is coupled to the second voltage terminal.
- the controlled terminal of the fourth voltage-controlled switch is provided with the first selection signal.
- the first terminal of the fourth voltage-controlled switch is coupled to the second input terminal of the second operational amplifier.
- the second terminal of the fourth voltage-controlled switch is coupled to the second voltage terminal.
- the controlled terminal of the fifth voltage-controlled switch is provided with the first selection signal.
- the first terminal of the fifth voltage-controlled switch is coupled to the output terminal of the second operational amplifier.
- the second terminal of the fifth voltage-controlled switch is coupled to the second voltage terminal.
- the second operational amplifier selection circuit includes: a sixth voltage-controlled switch, a seventh voltage-controlled switch, and an eighth voltage-controlled switch.
- the controlled terminal of the sixth voltage-controlled switch is provided with the second selection signal.
- the first terminal of the sixth voltage-controlled switch is coupled to the second terminal of the first resistor.
- the second terminal of the sixth voltage-controlled switch is coupled to the first input terminal of the second operational amplifier.
- the controlled end of the seventh voltage-controlled switch is provided with a second selection signal.
- the first terminal of the seventh voltage-controlled switch is coupled to the second terminal of the second resistor.
- the second terminal of the seventh voltage-controlled switch is coupled to the second input terminal of the second operational amplifier.
- the controlled end of the eighth voltage-controlled switch is provided with a second selection signal.
- the first terminal of the eighth voltage-controlled switch is coupled to the output terminal of the second offset current injection circuit.
- the second terminal of the eighth voltage-controlled switch is coupled to the non-inverting input terminal of the second operational amplifier.
- a circuit for sampling a target current flowing through a target resistor includes: a first resistor, a second resistor, a third resistor, a first operational amplifier, a second operational amplifier, first to fourth transistors, a first current source, a second current source, and a voltage comparator. , an inverter, and first to eighth voltage-controlled switches.
- the first terminal of the first resistor is coupled to the first terminal of the target resistor.
- the second terminal of the first resistor is coupled to the inverting input terminal of the first operational amplifier.
- the first terminal of the second resistor is coupled to the second terminal of the target resistor.
- the second terminal of the second resistor is coupled Connect to the non-inverting input of the first op amp.
- the first input terminal of the voltage comparator is coupled to one terminal of the target resistor.
- the second input terminal of the voltage comparator is coupled to the reference voltage terminal.
- the output terminal of the voltage comparator is coupled to the input terminal of the inverter.
- the controlled terminal of the first voltage-controlled switch is coupled to the output terminal of the voltage comparator.
- the first terminal of the first voltage-controlled switch is coupled to the second terminal of the second resistor.
- the second terminal of the first voltage-controlled switch is coupled to the first current source.
- the control electrode of the first transistor is coupled to the output terminal of the first operational amplifier.
- the first pole of the first transistor is coupled to the inverting input terminal of the first operational amplifier.
- the second pole of the first transistor is coupled to the first terminal of the second voltage-controlled switch.
- the controlled terminal of the second voltage-controlled switch is coupled to the output terminal of the voltage comparator.
- the second terminal of the second voltage-controlled switch is coupled to the first terminal of the third resistor and the sampling voltage output terminal.
- the controlled terminal of the third voltage-controlled switch is coupled to the output terminal of the voltage comparator.
- the first terminal of the third voltage-controlled switch is coupled to the non-inverting input terminal of the second operational amplifier.
- the second terminal of the third voltage-controlled switch is coupled to the second voltage terminal.
- the controlled terminal of the fourth voltage-controlled switch is coupled to the output terminal of the voltage comparator.
- the first terminal of the fourth voltage-controlled switch is coupled to the inverting input terminal of the second operational amplifier.
- the second terminal of the fourth voltage-controlled switch is coupled to the second voltage terminal.
- the controlled terminal of the fifth voltage-controlled switch is coupled to the output terminal of the voltage comparator.
- the first terminal of the fifth voltage-controlled switch is coupled to the output terminal of the second operational amplifier.
- the second terminal of the fifth voltage-controlled switch is coupled to the second voltage terminal.
- the controlled terminal of the sixth voltage-controlled switch is coupled to the output terminal of the inverter.
- the first terminal of the sixth voltage-controlled switch is coupled to the second terminal of the first resistor.
- the second terminal of the sixth voltage-controlled switch is coupled to the non-inverting input terminal of the second operational amplifier.
- the controlled terminal of the seventh voltage-controlled switch is coupled to the output terminal of the inverter.
- the first terminal of the seventh voltage-controlled switch is coupled to the second terminal of the second resistor.
- the second terminal of the seventh voltage-controlled switch is coupled to the inverting input terminal of the second operational amplifier.
- the controlled terminal of the eighth voltage-controlled switch is coupled to the output terminal of the inverter.
- the first end of the eighth voltage-controlled switch is coupled to the second current source.
- the second terminal of the eighth voltage-controlled switch is coupled to the non-inverting input terminal of the second operational amplifier.
- the control electrode of the second transistor is coupled to the output terminal of the second operational amplifier.
- the first pole of the second transistor is coupled to the inverting input terminal of the second operational amplifier.
- the second electrode of the second transistor is coupled to the control electrode and the second electrode of the third transistor.
- the first pole of the third transistor is coupled to the first voltage terminal.
- the control electrode of the fourth transistor is coupled to the control electrode of the third transistor.
- the first pole of the fourth transistor is coupled to the first voltage terminal.
- the second pole of the fourth transistor is coupled to the sampling voltage output terminal.
- the second terminal of the third resistor is coupled to the second voltage terminal.
- a DC-DC converter includes a circuit for sampling a target current flowing through a target resistor according to the first or second aspect of the present disclosure.
- FIG. 1 is a schematic block diagram of a circuit for sampling a target current flowing through a target resistor according to an embodiment of the present disclosure
- FIG. 2 is an exemplary circuit diagram of a circuit for sampling a target current flowing through a target resistor according to an embodiment of the present disclosure.
- Road map ;
- FIG. 3 is another exemplary circuit diagram of a circuit for sampling a target current flowing through a target resistor in accordance with an embodiment of the present disclosure
- FIG. 4 is yet another exemplary circuit diagram of a circuit for sampling a target current flowing through a target resistor in accordance with an embodiment of the present disclosure
- FIG. 5 is yet another exemplary circuit diagram of a circuit for sampling a target current flowing through a target resistor in accordance with an embodiment of the present disclosure.
- FIG. 6 is a schematic block diagram of a DC-DC converter according to an embodiment of the present disclosure.
- the source and drain (emitter and collector) of the transistor are symmetrical, and the source and drain (emitter and collector) of the N-type transistor and the P-type transistor are The direction of the conduction current between the transistor and the transistor is opposite, so in the embodiment of the present disclosure, the controlled intermediate end of the transistor is called the control electrode, and the remaining two ends of the transistor are called the first pole and the second pole respectively.
- terms such as “first” and “second” are only used to distinguish one component (or part of a component) from another component (or part of a component).
- the inductor current needs to be sampled in the DC-DC converter.
- the inductor current may change from a positive current (flowing out from the output of the DC-DC converter) to a negative current (flowing from the output of the DC-DC converter).
- a positive current flowing out from the output of the DC-DC converter
- a negative current flowing from the output of the DC-DC converter
- Embodiments of the present disclosure propose a circuit that samples a target current flowing through a target resistor.
- the target resistor is a resistor coupled between the inductor in the DC-DC converter and the output of the DC-DC converter, and the target current is the inductor current.
- 1 shows a schematic block diagram of a circuit 100 for sampling a target current IL flowing through a target resistor Rs according to an embodiment of the present disclosure.
- the circuit 100 includes: a first resistor R1, a second resistor R2, a first operational amplifier op1, a first offset current injection circuit 110, a first current sampling circuit 120, and a sampling voltage output circuit 130.
- the first terminal of the first resistor R1 is coupled to the first terminal of the target resistor Rs.
- the second terminal of the first resistor R1 is coupled to the first input terminal of the first operational amplifier op1.
- the first terminal of the second resistor R2 is coupled to the second terminal of the target resistor Rs.
- the second terminal of the second resistor R2 is coupled to the second input terminal of the first operational amplifier op1.
- one of the first input terminal and the second input terminal of the first operational amplifier op1 is a non-inverting input terminal, and the other is an inverting input terminal.
- the first offset current injection circuit 110 may be coupled to the non-inverting input terminal of the first operational amplifier op1.
- the first offset current injection circuit 110 may be configured to generate a first offset current I1 and inject the first offset current I1 into the non-inverting input terminal of the first operational amplifier op1.
- the first current sampling circuit 120 may be coupled to the output terminal and the inverting input terminal of the first operational amplifier op1.
- the first current sampling circuit 120 may also be coupled to the sampling voltage output circuit 130 .
- the first current sampling circuit 120 may be configured to generate the sampling current Iss according to the target current IL and the first offset current I1.
- the sampling voltage output circuit 130 may be coupled to the first current sampling circuit 120 and receive the sampling current Iss from the first current sampling circuit 120.
- the sampling voltage output circuit 130 may be configured to generate the sampling voltage Vsense according to the sampling current Iss, and output the sampling voltage Vsense via the sampling voltage output terminal.
- the resistance value of the first resistor R1 can be set equal to the resistance value of the second resistor R2.
- R is used to represent the resistance values of the first resistor R1 and the second resistor R2.
- the voltage V+ at the non-inverting input terminal of the first operational amplifier op1 is equal to the voltage V- at the inverting input terminal of the first operational amplifier op1.
- V- Vsenp-R ⁇ (Iss+Io).
- V+ Vsenn-R ⁇ (I1+Io).
- Io represents the current flowing through the two input terminals of the first operational amplifier op1.
- the first offset current I1 can be set according to the actual application so that the sampling current Iss is positive when IL is negative. In this way, no matter the target current is a positive current or a negative current, the circuit 100 according to the embodiment of the present disclosure can accurately sample the target current.
- FIG. 2 illustrates a circuit 200 for sampling a target current IL flowing through a target resistor Rs according to an embodiment of the present disclosure.
- the first input terminal of the first operational amplifier op1 is an inverting input terminal.
- the second input terminal of the first operational amplifier op1 is a non-inverting input terminal.
- the first current sampling circuit 220 may include a first transistor M1. Wherein, the control electrode of the first transistor M1 is coupled to the output terminal of the first operational amplifier op1. The first pole of the first transistor M1 is coupled to the inverting input terminal of the first operational amplifier op1. The second pole of the first transistor M1 is coupled to the sampling voltage output terminal.
- the sampling voltage output circuit 230 may include a third resistor R3.
- the first terminal of the third resistor R3 is coupled to the sampling voltage output terminal.
- the first terminal of the third resistor R3 is coupled to the second voltage terminal V2.
- the first offset current injection circuit 210 may include a first current source.
- the first current source may generate a first offset current I1.
- the flow direction of the first offset current I1 is from the non-inverting input terminal of the first operational amplifier op1 to the second voltage terminal V2.
- the first transistor M1 is a high voltage transistor.
- FIG. 3 shows another exemplary circuit diagram of a circuit 300 for sampling a target current IL flowing through a target resistor Rs according to an embodiment of the present disclosure.
- a Zener diode ZD is added to the first current sampling circuit 320 .
- the anode of the Zener diode ZD is coupled to the second voltage terminal V2.
- the cathode of the Zener diode ZD is coupled to the second electrode of the first transistor M1. Since the first transistor M1 is a high-voltage transistor, when the first transistor M1 is turned on, the voltage of the second pole of the first transistor M1 is a high voltage. In order to prevent leakage at this point from causing damage to other devices, a Zener diode ZD is installed here.
- FIG. 2 and 3 apply when the common-mode voltage across the target resistor Rs is high. Embodiments of the present disclosure also propose specific implementations suitable for the case where the common mode voltage across the target resistor Rs is lower (lower than the power supply voltage of the circuit that samples the target current).
- 4 shows yet another exemplary circuit diagram of a circuit 400 for sampling a target current IL flowing through a target resistor Rs according to an embodiment of the present disclosure.
- the first input terminal of the first operational amplifier op1 is a non-inverting input terminal.
- the second input terminal of the first operational amplifier op1 is an inverting input terminal.
- the first current sampling circuit 420 may include a second transistor M2, a third transistor M3, and a fourth transistor M4.
- the control electrode of the second transistor M2 is coupled to the output terminal of the first operational amplifier op1.
- the first pole of the second transistor M2 is coupled to the inverting input terminal of the first operational amplifier op1.
- the second electrode of the second transistor M2 is coupled to the control electrode and the second electrode of the third transistor M3.
- the first pole of the third transistor M3 is coupled to the first voltage terminal V1.
- the control electrode of the fourth transistor M4 is coupled to the control electrode of the third transistor M3.
- the first pole of the fourth transistor M4 is coupled to the first voltage terminal V1.
- the second pole of the fourth transistor M4 is coupled to the sampling voltage output terminal.
- the sampling voltage output circuit 430 may include a third resistor R3.
- the first terminal of the third resistor R3 is coupled to the sampling voltage output terminal.
- the first terminal of the third resistor R3 is coupled to the second voltage terminal V2.
- the first offset current injection circuit 410 may include a first current source.
- the first current source may generate a first offset current I1. exist In the example of FIG. 4 , the flow direction of the first offset current is from the first voltage terminal V1 to the non-inverting input terminal of the first operational amplifier op1 .
- FIG. 5 shows yet another exemplary circuit diagram of a circuit 500 for sampling a target current IL flowing through a target resistor Rs according to an embodiment of the present disclosure. Based on the embodiment of FIG.
- the circuit 500 for sampling the target current IL flowing through the target resistor Rs may further include: a second operational amplifier op2, a second offset current injection circuit 570, a second current sampling circuit 580, Voltage judgment circuit 540, first operational amplifier selection circuit 550, and second operational amplifier selection circuit 560.
- the voltage judgment circuit 540 may be coupled to one end of the target resistor Rs, the reference voltage end, the first operational amplifier selection circuit 550, and the second operational amplifier selection circuit 560.
- the voltage judgment circuit 540 may be configured to generate the first selection signal hs and the second selection signal ls according to the voltage of one end (the first end or the second end) of the target resistor Rs and the reference voltage Vref from the reference voltage end.
- the first selection signal hs and the second selection signal ls are inverse signals of each other.
- the first selection signal hs is at the active level and the second selection signal ls is at the inactive level.
- the first selection signal hs is at the inactive level and the second selection signal ls is at the active level.
- the first operational amplifier selection circuit 550 may be coupled to the voltage determination circuit 540, the second resistor R2, the first operational amplifier op1, the first offset current injection circuit 210, the first current sampling circuit 320, the second operational amplifier op2, and the second operational amplifier op1.
- the first offset current injection circuit 210 may be coupled to the non-inverting input terminal of the first operational amplifier op1 via the first operational amplifier selection circuit 550 .
- the sampling voltage output circuit 230 may be coupled to the first current sampling circuit 320 via the first operational amplifier selection circuit 550 .
- the first operational amplifier selection circuit 550 may be configured to: disconnect the first offset current injection circuit 210 from the first operational amplifier op1 and disconnect the first current sampling when the first selection signal hs is at an inactive level. The connection between the circuit 320 and the sampling voltage output circuit 230 does not affect the operation of the second operational amplifier op2 and the second current sampling circuit 580 .
- the first operational amplifier selection circuit 550 may also be configured to: when the first selection signal hs is at an active level, the first offset current injection circuit 210 is coupled to the first operational amplifier op1, so that the first current sampling circuit 320 is coupled to the sampling voltage output circuit 230 and controls the second operational amplifier op2 and the second current sampling circuit 580 to stop working.
- the second operational amplifier selection circuit 560 may be coupled to the voltage determination circuit 540, the first resistor R1, the second resistor R2, the second offset current injection circuit 570, the second operational amplifier op2, the second current sampling circuit 580, and the One voltage terminal V1.
- the second offset current injection circuit 570 may be coupled to the non-inverting input terminal of the second operational amplifier op2 via the second operational amplifier selection circuit 560 .
- the second operational amplifier op2 may be coupled to the first resistor R1 and the second resistor R2 via the second operational amplifier selection circuit 560 .
- the second op amp selects the power
- the path 560 may be configured to: when the second selection signal ls is at an active level, the second offset current injection circuit 570 is coupled to the non-inverting input terminal of the second operational amplifier op2, so that the first input terminal of the second operational amplifier op2 The input terminal is coupled to the second terminal of the first resistor R1, so that the second input terminal of the second operational amplifier op2 is coupled to the second terminal of the second resistor R2.
- the second operational amplifier selection circuit 560 may also be configured to: when the second selection signal ls is at an inactive level, disconnect the second offset current injection circuit 570 from the second operational amplifier op2, and disconnect the second operational amplifier op2. Connect op2 to the first resistor R1, and disconnect the second op amp op2 from the second resistor R2.
- the first input terminal of the second operational amplifier op2 is a non-inverting input terminal, and the second input terminal of the second operational amplifier op2 is an inverting input terminal. In other embodiments of the present disclosure, the first input terminal of the second operational amplifier op2 is an inverting input terminal, and the second input terminal of the second operational amplifier op2 is a non-inverting input terminal.
- the second offset current injection circuit 570 may be coupled to the second operational amplifier selection circuit 560 and the first voltage terminal V1.
- the second offset current injection circuit 570 may be configured to generate a second offset current I2.
- the second current sampling circuit 580 may be coupled to the output terminal and the inverting input terminal of the second operational amplifier op2.
- the second current sampling circuit 580 may also be coupled to the sampling voltage output circuit 230 .
- the second current sampling circuit 580 may be configured to generate the sampling current Iss according to the target current IL and the second offset current I2.
- only one of the first current sampling circuit 320 and the second current sampling circuit 580 can provide the sampling current Iss to the sampling voltage output circuit 230.
- the second current sampling circuit 580 may include: a second transistor M2, a third transistor M3, and a fourth transistor M4.
- the control electrode of the second transistor M2 is coupled to the output terminal of the second operational amplifier op2.
- the first pole of the second transistor M2 is coupled to the inverting input terminal of the second operational amplifier op2.
- the second electrode of the second transistor M2 is coupled to the control electrode and the second electrode of the third transistor M3.
- the first pole of the third transistor M3 is coupled to the first voltage terminal V1.
- the control electrode of the fourth transistor M4 is coupled to the control electrode of the third transistor M3.
- the first pole of the fourth transistor M4 is coupled to the first voltage terminal V1.
- the second pole of the fourth transistor M4 is coupled to the sampling voltage output terminal.
- the first input terminal of the second operational amplifier op2 is a non-inverting input terminal.
- the second input terminal of the second operational amplifier op2 is an inverting input terminal.
- the voltage judgment circuit 540 may include: a voltage comparator comp, and an inverter NG.
- the first input terminal of the voltage comparator comp is coupled to one end of the target resistor Rs.
- the second input terminal of the voltage comparator comp is coupled to the reference voltage terminal.
- the output terminal of the voltage comparator comp is coupled to the input terminal of the inverter NG.
- the first selection signal hs is output from the output terminal of the voltage comparator comp.
- the second selection signal ls is output from the output terminal of the inverter NG.
- the first input terminal of the voltage comparator comp is the non-inverting input terminal.
- the second input terminal of the voltage comparator comp is the inverting input terminal.
- the effective levels of the first selection signal hs and the second selection signal ls are high levels.
- the first selection signal hs and the second selection signal ls are high levels.
- the invalid level of the selection signal ls is a low level.
- the first operational amplifier selection circuit 550 may include: first to fifth voltage-controlled switches s1 to s5. Among them, the controlled end of the first voltage-controlled switch s1 is provided with the first selection signal hs. The first terminal of the first voltage-controlled switch s1 is coupled to the second terminal of the second resistor R2. The second terminal of the first voltage-controlled switch s1 is coupled to the output terminal of the first offset current injection circuit 210 . The controlled terminal of the second voltage-controlled switch s2 is provided with the first selection signal hs. The first terminal of the second voltage-controlled switch s2 is coupled to the output terminal of the first current sampling circuit 320 .
- the second terminal of the second voltage-controlled switch s2 is coupled to the sampling voltage output terminal.
- the controlled terminal of the third voltage-controlled switch s3 is provided with the first selection signal hs.
- the first terminal of the third voltage-controlled switch s3 is coupled to the first input terminal of the second operational amplifier op2.
- the second terminal of the third voltage-controlled switch s3 is coupled to the second voltage terminal V2.
- the controlled terminal of the fourth voltage-controlled switch s4 is provided with the first selection signal hs.
- the first terminal of the fourth voltage-controlled switch s4 is coupled to the second input terminal of the second operational amplifier op2.
- the second terminal of the fourth voltage-controlled switch s4 is coupled to the second voltage terminal V2.
- the controlled terminal of the fifth voltage-controlled switch s5 is provided with the first selection signal hs.
- the first terminal of the fifth voltage-controlled switch s5 is coupled to the output terminal of the second operational amplifier op2.
- the second terminal of the fifth voltage-controlled switch s5 is coupled to the second voltage terminal V2.
- the second operational amplifier selection circuit 560 may include: a sixth voltage-controlled switch s6, a seventh voltage-controlled switch s7, and an eighth voltage-controlled switch s8.
- the controlled end of the sixth voltage-controlled switch s6 is provided with the second selection signal ls.
- the first terminal of the sixth voltage-controlled switch s6 is coupled to the second terminal of the first resistor R1.
- the second terminal of the sixth voltage-controlled switch s6 is coupled to the first input terminal (for example, the non-inverting input terminal) of the second operational amplifier op2.
- the controlled end of the seventh voltage-controlled switch s7 is provided with the second selection signal ls.
- the first terminal of the seventh voltage-controlled switch s7 is coupled to the second terminal of the second resistor R2.
- the second terminal of the seventh voltage-controlled switch s7 is coupled to the second input terminal (for example, the inverting input terminal) of the second operational amplifier op2.
- the controlled terminal of the eighth voltage-controlled switch s8 is provided with the second selection signal ls.
- the first terminal of the eighth voltage-controlled switch s8 is coupled to the output terminal of the second offset current injection circuit 570 .
- the second terminal of the eighth voltage-controlled switch s8 is coupled to the non-inverting input terminal of the second operational amplifier op2.
- a high voltage signal is input from the first voltage terminal V1 and the second voltage terminal V2 is grounded.
- the first transistor M1, the third transistor M3 and the fourth transistor M4 are PMOS transistors.
- the second transistor M2 is an NMOS transistor.
- the above-mentioned transistors and voltage terminals may also have different arrangements from the examples shown in FIGS. 2 to 5 .
- the internal structures of each circuit in Figures 2 to 5 are exemplary, and they can also be implemented by other circuits.
- the first to eighth voltage-controlled switches s1 to s8 may be implemented by switching transistors.
- the first selection signal hs when the voltage Vsenp at one end of the target resistor Rs is higher than or equal to the reference voltage Vref, the first selection signal hs is at a high level and the second selection signal ls is at a low level.
- First selection signal hs control The first to fifth voltage-controlled switches s1 to s5 are closed. Therefore, the first current source is coupled to the non-inverting input terminal of the first operational amplifier op1.
- the second pole of the first transistor M1 is coupled to the sampling voltage output terminal.
- the two input terminals and output terminals of the second operational amplifier op2 are grounded and therefore stop working.
- the control electrode of the second transistor M2 is grounded, so it also stops working.
- the second selection signal ls controls the sixth to eighth voltage-controlled switches s6 to s8 to be turned off. Therefore, the two input terminals of the second operational amplifier op2 are disconnected from the first resistor R1 and the second resistor R2, and the second current source is also disconnected from the second operational amplifier op2. At this time, the circuit 500 of FIG. 5 can be equivalent to the circuit 300 of FIG. 3 .
- the resistance value R of the first resistor R1 can be set equal to the resistance value R of the second resistor R2.
- the voltage V+ at the non-inverting input terminal of the first operational amplifier op1 is equal to the voltage V- at the inverting input terminal of the first operational amplifier op1.
- V- Vsenp-R ⁇ (Iss+Io).
- the first offset current I1 can be set according to the actual application so that the sampling current Iss is positive when IL is negative. In this way, regardless of whether the target current is a positive current or a negative current, the circuit 500 according to the embodiment of the present disclosure can accurately sample the target current.
- the first selection signal hs When the voltage Vsenp at one end of the target resistor Rs is lower than the reference voltage Vref, the first selection signal hs is at low level and the second selection signal ls is at high level.
- the first selection signal hs controls the first to fifth voltage-controlled switches s1 to s5 to be turned off. Therefore, the first current source is disconnected from the first operational amplifier op1.
- the connection between the second pole of the first transistor M1 and the sampling voltage output terminal is also disconnected.
- the second selection signal ls controls the sixth to eighth voltage-controlled switches s6 to s8 to close.
- the non-inverting input terminal of the second operational amplifier op2 is coupled to the second terminal of the first resistor R1
- the inverting input terminal of the second operational amplifier op2 is coupled to the second terminal of the second resistor R2
- the circuit 500 of FIG. 5 can be equivalent to the circuit 400 of FIG. 4 (only the names of some components are different).
- the resistance value R of the first resistor R1 may be set equal to the resistance value R of the second resistor R2.
- the voltage V+ at the non-inverting input terminal of the first operational amplifier op1 is equal to the voltage V- at the inverting input terminal of the first operational amplifier op1.
- V- Vsenp-R ⁇ (Iss-Io).
- the second offset current I2 can be set according to the actual application so that the sampling current Iss is positive when IL is negative. In this way, no matter whether the target current is a positive current or a negative current, the circuit 500 according to the embodiment of the present disclosure can accurately sample the target current.
- FIG. 6 shows a schematic block diagram of the DC-DC converter Conv according to an embodiment of the present disclosure.
- the DC-DC converter Conv may include circuits (100, 200, 300, 400 in FIGS. 1 to 5 for sampling the target current flowing through the target resistor). and 500) any one.
- the circuit for sampling the target current flowing through the target resistor according to the embodiment of the present disclosure is applicable to the case where the target current switches between the positive current and the negative current. Further, the circuit for sampling the target current flowing through the target resistor according to the embodiment of the present disclosure is also applicable to the case where the common-mode voltage of the target resistor has a large variation range.
- the DC-DC converter according to the embodiment of the present disclosure can use the above circuit to sample the inductor current, and therefore, the DC-DC converter according to the embodiment of the present disclosure can sample the inductor current more accurately.
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Abstract
本公开的实施例提供一种对流过目标电阻器的目标电流进行采样的电路。该电路包括:第一和第二电阻器、第一运放、第一失调电流注入电路、第一电流采样电路、以及采样电压输出电路。第一电阻器的第一端耦接目标电阻器的第一端。第一电阻器的第二端耦接第一运放的第一输入端。第二电阻器的第一端耦接目标电阻器的第二端。第二电阻器的第二端耦接第一运放的第二输入端。第一失调电流注入电路向第一运放的同相输入端注入第一失调电流。第一电流采样电路耦接第一运放的输出端和反相输入端,并根据目标电流和第一失调电流生成采样电流。采样电压输出电路根据采样电流生成采样电压。第一运放的第一和第二输入端中的一者是同相输入端,另一者是反相输入端。
Description
相关申请的交叉引用
本申请要求于2022年9月23日递交的中国专利申请第202211167625.8号的优先权,在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
本公开的实施例涉及集成电路技术领域,具体地,涉及对流过目标电阻器的目标电流进行采样的电路。
在集成电路的实际应用中有一些电流值不适合直接检测,因此可使用电流采样电路来间接检测目标电流值。具体地,电流采样电路可对目标电流值进行采样,并输出采样电流值,或者将采样电流转换成采样电压。通过测量输出的采样电流或采样电压来确定目标电流值的大小。电流采样电路可应用于DC-DC变换器等电路中。当流经DC-DC变换器中的电感器的电感电流过大时,可通过控制功率管和续流管来停止对电感器充电。在电感电流下降至谷值限流值时允许再次对电感器进行充电。这样可实现过流保护的功能。
发明内容
本文中描述的实施例提供了一种对流过目标电阻器的目标电流进行采样的电路、以及DC-DC变换器。
根据本公开的第一方面,提供了一种对流过目标电阻器的目标电流进行采样的电路。该电路包括:第一电阻器、第二电阻器、第一运放、第一失调电流注入电路、第一电流采样电路、以及采样电压输出电路。其中,第一电阻器的第一端耦接目标电阻器的第一端。第一电阻器的第二端耦接第一运放的第一输入端。第二电阻器的第一端耦接目标电阻器的第二端。第二电阻器的第二端耦接第一运放的第二输入端。第一失调电流注入电路被配置为向第一运放的同相输入端注入第一失调电流。第一电流采样电路耦接第一运放的输出端和反相输入端,并被配置为根据目标电流和第一失调电流来生成采样电流。采样电压输出电路被配置为根据采样电流来生成采样电压,并经由采样电压输出端输出采样电压。其中,第一运放的第一输
入端和第二输入端中的一者是同相输入端,另一者是反相输入端。
在本公开的一些实施例中,第一运放的第一输入端是反相输入端。第一运放的第二输入端是同相输入端。第一电流采样电路包括:第一晶体管。其中,第一晶体管的控制极耦接第一运放的输出端。第一晶体管的第一极耦接第一运放的反相输入端。第一晶体管的第二极耦接采样电压输出端。
在本公开的一些实施例中,第一运放的第一输入端是反相输入端。第一运放的第二输入端是同相输入端。第一电流采样电路包括:第一晶体管、以及稳压二极管。其中,第一晶体管的控制极耦接第一运放的输出端。第一晶体管的第一极耦接第一运放的反相输入端。第一晶体管的第二极耦接采样电压输出端。稳压二极管的阳极耦接第二电压端。稳压二极管的阴极耦接第一晶体管的第二极。
在本公开的一些实施例中,第一运放的第一输入端是同相输入端。第一运放的第二输入端是反相输入端。第一电流采样电路包括:第二晶体管、第三晶体管、以及第四晶体管。其中,第二晶体管的控制极耦接第一运放的输出端。第二晶体管的第一极耦接第一运放的反相输入端。第二晶体管的第二极耦接第三晶体管的控制极和第二极。第三晶体管的第一极耦接第一电压端。第四晶体管的控制极耦接第三晶体管的控制极。第四晶体管的第一极耦接第一电压端。第四晶体管的第二极耦接采样电压输出端。
在本公开的一些实施例中,电路还包括:第二运放、第二失调电流注入电路、第二电流采样电路、电压判断电路、第一运放选择电路、以及第二运放选择电路。其中,电压判断电路被配置为根据目标电阻器的一端的电压和来自参考电压端的参考电压来生成第一选择信号和第二选择信号。第一运放选择电路被配置为:在第一选择信号处于无效电平的情况下,断开第一失调电流注入电路与第一运放的连接并断开第一电流采样电路与采样电压输出电路的连接;在第一选择信号处于有效电平的情况下,控制第二运放和第二电流采样电路停止工作。第二运放选择电路被配置为:在第二选择信号处于有效电平的情况下,使得第二失调电流注入电路耦接第二运放的同相输入端、使得第二运放的第一输入端耦接第一电阻器的第二端,使得第二运放的第二输入端耦接第二电阻器的第二端。第二失调电流注入电路被配置为:生成第二失调电流。第二电流采样电路耦接第二运放的输出端和反相输入端,并被配置为:根据目标电流和第二失调电流来生成采样电流。
在本公开的一些实施例中,第二运放的第一输入端是同相输入端。第二运放的第二输入端是反相输入端。第二电流采样电路包括:第二晶体管、第三晶体管、以及第四晶体管。其
中,第二晶体管的控制极耦接第二运放的输出端。第二晶体管的第一极耦接第二运放的反相输入端。第二晶体管的第二极耦接第三晶体管的控制极和第二极。第三晶体管的第一极耦接第一电压端。第四晶体管的控制极耦接第三晶体管的控制极。第四晶体管的第一极耦接第一电压端。第四晶体管的第二极耦接采样电压输出端。
在本公开的一些实施例中,电压判断电路包括:电压比较器、以及反相器。其中,电压比较器的第一输入端耦接目标电阻器的一端。电压比较器的第二输入端耦接参考电压端。电压比较器的输出端耦接反相器的输入端。从电压比较器的输出端输出第一选择信号。从反相器的输出端输出第二选择信号。
在本公开的一些实施例中,第一运放选择电路包括:第一压控开关至第五压控开关。其中,第一压控开关的受控端被提供第一选择信号。第一压控开关的第一端耦接第二电阻器的第二端。第一压控开关的第二端耦接第一失调电流注入电路的输出端。第二压控开关的受控端被提供第一选择信号。第二压控开关的第一端耦接第一电流采样电路的输出端。第二压控开关的第二端耦接采样电压输出端。第三压控开关的受控端被提供第一选择信号。第三压控开关的第一端耦接第二运放的第一输入端。第三压控开关的第二端耦接第二电压端。第四压控开关的受控端被提供第一选择信号。第四压控开关的第一端耦接第二运放的第二输入端。第四压控开关的第二端耦接第二电压端。第五压控开关的受控端被提供第一选择信号。第五压控开关的第一端耦接第二运放的输出端。第五压控开关的第二端耦接第二电压端。
在本公开的一些实施例中,第二运放选择电路包括:第六压控开关、第七压控开关、以及第八压控开关。其中,第六压控开关的受控端被提供第二选择信号。第六压控开关的第一端耦接第一电阻器的第二端。第六压控开关的第二端耦接第二运放的第一输入端。第七压控开关的受控端被提供第二选择信号。第七压控开关的第一端耦接第二电阻器的第二端。第七压控开关的第二端耦接第二运放的第二输入端。第八压控开关的受控端被提供第二选择信号。第八压控开关的第一端耦接第二失调电流注入电路的输出端。第八压控开关的第二端耦接第二运放的同相输入端。
根据本公开的第二方面,提供了一种对流过目标电阻器的目标电流进行采样的电路。该电路包括:第一电阻器、第二电阻器、第三电阻器、第一运放、第二运放、第一晶体管至第四晶体管、第一电流源、第二电流源、电压比较器、反相器、以及第一压控开关至第八压控开关。其中,第一电阻器的第一端耦接目标电阻器的第一端。第一电阻器的第二端耦接第一运放的反相输入端。第二电阻器的第一端耦接目标电阻器的第二端。第二电阻器的第二端耦
接第一运放的同相输入端。电压比较器的第一输入端耦接目标电阻器的一端。电压比较器的第二输入端耦接参考电压端。电压比较器的输出端耦接反相器的输入端。第一压控开关的受控端耦接电压比较器的输出端。第一压控开关的第一端耦接第二电阻器的第二端。第一压控开关的第二端耦接第一电流源。第一晶体管的控制极耦接第一运放的输出端。第一晶体管的第一极耦接第一运放的反相输入端。第一晶体管的第二极耦接第二压控开关的第一端。第二压控开关的受控端耦接电压比较器的输出端。第二压控开关的第二端耦接第三电阻器的第一端和采样电压输出端。第三压控开关的受控端耦接电压比较器的输出端。第三压控开关的第一端耦接第二运放的同相输入端。第三压控开关的第二端耦接第二电压端。第四压控开关的受控端耦接电压比较器的输出端。第四压控开关的第一端耦接第二运放的反相输入端。第四压控开关的第二端耦接第二电压端。第五压控开关的受控端耦接电压比较器的输出端。第五压控开关的第一端耦接第二运放的输出端。第五压控开关的第二端耦接第二电压端。第六压控开关的受控端耦接反相器的输出端。第六压控开关的第一端耦接第一电阻器的第二端。第六压控开关的第二端耦接第二运放的同相输入端。第七压控开关的受控端耦接反相器的输出端。第七压控开关的第一端耦接第二电阻器的第二端。第七压控开关的第二端耦接第二运放的反相输入端。第八压控开关的受控端耦接反相器的输出端。第八压控开关的第一端耦接第二电流源。第八压控开关的第二端耦接第二运放的同相输入端。第二晶体管的控制极耦接第二运放的输出端。第二晶体管的第一极耦接第二运放的反相输入端。第二晶体管的第二极耦接第三晶体管的控制极和第二极。第三晶体管的第一极耦接第一电压端。第四晶体管的控制极耦接第三晶体管的控制极。第四晶体管的第一极耦接第一电压端。第四晶体管的第二极耦接采样电压输出端。第三电阻器的第二端耦接第二电压端。
根据本公开的第三方面,提供了一种DC-DC变换器。该DC-DC变换器包括根据本公开的第一方面或第二方面所述的对流过目标电阻器的目标电流进行采样的电路。
为了更清楚地说明本公开的实施例的技术方案,下面将对实施例的附图进行简要说明,应当知道,以下描述的附图仅仅涉及本公开的一些实施例,而非对本公开的限制,其中:
图1是根据本公开的实施例的对流过目标电阻器的目标电流进行采样的电路的示意性框图;
图2是根据本公开的实施例的对流过目标电阻器的目标电流进行采样的电路的示例性电
路图;
图3是根据本公开的实施例的对流过目标电阻器的目标电流进行采样的电路的另一示例性电路图;
图4是根据本公开的实施例的对流过目标电阻器的目标电流进行采样的电路的又一示例性电路图;
图5是根据本公开的实施例的对流过目标电阻器的目标电流进行采样的电路的再一示例性电路图;以及
图6是根据本公开的实施例的DC-DC变换器的示意性框图。
在附图中,最后两位数字相同的标记对应于相同的元素。需要注意的是,附图中的元素是示意性的,没有按比例绘制。
为了使本公开的实施例的目的、技术方案和优点更加清楚,下面将结合附图,对本公开的实施例的技术方案进行清楚、完整的描述。显然,所描述的实施例是本公开的一部分实施例,而不是全部的实施例。基于所描述的本公开的实施例,本领域技术人员在无需创造性劳动的前提下所获得的所有其它实施例,也都属于本公开保护的范围。
除非另外定义,否则在此使用的所有术语(包括技术和科学术语)具有与本公开主题所属领域的技术人员所通常理解的相同含义。进一步将理解的是,诸如在通常使用的词典中定义的那些的术语应解释为具有与说明书上下文和相关技术中它们的含义一致的含义,并且将不以理想化或过于正式的形式来解释,除非在此另外明确定义。如在此所使用的,将两个或更多部分“连接”或“耦接”到一起的陈述应指这些部分直接结合到一起或通过一个或多个中间部件结合。
在本公开的所有实施例中,由于晶体管的源极和漏极(发射极和集电极)是对称的,并且N型晶体管和P型晶体管的源极和漏极(发射极和集电极)之间的导通电流方向相反,因此在本公开的实施例中,将晶体管的受控中间端称为控制极,将晶体管的其余两端分别称为第一极和第二极。另外,诸如“第一”和“第二”的术语仅用于将一个部件(或部件的一部分)与另一个部件(或部件的另一部分)区分开。
如上所述,在DC-DC变换器中需要对电感电流进行采样。在一些情况下,电感电流可能从正向电流(从DC-DC变换器的输出端流出)变成负向电流(从DC-DC变换器的输出端流入)。
当电流由正向到负向切换的时候,用同一个采样电路往往很难对电流进行准确的采样。
本公开的实施例提出了一种对流过目标电阻器的目标电流进行采样的电路。在对DC-DC变换器中的电感电流进行采样的示例中,目标电阻器是耦接在DC-DC变换器中的电感器与DC-DC变换器的输出端之间的电阻器,目标电流是电感电流。图1示出根据本公开的实施例的对流过目标电阻器Rs的目标电流IL进行采样的电路100的示意性框图。该电路100包括:第一电阻器R1、第二电阻器R2、第一运放op1、第一失调电流注入电路110、第一电流采样电路120、以及采样电压输出电路130。
第一电阻器R1的第一端耦接目标电阻器Rs的第一端。第一电阻器R1的第二端耦接第一运放op1的第一输入端。第二电阻器R2的第一端耦接目标电阻器Rs的第二端。第二电阻器R2的第二端耦接第一运放op1的第二输入端。其中,第一运放op1的第一输入端和第二输入端中的一者是同相输入端,另一者是反相输入端。
第一失调电流注入电路110可耦接第一运放op1的同相输入端。第一失调电流注入电路110可被配置为:生成第一失调电流I1,并向第一运放op1的同相输入端注入第一失调电流I1。
第一电流采样电路120可耦接第一运放op1的输出端和反相输入端。第一电流采样电路120还可耦接采样电压输出电路130。第一电流采样电路120可被配置为根据目标电流IL和第一失调电流I1来生成采样电流Iss。
采样电压输出电路130可耦接第一电流采样电路120,并从第一电流采样电路120接收采样电流Iss。采样电压输出电路130可被配置为根据采样电流Iss来生成采样电压Vsense,并经由采样电压输出端输出采样电压Vsense。
在图1的示例中可设置第一电阻器R1的电阻值等于第二电阻器R2的电阻值。在上下文中,用R表示第一电阻器R1和第二电阻器R2的电阻值。根据运放的虚短虚断特性可知,第一运放op1的同相输入端的电压V+等于第一运放op1的反相输入端的电压V-。V-=Vsenp-R×(Iss+Io)。V+=Vsenn-R×(I1+Io)。其中,Io表示流过第一运放op1的两个输入端的电流。因此,Vsenp-Vsenn=R×(Iss+Io)-R×(I1+Io)。又因为,Vsenp-Vsenn=IL×Rs。所以IL×Rs=R×Iss-R×I1。Iss=IL×Rs/R+I1。第一失调电流I1可根据实际应用来设置以使得在IL为负的情况下采样电流Iss为正。这样无论目标电流是正向电流还是负向电流,根据本公开的实施例的电路100都可以对目标电流进行准确的采样。
图2示出根据本公开的实施例的对流过目标电阻器Rs的目标电流IL进行采样的电路200
的示例性电路图。在图2的示例中,第一运放op1的第一输入端是反相输入端。第一运放op1的第二输入端是同相输入端。
第一电流采样电路220可包括第一晶体管M1。其中,第一晶体管M1的控制极耦接第一运放op1的输出端。第一晶体管M1的第一极耦接第一运放op1的反相输入端。第一晶体管M1的第二极耦接采样电压输出端。
采样电压输出电路230可包括第三电阻器R3。第三电阻器R3的第一端耦接采样电压输出端。第三电阻器R3的第一端耦接第二电压端V2。
第一失调电流注入电路210可包括第一电流源。第一电流源可生成第一失调电流I1。在图2的示例中,第一失调电流I1的流向是从第一运放op1的同相输入端到第二电压端V2。
在本公开的一些实施例中,第一晶体管M1是高压晶体管。
图3示出根据本公开的实施例的对流过目标电阻器Rs的目标电流IL进行采样的电路300的另一示例性电路图。在图2的示例的基础上,在图3的示例中,在第一电流采样电路320中增加了稳压二极管ZD。稳压二极管ZD的阳极耦接第二电压端V2。稳压二极管ZD的阴极耦接第一晶体管M1的第二极。由于第一晶体管M1是高压晶体管,当第一晶体管M1导通时,第一晶体管M1的第二极的电压是高电压。为防止该点发生漏电造成其他器件的损坏,在这里设置了稳压二极管ZD。
图2和图3的示例适用于目标电阻器Rs的两端的共模电压较高的情况。本公开的实施例还提出了适用于目标电阻器Rs的两端的共模电压较低(比对目标电流进行采样的电路的电源电压更低)的情况的具体实施方式。图4示出根据本公开的实施例的对流过目标电阻器Rs的目标电流IL进行采样的电路400的又一示例性电路图。在图4的示例中,第一运放op1的第一输入端是同相输入端。第一运放op1的第二输入端是反相输入端。第一电流采样电路420可包括:第二晶体管M2、第三晶体管M3、以及第四晶体管M4。其中,第二晶体管M2的控制极耦接第一运放op1的输出端。第二晶体管M2的第一极耦接第一运放op1的反相输入端。第二晶体管M2的第二极耦接第三晶体管M3的控制极和第二极。第三晶体管M3的第一极耦接第一电压端V1。第四晶体管M4的控制极耦接第三晶体管M3的控制极。第四晶体管M4的第一极耦接第一电压端V1。第四晶体管M4的第二极耦接采样电压输出端。
采样电压输出电路430可包括第三电阻器R3。第三电阻器R3的第一端耦接采样电压输出端。第三电阻器R3的第一端耦接第二电压端V2。
第一失调电流注入电路410可包括第一电流源。第一电流源可生成第一失调电流I1。在
图4的示例中,第一失调电流的流向是从第一电压端V1到第一运放op1的同相输入端。
如上所述,图2和图3的示例适用于目标电阻器Rs的两端的共模电压较高的情况。而图4的示例适用于目标电阻器Rs的两端的共模电压较低的情况。上述示例都不适用于共模电压的变化范围较大的情况。针对共模电压的变化范围较大的情况,本公开的实施例提出了另一实施方式。图5示出根据本公开的实施例的对流过目标电阻器Rs的目标电流IL进行采样的电路500的再一示例性电路图。在图1的实施例的基础上,对流过目标电阻器Rs的目标电流IL进行采样的电路500还可包括:第二运放op2、第二失调电流注入电路570、第二电流采样电路580、电压判断电路540、第一运放选择电路550、以及第二运放选择电路560。
电压判断电路540可耦接目标电阻器Rs的一端、参考电压端、第一运放选择电路550、以及第二运放选择电路560。电压判断电路540可被配置为:根据目标电阻器Rs的一端(第一端或第二端)的电压和来自参考电压端的参考电压Vref来生成第一选择信号hs和第二选择信号ls。其中,第一选择信号hs和第二选择信号ls互为反相信号。在一个示例中,在目标电阻器Rs的一端的电压高于或者等于参考电压Vref的情况下,第一选择信号hs处于有效电平,第二选择信号ls处于无效电平。在目标电阻器Rs的一端的电压低于参考电压Vref的情况下,第一选择信号hs处于无效电平,第二选择信号ls处于有效电平。
第一运放选择电路550可耦接电压判断电路540、第二电阻器R2、第一运放op1、第一失调电流注入电路210、第一电流采样电路320、第二运放op2、第二电流采样电路580、以及第二电压端V2。第一失调电流注入电路210可经由第一运放选择电路550耦接第一运放op1的同相输入端。采样电压输出电路230可经由第一运放选择电路550耦接第一电流采样电路320。第一运放选择电路550可被配置为:在第一选择信号hs处于无效电平的情况下,断开第一失调电流注入电路210与第一运放op1的连接并断开第一电流采样电路320与采样电压输出电路230的连接,以及不影响第二运放op2和第二电流采样电路580的工作。第一运放选择电路550还可被配置为:在第一选择信号hs处于有效电平的情况下,使得第一失调电流注入电路210与第一运放op1耦接,使得第一电流采样电路320与采样电压输出电路230耦接,控制第二运放op2和第二电流采样电路580停止工作。
第二运放选择电路560可耦接电压判断电路540、第一电阻器R1、第二电阻器R2、第二失调电流注入电路570、第二运放op2、第二电流采样电路580、以及第一电压端V1。第二失调电流注入电路570可经由第二运放选择电路560耦接第二运放op2的同相输入端。第二运放op2可经由第二运放选择电路560耦接第一电阻器R1和第二电阻器R2。第二运放选择电
路560可被配置为:在第二选择信号ls处于有效电平的情况下,使得第二失调电流注入电路570耦接第二运放op2的同相输入端、使得第二运放op2的第一输入端耦接第一电阻器R1的第二端,使得第二运放op2的第二输入端耦接第二电阻器R2的第二端。第二运放选择电路560还可被配置为:在第二选择信号ls处于无效电平的情况下,断开第二失调电流注入电路570与第二运放op2的连接,断开第二运放op2与第一电阻器R1的连接,以及断开第二运放op2与第二电阻器R2的连接。
在本公开的一些实施例中,第二运放op2的第一输入端是同相输入端,第二运放op2的第二输入端是反相输入端。在本公开的另一些实施例中,第二运放op2的第一输入端是反相输入端,第二运放op2的第二输入端是同相输入端。
第二失调电流注入电路570可耦接第二运放选择电路560和第一电压端V1。第二失调电流注入电路570可被配置为:生成第二失调电流I2。
第二电流采样电路580可耦接第二运放op2的输出端和反相输入端。第二电流采样电路580还可耦接采样电压输出电路230。第二电流采样电路580可被配置为:根据目标电流IL和第二失调电流I2来生成采样电流Iss。
在第一运放选择电路550和第二运放选择电路560的控制下,只有第一电流采样电路320和第二电流采样电路580中的一者能够向采样电压输出电路230提供采样电流Iss。
在本公开的一些实施例中,第二电流采样电路580可包括:第二晶体管M2、第三晶体管M3、以及第四晶体管M4。其中,第二晶体管M2的控制极耦接第二运放op2的输出端。第二晶体管M2的第一极耦接第二运放op2的反相输入端。第二晶体管M2的第二极耦接第三晶体管M3的控制极和第二极。第三晶体管M3的第一极耦接第一电压端V1。第四晶体管M4的控制极耦接第三晶体管M3的控制极。第四晶体管M4的第一极耦接第一电压端V1。第四晶体管M4的第二极耦接采样电压输出端。在该实施例中,第二运放op2的第一输入端是同相输入端。第二运放op2的第二输入端是反相输入端。
在本公开的一些实施例中,电压判断电路540可包括:电压比较器comp、以及反相器NG。其中,电压比较器comp的第一输入端耦接目标电阻器Rs的一端。电压比较器comp的第二输入端耦接参考电压端。电压比较器comp的输出端耦接反相器NG的输入端。从电压比较器comp的输出端输出第一选择信号hs。从反相器NG的输出端输出第二选择信号ls。在图5的示例中,电压比较器comp的第一输入端是同相输入端。电压比较器comp的第二输入端是反相输入端。第一选择信号hs和第二选择信号ls的有效电平是高电平。第一选择信号hs和第二选
择信号ls的无效电平是低电平。
在本公开的一些实施例中,第一运放选择电路550可包括:第一压控开关s1至第五压控开关s5。其中,第一压控开关s1的受控端被提供第一选择信号hs。第一压控开关s1的第一端耦接第二电阻器R2的第二端。第一压控开关s1的第二端耦接第一失调电流注入电路210的输出端。第二压控开关s2的受控端被提供第一选择信号hs。第二压控开关s2的第一端耦接第一电流采样电路320的输出端。第二压控开关s2的第二端耦接采样电压输出端。第三压控开关s3的受控端被提供第一选择信号hs。第三压控开关s3的第一端耦接第二运放op2的第一输入端。第三压控开关s3的第二端耦接第二电压端V2。第四压控开关s4的受控端被提供第一选择信号hs。第四压控开关s4的第一端耦接第二运放op2的第二输入端。第四压控开关s4的第二端耦接第二电压端V2。第五压控开关s5的受控端被提供第一选择信号hs。第五压控开关s5的第一端耦接第二运放op2的输出端。第五压控开关s5的第二端耦接第二电压端V2。
在本公开的一些实施例中,第二运放选择电路560可包括:第六压控开关s6、第七压控开关s7、以及第八压控开关s8。其中,第六压控开关s6的受控端被提供第二选择信号ls。第六压控开关s6的第一端耦接第一电阻器R1的第二端。第六压控开关s6的第二端耦接第二运放op2的第一输入端(例如,同相输入端)。第七压控开关s7的受控端被提供第二选择信号ls。第七压控开关s7的第一端耦接第二电阻器R2的第二端。第七压控开关s7的第二端耦接第二运放op2的第二输入端(例如,反相输入端)。第八压控开关s8的受控端被提供第二选择信号ls。第八压控开关s8的第一端耦接第二失调电流注入电路570的输出端。第八压控开关s8的第二端耦接第二运放op2的同相输入端。
在图2至图5的示例中,从第一电压端V1输入高电压信号,第二电压端V2接地。第一晶体管M1、第三晶体管M3和第四晶体管M4是PMOS晶体管。第二晶体管M2是NMOS晶体管。本领域技术人员应理解,基于上述发明构思对图2至图5所示的电路进行的变型也应落入本公开的保护范围之内。在该变型中,上述晶体管和电压端也可以具有与图2至图5所示的示例不同的设置。本领域技术人员应理解,图2至图5中的各个电路的内部结构是示例性的,它们还可以通过其他电路来实现。第一压控开关s1至第八压控开关s8可由开关晶体管来实现。
在图5的示例中,在目标电阻器Rs的一端的电压Vsenp高于或者等于参考电压Vref的情况下,第一选择信号hs处于高电平,第二选择信号ls处于低电平。第一选择信号hs控制
第一压控开关s1至第五压控开关s5闭合。因此,第一电流源耦接到第一运放op1的同相输入端。第一晶体管M1的第二极耦接到采样电压输出端。第二运放op2的两个输入端和输出端都接地,因此停止工作。第二晶体管M2的控制极接地,因此也停止工作。第二选择信号ls控制第六压控开关s6至第八压控开关s8断开。因此,第二运放op2的两个输入端与第一电阻器R1和第二电阻器R2的连接被断开,并且第二电流源与第二运放op2的连接也被断开。此时,图5的电路500可被等效成图3的电路300。
如上所述,可设置第一电阻器R1的电阻值R等于第二电阻器R2的电阻值R。根据运放的虚短虚断特性可知,第一运放op1的同相输入端的电压V+等于第一运放op1的反相输入端的电压V-。V-=Vsenp-R×(Iss+Io)。V+=Vsenn-R×(I1+Io)。因此,Vsenp-Vsenn=R×(Iss+Io)-R×(I1+Io)。又因为,Vsenp-Vsenn=IL×Rs。所以IL×Rs=R×Iss-R×I1。Iss=IL×Rs/R+I1。第一失调电流I1可根据实际应用来设置以使得在IL为负的情况下采样电流Iss为正。这样无论目标电流是正向电流还是负向电流,根据本公开的实施例的电路500都可以对目标电流进行准确的采样。采样电压Vsense=Iss×R3=IL×Rs×R3/R+I1×R3。
在目标电阻器Rs的一端的电压Vsenp低于参考电压Vref的情况下,第一选择信号hs处于低电平,第二选择信号ls处于高电平。第一选择信号hs控制第一压控开关s1至第五压控开关s5断开。因此,第一电流源与第一运放op1的连接断开。第一晶体管M1的第二极与采样电压输出端的连接也断开。第二选择信号ls控制第六压控开关s6至第八压控开关s8闭合。因此,第二运放op2的同相输入端耦接第一电阻器R1的第二端,第二运放op2的反相输入端耦接第二电阻器R2的第二端,并且第二电流源耦接第二运放op2的同相输入端。此时,图5的电路500可被等效成图4的电路400(只是其中一些元器件的名称不同)。
如上所述,可设置第一电阻器R1的电阻值R等于第二电阻器R2的电阻值R。根据运放的虚短虚断特性可知,第一运放op1的同相输入端的电压V+等于第一运放op1的反相输入端的电压V-。V-=Vsenp-R×(Iss-Io)。V+=Vsenn-R×(I2-Io)。因此,Vsenp-Vsenn=R×(Iss-Io)-R×(I2-Io)。又因为,Vsenp-Vsenn=IL×Rs。所以IL×Rs=R×Iss-R×I2。Iss=IL×Rs/R+I2。第二失调电流I2可根据实际应用来设置以使得在IL为负的情况下采样电流Iss为正。这样无论目标电流是正向电流还是负向电流,根据本公开的实施例的电路500都可以对目标电流进行准确的采样。采样电压Vsense=Iss×R3=IL×Rs×R3/R+I2×R3。
图6示出根据本公开的实施例的DC-DC变换器Conv的示意性框图。该DC-DC变换器Conv可包括图1至图5中的对流过目标电阻器的目标电流进行采样的电路(100、200、300、400
和500)中的任一个。
综上所述,根据本公开的实施例的对流过目标电阻器的目标电流进行采样的电路适用于目标电流在正向电流和负向电流之间切换的情况。进一步地,根据本公开的实施例的对流过目标电阻器的目标电流进行采样的电路还适用于目标电阻器的共模电压的变化范围较大的情况。根据本公开的实施例的DC-DC变换器可使用上述电路对电感电流进行采样,因此,根据本公开的实施例的DC-DC变换器对电感电流的采样能够更加准确。
除非上下文中另外明确地指出,否则在本文和所附权利要求中所使用的词语的单数形式包括复数,反之亦然。因而,当提及单数时,通常包括相应术语的复数。相似地,措辞“包含”和“包括”将解释为包含在内而不是独占性地。同样地,术语“包括”和“或”应当解释为包括在内的,除非本文中明确禁止这样的解释。在本文中使用术语“示例”之处,特别是当其位于一组术语之后时,所述“示例”仅仅是示例性的和阐述性的,且不应当被认为是独占性的或广泛性的。
适应性的进一步的方面和范围从本文中提供的描述变得明显。应当理解,本申请的各个方面可以单独或者与一个或多个其它方面组合实施。还应当理解,本文中的描述和特定实施例旨在仅说明的目的并不旨在限制本申请的范围。
以上对本公开的若干实施例进行了详细描述,但显然,本领域技术人员可以在不脱离本公开的精神和范围的情况下对本公开的实施例进行各种修改和变型。本公开的保护范围由所附的权利要求限定。
Claims (20)
- 一种对流过目标电阻器的目标电流进行采样的电路,包括:第一电阻器、第二电阻器、第一运放、第一失调电流注入电路、第一电流采样电路、以及采样电压输出电路,其中,所述第一电阻器的第一端耦接所述目标电阻器的第一端,所述第一电阻器的第二端耦接所述第一运放的第一输入端;所述第二电阻器的第一端耦接所述目标电阻器的第二端,所述第二电阻器的第二端耦接所述第一运放的第二输入端;所述第一失调电流注入电路被配置为向所述第一运放的同相输入端注入第一失调电流;所述第一电流采样电路耦接所述第一运放的输出端和反相输入端,并被配置为根据所述目标电流和所述第一失调电流来生成采样电流;所述采样电压输出电路被配置为根据所述采样电流来生成采样电压,并经由采样电压输出端输出所述采样电压;其中,所述第一运放的所述第一输入端和所述第二输入端中的一者是所述第一运放的同相输入端,另一者是所述第一运放的反相输入端。
- 根据权利要求1所述的电路,其中,所述第一运放的所述第一输入端是所述第一运放的反相输入端,所述第一运放的所述第二输入端是所述第一运放的同相输入端,所述第一电流采样电路包括:第一晶体管,其中,所述第一晶体管的控制极耦接所述第一运放的所述输出端,所述第一晶体管的第一极耦接所述第一运放的所述反相输入端,所述第一晶体管的第二极耦接所述采样电压输出端。
- 根据权利要求1所述的电路,其中,所述第一运放的所述第一输入端是所述第一运放的反相输入端,所述第一运放的所述第二输入端是所述第一运放的同相输入端,所述第一电流采样电路包括:第一晶体管、以及稳压二极管,其中,所述第一晶体管的控制极耦接所述第一运放的所述输出端,所述第一晶体管的第一极耦接所述第一运放的所述反相输入端,所述第一晶体管的第二极耦接所述采样电压输出端;所述稳压二极管的阳极耦接第二电压端,所述稳压二极管的阴极耦接所述第一晶体管的所述第二极。
- 根据权利要求1所述的电路,其中,所述第一运放的所述第一输入端是所述第一运放 的同相输入端,所述第一运放的所述第二输入端是所述第一运放的反相输入端,所述第一电流采样电路包括:第二晶体管、第三晶体管、以及第四晶体管,其中,所述第二晶体管的控制极耦接所述第一运放的所述输出端,所述第二晶体管的第一极耦接所述第一运放的所述反相输入端,所述第二晶体管的第二极耦接所述第三晶体管的控制极和第二极;所述第三晶体管的第一极耦接第一电压端;所述第四晶体管的控制极耦接所述第三晶体管的所述控制极,所述第四晶体管的第一极耦接所述第一电压端,所述第四晶体管的第二极耦接所述采样电压输出端。
- 根据权利要求1所述的电路,还包括:第二运放、第二失调电流注入电路、第二电流采样电路、电压判断电路、第一运放选择电路、以及第二运放选择电路,其中,所述电压判断电路被配置为根据所述目标电阻器的一端的电压和来自参考电压端的参考电压来生成第一选择信号和第二选择信号;所述第一运放选择电路被配置为:在所述第一选择信号处于无效电平的情况下,断开所述第一失调电流注入电路与所述第一运放的连接并断开所述第一电流采样电路与所述采样电压输出电路的连接;以及在所述第一选择信号处于有效电平的情况下,控制所述第二运放和所述第二电流采样电路停止工作;所述第二运放选择电路被配置为:在所述第二选择信号处于有效电平的情况下,使得所述第二失调电流注入电路耦接所述第二运放的同相输入端、使得所述第二运放的第一输入端耦接所述第一电阻器的所述第二端,使得所述第二运放的第二输入端耦接所述第二电阻器的所述第二端;所述第二失调电流注入电路被配置为:生成第二失调电流;所述第二电流采样电路耦接所述第二运放的输出端和反相输入端,并被配置为:根据所述目标电流和所述第二失调电流来生成采样电流。
- 根据权利要求5所述的电路,其中,所述第二运放的所述第一输入端是所述第二运放的同相输入端,所述第二运放的所述第二输入端是所述第二运放的反相输入端,所述第二电流采样电路包括:第二晶体管、第三晶体管、以及第四晶体管,其中,所述第二晶体管的控制极耦接所述第二运放的所述输出端,所述第二晶体管的第一极耦接所述第二运放的所述反相输入端,所述第二晶体管的第二极耦接所述第三晶体管的控制极和第二极;所述第三晶体管的第一极耦接第一电压端;所述第四晶体管的控制极耦接所述第三晶体管的所述控制极,所述第四晶体管的第一极耦接所述第一电压端,所述第四晶体管的第二极耦接所述采样电压输出端。
- 根据权利要求5所述的电路,其中,所述电压判断电路包括:电压比较器、以及反相器,其中,所述电压比较器的第一输入端耦接所述目标电阻器的一端,所述电压比较器的第二输入端耦接所述参考电压端,所述电压比较器的输出端耦接所述反相器的输入端;从所述电压比较器的所述输出端输出所述第一选择信号,从所述反相器的输出端输出所述第二选择信号。
- 根据权利要求5所述的电路,其中,所述第一运放选择电路包括:第一压控开关至第五压控开关,其中,所述第一压控开关的受控端被提供所述第一选择信号,所述第一压控开关的第一端耦接所述第二电阻器的所述第二端,所述第一压控开关的第二端耦接所述第一失调电流注入电路的输出端;第二压控开关的受控端被提供所述第一选择信号,所述第二压控开关的第一端耦接所述第一电流采样电路的输出端,所述第二压控开关的第二端耦接所述采样电压输出端;第三压控开关的受控端被提供所述第一选择信号,所述第三压控开关的第一端耦接所述第二运放的所述第一输入端,所述第三压控开关的第二端耦接第二电压端;第四压控开关的受控端被提供所述第一选择信号,所述第四压控开关的第一端耦接所述第二运放的所述第二输入端,所述第四压控开关的第二端耦接所述第二电压端;所述第五压控开关的受控端被提供所述第一选择信号,所述第五压控开关的第一端耦接所述第二运放的所述输出端,所述第五压控开关的第二端耦接所述第二电压端。
- 根据权利要求5所述的电路,其中,所述第二运放选择电路包括:第六压控开关、第七压控开关、以及第八压控开关,其中,所述第六压控开关的受控端被提供所述第二选择信号,所述第六压控开关的第一端耦接所述第一电阻器的所述第二端,所述第六压控开关的第二端耦接所述第二运放的所述第一输入端;所述第七压控开关的受控端被提供所述第二选择信号,所述第七压控开关的第一端耦接所述第二电阻器的所述第二端,所述第七压控开关的第二端耦接所述第二运放的所述第二输 入端;所述第八压控开关的受控端被提供所述第二选择信号,所述第八压控开关的第一端耦接所述第二失调电流注入电路的输出端,所述第八压控开关的第二端耦接所述第二运放的所述同相输入端。
- 根据权利要求2所述的电路,还包括:第二运放、第二失调电流注入电路、第二电流采样电路、电压判断电路、第一运放选择电路、以及第二运放选择电路,其中,所述电压判断电路被配置为根据所述目标电阻器的一端的电压和来自参考电压端的参考电压来生成第一选择信号和第二选择信号;所述第一运放选择电路被配置为:在所述第一选择信号处于无效电平的情况下,断开所述第一失调电流注入电路与所述第一运放的连接并断开所述第一电流采样电路与所述采样电压输出电路的连接;以及在所述第一选择信号处于有效电平的情况下,控制所述第二运放和所述第二电流采样电路停止工作;所述第二运放选择电路被配置为:在所述第二选择信号处于有效电平的情况下,使得所述第二失调电流注入电路耦接所述第二运放的同相输入端、使得所述第二运放的第一输入端耦接所述第一电阻器的所述第二端,使得所述第二运放的第二输入端耦接所述第二电阻器的所述第二端;所述第二失调电流注入电路被配置为:生成第二失调电流;所述第二电流采样电路耦接所述第二运放的输出端和反相输入端,并被配置为:根据所述目标电流和所述第二失调电流来生成采样电流。
- 根据权利要求10所述的电路,其中,所述第二运放的所述第一输入端是所述第二运放的同相输入端,所述第二运放的所述第二输入端是所述第二运放的反相输入端,所述第二电流采样电路包括:第二晶体管、第三晶体管、以及第四晶体管,其中,所述第二晶体管的控制极耦接所述第二运放的所述输出端,所述第二晶体管的第一极耦接所述第二运放的所述反相输入端,所述第二晶体管的第二极耦接所述第三晶体管的控制极和第二极;所述第三晶体管的第一极耦接第一电压端;所述第四晶体管的控制极耦接所述第三晶体管的所述控制极,所述第四晶体管的第一极耦接所述第一电压端,所述第四晶体管的第二极耦接所述采样电压输出端。
- 根据权利要求10所述的电路,其中,所述电压判断电路包括:电压比较器、以及反 相器,其中,所述电压比较器的第一输入端耦接所述目标电阻器的一端,所述电压比较器的第二输入端耦接所述参考电压端,所述电压比较器的输出端耦接所述反相器的输入端;从所述电压比较器的所述输出端输出所述第一选择信号,从所述反相器的输出端输出所述第二选择信号。
- 根据权利要求10所述的电路,其中,所述第一运放选择电路包括:第一压控开关至第五压控开关,其中,所述第一压控开关的受控端被提供所述第一选择信号,所述第一压控开关的第一端耦接所述第二电阻器的所述第二端,所述第一压控开关的第二端耦接所述第一失调电流注入电路的输出端;第二压控开关的受控端被提供所述第一选择信号,所述第二压控开关的第一端耦接所述第一电流采样电路的输出端,所述第二压控开关的第二端耦接所述采样电压输出端;第三压控开关的受控端被提供所述第一选择信号,所述第三压控开关的第一端耦接所述第二运放的所述第一输入端,所述第三压控开关的第二端耦接第二电压端;第四压控开关的受控端被提供所述第一选择信号,所述第四压控开关的第一端耦接所述第二运放的所述第二输入端,所述第四压控开关的第二端耦接所述第二电压端;所述第五压控开关的受控端被提供所述第一选择信号,所述第五压控开关的第一端耦接所述第二运放的所述输出端,所述第五压控开关的第二端耦接所述第二电压端。
- 根据权利要求10所述的电路,其中,所述第二运放选择电路包括:第六压控开关、第七压控开关、以及第八压控开关,其中,所述第六压控开关的受控端被提供所述第二选择信号,所述第六压控开关的第一端耦接所述第一电阻器的所述第二端,所述第六压控开关的第二端耦接所述第二运放的所述第一输入端;所述第七压控开关的受控端被提供所述第二选择信号,所述第七压控开关的第一端耦接所述第二电阻器的所述第二端,所述第七压控开关的第二端耦接所述第二运放的所述第二输入端;所述第八压控开关的受控端被提供所述第二选择信号,所述第八压控开关的第一端耦接所述第二失调电流注入电路的输出端,所述第八压控开关的第二端耦接所述第二运放的所述同相输入端。
- 根据权利要求3所述的电路,还包括:第二运放、第二失调电流注入电路、第二电流采样电路、电压判断电路、第一运放选择电路、以及第二运放选择电路,其中,所述电压判断电路被配置为根据所述目标电阻器的一端的电压和来自参考电压端的参考电压来生成第一选择信号和第二选择信号;所述第一运放选择电路被配置为:在所述第一选择信号处于无效电平的情况下,断开所述第一失调电流注入电路与所述第一运放的连接并断开所述第一电流采样电路与所述采样电压输出电路的连接;以及在所述第一选择信号处于有效电平的情况下,控制所述第二运放和所述第二电流采样电路停止工作;所述第二运放选择电路被配置为:在所述第二选择信号处于有效电平的情况下,使得所述第二失调电流注入电路耦接所述第二运放的同相输入端、使得所述第二运放的第一输入端耦接所述第一电阻器的所述第二端,使得所述第二运放的第二输入端耦接所述第二电阻器的所述第二端;所述第二失调电流注入电路被配置为:生成第二失调电流;所述第二电流采样电路耦接所述第二运放的输出端和反相输入端,并被配置为:根据所述目标电流和所述第二失调电流来生成采样电流。
- 根据权利要求15所述的电路,其中,所述第二运放的所述第一输入端是所述第二运放的同相输入端,所述第二运放的所述第二输入端是所述第二运放的反相输入端,所述第二电流采样电路包括:第二晶体管、第三晶体管、以及第四晶体管,其中,所述第二晶体管的控制极耦接所述第二运放的所述输出端,所述第二晶体管的第一极耦接所述第二运放的所述反相输入端,所述第二晶体管的第二极耦接所述第三晶体管的控制极和第二极;所述第三晶体管的第一极耦接第一电压端;所述第四晶体管的控制极耦接所述第三晶体管的所述控制极,所述第四晶体管的第一极耦接所述第一电压端,所述第四晶体管的第二极耦接所述采样电压输出端。
- 根据权利要求15所述的电路,其中,所述电压判断电路包括:电压比较器、以及反相器,其中,所述电压比较器的第一输入端耦接所述目标电阻器的一端,所述电压比较器的第二输入端耦接所述参考电压端,所述电压比较器的输出端耦接所述反相器的输入端;从所述电压比较器的所述输出端输出所述第一选择信号,从所述反相器的输出端输出所 述第二选择信号。
- 根据权利要求15所述的电路,其中,所述第一运放选择电路包括:第一压控开关至第五压控开关,其中,所述第一压控开关的受控端被提供所述第一选择信号,所述第一压控开关的第一端耦接所述第二电阻器的所述第二端,所述第一压控开关的第二端耦接所述第一失调电流注入电路的输出端;第二压控开关的受控端被提供所述第一选择信号,所述第二压控开关的第一端耦接所述第一电流采样电路的输出端,所述第二压控开关的第二端耦接所述采样电压输出端;第三压控开关的受控端被提供所述第一选择信号,所述第三压控开关的第一端耦接所述第二运放的所述第一输入端,所述第三压控开关的第二端耦接第二电压端;第四压控开关的受控端被提供所述第一选择信号,所述第四压控开关的第一端耦接所述第二运放的所述第二输入端,所述第四压控开关的第二端耦接所述第二电压端;所述第五压控开关的受控端被提供所述第一选择信号,所述第五压控开关的第一端耦接所述第二运放的所述输出端,所述第五压控开关的第二端耦接所述第二电压端。
- 一种对流过目标电阻器的目标电流进行采样的电路,包括:第一电阻器、第二电阻器、第三电阻器、第一运放、第二运放、第一晶体管至第四晶体管、第一电流源、第二电流源、电压比较器、反相器、以及第一压控开关至第八压控开关,其中,所述第一电阻器的第一端耦接所述目标电阻器的第一端,所述第一电阻器的第二端耦接所述第一运放的反相输入端;所述第二电阻器的第一端耦接所述目标电阻器的第二端,所述第二电阻器的第二端耦接所述第一运放的同相输入端;所述电压比较器的第一输入端耦接所述目标电阻器的一端,所述电压比较器的第二输入端耦接参考电压端,所述电压比较器的输出端耦接所述反相器的输入端;所述第一压控开关的受控端耦接所述电压比较器的所述输出端,所述第一压控开关的第一端耦接所述第二电阻器的所述第二端,所述第一压控开关的第二端耦接所述第一电流源;所述第一晶体管的控制极耦接所述第一运放的输出端,所述第一晶体管的第一极耦接所述第一运放的所述反相输入端,所述第一晶体管的第二极耦接第二压控开关的第一端;所述第二压控开关的受控端耦接所述电压比较器的所述输出端,所述第二压控开关的第二端耦接所述第三电阻器的第一端和采样电压输出端;第三压控开关的受控端耦接所述电压比较器的所述输出端,所述第三压控开关的第一端耦接所述第二运放的同相输入端,所述第三压控开关的第二端耦接第二电压端;第四压控开关的受控端耦接所述电压比较器的所述输出端,所述第四压控开关的第一端耦接所述第二运放的反相输入端,所述第四压控开关的第二端耦接所述第二电压端;第五压控开关的受控端耦接所述电压比较器的所述输出端,所述第五压控开关的第一端耦接所述第二运放的输出端,所述第五压控开关的第二端耦接所述第二电压端;第六压控开关的受控端耦接所述反相器的输出端,所述第六压控开关的第一端耦接所述第一电阻器的所述第二端,所述第六压控开关的第二端耦接所述第二运放的所述同相输入端;第七压控开关的受控端耦接所述反相器的所述输出端,所述第七压控开关的第一端耦接所述第二电阻器的所述第二端,所述第七压控开关的第二端耦接所述第二运放的所述反相输入端;所述第八压控开关的受控端耦接所述反相器的所述输出端,所述第八压控开关的第一端耦接所述第二电流源,所述第八压控开关的第二端耦接所述第二运放的所述同相输入端;第二晶体管的控制极耦接所述第二运放的所述输出端,所述第二晶体管的第一极耦接所述第二运放的所述反相输入端,所述第二晶体管的第二极耦接第三晶体管的控制极和第二极;所述第三晶体管的第一极耦接第一电压端;所述第四晶体管的控制极耦接所述第三晶体管的所述控制极,所述第四晶体管的第一极耦接所述第一电压端,所述第四晶体管的第二极耦接所述采样电压输出端;所述第三电阻器的第二端耦接所述第二电压端。
- 一种DC-DC变换器,包括:根据权利要求1所述的对流过目标电阻器的目标电流进行采样的电路,其中,所述目标电阻器是耦接在所述DC-DC变换器中的电感器与输出端之间的电阻器,所述目标电流是流过所述电感器的电感电流。
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Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20020180418A1 (en) * | 2001-05-30 | 2002-12-05 | Texas Instruments Incorporated | Current sense amplifier and method |
JP2004309193A (ja) * | 2003-04-03 | 2004-11-04 | Murata Mfg Co Ltd | 測定器の保護回路 |
CN102858049A (zh) * | 2011-06-30 | 2013-01-02 | 海洋王照明科技股份有限公司 | 一种过流保护采样电路、led驱动电路及led灯具 |
CN105675958A (zh) * | 2016-01-27 | 2016-06-15 | 佛山市南海区联合广东新光源产业创新中心 | 一种用于led芯片内电流检测的电路 |
CN108594004A (zh) * | 2018-07-09 | 2018-09-28 | 珠海市微半导体有限公司 | 双向电流检测电路和检测方法 |
CN115567055A (zh) * | 2022-09-23 | 2023-01-03 | 圣邦微电子(北京)股份有限公司 | 对流过目标电阻器的目标电流进行采样的电路 |
-
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-
2023
- 2023-04-25 WO PCT/CN2023/090712 patent/WO2024060614A1/zh unknown
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20020180418A1 (en) * | 2001-05-30 | 2002-12-05 | Texas Instruments Incorporated | Current sense amplifier and method |
JP2004309193A (ja) * | 2003-04-03 | 2004-11-04 | Murata Mfg Co Ltd | 測定器の保護回路 |
CN102858049A (zh) * | 2011-06-30 | 2013-01-02 | 海洋王照明科技股份有限公司 | 一种过流保护采样电路、led驱动电路及led灯具 |
CN105675958A (zh) * | 2016-01-27 | 2016-06-15 | 佛山市南海区联合广东新光源产业创新中心 | 一种用于led芯片内电流检测的电路 |
CN108594004A (zh) * | 2018-07-09 | 2018-09-28 | 珠海市微半导体有限公司 | 双向电流检测电路和检测方法 |
CN115567055A (zh) * | 2022-09-23 | 2023-01-03 | 圣邦微电子(北京)股份有限公司 | 对流过目标电阻器的目标电流进行采样的电路 |
Non-Patent Citations (1)
Title |
---|
YANG WEI-LI, ZHAO YE, HEI YONG: "A High-Low Side Current Sense Circuits for High Power LED Driver", WEIDIANZIXU YU JISUANJI - MICROELECTRONICS AND COMPUTER, WEI DIAN ZI XUE YU JI SUAN JI BIAN JI BU, CN, vol. 30, no. 1, 31 January 2013 (2013-01-31), CN , pages 94 - 99, XP009553411, ISSN: 1000-7180 * |
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