WO2024060365A1 - 字线驱动器以及存储装置 - Google Patents

字线驱动器以及存储装置 Download PDF

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Publication number
WO2024060365A1
WO2024060365A1 PCT/CN2022/129996 CN2022129996W WO2024060365A1 WO 2024060365 A1 WO2024060365 A1 WO 2024060365A1 CN 2022129996 W CN2022129996 W CN 2022129996W WO 2024060365 A1 WO2024060365 A1 WO 2024060365A1
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WIPO (PCT)
Prior art keywords
word line
holding transistor
transistor
line driver
main body
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PCT/CN2022/129996
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English (en)
French (fr)
Inventor
赵阳
车载龙
金成镇
韩东玄
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长鑫存储技术有限公司
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Publication of WO2024060365A1 publication Critical patent/WO2024060365A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/14—Word line organisation; Word line lay-out
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

Definitions

  • Embodiments of the present disclosure relate to the field of semiconductor technology, and in particular to a word line driver and a memory device.
  • Memory is a common semiconductor structure. As the size of semiconductor structures continues to shrink, more memories can be incorporated on the chip, thus helping to increase product capacity.
  • DRAM dynamic random access memory
  • data needs to be written to/from memory cells by using word lines and bit lines, and operates based on the voltage applied to the word lines.
  • a word line can be divided into multiple sub-word lines and drive each sub-word line by using a sub-word-line driver (SWD), where the sub-word-line driver can be set at in the word line driver circuit.
  • SWD sub-word-line driver
  • Embodiments of the present disclosure provide a word line driver and a memory device, which are at least beneficial to reducing the off-current of the holding transistor without increasing the layout area.
  • embodiments of the present disclosure provide a word line driver, including: a first sub-word line driver including a first holding transistor, the first holding transistor is configured to respond to a driving signal to The first word line provides a first preset voltage; the second sub-word line driver includes a second holding transistor, the second holding transistor is configured to provide the first word line to the second word line in response to the driving signal.
  • the first holding transistor and the second holding transistor include: an active region, the active region includes: a main body portion extending along the first direction and a portion adjacent to the main body portion And a protruding portion located on one side of the main body portion, the protruding portion has a first source region and a second source region; a gate electrode, the gate electrode is located at least in the main body portion and directly opposite the protruding portion.
  • a first drain region and a second drain region are respectively located on the main body portion on opposite sides of the gate electrode along the first direction; wherein, the first drain region, the gate electrode And the first source region is used to form the first holding transistor, and the second drain region, the gate electrode and the second source region are used to form the second holding transistor.
  • the first source region and the second source region are the same source region.
  • the active area further includes: a first recessed part, the first recessed part is located in the main body part and is away from the sidewall of the protruding part from the main body part and is close to the sidewall of the protruding part.
  • the direction of the protruding portion is recessed; the gate is also located directly above the first recessed portion.
  • the bottom surface of the first recessed portion facing the protruding portion is located directly under the gate.
  • the gate electrode covers the entire first recessed portion and also covers a partial area of the main body portion adjacent to the first recessed portion along the first direction.
  • the first recessed portion has two opposite end surfaces along the first direction; along the first direction, the main body portion adjacent to one of the end surfaces is covered by the gate.
  • the length is the first length
  • the length of the main body portion adjacent to the other end surface covered by the gate is the second length
  • the first length is equal to the second length
  • the gate includes a first part and a second part forming a T-shape, the first part being close to the protruding part relative to the second part, the first part being a T-shape
  • the lateral side of the first recessed portion is located within the orthographic projection of the second portion in the active area.
  • the shape of the orthographic projection of the gate on the active area includes a rectangle or an H-shape.
  • the active area further includes: a second recessed portion, the second recessed portion is located in the main body portion and extends away from the protruding portion from the main body portion toward the side wall of the protruding portion.
  • the direction of the outgoing portion is recessed, the second recessed portion is located between the first source region and the first drain region, and the second recessed portion and the protruding portion are located along the first direction.
  • the gate is also located directly above part of the second recessed portion; a third recessed portion, the third recessed portion is located in the main body portion, from the main body portion toward the side wall of the protruding portion
  • the third recessed portion is recessed in a direction away from the protruding portion, the third recessed portion is located between the second source region and the second drain region, and the third recessed portion and the protruding portion are located along the The first directions are staggered; the gate is also located directly above part of the third recessed portion.
  • the protruding portion includes: a first protruding portion and a second protruding portion located on opposite sides of the main body portion, wherein the first protruding portion has the first source area, the second protrusion has the second source area.
  • the first retention transistor and the second retention transistor constitute a retention transistor unit;
  • the word line driver includes a plurality of the retention transistor units; wherein the two retention transistor units are mirror-symmetric in a second direction, the second direction is perpendicular to the first direction, and the active areas corresponding to the two retention transistor units facing each other in the second direction share the same protrusion and the source area.
  • the first sub-word line driver further includes: a first pull-up transistor configured to pull up the first word line to a second preset voltage in response to a first enable signal provided by the first main word line, the second preset voltage being greater than the first preset voltage; a first pull-down transistor configured to pull down the first word line to the first preset voltage in response to the first enable signal provided by the first main word line; wherein the first pull-down transistor is arranged on a side of the first holding transistor away from the second holding transistor, and the first pull-down transistor is arranged adjacent to the first holding transistor; the second sub-word line driver further includes: a second pull-up transistor configured to pull up the second word line to a second preset voltage in response to a second enable signal provided by the second main word line, the second preset voltage being greater than the first preset voltage; a second pull-down transistor configured to pull down the second word line to the first preset voltage in response to the second enable signal provided by the second main word line; wherein the second pull-down transistor is
  • the first pull-down transistor and the first holding transistor share the first drain region; the second pull-down transistor and the second holding transistor share the second drain region.
  • both the first holding transistor and the second holding transistor are NMOS transistors.
  • another aspect of the present disclosure provides a memory device, including: a memory cell array including a plurality of memory cells, a plurality of word lines and a plurality of bit lines, and the memory cells are connected to corresponding The word line and the corresponding bit line; the word line driver provided in any of the above embodiments.
  • the word line driver provided by the embodiment of the present disclosure includes a first sub-word line driver having a first holding transistor and a second sub-word line driver having a second holding transistor, wherein the first source region of the first holding transistor is connected to the first holding transistor.
  • the length direction of the channel region between the drain regions is inclined relative to the extension direction of the active region, which increases the length of the channel region of the first holding transistor without increasing the layout area, thus helping to reduce the length of the first holding transistor.
  • the turn-off current of the transistor ensures that the first word line can be completely turned off. In other words, the first holding transistor can be used to completely pull down the first word line to the first preset voltage.
  • the length direction of the channel region between the second source region and the second drain region of the second retention transistor is tilted relative to the extension direction of the active region, so that the second retention transistor can be increased without increasing the layout area.
  • the length of the channel region of the transistor is conducive to reducing the turn-off current of the second holding transistor, thereby ensuring that the second word line can be completely turned off.
  • the second holding transistor can be used to completely pull down the second word line. to the first preset voltage.
  • Figure 1 is a schematic diagram of the layout structure of a word line driver
  • Figure 2 is a schematic circuit structure diagram of a word line driver provided by an embodiment of the present disclosure
  • 3 to 8 are schematic diagrams of various layout structures of word line drivers provided by embodiments of the present disclosure.
  • Figure 9 is a schematic diagram of another circuit structure of a word line driver provided by an embodiment of the present disclosure.
  • FIG. 10 is a schematic layout structure diagram of the word line driver corresponding to FIG. 9 .
  • the word line driver includes a plurality of sub-word line drivers, and each sub-word line driver includes a pull-down transistor and a holding transistor.
  • Figure 1 is a schematic layout structure diagram of a word line driver. Referring to Figure 1, the word line driver includes: a plurality of mutually independent active areas 10. Each active area 10 is used to define multiple pull-down transistors and multiple holding transistors.
  • the multiple pull-down transistors are marked by N12, N13, N16 and N17 respectively
  • the multiple holding transistors are marked by N23, N22, N26 and N27 respectively
  • N13 and N23 are used to form a sub-word line driver
  • N17 and N27 are used to To form a sub-word line driver
  • N12 and N22 are used to form a sub-word line driver
  • N16 and N26 are used to form a sub-word line driver.
  • N12 and N13 share the first gate 11 and belong to different active areas 10 respectively.
  • N23 and N27 belong to the same active area 10 and share the second gate 12.
  • N22 and N26 belong to the same active area 10 and share the third gate.
  • N16 and N17 belong to different active areas 10 and share the fourth gate 14; multiple conductive plugs 15, each conductive plug 15 is used to electrically connect the source or drain of the pull-down transistor, and electrically connect Hold the source or drain of the transistor.
  • the channel length of the retention transistor is determined by the length of the corresponding gate along the extension direction of the active area. In order to reduce the off-current of the retention transistor, the channel length can be made larger and the length of the corresponding gate along the extension direction can be increased. The length of the active area 10 in the extending direction. However, the area occupied by the gate electrode in the layout will also increase accordingly, which will result in a smaller area in the layout where the conductive plug 15 can be designed, and higher requirements on the photolithography process for forming the conductive plug 15, especially around the gate electrode 12. The formed area becomes smaller, which will increase the difficulty of the formation process of the conductive plug 15 in the area surrounded by the second gate electrode 12, and this method will also be limited by process limits.
  • FIG. 2 is a schematic circuit structure diagram of a word line driver provided by an embodiment of the present disclosure.
  • FIGS. 3 to 8 are schematic diagrams of various layout structures of the word line driver provided by an embodiment of the present disclosure.
  • the word line driver provided in the embodiment of the present disclosure includes: a first sub-word line driver SWD1, including a first holding transistor N23, the first holding transistor N23 is configured to provide a first preset voltage VL to the first word line WL3 in response to a driving signal; a second sub-word line driver SWD1, including a second holding transistor N27, the second holding transistor is configured to provide a first preset voltage VL to the second word line WL7 in response to a driving signal PXID; wherein the first holding transistor N23 and the second holding transistor N27 include: an active region 101, the active region 101 includes: a main body portion 111 extending along a first direction X and a portion of the main body portion 111 extending along a first direction X.
  • the direction from the first source region S11 to the first drain region D1 in the above embodiment is inclined relative to the first direction X, so that the first holding transistor N23 has a larger channel length, which is conducive to reducing the turn-off current of the first holding transistor N23, so that the first word line can be completely turned off.
  • the direction from the second source region S2 to the second drain region D2 is also inclined relative to the first direction X, which also makes the second holding transistor N27 have a larger channel length, which is conducive to reducing the turn-off current of the second holding transistor N27.
  • Active area 101 is the AA area, usually called Active Area.
  • the first source region S1 and the first drain region D1 are respectively used to define the source (source) and the drain (draini) of the first holding transistor N23; the second source region S2 and the second drain region D2 are respectively used to define the second Hold the source and drain of transistor N27.
  • the functions of the first holding transistor N23 include: after the first word line WL3 changes from the selected state (ie, the activated state) to the unselected state (ie, the closed state), the first holding transistor N23 can ensure that the voltage of the first word line WL3 is pulled down. to the first preset voltage VL to avoid the problem that the first word line WL3 cannot be completely turned off due to interference such as noise.
  • the functions of the second holding transistor N27 include: after the second word line WL7 changes from the selected state to the unselected state, the second holding transistor N27 can ensure that the voltage of the second word line WL7 is pulled down to the first preset voltage VL to avoid The second word line WL7 cannot be completely turned off due to interference such as noise.
  • the first source area S1 and the second source area S2 are both used to connect to a preset power supply.
  • the level of the preset power supply is the first preset voltage, or the level of the preset power supply is equivalent to the first preset voltage VL.
  • “equivalent” means that the difference between the level of the preset power supply and the first preset voltage VL is within the allowable range, and within this allowable range, the two levels can be considered to be the same.
  • the first source region S1 and the second source region S2 can be regarded as nodes with the same potential, that is, the first source region S1 and the second source region S2 are electrically connected.
  • the first source region S1 and the second source region S2 may be the same source region, that is, the first source region S1 and the second source region S2 are located in the same protrusion 121 and are the same source region, and the source region is indicated by S1/S2 in FIG3 .
  • the layout area can be saved and the area of the word line driver can be reduced;
  • the electrical connection between the first source region S1 and the second source region S2 can be realized by using the source region, and there is no need to form the contact structure and metal layer required for realizing the electrical connection, which is conducive to reducing the manufacturing difficulty of the word line driver and saving the manufacturing cost.
  • the solid line with arrows indicates the channel length direction of the first holding transistor and the channel length direction of the second holding transistor. Accordingly, a contact structure (LiCon, local interconnect contact) can be set in the same source region to serve as a source lead.
  • a contact structure LiCon, local interconnect contact
  • the first source region S1 and the second source region S2 may be in the same protrusion 121 , and the first source region S1 and the second source region S2 may be separated from each other.
  • the benefits of this arrangement include: the first source region S1 and the second source region S2 are separated from each other, and the respective doping concentrations of the first source region S1 and the second source region S2 can be different to satisfy the needs of the first holding transistor N23 and the second holding transistor N23.
  • the doping concentration refers to the doping concentration of N-type ions or P-type ions; in addition, the first holding transistor N23 has a first channel, and the second holding transistor N27 has a second channel, Since the first source region S1 and the second source region S2 are independent of each other, correspondingly, the first channel and the second channel can be independent of each other, which is beneficial to increasing the size of the first channel and the size of the second channel, and reducing the size of the first channel.
  • the carrier crowding effect of the first drain region D1 is reduced, and the carrier crowding effect of the second drain region D2 is reduced.
  • the first holding transistor N23 and the second holding transistor N27 may both be NMOS transistors, and the above doping concentration refers to the doping concentration of N-type ions.
  • the first source region S1 and the second source region can be realized by respectively arranging contact structures above the first source region S1 and the second source region S2 and a metal layer electrically connected to the two contact structures. Electrical connection for S2.
  • solid lines with arrows indicate the channel length direction of the first holding transistor and the channel length direction of the second holding transistor.
  • Figure 5 is a schematic diagram of a layout of a word line driver and a structural diagram of an active area.
  • the left diagram in Figure 5 is a diagram of a layout structure of a word line driver, and the diagram on the right side is a diagram of the active area in the left diagram. Schematic.
  • the active area 101 may further include: a first recess 131 located in the main body 111 and approaching from the side wall of the main body 111 away from the protruding part 121 .
  • the direction of the protruding portion 121 is concave.
  • the first recessed portion 131 is provided to reduce the conduction area between the first drain region D1 and the second drain region D2, which is beneficial to suppress leakage between the first drain region D1 and the second drain region D2.
  • the first drain region D1 may be electrically connected to the first word line WL3
  • the second drain region D2 may be electrically connected to the second word line WL7
  • the first recess 131 may be provided to reduce the size of the first word line WL3 to the second word line WL7. Leakage between wires WL7.
  • the word line driver may further include an isolation structure, and the isolation structure is filled in the first recess 131 .
  • the gate 102 can also be located directly above the first recess 131 , which is beneficial to increasing the volume of the gate 102 and reducing the resistance of the gate 102 .
  • the first recess 131 may be a square recess or an arc-shaped recess. In some embodiments, in the direction perpendicular to the first direction The recessed portion 131 is sufficient to suppress the leakage problem between the first drain region D1 and the second drain region D2, the first holding transistor N23 and the second holding transistor N27 have a relatively large saturation current Idast, and the first holding transistor N23
  • the second holding transistor N27 has a relatively small off-current Ioff, and the ratio of the first width W1 to the second width W2 is in the range of 0.3-0.7. In a specific example, the ratio of the first width W1 to the second width W2 is in the range of 0.4-0.6, for example, it can be 0.45, 0.5, or 0.55. This is beneficial to further ensuring a relatively large saturation current. Relatively small shutdown current Ioff.
  • the gate 102 may cover the entire first recessed portion 131 and also cover a portion of the main body portion 101 adjacent to the first recessed portion 131 along the first direction X. In other words, the first recessed portion 131 completely falls into the area covered by the gate electrode 102 .
  • the area covered by the gate electrode 102 is relatively large, so that the gate electrode 102 has a relatively large volume, which is beneficial to reducing the resistance of the gate electrode 102 .
  • the gate 102 covers the entire first recessed portion 131.
  • the gate 102 also covers a portion of the main body portion 111 adjacent to the first recessed portion 131, so that the first holding transistor N23 and The second holding transistors N27 each have a relatively large size, that is, the area of the active area occupied by the first holding transistor and the second holding transistor is relatively large, which is beneficial to increasing the saturation current.
  • the gate electrode 102 covers the entire first recessed portion 131 , so that the process of forming the gate electrode 102 has a relatively large process window, which is beneficial to reducing the difficulty of the formation process of the gate electrode 102 .
  • the first recess 131 may be filled with isolation structures.
  • the gate 102 can cover the bottom surface and side walls of the first recessed portion 131 . In this way, the bottom surface and sidewalls of the first recessed portion 131 covered by the gate electrode 102 will also serve as a part of the channel. Not only can The area of the channel controlled by the gate electrode 102 is increased, thereby improving the ability of the gate electrode 102 to control channel conduction. Moreover, since the gate conductive layer in the gate electrode 102 is correspondingly located in the first recessed portion 131, this can increase the gate conductivity. The volume of the electrode 102 further reduces the resistance of the gate 120 .
  • the channel includes a first channel corresponding to the first holding transistor N23 and a second channel corresponding to the second holding transistor N27;
  • the gate 102 includes a gate dielectric layer and a gate electrode located on the surface of the gate dielectric layer. layer, the gate electrode 102 covers the bottom surface and sidewalls of the first recessed portion 131 , which means that the gate dielectric layer is located on the bottom surface and sidewalls of the first recessed portion 131 , and the gate conductive layer is also located within the first recessed portion 131 .
  • the gate 102 can cover part of the bottom surface and part of the side surface.
  • the bottom of the gate 102 in the first recess 131 can be filled with an isolation structure; in another specific example, the gate 102 can cover the entire bottom surface and all top surfaces.
  • the gate 102 may only cover a part of the first recessed part 131 .
  • a part of the first recessed part 131 facing the protruding part 121 is covered by the gate 102 , while the first recessed part 131 The remaining area away from the protruding portion 121 is not covered by the gate electrode 102 .
  • the gate electrode 102 and the first recessed portion 131 may be completely offset.
  • the bottom surface of the first recessed portion 131 facing the protruding portion 121 may be located directly under the gate electrode 102 . In other embodiments, the bottom surface of the first recessed portion 131 facing the protruding portion 121 may also be flush with the side of the gate 102 away from the protruding portion 121 .
  • first recessed portion 131 may have two opposite end surfaces along the first direction X; along the first direction
  • the length of the main body portion 111 of one end surface covered by the gate 102 is the second length L2, and the first length L1 may be equal to the second length L2. That is to say, along the first direction mismatch.
  • the first length L1 may also be different from the second length L2.
  • the first length L1 may be smaller than or larger than the second length L1.
  • the gate 102 may include a first portion 112 and a second portion 122 that form a T shape.
  • the first portion 112 is close to the protruding portion 121 relative to the second portion 122 , and the first portion 112 serves as a T-shape. T-shaped horizontal edge. That is, the first part 112 serves as the "one" part of the T-shape, the second part 122 serves as the " ⁇ " part of the T-shape, and the T-shaped gate 102 increases the volume of the gate 102 to reduce the resistance of the gate 102.
  • the " ⁇ " portion can reserve space for forming contact structures on opposite sides along the first direction D2 electrical connection.
  • the first recessed portion 131 may be located within an orthographic projection of the second portion 122 in the active area 101 .
  • the first recessed portion 131 may have two opposite end surfaces along the first direction; along the first direction
  • the length of the main body part 111 of one end surface covered by the second part 122 is the second length L2, and the first length L1 may be equal to the second length L2.
  • the shape of the orthographic projection of the gate 102 on the active area 101 may also be rectangular or H-shaped.
  • the H-shaped gate 102 includes two opposite beams and a connecting portion between the beams, wherein the two beams are arranged along the first direction X, and the first recessed portion 131 can also be located at the connecting portion. Right below the top.
  • FIG6 is another schematic diagram of the layout structure of the word line driver.
  • the active area 101 may further include: a second recessed portion 141, which is located in the main body 111, and is recessed from the main body 111 toward the side wall of the protruding portion 121 in a direction away from the protruding portion 121, and is located between the first drain region D1 and the protruding portion 121, and the second recessed portion 141 and the protruding portion 121 are staggered along the first direction X.
  • the second recessed portion 141 may be located between the first source region S1 and the first drain region D1.
  • the provision of the second recessed portion 141 is beneficial to further increase the length of the channel region in the first holding transistor N23 and further reduce the turn-off current of the first holding transistor N23.
  • the active region 101 may further include: a third recessed portion 151, the third recessed portion 151 is located in the main body 111, is recessed from the main body 111 toward the sidewall of the protruding portion 121 in a direction away from the protruding portion 111, is located between the second drain region D2 and the protruding portion 121, and the third recessed portion 151 and the protruding portion 121 are staggered along the first direction X.
  • the third recessed portion 151 may also be located between the second source region S2 and the second drain region D2.
  • the provision of the third recessed portion 151 is conducive to further increasing the length of the channel region in the second holding transistor N27 and further reducing the turn-off current of the second holding transistor N27.
  • the gate 102 may also be located directly above part of the second recess 141 , and the gate 102 may also be located directly above part of the third recess 151 . In this way, it is beneficial to further increase the volume of the gate 102 and reduce the resistance of the gate 102 .
  • the active region 101 may include any one of the first recess 131 , the second recess 141 , or the third recess 151 , or a combination of more than one of the first recess 131 , the second recess 141 , or the third recess 151 .
  • Figure 7 is a schematic structural diagram of the active area 101 including the first recessed portion 131, the second recessed portion 141 and the third recessed portion 151.
  • the first recessed portion 131, the second recessed portion 151 and the third recessed portion 151 may be an arc-shaped recess, so that corner rounding (corner rouding) can be achieved to avoid problems such as corner tip discharge.
  • FIG. 8 is a schematic diagram of another layout structure of the word line driver.
  • the protruding part 121 may also include: a first protruding part 1 and a second protruding part 1 respectively located on opposite sides of the main body part 111 .
  • the protruding part 2 wherein the first protruding part 1 has a first source region S1, and the second protruding part 2 has a second source region S2.
  • the first source region S1 and the second source region S2 are respectively located in different protrusions 121, which can provide a larger process window for forming the first source region S1 and the second source region S2, and is conducive to increasing the number of The areas of the first source region S1 and the second source region S2 are thereby reduced in contact resistance of the first source region S1 and the second source region S2.
  • the active area 101 may include two second recessed portions 141 and two third recessed portions 151 .
  • a first recessed portion 141 is located between the first drain region D1 and the first protruding portion 1 .
  • another first recessed portion 141 is located between the first drain region D1 and the second protruding portion 2
  • a second recessed portion 151 is located between the second drain region D1 and the first protruding portion 1
  • another second recessed portion 151 is located between the second drain region D1 and the first protruding portion 1.
  • the recessed portion 151 is located between the second drain region D2 and the second protruding portion 2 .
  • the first sub-word line driver SWD1 may further include: a first pull-up transistor P13 configured to pull up the first word line WL3 to a second preset voltage PXID greater than the first preset voltage VL in response to a first enable signal provided by the first main word line MWLa; a first pull-down transistor N13 configured to pull down the first word line WL3 to the first preset voltage VL in response to the first enable signal provided by the first main word line MWLa.
  • the second sub-word line driver SWD2 may further include: a second pull-up transistor P17 configured to pull up the second word line WL7 to a second preset voltage PXID greater than the first preset voltage VL in response to a second enable signal provided by the second main word line MWLb; and a second pull-down transistor N17 configured to pull down the second word line WL7 to the first preset voltage VL in response to a second enable signal provided by the second main word line MWLb.
  • the word line driver further includes: a first pull-down gate 201, used as the gate of the first pull-down transistor N13; and a second pull-down gate 202, used as the gate of the second pull-down transistor N17.
  • the extension directions of the first pull-down gate 201 and the second pull-down gate 202 are both perpendicular to the first direction X.
  • the following uses the first sub-word line driver SWD1 as an example to explain the working principle of the first sub-word line driver SWD1:
  • the first enable signal includes a first state and a second state, and the level of the first state is different from the level of the second state; while the first enable signal is in the first state, the first sub-word line driver SWD11 receives With a valid driving signal, the first pull-up transistor P13 is turned on, and the first word line WL3 is pulled up to the second preset voltage PXID.
  • the voltage of the second preset voltage PXID is the same as or equivalent to the voltage of the driving signal; then, While the first enable signal is in the second state, the first pull-down transistor N13 is turned on, the first word line WL3 is pulled down to the first preset voltage VL, and the first holding transistor N23 is turned on, which is beneficial to further ensuring that the first One word line WL3 is pulled down to the first preset voltage VL to prevent signal noise from causing interference to the first word line WL3.
  • the working principle of the second sub-word line driver can refer to the working principle of the first sub-word line driver, which will not be repeated here.
  • the first pull-up transistor P13 and the second pull-up transistor P17 can both be PMOS transistors
  • the first pull-down transistor N13 and the second pull-down transistor N17 can both be NMOS transistors
  • the first holding transistor N23 and the second holding transistor N27 can both be NMOS transistors.
  • the first pull-down transistor N13 may be disposed on a side of the first holding transistor N23 away from the second holding transistor N27 , and the first pull-down transistor N13 may be disposed adjacent to the first holding transistor N23 .
  • the second pull-down transistor N17 may be disposed on a side of the second holding transistor N27 away from the first holding transistor N23, and the second pull-down transistor N17 may be disposed adjacent to the second holding transistor N27.
  • N13, N23, P13, N17, N27, and P17 are used to mark the channel region of each transistor corresponding to the active region in FIG. 3 .
  • the first pull-down transistor N13 and the first holding transistor N23 may share the first drain region D1. By sharing the first drain region D1, the drain of the first pull-down transistor and the drain of the first holding transistor are electrically connected. , there is no need to form additional contact structures and metal layers, which is beneficial to reducing the complexity of the layout structure.
  • the second pull-down transistor N17 and the second holding transistor N27 may share the second drain region D2. By sharing the second drain region D2, the drain of the second pull-down transistor and the drain of the second holding transistor are electrically connected without the need for The additional formation of contact structures and metal layers is beneficial to reducing the complexity of the layout structure.
  • FIG. 9 is a schematic diagram of another circuit structure of a word line driver provided by an embodiment of the present disclosure.
  • FIG. 10 is a schematic diagram of a layout structure of the word line driver corresponding to FIG. 9 .
  • the first holding transistor N23 and the second holding transistor N27 constitute the holding transistor unit 10;
  • the word line driver includes a plurality of holding transistor units 10; wherein, the two holding transistor units 10 are in The mirror images are opposite each other in the second direction Y, and the second direction Y is perpendicular to the first direction X.
  • the first holding transistors in different holding transistor units 10 are labeled with different reference numbers, including N20, N21, N22, N23, and different first holding transistors in the holding transistor units 10.
  • the first word lines connected to a holding transistor are marked with WL0, WL1, WL2, and WL3 respectively; the second holding transistors in different holding transistor units 10 are marked with different reference numbers, including N24, N25, N26, and N27, and The second word lines connected to different second holding transistors are marked with WL4, WL5, WL6, and WL7 respectively; different first pull-down transistors are marked with N10, N11, N12, and N13 respectively; different second pull-down transistors are marked with N14, N15, N16, and N17 are marked; different first pull-up transistors are marked with P10, P11, P12, and P13 respectively; different second pull-up transistors are marked with P14, P15, P16, and P17 respectively.
  • the active regions 101 corresponding to the two holding transistor units 10 facing each other in the second direction Y share the same protrusion 121, and the two holding transistor units 10 facing each other in the second direction Y may also share the source region.
  • the first holding transistor N23/N22 and the second holding transistor N27/N26 in the two holding transistor units 10 may share the same active region, that is, the four holding transistors share the same active region, and the active region is located at the same protrusion 121. In this way, it is beneficial to further save the layout area and reduce the complexity of the layout structure.
  • the two first holding transistors in the two holding transistor units 10 may share the same source region located on the same protrusion 121 , and the two second holding transistors and the first holding transistor do not share a source region.
  • the two second holding transistors of the two holding transistor units 10 may share the same source region located on the same protrusion 121 , and the two first holding transistors and the second holding transistor do not share the source region.
  • the word line driver may further include: a plurality of contact structures 105, each contact structure 105 being used to be electrically connected to the corresponding first source region S1, the second source region S2, the first drain region D1 or the second drain region D2, and further For electrical connection with the source region or the drain region of the first pull-down transistor, the second pull-down transistor, the first pull-up transistor and the second pull-up transistor.
  • the channel length direction of the two retention transistors is designed to be inclined relative to the extension direction of the active area 101. This can increase the length of the channel region of the retention transistors without increasing the layout area. Thereby, the turn-off current of the holding transistor is reduced, and the ability of the holding transistor to turn off the word line connected to the holding transistor is improved.
  • the length direction of the channel is inclined relative to the extension direction of the active area 101, which can also reserve more space for laying out the contact structure 105 and improve the space utilization of the layout.
  • embodiments of the present disclosure also provide a storage device, including the word line driver provided in the above embodiments.
  • the storage device provided by the embodiments of the present disclosure will be described in detail below. For parts that are the same as or corresponding to the previous embodiments, please refer to The detailed description of the foregoing embodiments will not be described again below.
  • the memory device includes: a memory cell array including a plurality of memory cells, a plurality of word lines and a plurality of bit lines, and the memory cells are connected to the corresponding word lines and the corresponding bit lines; the word lines provided in the above embodiments driver.
  • Each sub-word line driver in the word line driver is electrically connected to the corresponding word line, and is used to select/activate the corresponding word line or turn off the corresponding word line.
  • the storage device may be a DRAM storage system, such as a DDR5 DRAM storage system or a DDR4 DRAM storage system. In other embodiments, the storage device may also be an SRAM storage system, an SDRAM storage system, a ROM storage system or a flash memory storage system.

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Abstract

本公开实施例提供一种字线驱动器以及存储装置，字线驱动器包括：第一保持晶体管和第二保持晶体管；有源区，有源区包括：沿第一方向延伸的主体部以及与部分主体部相邻接且位于主体部一侧的凸出部，凸出部具有第一源区和第二源区；栅极，栅极至少位于主体部中与凸出部正对的部分区域上方；第一漏区以及第二漏区，分别位于栅极沿第一方向相对两侧的主体部；其中，第一漏区、栅极以及第一源区用于构成所述第一保持晶体管，第二漏区、栅极以及第二源区用于构成所述第二保持晶体管。

Description

字线驱动器以及存储装置
交叉引用
本公开要求于2022年09月19日递交的名称为“字线驱动器以及存储装置”、申请号为202211138984.0的中国专利申请的优先权，其通过引用被全部并入本公开。
技术领域
本公开实施例涉及半导体技术领域，特别涉及一种字线驱动器以及存储装置。
背景技术
存储器是一种常见的半导体结构，随着半导体结构尺寸的连续缩小，使得芯片上可以并入更多数量的存储器，从而有助于产品容量的增加。在动态随机存取存储器(dynamic random access memory，DRAM)中，需要通过使用字线和位线向/从存储器单元中写入/读取数据，并基于施加到字线的电压来操作。
随着DRAM容量的增大，连接到一个字线的存储器单元的数量增加，并且字线之间的距离缩小，可能发生速度延迟问题。为了改善字线电压的延迟，可以将一个字线划分成多个子字线并通过使用子字线驱动器(sub word-line driver，SWD)驱动每个子字线，其中，子字线驱动器可以设置在字线驱动电路中。
发明内容
本公开实施例提供一种字线驱动器以及存储装置，至少有利于在不增加版图面积的前提下降低保持晶体管的关断电流。
根据本公开一些实施例，本公开实施例一方面提供一种字线驱动器，包括：第一子字线驱动器，包括第一保持晶体管，所述第一保持晶体管被配置为，响应于驱动信号向第一字线提供第一预设电压；第二子字线驱动器，包括第二保持晶体管，所述第二保持晶体管被配置为，响应于所述驱动信号向第二字线提供所述第一预设电压；其中，所述第一保持晶体管以及所述第二保持晶体管包括：有源区，所述有源区包括：沿第一方向延伸的主体部以及与部分所述主体部相邻接且位于所述主体部一侧的凸出部，所述凸出部具有第一源区和第二源区；栅极，所述栅极至少位于所述主体部中与所述凸出部正对的部分区域上方；第一漏区以及第二漏区，分别位于所述栅极沿所述第一方向相对两侧的所述主体部；其中，所述第一漏区、所述栅极以及所述第一源区用于构成所述第一保持晶体管，所述第二漏区、所述栅极以及所述第二源区用于构成所述第二保持晶体管。
在一些实施例中，所述第一源区和所述第二源区为同一源区。
在一些实施例中，所述有源区还包括：第一凹陷部，所述第一凹陷部位于所述主体部内，且自所述主体部远离所述凸出部的侧壁向靠近所述凸出部的方向凹陷；所述栅极还位于所述第一凹陷部正上方。
在一些实施例中，所述第一凹陷部朝向所述凸出部的底面位于所述栅极正下方。
在一些实施例中，所述栅极覆盖整个所述第一凹陷部，且还覆盖在沿所述第一方向上与所述第一凹陷部邻近的所述主体部的部分区域。
在一些实施例中，所述第一凹陷部具有沿所述第一方向相对的两个端面；在沿所述第一方向上，邻近一所述端面的所述主体部被所述栅极覆盖的长度为第一长度，邻近另一所述端面的所述主体部被所述栅极覆盖的长度为第二长度，所述第一长度与所述第二长度相等。
在一些实施例中，所述栅极包括构成T型的第一部和第二部，所述第一部相对于所述第二部靠近所述凸出部，所述第一部作为T型的横边；所述第一凹陷部位于所述第二部在所述有源区的正投影内。
在一些实施例中，所述栅极在所述有源区上的正投影的形状包括矩形或者H形。
在一些实施例中，所述有源区还包括：第二凹陷部，所述第二凹陷部位于所述主体部内，自所述主体部朝向所述凸出部的侧壁向远离所述凸出部的方向凹陷，所述第二凹陷部位于所述第一源区与所述第一漏区之间，且所述第二凹陷部与所述凸出部在沿所述第一方向上相错开；所述栅极还位于部分所述第二凹陷部正上方；第三凹陷部，所述第三凹陷部位于所述主体部内，自所述主体部朝向所述凸出部的侧壁向远离所述凸出部的方向凹陷，所述第三凹陷部位于所述第二源区与所述第二漏区之间，且所述第三凹陷部与所述凸出部在沿所述第一方向相错开；所述栅极还位于部分所述第三凹陷部正上方。
在一些实施例中，所述凸出部包括：分别位于所述主体部相对两侧的第一凸出部和第二凸出部，其中，所述第一凸出部具有所述第一源区，所述第二凸出部具有所述第二源区。
在一些实施例中，所述第一保持晶体管以及所述第二保持晶体管构成保持晶体管单元；所述字线驱动器包括多个所述保持晶体管单元；其中，两个所述保持晶体管单元在第二方向上镜像对称，所述第二方向与所述第一方向相垂直，在所述第二方向上正对的两个所述保持晶体管单元对应的所述有源区共用同一所述凸出部，且共用所述源区。
在一些实施例中，所述第一子字线驱动器还包括：第一上拉晶体管，被配置为，响应于第一主字线提供的第一使能信号，将所述第一字线上拉至第二预设电压，所述第二预设电压大于所述第一预设电压；第一下拉晶体管，被配置为，响应于所述第一主字线提供的所述第一使能信号，将所述第一字线下拉至所述第一预设电压；其中，所述第一下拉晶体管设置 在所述第一保持晶体管远离所述第二保持晶体管的一侧，且所述第一下拉晶体管与所述第一保持晶体管邻近设置；所述第二子字线驱动器还包括：第二上拉晶体管，被配置为，响应于第二主字线提供的第二使能信号，将所述第二字线上拉至第二预设电压，所述第二预设电压大于所述第一预设电压；第二下拉晶体管，被配置为，响应于所述第二主字线提供的所述第二使能信号，将所述第二字线下拉至所述第一预设电压；其中，所述第二下拉晶体管设置在所述第二保持晶体管远离所述第一保持晶体管的一侧，且所述第二下拉晶体管与所述第二保持晶体管邻近设置。
在一些实施例中，所述第一下拉晶体管与所述第一保持晶体管共用所述第一漏区；所述第二下拉晶体管与所述第二保持晶体管共用所述第二漏区。
在一些实施例中，所述第一保持晶体管以及所述第二保持晶体管均为NMOS晶体管。
根据本公开一些实施例，本公开实施例另一方面提供一种存储装置，包括：包括多个存储单元的存储单元阵列，多条字线以及多条位线，且所述存储单元连接相应的所述字线以及相应的所述位线；上述任一实施例提供的字线驱动器。
本公开实施例提供的技术方案至少具有以下优点：
本公开实施例提供的字线驱动器包括具有第一保持晶体管的第一子字线驱动器和具有第二保持晶体管的第二子字线驱动器，其中，第一保持晶体管的第一源区与第一漏区之间的沟道区的长度方向相对于有源区的延伸方向倾斜，在不增加版图面积的前提下即可增加第一保持晶体管的沟道区的长度，从而有利于降低第一保持晶体管的关断电流，进而保证第一字线可以被完全关断，换句话说，利用第一保持晶体管可以第一字线彻底下拉至第一预设电压。同理，第二保持晶体管的第二源区与第二漏区之间的沟道区的长度方向相对于有源区的延伸方向倾斜，在不增加版图面积的前提下即可增加第二保持晶体管的沟道区的长度，从而有利于降低第二保持晶体管的关断电流，进而保证第二字线可以被完全关断，换句话说，利用第二保持晶体管可以将第二字线彻底下拉至第一预设电压。
附图说明
一个或多个实施例通过与之对应的附图中的图片进行示例性说明，这些示例性说明并不构成对实施例的限定，附图中具有相同参考数字标号的元件表示为类似的元件，除非有特别申明，附图中的图不构成比例限制；为了更清楚地说明本公开实施例或传统技术中的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为一种字线驱动器的版图结构示意图；
图2为本公开实施例提供的字线驱动器的一种电路结构示意图；
图3至图8为本公开实施例提供的字线驱动器的多种不同的版图结构示意图；
图9为本公开实施例提供的字线驱动器的另一种电路结构示意图；
图10为图9对应的字线驱动器的一种版图结构示意图。
具体实施方式
字线驱动器包括多个子字线驱动器，每一子字线驱动器包括一下拉晶体管以及一保持晶体管。图1为一种字线驱动器的版图结构示意图，参考图1，字线驱动器包括：多个相互分立的有源区10，每一有源区10用于定义多个下拉晶体管以及多个保持晶体管，其中，多个下拉晶体管分别由N12、N13、N16和N17标示，多个保持晶体管分别由N23、N22、N26和N27标示，N13和N23用于构成一子字线驱动器，N17和N27用于构成一子字线驱动器，N12和N22用于构成一子字线驱动器，N16和N26用于构成一子字线驱动器。N12和N13共用第一栅极11且分属于不同有源区10，N23和N27属于同一有源区10且共用第二栅极12，N22和N26属于同一有源区10且共用第三栅极13，N16和N17分属于不同于有源区10且共用第四栅极14；多个导电插塞15，每一导电插塞15分别用于电连接下拉晶体管的源极或者漏极，电连接保持晶体管的源极或者漏极。
保持晶体管的沟道长度由对应的栅极在沿有源区的延伸方向的长度决定，为了减小保持晶体管的关断电流，可以将该沟道长度做大，且增加对应的栅极在沿有源区10的延伸方向的长度。然而，栅极占据版图的面积也会相应增加，这将导致版图中可设计导电插塞15的区域变小，对形成导电插塞15的光刻工艺的要求也更高，尤其栅极12围成的区域变小，相应会增加第二栅极12围成的区域内的导电插塞15的形成工艺难度，且这种方式还会受到工艺极限的限制。
下面将结合附图对本公开的各实施例进行详细的阐述。然而，本领域的普通技术人员可以理解，在本公开各实施例中，为了使读者更好地理解本公开而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施例的种种变化和修改，也可以实现本公开所要求保护的技术方案。
图2为本公开实施例提供的字线驱动器的一种电路结构示意图，图3至图8为本公开实施例提供的字线驱动器的多种不同的版图结构示意图。
结合参考图2至图8，本公开实施例提供的字线驱动器包括：第一子字线驱动器 SWD1，包括第一保持晶体管N23，第一保持晶体管N23被配置为，响应于驱动信号向第一字线WL3提供第一预设电压VL；第二子字线驱动器SWD1，包括第二保持晶体管N27，第二保持晶体管被配置为，响应于驱动信号PXID向第二字线WL7提供第一预设电压VL；其中，第一保持晶体管N23以及第二保持晶体管N27包括：有源区101，有源区101包括：沿第一方向X延伸的主体部111以及与部分主体部111相邻接且位于主体部111一侧的凸出部121，凸出部121具有第一源区S1和第二源区S2；栅极102，栅极102至少位于主体部111中与凸出部121正对的部分区域上方；第一漏区D1以及第二漏区D2，分别位于栅极102沿第一方向相对两侧的主体部111；其中，第一漏区D1、栅极102以第一源区S1D用于构成第一保持晶体管N23，第二漏区D2、栅极102以及第二源区S2用于构成第二保持晶体管N27。
上述实施例中，由于第一保持晶体管N23的第一源区S1位于凸出部121，且凸出部121位于主体部111沿第一方向X延伸的外侧，即第一漏区D1和第一源区S1并非沿第一方向X排布，使得相较于第一漏区和第一源区位于栅极沿第一方向相对两侧的方案而言，上述实施例中第一源区S11至第一漏区D1的方向相对于第一方向X倾斜，使得第一保持晶体管N23具有更大的沟道长度，从而有利于降低第一保持晶体管N23的关断电流，使得第一字线能够被彻底关断。同理，上述实施例中第二源区S2至第二漏区D2的方向也相对于第一方向X倾斜，也使得第二保持晶体管N27具有更大的沟道长度，从而有利于降低第二保持晶体管N27的关断电流。
以下将结合附图对本公开实施例提供的字线驱动器进行更为详细的说明。
有源区101即为AA区，通常称为Active Area。第一源区S1和第一漏区D1分别用于定义第一保持晶体管N23的源极(source)和漏极(draini)；第二源区S2和第二漏区D2分别用于定义第二保持晶体管N27的源极和漏极。
第一保持晶体管N23的作用包括，在第一字线WL3由选中状态(即激活状态)变为未选中状态(即关闭状态)后，第一保持晶体管N23可以保证第一字线WL3的电压下拉至第一预设电压VL，避免由于噪声等干扰导致的第一字线WL3无法完全关闭的问题。第二保持晶体管N27的作用包括，在第二字线WL7由选中状态变为未选中状态后，第二保持晶体管N27可以保证第二字线WL7的电压下拉至第一预设电压VL，避免由于噪声等干扰导致的第二字线WL7无法完全关闭的问题。
第一源区S1和第二源区S2均用于连接预设电源，该预设电源的电平为第一预设电压，或者，该预设电源的电平与第一预设电压VL相当，可以理解的是，即“相当”指的是，预设电源的电平与第一预设电压VL的差值在允许范围内，在这一允许范围内可认为二者的电平相同。换句话说，在字线驱动器对应的电路中，第一源区S1和第二源区S2可认为具有相同电位的节点，即第一源区S1和第二源区S2电连接。
在一些实施例中，参考图3，第一源区S1和第二源区S2可以同一源区，即，第一源区S1和第二源区S2位于同一凸出部121且为同一源区，图3中以S1/S2标示该源区。如此，一方面可以节约版图(layout)面积，减小字线驱动器的面积；另一方面，利用源区即可实现第一源区S1和第二源区S2的电连接，无需形成为实现电连接所需的接触结构和金属层，有利于降低字线驱动器的制造难度，节约制造成本。图3中以带箭头的实线指示出了第一保持晶体管的沟道长度方向以及第二保持晶体管的沟道长度方向。相应的，在该同一源区可以设置接触结构(LiCon，local interconnect contact)，以作为源极引出端。
在另一些实施例中，参考图4，第一源区S1和第二源区S2可以处于同一凸出部121，且第一源区S1和第二源区S2可以相互分立。这样设置的好处包括：第一源区S1和第二源区S2相互分立，第一源区S1和第二源区S2各自的掺杂浓度可以不同，以满足第一保持晶体管N23和第二保持晶体管N27各自的电性需求，掺杂浓度指的是N型离子或者P型离子的掺杂浓度；另外，第一保持晶体管N23具有第一沟道，第二保持晶体管N27具有第二沟道，由于第一源区S1和第二源区S2相互独立，相应的，第一沟道与第二沟道可以相互独立，有利于增加第一沟道的尺寸以及第二沟道的尺寸，且减小第一漏区D1的载流子拥挤效应，减小第二漏区D2的载流子拥挤效应。在一个具体例子中，第一保持晶体管N23和第二保持晶体管N27可以均为NMOS管，则上述掺杂浓度指的是N型离子的掺杂浓度。可以理解的是，可以通过在第一源区S1和第二源区S2上方分别设置接触结构以及与这两个接触结构电连接的金属层的方式，实现第一源区S1和第二源区S2的电连接。图4中以带箭头的实线指示出了第一保持晶体管的沟道长度方向以及第二保持晶体管的沟道长度方向。
图5为字线驱动器的一种版图以及有源区的结构示意图，其中，图5中左侧图为字线驱动器的一种版图结构示意图，右侧图为左侧图中的有源区的结构示意图。参考图5，在一些实施例中，有源区101还可以包括：第一凹陷部131，第一凹陷部131位于主体部111内，且自主体部111远离凸出部121的侧壁向靠近凸出部121的方向凹陷。设置第一凹陷部131，使得第一漏区D1与第二漏区D2之间的导通面积变小，从而有利于抑制第一漏区D1与第二漏区D2之间的漏电。另外，第一漏区D1可以与第一字线WL3电连接，第二漏区D2可以与第二字线WL7电连接，设置第一凹陷部131可以减小第一字线WL3到第二字线WL7之间的漏电。可以理解的是，字线驱动器还可以包括：隔离结构，且隔离结构填充于第一凹陷部131内。
此外，在一些实施例中，栅极102还可以位于第一凹陷部131正上方，有利于增加栅极102的体积，减小栅极102电阻。
第一凹陷部131可以为方形凹陷或者弧形凹陷。在一些实施例中，在垂直于第一方向X1的方向上，定义第一凹陷部131的最大凹陷深度为第一宽度W1，定义主体部111的最大 宽度为第二宽度W2，为保证第一凹陷部131具有足够的抑制第一漏区D1与第二漏区D2之间的漏电问题，第一保持晶体管N23和第二保持晶体管N27具有相对较大的饱和电流Idast，且第一保持晶体管N23和第二保持晶体管N27具有相对较小的关断电流Ioff，第一宽度W1与第二宽度W2的比值在0.3-0.7范围内。在一个具体例子中，第一宽度W1与第二宽度W2的比值在0.4-0.6范围内，例如可以为0.45、0.5、0.55，如此，有利于进一步在保证具有相对较大饱和电流的前提下保证相对较小的关断电流Ioff。
在一些实施例中，栅极102可以覆盖整个第一凹陷部131，且还覆盖在沿第一方向X上与第一凹陷部131邻近的主体部101的部分区域。换句话说，第一凹陷部131完全落入栅极102所覆盖的区域内。一方面，栅极102覆盖的区域相对较大，使得栅极102具有相对较大的体积，有利于减小栅极102的电阻。另一方面，栅极102覆盖整个第一凹陷部131，在满足此位置关系的前提下，栅极102还会覆盖邻近第一凹陷部131的部分主体部111，可以使得第一保持晶体管N23和第二保持晶体管N27均具有相对较大的尺寸，即第一保持晶体管和第二保持晶体管占据的有源区的面积相对较大，有利于提高饱和电流。此外，栅极102覆盖整个第一凹陷部131，使得形成栅极102的工艺具有相对较大的工艺窗口，有利于降低栅极102的形成工艺难度。
在一些实施例中，第一凹陷部131内可以填充满隔离结构。在另一些实施例中，栅极102可以覆盖第一凹陷部131的底面和侧面，这样，被栅极102覆盖的第一凹陷部131的底面和侧壁也将作为沟道的一部分，不仅可以增加受到栅极102控制的沟道的面积，从而提高栅极102控制沟道导通的能力，而且由于栅极102中的栅导电层还相应的位于第一凹陷部131内，如此可以增加栅极102的体积，进一步降低栅极120的电阻。可以理解的是，沟道包括与第一保持晶体管N23对应的第一沟道以及与第二保持晶体管N27对应的第二沟道；栅极102包括栅介质层以及位于栅介质层表面的栅电极层，栅极102覆盖第一凹陷部131的底面和侧壁，指的是栅介质层位于第一凹陷部131的底面和侧壁，且栅导电层还位于第一凹陷部131内。
在一个具体例子中，栅极102可以覆盖部分底面和部分侧面，相应的，第一凹陷部131内的栅极102下方可以填充有隔离结构；在另一个具体例子中，栅极102可以覆盖全部底面和全部顶面。
在另一些实施例中，栅极102也可以仅覆盖第一凹陷部131的部分区域，例如，第一凹陷部131朝向凸出部121的部分区域被栅极102覆盖，而第一凹陷部131远离凸出部121的其余部分区域未被栅极102覆盖。或者，栅极102与第一凹陷部131也可以完全错开。
在一些实施例中，第一凹陷部131朝向凸出部121的底面可以位于栅极102正下方。在另一些实施例中，第一凹陷部131朝向凸出部121的底面也可以与栅极102远离凸出部121 的侧面齐平。
另外，第一凹陷部131可以具有沿第一方向X相对的两个端面；在沿第一方向X上，邻近一端面的主体部111被栅极102覆盖的长度为第一长度L1，邻近另一端面的主体部111被栅极102覆盖的长度为第二长度L2，第一长度L1可以与所述第二长度L2相等。也就是说，在沿第一方向X上，第一凹陷部131位于栅极102的正中间位置，这样，有利于提高第一保持晶体管N23和第二保持晶体管N27的对称性，减小不同晶体管的失配。
可以理解的是，在其他实施例中，第一长度L1也可以与第二长度L2不同，例如第一长度L1可以小于或大于第二长度L1。
在一些实施例中，参考图4，栅极102可以包括构成T型的第一部112和第二部122，第一部112相对于第二部122靠近凸出部121，第一部112作为T型的横边。即，第一部112作为T型的“一”部，第二部122作为T型的“丨”部，T型的栅极102，在增加栅极102体积以减小栅极102的电阻的同时，“丨”部在沿第一方向X相对两侧可以为形成接触结构预留空间位置，一接触结构用于与第一漏区D1电连接，另一接触结构用于与第二漏区D2电连接。
第一凹陷部131可以位于第二部122在有源区101的正投影内。另外，第一凹陷部131可以具有沿第一方向相对的两个端面；在沿第一方向X上，邻近一端面的主体部111被第二部122覆盖的长度为第一长度L1，邻近另一端面的主体部111被第二部122覆盖的长度为第二长度L2，第一长度L1可以与所述第二长度L2相等。
在另一些实施例中，栅极102在有源区101上的正投影的形状也可以为矩形或者H形。在一个具体例子中，H形的栅极102包括两个相对的横梁以及位于横梁之间的连接部，其中，两个横梁沿第一方向X排布，且第一凹陷部131还可以位于连接部的正下方。
图6为字线驱动器的另一种版图结构示意图，参考图6，有源区101还可以包括：第二凹陷部141，第二凹陷部141位于主体部111内，自主体部111朝向凸出部121的侧壁向远离凸出部121的方向凹陷，位于第一漏区D1与凸出部121之间，且第二凹陷部141与凸出部121在沿第一方向上X相错开。其中，第二凹陷部141可以位于第一源区S1与第一漏区D1之间。
第二凹陷部141的设置，有利于进一步增加第一保持晶体管N23中沟道区的长度，进一步降低第一保持晶体管N23的关断电流。
继续参考图6，有源区101还可以包括：第三凹陷部151，第三凹陷部151位于主体部111内，自主体部111朝向凸出部121的侧壁向远离凸出部111的方向凹陷，位于第二漏区D2与凸出部121之间，且第三凹陷部151与凸出部121在沿第一方向X相错开。其中， 第三凹陷部151还可以位于第二源区S2与第二漏区D2之间。
第三凹陷部151的设置，有利于进一步增加第二保持晶体管N27中沟道区的长度，进一步降低第二保持晶体管N27的关断电流。
继续参考图6，栅极102还可以位于部分第二凹陷部141正上方，且栅极102还可以位于部分第三凹陷部151正上方。如此，有利于进一步增加栅极102的体积，减小栅极102的电阻。
可以理解的是，在一个具体例子中，有源区101可以包括第一凹陷部131、第二凹陷部141或者第三凹陷部151中的任一个或者多个的组合。
图7为包括第一凹陷部131、第二凹陷部141以及第三凹陷部151的有源区101的一种结构示意图，参考图7，在一些实施例中，第一凹陷部131、第二凹陷部141和第三凹陷部151中的至少一者可以为弧形凹陷，这样，可以实现拐角圆润化(corner rouding)，以避免拐角尖端放电等问题。
图8为字线驱动器的另一种版图结构示意图，参考图8，在一些实施例中，凸出部121还可以包括：分别位于主体部111相对两侧的第一凸出部1和第二凸出部2，其中，第一凸出部1具有第一源区S1，第二凸出部2具有第二源区S2。也就是说，第一源区S1和第二源区S2分别位于不同的凸出部121内，可以为形成第一源区S1和第二源区S2提供较大的工艺窗口，且有利于增加第一源区S1和第二源区S2的面积，从而减小第一源区S1和第二源区S2的接触电阻。
相应的，参考图8，有源区101可以包括两个第二凹陷部141和两个第三凹陷部151，一第一凹陷部141位于第一漏区D1与第一凸出部1之间，另一第一凹陷部141位于第一漏区D1与第二凸出部2之间，一第二凹陷部151位于第二漏区D1与第一凸出部1之间，另一第二凹陷部151位于第二漏区D2与第二凸出部2之间。
参考图2至图7，第一子字线驱动器SWD1还可以包括：第一上拉晶体管P13，被配置为，响应于第一主字线MWLa提供的第一使能信号，将第一字线WL3上拉至第二预设电压PXID，第二预设电压PXID大于第一预设电压VL；第一下拉晶体管N13，被配置为，响应于第一主字线MWLa提供的第一使能信号，将第一字线WL3下拉至第一预设电压VL。第二子字线驱动器SWD2还包括：第二上拉晶体管P17，被配置为，响应于第二主字线MWLb提供的第二使能信号，将第二字线WL7上拉至第二预设电压PXID，第二预设电压PXID大于第一预设电压VL；第二下拉晶体管N17，被配置为，响应于第二主字线MWLb提供的第二使能信号，将第二字线WL7下拉至第一预设电压VL。相应的，字线驱动器还包括：第一下拉栅极201，用于作为第一下拉晶体管N13的栅极；第二下拉栅极202，用于作为第二下拉晶体管N17的栅极。其中，第一下拉栅极201以及第二下拉栅极202的延伸方向均与第一 方向X垂直。
以下将以第一子字线驱动器SWD1为例对第一子字线驱动器SWD1的工作原理进行说明：
第一使能信号包括第一状态和第二状态，第一状态的电平与第二状态的电平不同；在第一使能信号处于第一状态期间，第一子字线驱动器SWD11接收到有效的驱动信号，第一上拉晶体管P13导通，则第一字线WL3被上拉至第二预设电压PXID，第二预设电压PXID的电压与驱动信号的电压相同或者相当；接着，在第一使能信号处于第二状态期间，第一下拉晶体管N13导通，第一字线WL3被下拉至第一预设电压VL，且第一保持晶体管N23导通，有利于进一步保证第一字线WL3被下拉至第一预设电压VL，避免信号噪声对第一字线WL3造成干扰。
有关第二子字线驱动器的工作原理可参考第一子字线驱动器的工作原理，在此不再赘述。在一个具体例子中，第一上拉晶体管P13和第二上拉晶体管P17可以均为PMOS管，第一下拉晶体管N13和第二下拉晶体管N17可以均为NMOS管。第一保持晶体管N23和第二保持晶体管N27可以均为NMOS管。
参考图3，在一些实施例中，第一下拉晶体管N13可以设置在第一保持晶体管N23远离第二保持晶体管N27的一侧，且第一下拉晶体管N13可以与第一保持晶体管N23邻近设置。其中，第二下拉晶体管N17可以设置在第二保持晶体管N27远离第一保持晶体管N23的一侧，且第二下拉晶体管N17可以与第二保持晶体管N27邻近设置。
需要说明的是，为了便于图示和说明，图3中用以N13、N23、P13、N17、N27、P17标示出了各晶体管的沟道区对应在有源区所在的区域。
第一下拉晶体管N13与第一保持晶体管N23可以共用第一漏区D1，通过共用第一漏区D1的方式，实现第一下拉晶体管的漏极与第一保持晶体管的漏极的电连接，无需额外形成接触结构以及金属层，有利于降低版图结构复杂度。第二下拉晶体管N17与第二保持晶体管N27可以共用第二漏区D2，通过共用第二漏区D2的方式，实现第二下拉晶体管的漏极与第二保持晶体管的漏极的电连接，无需额外形成接触结构以及金属层，有利于降低版图结构复杂度。
图9为本公开实施例提供的字线驱动器的另一种电路结构示意图，图10为图9对应的字线驱动器的一种版图结构示意图。参考图9及图10，在一些实施例中，第一保持晶体管N23以及第二保持晶体管N27构成保持晶体管单元10；字线驱动器包括多个保持晶体管单元10；其中，两个保持晶体管单元10在第二方向Y上镜像正对，第二方向Y与第一方向X相垂直。
需要说明的是，为了便于图示和说明，图9及图10中，不同保持晶体管单元10中的第一保持晶体管采用不同附图标记进行标示，包括N20、N21、N22、N23，与不同第一保持晶体管连接的第一字线分别用WL0、WL1、WL2、WL3进行标示；不同保持晶体管单元10中的第二保持晶体管采用不同附图标记进行标示，包括N24、N25、N26、N27，与不同第二保持晶体管连接的第二字线分别用WL4、WL5、WL6、WL7进行标示；不同第一下拉晶体管分别用N10、N11、N12、N13进行标示；不同第二下拉晶体管分别用N14、N15、N16、N17进行标示；不同第一上拉晶体管分别用P10、P11、P12、P13进行标示；不同第二上拉晶体管分别用P14、P15、P16、P17进行标示。
在一些实施例中，参考图10，在第二方向Y上正对的两个保持晶体管单元10对应的有源区101共用同一凸出部121，在第二方向Y上正对的两个保持晶体管单元10也可以共用源区。例如，两个保持晶体管单元10中的第一保持晶体管N23/N22以及第二保持晶体管N27/N26可以共用同一有源区，即4个保持晶体管共用同一有源区，且该有源区位于同一凸出部121。如此，有利于进一步节约版图面积，降低版图结构复杂度。
在另一些实施例中，两个保持晶体管单元10中两个第一保持晶体管可以共用位于同一凸出部121的同一源区，两个第二保持晶体管与第一保持晶体管不共用源区。或者，两个保持晶体管单元10的两个第二保持晶体管可以共用位于同一凸出部121的同一源区，两个第一保持晶体管与第二保持晶体管不共用源区。
字线驱动器还可以包括：多个接触结构105，每一接触结构105用于与对应的第一源区S1、第二源区S2、第一漏区D1或者第二漏区D2电连接，还用于与第一下拉晶体管、第二下拉晶体管、第一上拉晶体管以及第二上拉晶体管的源区或者漏区电连接。
上述实施例提供的字线驱动器，将两个保持晶体管的沟道长度方向设计为相对于有源区101延伸方向倾斜，在不增加版图面积的情况下，可以增加保持晶体管的沟道区长度，从而降低保持晶体管的关断电流，提高保持晶体管关断与该保持晶体管连接的字线的能力。此外，沟道长度方向相对于有源区101延伸方向倾斜，还可以为布局接触结构105预留更多的空间位置，提高版图的空间利用率。
相应地，本公开实施例还提供一种存储装置，包括上述实施例提供的字线驱动器，以下将对本公开实施例提供的存储装置进行详细说明，与前述实施例相同或者相应的部分，可参考前述实施例的详细说明，以下将不做赘述。
本公开实施例提供的存储装置包括：包括多个存储单元的存储单元阵列，多条字线以及多条位线，存储单元连接相应的字线以及相应的位线；上述实施例提供的字线驱动器。
字线驱动器中的每一子字线驱动器与相应的字线电连接，用于选中/激活相应的字线或者关闭相应的字线。
该存储装置可以为DRAM存储***，例如为DDR5DRAM存储***或者DDR4DRAM存储***。在其他实施例中，存储装置还可以为SRAM存储***、SDRAM存储***、ROM存储***或者闪存存储***。
本领域的普通技术人员可以理解，上述各实施方式是实现本公开的具体实施例，而在实际应用中，可以在形式上和细节上对其作各种改变，而不偏离本公开实施例的精神和范围。任何本领域技术人员，在不脱离本公开实施例的精神和范围内，均可作各自更动与修改，因此本公开实施例的保护范围应当以权利要求限定的范围为准。

Claims (15)

  1. 一种字线驱动器，包括：
    第一子字线驱动器，包括第一保持晶体管，所述第一保持晶体管被配置为，响应于驱动信号向第一字线提供第一预设电压；
    第二子字线驱动器，包括第二保持晶体管，所述第二保持晶体管被配置为，响应于所述驱动信号向第二字线提供所述第一预设电压；
    其中，所述第一保持晶体管以及所述第二保持晶体管包括：
    有源区，所述有源区包括：沿第一方向延伸的主体部以及与部分所述主体部相邻接且位于所述主体部一侧的凸出部，所述凸出部具有第一源区和第二源区；
    栅极，所述栅极至少位于所述主体部中与所述凸出部正对的部分区域上方；
    第一漏区以及第二漏区，分别位于所述栅极沿所述第一方向相对两侧的所述主体部；
    其中，所述第一漏区、所述栅极以及所述第一源区用于构成所述第一保持晶体管，所述第二漏区、所述栅极以及所述第二源区用于构成所述第二保持晶体管。
  2. 如权利要求1所述的字线驱动器，其中，所述第一源区和所述第二源区为同一源区。
  3. 如权利要求2所述的字线驱动器，其中，所述有源区还包括：第一凹陷部，所述第一凹陷部位于所述主体部内，且自所述主体部远离所述凸出部的侧壁向靠近所述凸出部的方向凹陷；所述栅极还位于所述第一凹陷部正上方。
  4. 如权利要求3所述的字线驱动器，其中，所述第一凹陷部朝向所述凸出部的底面位于所述栅极正下方。
  5. 如权利要求3所述的字线驱动器，其中，所述栅极覆盖整个所述第一凹陷部，且还覆盖在沿所述第一方向上与所述第一凹陷部邻近的所述主体部的部分区域。
  6. 如权利要求5所述的字线驱动器，其中，所述第一凹陷部具有沿所述第一方向相对的两个端面；在沿所述第一方向上，邻近一所述端面的所述主体部被所述栅极覆盖的长度为第一长度，邻近另一所述端面的所述主体部被所述栅极覆盖的长度为第二长度，所述第一长度与所述第二长度相等。
  7. 如权利要求3所述的字线驱动器，其中，所述栅极包括构成T型的第一部和第二部，所述第一部相对于所述第二部靠近所述凸出部；所述第一凹陷部位于所述第二部在所述有源区的正投影内。
  8. 如权利要求1-7任一项所述的字线驱动器，其中，所述栅极在所述有源区上的正投影的形状包括矩形或者H形。
  9. 如权利要求1所述的字线驱动器，其中，所述有源区还包括：
    第二凹陷部，所述第二凹陷部位于所述主体部内，自所述主体部朝向所述凸出部的侧壁向远离所述凸出部的方向凹陷，所述第二凹陷部位于所述第一源区与所述第一漏区之间，且所述第二凹陷部与所述凸出部在沿所述第一方向上相错开；所述栅极还位于部分所述第二凹陷部正上方；
    第三凹陷部，所述第三凹陷部位于所述主体部内，自所述主体部朝向所述凸出部的侧壁向远离所述凸出部的方向凹陷，所述第三凹陷部位于所述第二源区与所述第二漏区之间，且所述第三凹陷部与所述凸出部在沿所述第一方向相错开；所述栅极还位于部分所述第三凹陷部正上方。
  10. 如权利要求1所述的字线驱动器，其中，所述凸出部包括：分别位于所述主体部相对两侧的第一凸出部和第二凸出部，其中，所述第一凸出部具有所述第一源区，所述第二凸出部具有所述第二源区。
  11. 如权利要求2所述的字线驱动器，其中，所述第一保持晶体管以及所述第二保持晶体管构成保持晶体管单元；所述字线驱动器包括多个所述保持晶体管单元；
    其中，两个所述保持晶体管单元在第二方向上镜像对称，所述第二方向与所述第一方向相垂直，在所述第二方向上正对的两个所述保持晶体管单元对应的所述有源区共用同一所述凸出部，且共用所述源区。
  12. 如权利要求1所述的字线驱动器，其中，所述第一子字线驱动器还包括：
    第一上拉晶体管，被配置为，响应于第一主字线提供的第一使能信号，将所述第一字线上拉至第二预设电压，所述第二预设电压大于所述第一预设电压；
    第一下拉晶体管，被配置为，响应于所述第一主字线提供的所述第一使能信号，将所述第一字线下拉至所述第一预设电压；
    其中，所述第一下拉晶体管设置在所述第一保持晶体管远离所述第二保持晶体管的一侧，且所述第一下拉晶体管与所述第一保持晶体管邻近设置；
    所述第二子字线驱动器还包括：
    第二上拉晶体管，被配置为，响应于第二主字线提供的第二使能信号，将所述第二字线上拉至第二预设电压，所述第二预设电压大于所述第一预设电压；
    第二下拉晶体管，被配置为，响应于所述第二主字线提供的所述第二使能信号，将所述第 二字线下拉至所述第一预设电压；其中，所述第二下拉晶体管设置在所述第二保持晶体管远离所述第一保持晶体管的一侧，且所述第二下拉晶体管与所述第二保持晶体管邻近设置。
  13. 如权利要求12所述的字线驱动器，其中，所述第一下拉晶体管与所述第一保持晶体管共用所述第一漏区；所述第二下拉晶体管与所述第二保持晶体管共用所述第二漏区。
  14. 如权利要求1所述的字线驱动器，其中，所述第一保持晶体管以及所述第二保持晶体管均为NMOS晶体管。
  15. 一种存储装置，包括：
    包括多个存储单元的存储单元阵列，多条字线以及多条位线，且所述存储单元连接相应的所述字线以及相应的所述位线；
    如权利要求1-14任一项所述的字线驱动器。
PCT/CN2022/129996 2022-09-19 2022-11-04 字线驱动器以及存储装置 WO2024060365A1 (zh)

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CN116189727B (zh) * 2023-04-26 2023-09-19 长鑫存储技术有限公司 半导体结构、存储器及半导体结构的制造方法
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060267059A1 (en) * 2005-05-25 2006-11-30 Macronix International Co., Ltd. Peripheral circuit architecture for array memory
CN109935258A (zh) * 2017-12-18 2019-06-25 三星电子株式会社 子字线驱动器和相关的半导体存储器设备
US20210111179A1 (en) * 2019-10-11 2021-04-15 Intel Corporation 3d-ferroelectric random access memory (3d-fram)
CN114446344A (zh) * 2020-11-04 2022-05-06 三星电子株式会社 包括字线驱动电路的集成电路装置
CN114913891A (zh) * 2021-02-09 2022-08-16 美光科技公司 存储器子字驱动器布局

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005032991A (ja) * 2003-07-14 2005-02-03 Renesas Technology Corp 半導体装置
KR100735610B1 (ko) * 2005-01-24 2007-07-04 삼성전자주식회사 서브 워드라인 드라이버들의 레이아웃구조
KR102660230B1 (ko) * 2016-12-27 2024-04-25 에스케이하이닉스 주식회사 반도체 메모리 장치의 서브 워드라인 드라이버
KR20210110012A (ko) * 2020-02-28 2021-09-07 에스케이하이닉스 주식회사 서브 워드라인 드라이버
KR20220066726A (ko) * 2020-11-16 2022-05-24 삼성전자주식회사 공유 게이트 구조를 구비한 트랜지스터 유닛, 및 그 트랜지스터 유닛을 기반으로 한 서브-워드 라인 드라이버 및 반도체 소자

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060267059A1 (en) * 2005-05-25 2006-11-30 Macronix International Co., Ltd. Peripheral circuit architecture for array memory
CN109935258A (zh) * 2017-12-18 2019-06-25 三星电子株式会社 子字线驱动器和相关的半导体存储器设备
US20210111179A1 (en) * 2019-10-11 2021-04-15 Intel Corporation 3d-ferroelectric random access memory (3d-fram)
CN114446344A (zh) * 2020-11-04 2022-05-06 三星电子株式会社 包括字线驱动电路的集成电路装置
CN114913891A (zh) * 2021-02-09 2022-08-16 美光科技公司 存储器子字驱动器布局

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