WO2024045142A1 - 一种通信装置以及信号采样方法 - Google Patents
一种通信装置以及信号采样方法 Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
Definitions
- the present application relates to the technical field of clock synchronization, and specifically to a communication device and a signal sampling method.
- analog signals need to be converted into digital signals for processing through an analog to digital converter (ADC).
- ADC analog to digital converter
- the sampling frequency of the ADC is theoretically required to be greater than or equal to 2 times the bandwidth occupied by the original analog signal, and the sampling clock is restored in the digital domain to determine the best sampling moment. Due to the channel transmission delay and the clock offset between the transmitter and the receiver, the ADC cannot sample at the optimal sampling moment, resulting in a deviation between the collected data and the original data. For this purpose, clock synchronization is required.
- the overhead-assisted synchronization method refers to inserting a low-speed overhead signal into the data signal and performing narrow-band filtering at the receiving end to recover the sampling clock.
- the overhead-assisted synchronization method brings additional spectrum overhead and requires the filter at the receiving end to have a narrow bandwidth. In a large-bandwidth system, filter design is difficult.
- This application provides a communication device and a signal sampling method to achieve sampling clock synchronization.
- inventions of the present application provide a communication device, which can be applied to a receiver.
- the communication device includes a clock control circuit, a data sampling circuit and a clock recovery circuit.
- the clock control circuit is used to determine the sampling clock deviation of the data sampling circuit, and generates a first clock control signal according to the sampling clock deviation.
- the first clock control signal is used to adjust the sampling clock of the data sampling circuit.
- the clock recovery circuit is used to adjust the sampling clock of the data sampling circuit according to the first clock control signal and send the clock signal to the data sampling circuit.
- the data sampling circuit is used to sample the input analog signal according to the clock signal.
- the data sampling circuit is, for example, an ADC module.
- the clock control circuit may generate a corresponding first clock control signal and feed it back to the clock recovery circuit according to the sampling clock deviation of the data sampling circuit.
- the clock recovery circuit can adjust the sampling clock of the data sampling circuit according to the first clock control signal, and feed back the clock signal obtained by the adjusted sampling clock to the data sampling circuit, so that the data sampling circuit performs sampling according to the adjusted sampling clock.
- the data sampling circuit can feed back the signal sampled according to the adjusted sampling clock to the clock control circuit.
- the clock control circuit again determines the sampling clock deviation of the data sampling circuit and generates a corresponding clock control signal to feed back to the clock recovery circuit.
- the clock recovery circuit can again adjust the sampling clock of the data sampling circuit according to the received clock control signal, and feed back the clock signal obtained by the adjusted sampling clock to the data sampling circuit. Since the clock control circuit and the clock recovery circuit cooperate to adjust the sampling clock of the data sampling circuit multiple times, the sampling clock of the data sampling circuit can be locked at the best sampling time. In this way, there is no need to oversample the original analog signal, and the sampled digital signal can retain the useful information of the original analog signal. Since there is no need to oversample the original analog signal, even in large-bandwidth scenarios, the complexity of the ADC and the complexity of the filters in the receiver will not be increased.
- the clock signal when the first clock control signal indicates that the sampling clock deviation of the data sampling circuit is lower than the first threshold, the clock signal is a target clock signal that can generate a sampling clock expected by the data sampling circuit.
- the sampling clock expected by the data sampling circuit can be regarded as the optimal sampling clock of the data sampling circuit.
- the actual sampling clock of the data sampling circuit and the optimal sampling clock gradually decrease until the actual sampling clock of the data sampling circuit is close to or even equal to the optimal sampling clock.
- the clock generated by the clock recovery circuit The signal is called the target clock signal, that is, the clock signal that can make the data sampling circuit achieve the optimal sampling clock.
- the clock recovery circuit includes a splitter, a first delayer, a second delayer and a multiplier, wherein the splitter and the input end of the first delayer and the input end of the second delayer
- the multiplier is connected to the output terminal of the first delayer and the output terminal of the second delayer.
- the output terminal of the first delayer and the output terminal of the second delayer are also connected to the input terminal of the clock control circuit.
- the splitter is used to divide the input analog signal into a first analog sub-signal and a second analog sub-signal.
- the first delayer is used to delay the first analog sub-signal according to the first clock control signal, obtain the first delay signal, and output the first delay signal to the multiplication circuit and the clock control circuit.
- the second delayer is used to delay the second analog word signal according to the first clock control signal, obtain a second delay signal, and output the second delay signal to the multiplication circuit and the clock control circuit.
- the multiplication circuit is used to multiply the first delay signal and the second delay signal to obtain a first signal, and output the first signal to the data sampling circuit.
- the analog signal input to the clock recovery circuit and the analog signal input to the data sampling circuit are the same. Therefore, the clock recovery circuit processes the input analog signal to adjust the sampling clock of the data sampling circuit. For example, the clock recovery circuit divides the input analog signal into two channels, and controls the delay time of the two channels to adjust the sampling clock of the data sampling circuit, so that the sampling clock of the data sampling circuit reaches the optimal sampling clock. .
- the clock control circuit includes a processor and a decider.
- the processor can be used to determine the sampling clock deviation according to the first digital signal and the second digital signal output by the data sampling circuit, and generate according to the sampling clock deviation.
- the first clock control signal wherein, the first digital signal is the real component obtained by sampling the input analog signal by the data sampling circuit, and the second digital signal is the imaginary component obtained by sampling the analog signal by the data sampling circuit.
- the determiner may be configured to determine based on the first delay signal and the second delay signal that the clock recovery circuit cannot generate the target clock signal, and output a second clock control signal to the clock recovery circuit.
- the clock recovery circuit can gradually reduce the clock deviation of the data sampling circuit until the sampling clock of the data sampling circuit reaches the optimal sampling clock. Otherwise, it is necessary to continue to adjust the data sampling circuit through the clock recovery circuit. sampling clock. Therefore, the clock control circuit determines that the clock signal generated by the clock recovery circuit is not the target clock signal, and continues to output the clock control signal to the clock recovery circuit.
- the determiner is further configured to: determine based on the first delay signal and the second delay signal that the clock recovery circuit can generate the target clock signal, and output an indication signal to the clock recovery circuit.
- This indication information indicates that there is no need to adjust the sampling clock of the data sampling circuit.
- the clock control circuit determines that the clock signal generated by the clock recovery circuit is the target clock signal, it outputs an indication signal to the clock recovery circuit to indicate that the clock recovery circuit does not need to continue adjusting the sampling clock of the data sampling circuit.
- the determiner is specifically configured to: determine a first duration for which the first analog sub-signal is delayed based on the first delay signal, and determine a second duration for which the second analog sub-signal is delayed based on the second delay signal.
- the deviation between the difference between the first duration and the second duration and the sampling clock expected by the data sampling circuit is greater than the first threshold, it is determined that the clock recovery circuit cannot generate the target clock signal.
- the first delayer delays the first analog sub-signal according to the first clock control signal, including: when the first clock control signal indicates that the sampling clock deviation is greater than or equal to the first value, the first delayer delays the first analog sub-signal according to the first clock control signal.
- the delay step delays the first analog sub-signal.
- the first delayer delays the first analog sub-signal according to the second delay step, wherein the first delay step greater than the second delay step.
- the second delayer delays the second analog sub-signal according to the first clock control signal, including: when the first clock control signal indicates that the sampling clock deviation is greater than or equal to the first value, the second delayer delays the second analog sub-signal according to the third delay step.
- Analog sub-signal when the first clock control signal indicates that the sampling clock deviation is less than the first value, the second delayer delays the second analog sub-signal according to the fourth delay step, wherein the third delay step is greater than the fourth delay step length.
- multiple delay steps can be predefined for the first delayer and the second delayer respectively.
- the first delayer and the second delayer are configured according to the The longer delay step delays the input analog signal; when the data sampling clock deviation is small, correspondingly, the first delayer and the second delayer delay the input analog signal according to the shorter delay step. , to improve the sampling clock adjustment efficiency and accuracy.
- the clock recovery circuit further includes: a first low-pass filter connected to the multiplier, used to filter out high-frequency components in the first signal, thereby reducing interference caused by the high-frequency components.
- the clock recovery circuit also includes: a limiting amplifier connected to the first low-pass filter, used to filter out components of the signal output by the first low-pass filter that have an amplitude higher than the first amplitude, so as to reduce The probability of signal saturation.
- the clock recovery circuit also includes: a phase-locked loop connected to the limiting amplifier, used to make the frequency of the target clock signal consistent with the frequency of the first signal to improve phase stability.
- the communication device further includes a phase locking module, which is connected to the clock control circuit and the data sampling circuit respectively; wherein the phase locking circuit is used to: determine the sampling phase deviation of the data sampling circuit according to the error signal , generate a third control signal according to the sampling phase deviation, and output the third control signal to the data sampling circuit.
- the error signal is an error signal between the first digital signal and the second digital signal output by the data acquisition circuit.
- the third control signal is used to instruct the data sampling circuit to adjust the sampling phase.
- the embodiment of the present application takes into account the phase deviation of the sampling clock and sets a phase locking circuit.
- the phase deviation of the sampling clock of the data sampling circuit is calculated through the clock control circuit and fed back to the phase locking circuit.
- the phase locking circuit feeds back to the data sampling circuit to adjust the phase of the sampling clock.
- the phase locking module includes: a phase detector, a voltage-controlled oscillator and a second low-pass filter connected in sequence to the clock control circuit. Wherein, the input end of the second low-pass filter is connected to the voltage controlled oscillator, and the output end is connected to the data sampling circuit.
- embodiments of the present application provide a signal sampling method, which can be executed by a communication device.
- the communication device includes a clock control circuit, a data sampling circuit and a clock recovery circuit.
- the clock control circuit determines the sampling clock deviation of the data sampling circuit, and generates a first clock control signal according to the sampling clock deviation.
- the first clock control signal is used to adjust the sampling clock of the data sampling circuit.
- the clock recovery circuit adjusts the sampling clock of the data sampling circuit according to the first clock control signal and sends the clock signal to the data sampling circuit.
- the data sampling circuit samples the input analog signal according to the clock signal.
- the first clock control signal indicates that the sampling clock deviation of the data sampling circuit is lower than the first threshold, and the clock signal is a target clock signal capable of generating a sampling clock expected by the data sampling circuit.
- the clock recovery circuit includes a splitter, a first delayer, a second delayer and a multiplier.
- the first delayer is connected to the splitter and the clock control circuit
- the second delayer is connected to the splitter and the clock control circuit.
- the splitter divides the input analog signal into a first analog sub-signal and a second analog sub-signal.
- the first delayer delays the first analog sub-signal according to the first clock control signal, obtains the first delay signal, and outputs the first delay signal to the multiplication circuit and the clock control circuit.
- the second delayer delays the second analog word signal according to the first clock control signal to obtain a second delay signal, and outputs the second delay signal to the multiplication circuit and the clock control circuit.
- the multiplication circuit multiplies the first delay signal and the second delay signal to obtain a first signal, and outputs the first signal to the data sampling circuit.
- the clock control circuit includes a processor and a delayer, wherein the processor determines the sampling clock deviation according to the first digital signal and the second digital signal output by the data sampling circuit, and generates, according to the sampling clock deviation, The first clock control signal.
- the first digital signal is a real component obtained by sampling the input analog signal by the data sampling circuit
- the second digital signal is an imaginary component obtained by sampling the input analog signal by the data sampling circuit.
- the determiner determines that the clock recovery circuit cannot generate the target clock signal based on the first delay signal and the second delay signal, and outputs a second clock control signal to the clock recovery circuit.
- the determiner further determines that the clock recovery circuit can generate the target clock signal based on the first delay signal and the second delay signal, and outputs an indication signal to the clock recovery circuit. This indication information indicates that there is no need to adjust the sampling clock of the data sampling circuit.
- the determiner is specifically configured to: determine a first delay period for which the first analog sub-signal is delayed based on the first delay signal, and determine a delayed delay period for the second analog sub-signal based on the second delay signal. For two durations, when the deviation between the difference between the first duration and the second duration and the sampling clock expected by the data sampling circuit is greater than the first threshold, it is determined that the clock recovery circuit cannot generate the target clock signal.
- the first delayer delays the first analog sub-signal according to the first delay step.
- the first delayer delays the first analog sub-signal according to the second delay step, wherein the first delay step is greater than the second delay step.
- the second delayer delays the second analog sub-signal according to the third delay step.
- the second delayer delays the second analog sub-signal according to the third delay step. taking a value, the second delayer delays the second analog sub-signal according to a fourth delay step, where the third delay step is greater than the fourth delay step.
- the clock recovery circuit further includes a first low-pass filter connected to the multiplication circuit, where the first low-pass filter is used to filter out high-frequency components in the first signal.
- the clock recovery circuit further includes a limiting amplifier connected to the first low-pass filter.
- the limiting amplifier is used to filter out the signal output by the first low-pass filter with an amplitude higher than the first Amplitude components.
- the clock recovery circuit further includes a phase-locked loop connected to the limiting amplifier, and the phase-locked loop is used to make the frequency of the target clock signal consistent with the frequency of the first signal.
- the communication device further includes a phase locking module, which is connected to the clock control circuit and the data sampling circuit respectively.
- the method further includes: determining the data sampling circuit according to the error signal through the phase locking circuit. the sampling phase deviation, generate a third control signal according to the sampling phase deviation, and output the third control signal to the data sampling circuit.
- the error signal is an error signal between the first digital signal and the second digital signal output by the data acquisition circuit.
- the third control signal is used to instruct the data sampling circuit to adjust the sampling phase.
- the phase locking module includes a phase detector, a voltage-controlled oscillator and a second low-pass filter connected in sequence to the clock control circuit. Wherein, the input end of the second low-pass filter is connected to the voltage controlled oscillator, and the output end is connected to the data sampling circuit.
- an embodiment of the present application provides a receiver, which includes the communication device described in the first aspect and any possible implementation manner of the first aspect.
- embodiments of the present application provide a receiver, which includes an input-output interface and a logic circuit. Input and output interfaces are used to input and/or output information. Logic circuitry is used to perform the method described in the second aspect.
- embodiments of the present application provide a chip system that includes a communication interface and a processor, so that a device installed with a system chip executes the method described in the second aspect or any possible implementation of the second aspect.
- the chip system further includes a memory for storing a computer program.
- the chip system can be composed of chips or include chips and other discrete devices.
- the present application provides a computer-readable storage medium that stores a computer program.
- the computer program When the computer program is run, the above-mentioned second aspect or any possible implementation manner of the second aspect is implemented. the method described.
- a computer program product includes: computer program code.
- the above-mentioned second aspect or any possible implementation manner of the second aspect causes the above-mentioned second aspect or any possible implementation of the second aspect. method is executed.
- Figure 1 is a schematic diagram of the architecture of a communication system applicable to the embodiment of the present application.
- Figure 2 is a schematic structural diagram of a communication device provided by an embodiment of the present application.
- Figure 3 is a schematic diagram of the conditions that the optimal sampling clock of the data sampling circuit provided by the embodiment of the present application needs to meet;
- Figure 4 is another schematic structural diagram of a communication device provided by an embodiment of the present application.
- Figure 5 is another structural schematic diagram of a communication device provided by an embodiment of the present application.
- FIG. 6 is a schematic diagram of the deviation between the actual sampling clock and the expected sampling clock of the data sampling circuit provided by the embodiment of the present application.
- the technical solution provided by the embodiments of the present application can be applied to equipment that needs to perform ADC, such as a receiver.
- the receiver can communicate with the transmitter via a wireless channel or a wired cable.
- FIG. 1 is a schematic diagram of a network architecture of a communication system applicable to embodiments of the present application.
- the communication system may include a transmitter and a receiver.
- Figure 1 takes the transmitter and receiver communicating through wired cables as an example.
- the transmitter includes a baseband chip, a digital to analog converter (DAC), a radio frequency chip and a power amplifier.
- DAC digital to analog converter
- the base station chip is used to process the signal to be sent, and send the processed digital signal to the DAC for digital-to-analog conversion processing, that is, convert the digital signal into an analog signal.
- the analog signal passes through the radio frequency chip and becomes a radio frequency signal, and then passes through the power amplifier and is transmitted to the radio frequency chip in the receiver through a wireless channel or wired cable.
- the radio frequency chip in the receiver performs down-conversion processing on the received radio frequency information, and then converts it into a digital signal through the ADC. This digital signal can be used to restore the information carried by the signal sent by the transmitter.
- the baseband processing chip in the receiver processes the digital signal to obtain the original information sent by the transmitter. It should be noted that the components included in the transmitter and receiver in Figure 1 are only examples, and may also include other possible components, such as filters, mixers, etc., which will not be listed here.
- the sampling frequency of the ADC is theoretically required to be greater than or equal to 2 times the bandwidth occupied by the original analog signal. Considering the influence of some factors, a more accurate sampling frequency cannot be guaranteed, and the ADC is usually required to sample at a larger sampling frequency (also called oversampling).
- ADC oversampling correspondingly, requires sampling clock recovery in the digital domain to determine the optimal sampling moment. Due to the channel transmission delay and the clock offset between the transmitter and the receiver, the ADC cannot be sampled at the best sampling moment, resulting in a deviation between the collected data and the original data. For this reason, clock synchronization is required, such as As shown in Figure 1. Through sampling clock synchronization, the ADC can be sampled at the best sampling moment.
- the overhead-assisted synchronization method refers to inserting a low-speed overhead signal into the data signal and performing narrow-band filtering at the receiving end to recover the sampling clock.
- the overhead-assisted synchronization method brings additional spectrum overhead and requires the filter at the receiving end to have a narrow bandwidth. In a large-bandwidth system, filter design is difficult.
- the sampling clock of the ADC can be locked at a desired sampling clock (optimal sampling clock). Since the ADC is locked to work at the optimal clock, there is no need to oversample the original analog signal, and the sampled digital signal can retain useful information of the original analog signal. Since the ADC does not need to oversample the original analog signal, that is, the sampling frequency of the ADC has nothing to do with the bandwidth of the original analog signal, therefore, through the solution provided by the embodiment of this application, even in a large-bandwidth scenario, the complexity of the ADC will not be increased. degree and the complexity of the filters in the receiver.
- high frequency and low frequency are relative terms.
- the frequency range of high frequency can be [1.5 ⁇ Fs, ⁇ ]
- the frequency range of low frequency can be [0, 1.5 ⁇ Fs], where, Fs is the bandwidth of the first signal.
- Delays are also called delayers.
- FIG. 2 is a schematic structural diagram of a communication device provided by an embodiment of the present application.
- the communication device can be applied to a receiver.
- the communication device includes a clock control circuit 201 , a clock recovery circuit 202 and a data sampling circuit 203 .
- the clock control circuit 201 is connected to the data sampling circuit 203 and the clock recovery circuit respectively, and the clock recovery circuit 202 is also connected to the data sampling circuit 203.
- the data sampling circuit 203 is, for example, an ADC module.
- the clock control circuit 201 and the clock recovery circuit 202 can be two independent circuits or physical devices (this article takes this as an example), or they can be integrated together.
- the clock control circuit 201 and the clock recovery circuit 202 may be an integrated device, such as a clock data recovery (carrier data recovery, CDR) module.
- CDR carrier data recovery
- the clock control circuit 201 can determine the sampling clock deviation of the data sampling circuit 203 based on the signal collected by the data sampling circuit 203, and feed it back to the clock recovery circuit 202.
- the clock recovery circuit 202 can adjust the sampling clock of the data sampling circuit 203 according to the sampling clock deviation fed back by the clock control circuit 201, and feed back the adjusted sampling clock to the data sampling circuit 203.
- the data sampling circuit 203 performs sampling according to the sampling clock fed back by the clock recovery circuit 202, and outputs the sampled signal to the clock control circuit 201.
- the adjustment of the clock recovery circuit 202 can make the sampling clock deviation of the data sampling circuit 203 smaller.
- the sampling clock of the data sampling circuit 203 can be adjusted again.
- the data sampling circuit 203 can feed back the signal sampled according to the adjusted sampling clock to the clock control circuit 201, and the clock control circuit 201 again determines the sampling clock deviation of the data sampling circuit, and generates a corresponding clock control signal to feed back to the clock control circuit 201.
- Clock recovery circuit 202 The clock recovery circuit 202 can again adjust the sampling clock of the data sampling circuit 203 according to the received clock control signal, and feed back the clock signal obtained by the adjusted sampling clock to the data sampling circuit 203.
- the sampling clock of the data sampling circuit 203 is adjusted multiple times through the clock control circuit 201 and the clock recovery circuit 202 until the actual sampling clock of the data sampling circuit 203 reaches the optimal sampling clock.
- the sampling clock deviation of the data sampling circuit 203 is lower than the first threshold.
- the first threshold may be preset or preconfigured, and the embodiment of the present application does not limit the size of the first threshold.
- the first threshold may be a possible value obtained based on experimental testing.
- the size of the first threshold can also be different.
- the first threshold may be a normalized clock deviation, such as 10 -6 .
- the clock control signal generated by the clock control circuit is used to adjust the sampling clock of the data sampling circuit 203; when the sampling clock deviation of the data sampling circuit 203 is greater than or equal to First threshold, the clock control circuit 201 can generate an indication signal, which indicates that the sampling clock deviation of the data sampling circuit 203 is lower than the first threshold, and the clock recovery circuit 202 can determine that no further adjustment is needed based on the indication signal fed back by the clock control circuit 201 The sampling clock of the data sampling circuit 203.
- the clock recovery circuit 202 does not adjust the sampling clock of the data sampling circuit 203, and directly outputs the final clock signal (referred to as the target clock signal herein) to the data sampling circuit 203.
- the target clock signal can make the sampling of the data sampling circuit 203 The clock reaches the desired sample clock.
- the receiver receiving the first analog signal from the transmitter takes the first analog signal from the transmitter as an example.
- the first analog signal is divided into two signals, and the two signals are respectively called the I signal and the Q signal.
- the I signal is the real component of the first analog signal
- the Q signal is the imaginary component of the first analog signal.
- the I signal and the local oscillator signal pass through the mixer and then the low-pass filter, they are input to the data sampling circuit 203.
- the Q signal and the local oscillator signal pass through the mixer and then the low-pass filter, they are input to the data sampling circuit 203 .
- the I signal is sampled by the data acquisition circuit 203 to obtain the first digital signal
- the Q signal is sampled by the data acquisition circuit 203 to obtain the second digital signal.
- the data sampling circuit 203 outputs the first digital signal and the second digital signal to the clock control circuit 201.
- the first digital signal I′[k] and the second digital signal Q′[k] respectively satisfy the following formulas:
- I k + jQ k is the digital signal obtained by sampling the first analog signal by the data sampling circuit 203
- Ts is the sampling clock of the data sampling circuit 203
- ⁇ o is the sampling phase deviation of the data sampling circuit 203
- ⁇ f is the data sampling
- k is the index.
- the clock control circuit 201 may determine the sampling clock deviation of the data sampling circuit 203 according to the first digital signal and the second digital signal, and use the sampling clock deviation according to the sampling clock deviation. For example, the clock control circuit 201 operates according to the first deviation signal between I′[k] and Ik For example, the clock control circuit 201 operates according to the second deviation signal between Q′[k] and Qk Among them, m is a preset integer.
- the sampling clock deviation of the data sampling circuit 203 can be gradually reduced, that is, error_s can be gradually reduced.
- the adjustment amount of the sampling clock by the clock recovery circuit 202 indicated by the clock control signal is also reduced. That is, through different times of adjustment, the clock control signals generated by the clock recovery circuit 202 are different.
- the clock control signal determined for the first time by the clock control circuit 201 may be called the first clock control signal.
- the following uses the clock control signal generated by the clock control circuit 201 as the first clock control signal to describe how the clock recovery circuit 202 adjusts the sampling clock of the data sampling circuit 203 according to the clock control signal fed back by the clock control circuit 201 .
- the sampling clock of the data sampling circuit 203 can be locked at the optimal sampling clock.
- the clock recovery circuit 202 processes the sampling clock of the analog signal input to the data sampling circuit 203, and determines whether the sampling clock of the data sampling circuit 203 is the optimal sampling clock based on the processing result.
- the clock recovery circuit divides the input analog signal into two channels and controls the delay length of the two channels to adjust the sampling clock of the data sampling circuit.
- the clock recovery circuit 202 may include a splitter 2021, a first delayer 2022, a second delayer 2023, and a multiplier 2024.
- the splitter 2021 is used to divide the first analog signal into a first analog sub-signal r IF (t) and a second analog sub-signal r IF (t).
- A(t) is the first analog signal
- f0 the carrier frequency
- t time
- real finding the real part of the complex number
- exp is the exponential function.
- the first analog sub-signal r IF (t) is output to the first delayer 2022
- the second analog sub-signal r IF (t) is output to the second delayer 2023
- the first clock control signal is fed back to the input terminals of the first delayer 2022 and the second delayer 2023 respectively.
- the splitter 2021 can also be a power splitter, as long as it can divide one signal into two signals.
- the splitter 2021 can be a two-power splitter.
- the first delayer 2022 may delay the first analog sub-signal r IF (t) according to the first clock control signal
- the second delayer 2023 may delay the second analog sub-signal r IF (t) according to the first clock control signal.
- the first analog sub-signal r IF (t) is delayed for a duration ⁇ 1
- the second analog sub-signal r IF (t) is delayed for a duration ⁇ 2 .
- the delayed first analog sub-signal r IF (t) is recorded as r IF (t - ⁇ 1 )
- the delayed second analog sub-signal r IF (t) is recorded as r IF (t- ⁇ 2 ).
- the first signal S 1 (t) r IF (t- ⁇ 1 ) ⁇ r IF (t- ⁇ 2 ) is obtained.
- the first signal S 1 (t) is passed through a low-pass filter to filter out the high-frequency components:
- Ts is the sampling clock expected by the data sampling circuit 203
- a in A n is the amplitude of the signal
- n is the series
- the value of n ranges from a small negative number to a large positive integer
- the function g represents an integer Function
- function g′ represents the equivalent shaping function
- t represents time
- ⁇ represents ⁇
- f IF represents the carrier frequency
- G is the frequency domain expression of function g′, and m is an integer.
- Ts is the optimal sampling clock of the data sampling circuit 203.
- the power spectrum S2 (f) is shown.
- the sampling clock adjustment of the data sampling circuit 203 has not reached the expected sampling clock, and the clock recovery circuit 202 needs to continue to adjust the sampling clock of the data sampling circuit 203, that is, the clock recovery circuit 202 needs to pass the first A delayer 2022 and a second delayer 2023 continue to delay the received signal.
- the first delayer 2022 and the second delayer 2023 delay the received signal, which actually shifts the received signal in the time domain.
- the shift of the received signal in the time domain by the first delayer 2022 and the second delayer 2023 is opposite, that is, when ⁇ 1 is a positive number, ⁇ 2 is a negative number; ⁇ 1 is When negative, ⁇ 2 is positive.
- the sampling clock deviation of the data sampling circuit 203 can be gradually reduced until the sampling clock of the data sampling circuit 203 is adjusted to the desired sampling clock.
- the clock recovery circuit 202 should also adaptively reduce the delay time of the received signal through the first delayer 2022.
- the second The delay length of the second delayer 2023 should also be adaptively reduced for the received signal.
- multiple delay steps may be predefined for the first delayer 2022 and the second delayer 2023 respectively.
- the clock recovery circuit 202 receives the clock control signal from the clock control circuit 201 and can select a delay step that matches the first delayer 2022 and the second delayer 2023 according to the size of the sampling clock deviation indicated by the clock control signal. delay step size.
- the first delay step, the second delay step and the third delay step can be predefined. Wherein, the first delay step is larger than the second delay step, and the second delay step is larger than the third delay step.
- the first delayer 2022 delays the first analog sub-signal according to the first delay step ⁇ 11 to obtain a delay
- the signal is denoted as r IF (t- ⁇ 11 ).
- the first delayer 2022 delays the first analog sub-signal according to the second delay step ⁇ 12 to obtain a delay Signal, recorded as r IF (t- ⁇ 12 ).
- the first value is greater than the second value.
- the fourth delay step, the fifth delay step and the sixth delay step may also be predefined. Among them, the fourth delay step is larger than the fifth delay step, and the fifth delay step is larger than the sixth delay step. If the clock control signal received by the second delayer 2023 from the clock control circuit 201 indicates that the sampling clock deviation is greater than or equal to the first value, the second delayer 2023 delays the first analog sub-signal according to the fourth delay step ⁇ 21 to obtain a delay The signal is denoted as r IF (t- ⁇ 21 ).
- the second delayer 2023 delays the first analog sub-signal according to the fifth delay step ⁇ 22 to obtain a delay
- the signal is denoted as r IF (t- ⁇ 22 ).
- the first delay step, the second delay step and the third delay step are positive numbers
- the fourth delay step, the fifth delay step and the sixth delay step are negative numbers
- the first delay step, the second delay step and the third delay step are negative numbers
- the fourth delay step, the fifth delay step and the sixth delay step are positive numbers.
- the embodiments of the present application do not limit the sizes of the first delay step, the second delay step, and the third delay step, and also do not limit the sizes of the fourth delay step, the fifth delay step, and the sixth delay step. No restrictions.
- the devices in the splitter 2021, the first delayer 2022, the second delayer 2023 and the multiplier 2024 may be integrated together.
- the first delayer 2022 and the second delayer 2023 may be integrated together as one device.
- the first delayer 2022 and the second delayer 2023 feed back the generated signals to the clock control circuit 201, and the clock control circuit 201 determines whether the first delayer 2022 and the second delayer 2023 have changed the current sampling clock of the data sampling circuit 203. Adjust to desired sampling clock.
- the signal generated by the first delayer 2022 is called a first delayed signal
- the signal generated by the second delayer 2023 is called a second delayed signal.
- the clock control circuit 201 receives the first delay signal from the first delayer 2022, receives the second delay signal from the second delayer 2023, and determines whether the clock recovery circuit 202 has adjusted the current sampling clock of the data sampling circuit 203 to the desired sampling clock.
- the clock control circuit 201 includes a determiner 2012, through which the determiner 2012 determines a first duration for which the first analog sub-signal is delayed according to the first delay signal, and determines a second duration for which the second analog sub-signal is delayed according to the second delay signal. duration.
- the multiplier 2024 multiplies the first delay signal and the second delay signal to obtain the first The signal, that is, the clock signal generated by the clock recovery circuit 202 is not the target clock signal, that is, the clock recovery circuit 202 cannot generate the target clock signal.
- the clock control circuit 201 continues to calculate the sampling clock deviation based on the I signal and the Q signal received from the data sampling circuit 203, and generates a new clock control signal based on the sampling clock deviation, for example, called a second clock control signal.
- the processor 2011 in the clock control circuit 201 calculates a sampling clock deviation based on the I signal and the Q signal received from the data sampling circuit 203, and generates a second clock control signal based on the sampling clock deviation.
- the second clock control signal may indicate that the sampling clock deviation of the data utilization circuit 203 is lower than the second threshold.
- the second clock control signal is fed back to the first delayer 2022 and the second delayer 2023.
- the first delayer 2022 and the second delayer 2023 respectively delay the received signal according to the second clock control signal and generate the The delayed signal is fed back to the clock control circuit 201 again, and so on.
- the clock control circuit 201 determines that the difference between the delay duration corresponding to the first delay signal and the delay duration corresponding to the second delay signal and the sampling clock Ts expected by the data sampling circuit 203 is less than or equal to the first threshold.
- the clock control circuit 201 feeds back an indication signal to the first delayer 2022 and the second delayer 2023.
- the indication signal indicates that the sampling clock deviation of the data sampling circuit 203 is lower than the first threshold.
- the multiplier 2024 multiplies the first delay signal and the second delay signal to obtain a first signal which is the target clock signal.
- the indication signal is a special case of the clock control signal, and its specific implementation form is the same as the clock control signal. It can be understood that if the sampling clock of the data sampling circuit 203 is adjusted to reach the expected sampling clock, but during subsequent use, the actual sampling clock of the data sampling circuit 203 deviates from the expected sampling clock, then the aforementioned method can continue to be used. The sampling clock of the data sampling circuit 203 is adjusted to try to make the actual sampling clock of the data sampling circuit 203 the desired sampling clock.
- the clock recovery circuit 202 may also be used as a functional module to filter out the high-frequency component of the first signal.
- the clock recovery circuit 202 may also include a low-pass filter 2025 connected to the multiplier 2024 .
- the low-pass filter 2025 can filter out high-frequency components in the first signal, thereby reducing possible interference caused by the first signal.
- the clock recovery circuit 202 may also include a limiting amplifier 2026 connected to the low-pass filter 2025 .
- clock recovery circuit 202 may include a multiplier 2024, a low-pass filter 2025, and a limiting amplifier 2026, as shown in FIG. 4 .
- the limiting amplifier 2026 can filter out the components of the signal output by the low-pass filter 2025 whose amplitude is higher than the preset amplitude, so as to reduce the probability of amplitude saturation caused by the first signal.
- the clock recovery circuit 202 may also include a phase locked loop 2027 connected to the limiting amplifier 2026.
- the clock recovery circuit 202 may include a multiplication circuit 2024, a low-pass filter 2025, a limiting amplifier 2026, and a phase-locked loop 2027, as shown in FIG. 4 .
- the phase-locked loop 2027 can make the frequency of the target clock signal consistent with the frequency of the first signal output by the multiplication circuit 2024, so as to reduce the probability of instability of the sampling clock due to phase instability.
- the communication device may also include a phase locking module 204.
- the communication device includes a clock control circuit 201, a clock recovery circuit 202, a data sampling circuit 203, and a phase locking module 204.
- the clock control circuit 201 can be used to eliminate the sampling phase deviation of the data sampling circuit 203.
- the phase locking module 204 may include a phase detector 2041, a voltage-controlled oscillator 2042 and a low-pass filter 2043.
- the input terminal of the phase detector 2041 is connected to the clock control circuit 201 , and the output terminal of the phase detector 2041 is connected to the input terminal of the voltage controlled oscillator 2042 .
- the output terminal of the voltage controlled oscillator 2042 is connected to the input terminal of the low-pass filter 2043, and the output terminal of the low-pass filter 2043 is connected to the data sampling circuit.
- the processor 2011 in the clock control circuit 201 may determine the sampling phase deviation of the data sampling circuit according to the first digital signal and the second digital signal received from the data sampling circuit 203 .
- the first digital signal is denoted as I′(k)
- the second digital signal is denoted as Q′(k).
- the signal output by the digital sampling circuit 203 is I k +jQ k .
- ⁇ f is the frequency deviation
- ⁇ 0 is the sampling phase deviation, that is, the deviation between the expected sampling clock and the actual sampling clock, as shown in Figure 6.
- the processor 2011 in the clock control circuit 201 can extract the error signal error between I k +jQ k and I′(k)+Q′(k). As mentioned above, we can know: The processor 2011 feeds back the deviation signal to the phase detector 2041, and determines the sampling phase deviation through the voltage controlled oscillator 2042. The voltage-controlled oscillator 2042 generates a third control signal based on the sampling phase deviation, filters out the high-frequency component in the third control signal through the low-pass filter 2043, and outputs it to the data sampling circuit 203. In order to save resources, the third control signal may instruct the sampling phase to be increased or decreased, thereby ensuring that the sampling phase of the data sampling circuit 203 is stable.
- the sampling clock of the data sampling circuit 203 (ie, the ADC) can be locked to a desired sampling clock (optimal sampling clock). Since the ADC is locked to work at the optimal clock, there is no need to oversample the original analog signal, and the sampled digital signal can retain useful information of the original analog signal. Since the sampling frequency of the ADC has nothing to do with the bandwidth of the original analog signal, it can sample analog signals in various bandwidths. And because the ADC does not need to oversample the original analog signal, even in a large-bandwidth scenario, it will not increase the complexity of the ADC and the complexity of the filter in the receiver.
- the communication device provided by the embodiments of the present application is introduced from the perspective of signal processing and transmission paths between various circuits (or devices or functional modules) included in the communication device.
- Each functional module included in the communication device may be a hardware structure and/or a software module, and the above functions are implemented in the form of a hardware structure, a software module, or a hardware structure plus a software module. Whether one of the above functions is performed as a hardware structure, a software module, or a hardware structure plus a software module depends on the specific application and design constraints of the technical solution.
- each circuit (or device or functional module) included in the communication device may be independent, integrated together, or coupled to each other.
- the communication device may be a system on a chip.
- the chip system may be composed of chips, or may include chips and other discrete devices. For specific functions, please refer to the description in the above embodiment.
- the processor 2011 and the determiner 2012 can be independent or coupled together.
- the coupled processor 2011 and decision maker 2012 can also be called a processor, and the processor can also be called a processing unit or processing module, which can implement certain control functions.
- the processor may be a general-purpose processor or a special-purpose processor, etc.
- the central processing unit may be used to control the communication device, execute software programs and/or process data.
- Different processors may be independent devices, or may be integrated in one or more processors, for example, integrated on one or more application specific integrated circuits.
- the coupling in the embodiment of this application is an indirect coupling or communication connection between devices, units or modules, which may be in electrical, mechanical or other forms, and is used for information interaction between devices, units or modules. Multiple coupled modules can operate together.
- the communication device in the above embodiments may also be a circuit, a chip used in a device, or other combined devices, components, etc. that have the function of the above communication device.
- An embodiment of the present application also provides a receiver, which includes the communication device in the foregoing embodiment.
- the receiver also includes other necessary functional components, such as transceivers and antennas.
- the transceiver may be called a transceiver unit, transceiver module, transceiver, transceiver circuit, transceiver, input/output interface, etc., and is used to realize the transceiver function of the receiver through the antenna.
- the communication device that implements the communication described in this article can be an independent device (for example, an independent integrated circuit, a mobile phone, etc.), or it can be a part of a larger device (for example, a module that can be embedded in other devices).
- an independent device for example, an independent integrated circuit, a mobile phone, etc.
- it can be a part of a larger device (for example, a module that can be embedded in other devices).
- a module that can be embedded in other devices for details, please refer to the above-mentioned The description of terminal equipment and network equipment will not be repeated here.
- the communication device may also include one or more of the following components: a wireless communication module, an audio module, an external memory interface, an internal memory, a universal serial bus (USB) interface, a power management module, an antenna, and a speaker. , microphone, input and output module, sensor module, motor, camera, or display screen, etc. It can be understood that in some embodiments, the communication device may include more or fewer components, or some components may be integrated, or some components may be separated. These components may be implemented in hardware, software, or a combination of software and hardware.
- inventions of the present application also provide a signal sampling method applied to a receiver.
- the receiver includes a communication device.
- the communication device includes a clock control circuit 201, a clock recovery circuit 202, and a data sampling circuit 203.
- the method includes: determining the sampling clock deviation of the data sampling circuit 203 through the clock control circuit 201, and generating a first clock control signal according to the sampling clock deviation.
- the first clock control signal is used to adjust the sampling clock of the data sampling circuit 203; through clock recovery
- the circuit 202 adjusts the sampling clock of the data sampling circuit 203 according to the first clock control signal, and sends the clock signal to the data sampling circuit 203; the data sampling circuit 203 samples the input analog signal according to the clock signal.
- the first clock control signal indicates that the sampling clock deviation of the data sampling circuit 203 is lower than the first threshold, and the clock signal is a target clock signal that can generate the sampling clock desired by the data sampling circuit 203 .
- the clock recovery circuit 202 includes a splitter 2021, a first delayer 2022, a second delayer 2023 and a multiplication circuit 2024.
- the first delayer 2022 is connected to the splitter 2021 and the clock control circuit 201
- the second delayer 2023 is connected to the splitter 2021 and the clock control circuit 201 .
- the splitter 2021 divides the input analog signal into a first analog sub-signal and a second analog sub-signal.
- the first delayer 2022 delays the first analog sub-signal according to the first clock control signal to obtain a first delayed signal, and outputs the first delayed signal to the multiplication circuit 2024 and the clock control circuit 201 .
- the second delayer 2023 delays the second analog word signal according to the first clock control signal to obtain a second delayed signal, and outputs the second delayed signal to the multiplication circuit 2024 and the clock control circuit 201 .
- the multiplication circuit 2024 multiplies the first delay signal and the second delay signal to obtain a first signal, and outputs the first signal to the data sampling circuit 203 .
- the clock control circuit 201 includes a processor 2011 and a delayer 2012, wherein the processor 2011 determines the sampling clock deviation according to the first digital signal and the second digital signal output by the data sampling circuit 203, and determines the sampling clock deviation according to the first digital signal and the second digital signal output by the data sampling circuit 203.
- the clock deviation is sampled to generate a first clock control signal.
- the first digital signal is a real component obtained by sampling the input analog signal by the data sampling circuit 203
- the second digital signal is an imaginary component obtained by sampling the input analog signal by the data sampling circuit 203.
- the determiner 2012 determines that the clock recovery circuit 202 cannot generate the target clock signal based on the first delay signal and the second delay signal, and outputs a second clock control signal to the clock recovery circuit 202 .
- the determiner 2012 further determines that the clock recovery circuit 202 can generate the target clock signal based on the first delay signal and the second delay signal, and outputs an indication signal to the clock recovery circuit 202 .
- This indication information indicates that there is no need to adjust the sampling clock of the data sampling circuit 203.
- the determiner 2012 is specifically configured to: determine a first duration for which the first analog sub-signal is delayed based on the first delay signal, and determine a second duration for which the second analog sub-signal is delayed based on the second delay signal. duration, when the deviation between the difference between the first duration and the second duration and the sampling clock expected by the data sampling circuit 203 is greater than the first threshold, it is determined that the clock recovery circuit 202 cannot generate the target clock signal.
- the first delayer 2022 delays the first analog sub-signal according to the first delay step.
- the first clock control signal indicates that the sampling clock deviation is less than the first value
- the first delayer 2022 delays the first analog sub-signal according to the second delay step, where the first delay step is greater than the second delay step.
- the second delayer 2023 delays the second analog sub-signal according to the third delay step.
- the first clock control signal indicates that the sampling clock deviation is less than the first value
- the second delayer 2023 delays the second analog sub-signal according to the third delay step.
- the second delayer 2023 delays the second analog sub-signal according to a fourth delay step, where the third delay step is greater than the fourth delay step.
- the clock recovery circuit 202 further includes a first low-pass filter 2025 connected to the multiplication circuit 2024.
- the first low-pass filter 2025 is used to filter out high-frequency components in the first signal.
- the clock recovery circuit 202 also includes a limiting amplifier 2026 connected to the first low-pass filter 2025.
- the limiting amplifier 2026 is used to filter out the signal output by the first low-pass filter 2025. A component with an amplitude higher than the first amplitude.
- the clock recovery circuit 202 further includes a phase-locked loop 2027 connected to the limiting amplifier 2026.
- the phase-locked loop 2027 is used to make the frequency of the target clock signal consistent with the frequency of the first signal.
- the communication device further includes a phase locking module 204, which is connected to the clock control circuit 201 and the data sampling circuit 203 respectively.
- the method further includes: using the phase locking circuit 204 according to The error signal determines the sampling phase deviation of the data sampling circuit 203 , generates a third control signal according to the sampling phase deviation, and outputs the third control signal to the data sampling circuit 203 .
- the error signal is an error signal between the first digital signal and the second digital signal output by the data acquisition circuit 203.
- the third control signal is used to instruct the data sampling circuit 203 to adjust the sampling phase.
- the phase locking module includes a phase detector 2041, a voltage-controlled oscillator 2042 and a second low-pass filter 2043 connected in sequence to the clock control circuit 201.
- the input terminal of the second low-pass filter 2043 is connected to the voltage controlled oscillator 2042, and the output terminal is connected to the data sampling circuit 203.
- An embodiment of the present application also provides a communication system.
- the communication system includes the communication device and the sending device described in any one of Figures 2 to 5.
- the relevant descriptions in the above method embodiments which will not be described again here.
- An embodiment of the present application also provides a computer-readable storage medium, which includes instructions that, when run on a computer, enable the computer to implement the functions of the communication device described in any one of Figures 2 to 5.
- An embodiment of the present application also provides a computer program product, which includes instructions that, when run on a computer, enable the computer to implement the functions of the communication device described in any one of Figures 2 to 5.
- Embodiments of the present application provide a chip system.
- the chip system includes a processor and may also include a memory, so that a device installed with the chip system implements the functions of the communication device described in any one of Figures 2 to 5.
- the chip system can be composed of chips or include chips and other discrete devices.
- the size of the sequence numbers of the above-mentioned processes does not mean the order of execution.
- the execution order of each process should be determined by its functions and internal logic, and should not be used in the embodiments of the present application.
- the implementation process constitutes any limitation.
- the disclosed systems, devices and methods can be implemented in other ways.
- the device embodiments described above are only illustrative.
- the division of the units is only a logical function division. In actual implementation, there may be other division methods.
- multiple units or components may be combined or can be integrated into another system, or some features can be ignored, or not implemented.
- the coupling or direct coupling or communication connection between each other shown or discussed may be through some interfaces, and the indirect coupling or communication connection of the devices or units may be in electrical, mechanical or other forms.
- the units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place, or they may be distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.
- the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium.
- the computer software product is stored in a storage medium and includes a number of instructions to enable a A computer device (which may be a personal computer, a server, or a network device, etc.) executes all or part of the steps of the methods described in various embodiments of this application.
- the aforementioned storage media include: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), magnetic disk or optical disk and other media that can store program code.
- connection involved in this application describes the connection relationship between two objects and can represent two connection relationships.
- the connection between A and B can mean: A and B are directly connected, and A is connected through C and B.
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Abstract
一种通信装置以及信号采样方法,该通信装置包括:时钟控制电路、数据采样电路和时钟恢复电路。其中,时钟控制电路用于确定数据采样电路的采样时钟偏差,根据采样时钟偏差生成第一时钟控制信号,该第一时钟控制信号用于调整数据采样电路的采样时钟。时钟恢复电路用于根据第一时钟控制信号调整数据采样电路的采样时钟,并向数据采样电路发送时钟信号。数据采样电路用于根据时钟信号对输入的模拟信号进行采样。通过该通信装置可将数据采样电路的采样时钟锁定在最佳的采样时刻,无需对原始模拟信号进行过采样,也能够使得采样后的数字信号保留原始模拟信号的有用信息。此外,即使在大带宽场景下,也不会增加数据采样电路的复杂度。
Description
本申请涉及时钟同步技术领域,具体涉及一种通信装置以及信号采样方法。
在数字通信中,需要通过模拟数字转换器(analog to digital converter,ADC)将模拟信号转化为数字信号进行处理。为了使得数字信号保留原始模拟信号中的全部信息,理论上要求ADC的采样频率大于或等于原始模拟信号所占带宽的2倍,在数字域中再进行采样时钟恢复以确定最佳的采样时刻。由于信道传输时延以及发送端和接收端之间的时钟偏移,使得ADC无法在最佳采样时刻进行采样,导致采集的数据与原始数据之间存在偏差。为此,需要进行时钟同步。
目前常用的时钟同步方法有Gardner算法、开销辅助同步方法等。Gardner算法本质上是对采样的原始序列进行插值,使得原始序列在时域上扩展。采样时钟恢复时,对插值后的原始序列进行抽取(也称为降采样),以确定最佳的采样时刻。但是Gardner算法要求过采样,在大带宽场景下应用受限。开销辅助同步方法是指在数据信号中***低速的开销信号,在接收端进行窄带滤波,以恢复采样时钟。然而开销辅助同步方法带来额外的频谱开销,且要求接收端的滤波器的带宽窄,在大带宽***中,滤波器的设计难度较高。
可见,如何在大带宽场景下实现时钟同步是亟需解决的问题。
发明内容
本申请提供一种通信装置以及信号采样方法,用以实现采样时钟同步。
第一方面,本申请实施例提供一种通信装置,所述通信装置可以应用于接收机,该通信装置包括时钟控制电路、数据采样电路和时钟恢复电路。其中,时钟控制电路用于确定数据采样电路的采样时钟偏差,根据采样时钟偏差生成第一时钟控制信号,该第一时钟控制信号用于调整数据采样电路的采样时钟。时钟恢复电路用于根据第一时钟控制信号调整数据采样电路的采样时钟,并向数据采样电路发送时钟信号。数据采样电路用于根据时钟信号对输入的模拟信号进行采样。
其中,数据采样电路例如为ADC模块。在本申请实施例中,时钟控制电路可以根据数据采样电路的采样时钟偏差,生成相应的第一时钟控制信号反馈给时钟恢复电路。时钟恢复电路可以根据第一时钟控制信号对数据采样电路的采样时钟进行调整,并将调整后采样时钟获得的时钟信号反馈给数据采样电路,从而数据采样电路根据被调整后的采样时钟进行采样。数据采样电路可将根据调整后的采样时钟所采样的信号再反馈给时钟控制电路,由时钟控制电路再次确定数据采样电路的采样时钟偏差,并生成相应的时钟控制信号反馈给时钟恢复电路。时钟恢复电路可再次根据接收的时钟控制信号对数据采样电路的采样时钟进行调整,并将调整后采样时钟获得的时钟信号反馈给数据采样电路。由于时钟控制电路和时钟恢复电路配合对数据采样电路的采样时钟可以进行多次调整,因此,可将数据采样电路的采样时钟锁定在最佳的采样时刻。这样无需对原始模拟信号进行过采样,也能够使得采样后的数字信号保留原始模拟信号的有用信息。由于无需对原始模拟信号进行过采 样,即使在大带宽场景下,也不会增加ADC的复杂度以及接收机中滤波器的复杂度。
[根据细则91更正 18.10.2022]
在一种可能的设计中,当第一时钟控制信号指示数据采样电路的采样时钟偏差低于第一阈值,时钟信号为目标时钟信号,该目标时钟信号能够产生数据采样电路期望的采样时钟。数据采样电路期望的采样时钟,可以看作是,数据采样电路的最佳采样时钟。经过时钟恢复电路的多次调整,数据采样电路的实际采样时钟与最佳采样时钟逐渐减小,直到数据采样电路的实际采样时钟接近甚至等于最佳采样时钟,此时,时钟恢复电路生成的时钟信号称为目标时钟信号,即可以使得数据采样电路达到最佳采样时钟的时钟信号。
在一种可能的设计中,当第一时钟控制信号指示数据采样电路的采样时钟偏差低于第一阈值,时钟信号为目标时钟信号,该目标时钟信号能够产生数据采样电路期望的采样时钟。数据采样电路期望的采样时钟,可以看作是,数据采样电路的最佳采样时钟。经过时钟恢复电路的多次调整,数据采样电路的实际采样时钟与最佳采样时钟逐渐减小,直到数据采样电路的实际采样时钟接近甚至等于最佳采样时钟,此时,时钟恢复电路生成的时钟信号称为目标时钟信号,即可以使得数据采样电路达到最佳采样时钟的时钟信号。
在一种可能的设计中,时钟恢复电路包括分路器、第一延迟器、第二延迟器和乘法器,其中,分路器和第一延迟器的输入端以及第二延迟器的输入端连接,乘法器和第一延迟器的输出端以及第二延迟器的输出端连接。第一延迟器的输出端和第二延迟器的输出端还连接时钟控制电路的输入端。分路器用于将输入的模拟信号分为第一模拟子信号和第二模拟子信号。第一延迟器用于根据第一时钟控制信号延迟第一模拟子信号,获得第一延迟信号,并将第一延迟信号输出给乘法电路以及时钟控制电路。第二延迟器用于根据第一时钟控制信号延迟第二模拟字信号,获得第二延迟信号,并将第二延迟信号输出给乘法电路以及时钟控制电路。乘法电路用于对第一延迟信号和第二延迟信号进行相乘处理,获得第一信号,并将第一信号输出给数据采样电路。
在本申请实施例中,输入时钟恢复电路的模拟信号和输入数据采样电路的模拟信号是相同的。因此,时钟恢复电路通过对输入的模拟信号进行处理,以实现调整数据采样电路的采样时钟。例如,时钟恢复电路通过将输入的模拟信号分为两路,并通过控制这两路的延迟时长来达到调整数据采样电路的采样时钟的目的,以使得数据采样电路的采样时钟达到最佳采样时钟。
在一种可能的设计中,时钟控制电路包括处理器和判决器,该处理器可用于根据数据采样电路输出的第一数字信号和第二数字信号确定采样时钟偏差,并根据采样时钟偏差,生成第一时钟控制信号;其中,第一数字信号为数据采样电路对输入的模拟信号进行采样得到的实部分量,第二数字信号为所述数据采样电路对模拟信号进行采样得到的虚部分量。判决器可用于根据第一延迟信号和第二延迟信号确定时钟恢复电路不能生成目标时钟信号,向时钟恢复电路输出第二时钟控制信号。
在本申请实施例中,随着时钟恢复电路可以使得数据采样电路的采用时钟偏差逐渐减小,直到数据采样电路的采样时钟达到最佳采样时钟,否则还需要通过时钟恢复电路继续调整数据采样电路的采样时钟。因此,时钟控制电路确定时钟恢复电路所生成的时钟信号不是目标时钟信号,则继续向时钟恢复电路输出时钟控制信号。
在可能的设计中,判决器还用于:根据第一延迟信号和第二延迟信号确定时钟恢复电路能够生成目标时钟信号,向时钟恢复电路输出指示信号。该指示信息指示无需调整数据采样电路的采样时钟。当时钟控制电路确定时钟恢复电路所生成的时钟信号为目标时钟信号,则向时钟恢复电路输出指示信号,以指示时钟恢复电路无需继续调整数据采样电路的采样时钟。
在可能的设计中,判决器具体用于:根据第一延迟信号确定第一模拟子信号被延迟的第一时长,根据第二延迟信号确定第二模拟子信号被延迟的第二时长。当第一时长和第二时长之差与数据采样电路期望的采样时钟之间的偏差大于第一阈值,确定时钟恢复电路不能生成目标时钟信号。
在可能的设计中,第一延迟器根据第一时钟控制信号延迟第一模拟子信号,包括:当第一时钟控制信号指示采样时钟偏差大于或等于第一取值,第一延迟器按照第一延迟步长延迟第一模拟子信号,当第一时钟控制信号指示采样时钟偏差小于第一取值,第一延迟器按照第二延迟步长延迟第一模拟子信号,其中,第一延迟步长大于第二延迟步长。第二延迟器根据第一时钟控制信号延迟第二模拟子信号,包括:当第一时钟控制信号指示采样时钟偏差大于或等于第一取值,第二延迟器按照第三延迟步长延迟第二模拟子信号,当第一时钟控制信号指示采样时钟偏差小于所述第一取值,第二延迟器按照第四延迟步长延迟第二模拟子信号,其中,第三延迟步长大于第四延迟步长。
在本申请实施例中,针对第一延迟器和第二延迟器可分别预定义多个延时步长,当数据采样时钟偏差较大时,相应的,第一延迟器和第二延迟器按照较长的延时步长对输入的模拟信号进行延迟;当数据采样时钟偏差较小时,相应的,第一延迟器和第二延迟器按照较短的延时步长对输入的模拟信号进行延迟,以提高采样时钟调整效率以及精度。
在可能的设计中,时钟恢复电路还包括:与乘法器连接的第一低通滤波器,用于滤除第一信号中的高频分量,从而降低由于高频分量带来的干扰。
在可能的设计中,时钟恢复电路还包括:与第一低通滤波器连接的限幅放大器,用于滤除第一低通滤波器输出的信号中幅度高于第一幅度的分量,以降低信号饱和的概率。
在可能的设计中,时钟恢复电路还包括:与限幅放大器连接的锁相环,用于使得目标时钟信号的频率与第一信号的频率一致,以提高相位的稳定性。
在可能的设计中,所述通信装置还包括相位锁定模块,该相位锁定模块与时钟控制电路和数据采样电路分别连接;其中,相位锁定电路用于:根据误差信号确定数据采样电路的采样相位偏差,根据采样相位偏差生成第三控制信号,并向数据采样电路输出第三控制信号。误差信号为数据采集电路输出的第一数字信号和第二数字信号之间的误差信号。第三控制信号用于指示数据采样电路对采样相位进行调整。
本申请实施例考虑到采样时钟的相位偏差,设置相位锁定电路。通过时钟控制电路计算数据采样电路的采样时钟的相位偏差,并反馈给相位锁定电路。由相位锁定电路反馈给数据采样电路调整采样时钟的相位。
在可能的设计中,相位锁定模块包括:与时钟控制电路依次连接的鉴相器、压控振荡器和第二低通滤波器。其中,第二低通滤波器的输入端与压控振荡器连接,输出端与数据采样电路连接。
第二方面,本申请实施例提供一种信号采样方法,该方法可由通信装置执行,该通信装置包括时钟控制电路、数据采样电路和时钟恢复电路。其中,时钟控制电路确定数据采样电路的采样时钟偏差,根据采样时钟偏差生成第一时钟控制信号,该第一时钟控制信号用于调整数据采样电路的采样时钟。时钟恢复电路根据第一时钟控制信号调整数据采样电路的采样时钟,并向数据采样电路发送时钟信号。数据采样电路根据时钟信号对输入的模拟信号进行采样。
[根据细则91更正 18.10.2022]
在一种可能的实现方式中,第一时钟控制信号指示数据采样电路的采样时钟偏差低于第一阈值,时钟信号为目标时钟信号,该目标时钟信号能够产生数据采样电路期望的采样时钟。
在一种可能的实现方式中,第一时钟控制信号指示数据采样电路的采样时钟偏差低于第一阈值,时钟信号为目标时钟信号,该目标时钟信号能够产生数据采样电路期望的采样时钟。
在一种可能的实现方式中,时钟恢复电路包括分路器、第一延迟器、第二延迟器和乘法器。第一延迟器与分路器以及时钟控制电路连接,第二延迟器与分路器以及时钟控制电 路连接。其中,分路器将输入的模拟信号分为第一模拟子信号和第二模拟子信号。第一延迟器根据第一时钟控制信号延迟第一模拟子信号,获得第一延迟信号,并将第一延迟信号输出给乘法电路以及时钟控制电路。第二延迟器根据第一时钟控制信号延迟第二模拟字信号,获得第二延迟信号,并将第二延迟信号输出给乘法电路以及时钟控制电路。乘法电路对第一延迟信号和第二延迟信号进行相乘处理,获得第一信号,并将第一信号输出给数据采样电路。
在一种可能的实现方式中,时钟控制电路包括处理器和延迟器,其中,处理器根据数据采样电路输出的第一数字信号和第二数字信号确定采样时钟偏差,并根据采样时钟偏差,生成第一时钟控制信号。第一数字信号为数据采样电路对输入的模拟信号进行采样得到的实部分量,第二数字信号为数据采样电路对输入的模拟信号进行采样得到的虚部分量。判决器根据第一延迟信号和第二延迟信号确定时钟恢复电路不能生成目标时钟信号,向时钟恢复电路输出第二时钟控制信号。
在一种可能的实现方式中,判决器还根据第一延迟信号和第二延迟信号确定时钟恢复电路能够生成目标时钟信号,向时钟恢复电路输出指示信号。该指示信息指示无需调整数据采样电路的采样时钟。
在一种可能的实现方式中,所述判决器具体用于:根据第一延迟信号确定第一模拟子信号被延迟的第一时长,根据第二延迟信号确定第二模拟子信号被延迟的第二时长,当第一时长和第二时长之差与所述数据采样电路期望的采样时钟之间的偏差大于第一阈值,确定时钟恢复电路不能生成目标时钟信号。
在一种可能的实现方式中,当第一时钟控制信号指示采样时钟偏差大于或等于第一取值,第一延迟器按照第一延迟步长延迟第一模拟子信号,当第一时钟控制信号指示采样时钟偏差小于第一取值,第一延迟器按照第二延迟步长延迟第一模拟子信号,其中,第一延迟步长大于第二延迟步长。当第一时钟控制信号指示采样时钟偏差大于或等于第一取值,第二延迟器按照第三延迟步长延迟第二模拟子信号,当第一时钟控制信号指示所述采样时钟偏差小于第一取值,第二延迟器按照第四延迟步长延迟第二模拟子信号,其中,第三延迟步长大于第四延迟步长。
[根据细则91更正 18.10.2022]
在一种可能的实现方式中,时钟恢复电路还包括与乘法电路连接的第一低通滤波器,该第一低通滤波器用于滤除第一信号中的高频分量。
在一种可能的实现方式中,时钟恢复电路还包括与乘法电路连接的第一低通滤波器,该第一低通滤波器用于滤除第一信号中的高频分量。
在一种可能的实现方式中,时钟恢复电路还包括与第一低通滤波器连接的限幅放大器,该限幅放大器用于滤除第一低通滤波器输出的信号中幅度高于第一幅度的分量。
在一种可能的实现方式中,时钟恢复电路还包括与限幅放大器连接的锁相环,该锁相环用于使得目标时钟信号的频率与第一信号的频率一致。
在一种可能的实现方式中,所述通信装置还包括相位锁定模块,相位锁定模块与时钟控制电路和数据采样电路分别连接,所述方法还包括:通过相位锁定电路根据误差信号确定数据采样电路的采样相位偏差,并根据采样相位偏差生成第三控制信号,以及向数据采样电路输出所述第三控制信号。其中,误差信号为数据采集电路输出的第一数字信号和第二数字信号之间的误差信号。第三控制信号用于指示数据采样电路对采样相位进行调整。
在一种可能的实现方式中,相位锁定模块包括与时钟控制电路依次连接的鉴相器、压控振荡器和第二低通滤波器。其中,第二低通滤波器的输入端与压控振荡器连接,输出端与数据采样电路连接。
第三方面,本申请实施例提供一种接收机,该接收机包括第一方面和第一方面中任一种可能的实施方式中所述的通信装置。
第四方面,本申请实施例提供了一种接收机,该接收机包括输入输出接口和逻辑电路。输入输出接口用于输入和/或输出信息。逻辑电路用于执行第二方面中所述的方法。
第五方面,本申请实施例提供一种芯片***,该芯片***包括通信接口和处理器,使得安装有***芯片的设备执行如第二方面或第二方面任一可能实现方式中所述的方法。在一种可能的实现方式中,所述芯片***还包括存储器,用于保存计算机程序。该芯片***可以由芯片构成,也可以包含芯片和其他分立器件。
第六方面,本申请提供了一种计算机可读存储介质,该计算机可读存储介质存储有计算机程序,当该计算机程序被运行时,实现上述第二方面或第二方面任一可能实现方式中所述的方法。
第七方面,提供了一种计算机程序产品,所述计算机程序产品包括:计算机程序代码,当所述计算机程序代码被运行时,使得上述第二方面或第二方面任一可能实现方式中所述的方法被执行。
上述第二方面至第七方面及其实现方式的有益效果可以参考对第一方面及其可能设计方式的有益效果的描述。
图1为本申请实施例适用的通信***的架构示意图;
图2为本申请实施例提供的通信装置的一种结构示意图;
图3本申请实施例提供的数据采样电路的最佳采样时钟需要满足的条件的示意图;
图4为本申请实施例提供的通信装置的另一种结构示意图;
图5为本申请实施例提供的通信装置的又一种结构示意图;
图6为本申请实施例提供的数据采样电路的实际采样时钟与期望的采样时钟之间的偏差示意图。
本申请的实施例提供的技术方案可以应用于需要进行ADC的设备,例如接收机。该接收机可以通过无线信道或者有线线缆与发射机进行通信。作为一种示例,请参见图1,为本申请实施例适用的一种通信***的网络架构示意图,该通信***可包括发射机和接收机。图1以发射机和接收机通过有线线缆进行通信为例。其中,发射机包括基带芯片、数模转换器(digital to analog converter,DAC)、射频芯片以及功率放大器。基站芯片用于对要发送的信号进行处理,并将处理后得到的数字信号发送给DAC进行数模转换处理,即将数字信号转换为模拟信号。该模拟信号经过射频芯片变为射频信号,再经过功率放大器由无线信道或者有线线缆传输给接收机中的射频芯片。接收机中的射频芯片对所接收的射频信息进行下变频处理,再经过ADC转化为数字信号,该数字信号可用于还原发射机发送的信号所携带的信息。接收机中的基带处理芯片对该数字信号进行处理可获得发射机发送的原始信息。需要说明的是,图1中发射机和接收机所包括的器件仅是举例,还可以包 括其他可能的器件,例如滤波器、混频器等,这里不再一一列举。
为了使得数字信号保留发射机发送的模拟信号中的全部信息,理论上要求ADC的采样频率大于或等于原始模拟信号所占带宽的2倍。考虑到一些因素的影响,无法保证较为准确的采样频率,甚至通常需要ADC以更大的采样频率进行采样(也称为过采样)。ADC过采样,相应地,在数字域中需要进行采样时钟恢复以确定最佳的采样时刻。由于信道传输时延以及发送端和接收端之间的时钟偏移,无法使得ADC在最佳采样时刻进行采样,导致采集的数据以原始数据之间存在偏差,为此,需要进行时钟同步,如图1所示。通过采样时钟同步可以使得ADC在最佳采样时刻进行采样。
目前常用的时钟同步方法有Gardner算法、开销辅助同步方法等。Gardner算法本质上是对采样的原始序列进行插值,使得原始序列在时域上扩展。采样时钟恢复时,对插值后的原始序列进行抽取(也称为降采样),以确定最佳的采样时刻。但是Gardner算法要求过采样,在大带宽场景下应用受限。开销辅助同步方法是指在数据信号中***低速的开销信号,在接收端进行窄带滤波,以恢复采样时钟。然而开销辅助同步方法带来额外的频谱开销,且要求接收端的滤波器的带宽窄,在大带宽***中,滤波器的设计难度较高。
在本申请实施例中,可将ADC的采样时钟锁定在期望的采样时钟(最佳采样时钟)。由于ADC被锁定工作在最佳的采用时钟,因此无需对原始模拟信号进行过采样,也能够使得采样后的数字信号保留原始模拟信号的有用信息。由于ADC无需对原始模拟信号进行过采样,即ADC的采样频率与原始模拟信号所在带宽大小无关,因此,通过本申请实施例提供的方案,即使在大带宽场景下,也不会增加ADC的复杂度以及接收机中滤波器的复杂度。
下面结合附图介绍本申请实施例提供的技术方案。在本申请实施例中,高频和低频是相对而言的,例如,高频的频率范围可为[1.5×Fs,~],低频的频率范围可为[0,1.5×Fs],其中,Fs为第一信号的带宽。延迟器也称为延时器。
请参见图2,为本申请实施例提供的通信装置的结构示意图。该通信装置可应用到接收机。如图2所示,该通信装置包括时钟控制电路201、时钟恢复电路202和数据采样电路203。时钟控制电路201与数据采样电路203和时钟恢复电路分别连接,时钟恢复电路202还与数据采样电路203连接。数据采样电路203例如为ADC模块。需要说明的是,时钟控制电路201和时钟恢复电路202可以是独立的两个电路或物理器件(本文以此为例),也可以集成在一起。换句话说,时钟控制电路201和时钟恢复电路202可以是集成的一个器件,例如为时钟数据恢复(carrier data recovery,CDR)模块。
时钟控制电路201可根据数据采样电路203所采集的信号确定数据采样电路203的采样时钟偏差,并反馈给时钟恢复电路202。时钟恢复电路202可根据时钟控制电路201反馈的采样时钟偏差对数据采样电路203的采样时钟进行调整,并将调整后的采样时钟反馈给数据采样电路203。数据采样电路203根据时钟恢复电路202反馈的采样时钟进行采样,将采样后的信号输出给时钟控制电路201。经过时钟恢复电路202的调整可使得数据采样电路203的采样时钟偏差变小。如果经过时钟恢复电路202的一次调整,数据采样电路203的采样时钟与最佳采样时钟还是存在偏差,那么可再次对数据采样电路203的采样时钟进行调整。例如,数据采样电路203可将根据调整后的采样时钟所采样的信号再反馈给时钟控制电路201,由时钟控制电路201再次确定数据采样电路的采样时钟偏差,并生成相应的时钟控制信号反馈给时钟恢复电路202。时钟恢复电路202可再次根据接收的时钟控制 信号对数据采样电路203的采样时钟进行调整,并将调整后采样时钟获得的时钟信号反馈给数据采样电路203。以此类推,经过时钟控制电路201和时钟恢复电路202对数据采样电路203的采样时钟进行多次调整,直到数据采样电路203的实际采样时钟达到最佳采样时钟。
数据采样电路203的实际采样时钟达到最佳采样时钟,也可以理解为,数据采样电路203的采样时钟偏差低于第一阈值。该第一阈值可以是预设置的或者预配置的,本申请实施例对第一阈值的大小不作限制。例如,第一阈值可以是根据实验测试所得的可能的取值。根据对采样精度的不同,第一阈值的大小也可以不同。举例来说,第一阈值可以是归一化的时钟偏差,例如为10
-6。可以理解的是,数据采样电路203的采样时钟偏差低于第一阈值,时钟控制电路生成的时钟控制信号用于调整数据采样电路203的采样时钟;当数据采样电路203的采样时钟偏差大于或者等于第一阈值,时钟控制电路201可生成指示信号,该指示信号指示数据采样电路203的采样时钟偏差低于第一阈值,时钟恢复电路202根据时钟控制电路201反馈的指示信号,可确定无需继续调整数据采样电路203的采样时钟。此时,时钟恢复电路202不调整数据采样电路203的采样时钟,直接向数据采样电路203输出最终的时钟信号(本文中称为目标时钟信号),该目标时钟信号可以使得数据采样电路203的采样时钟达到期望的采样时钟。
为方便理解,下文以接收机从发射机接收第一模拟信号为例,该第一模拟信号分为两路信号,这两路信号分别称为I信号和Q信号。其中,I信号为第一模拟信号的实部分量,Q信号为第一模拟信号的虚部分量。
请继续参见图2,I信号和本振信号经过混频器之后,再经过低通滤波器之后,输入数据采样电路203。类似的,Q信号和本振信号经过混频器之后,再经过低通滤波器之后,输入数据采样电路203。I信号经过数据采集电路203的采样得到第一数字信号,Q信号经过数据采集电路203的采样得到第二数字信号。数据采样电路203将第一数字信号和第二数字信号输出给时钟控制电路201。例如,第一数字信号I′[k]和第二数字信号Q′[k]分别满足如下的公式:
其中,I
k+jQ
k为数据采样电路203对第一模拟信号进行采样得到的数字信号,Ts为数据采样电路203的采样时钟,θ
o为数据采样电路203的采样相位偏差,Δf为数据采样电路203的采样频率偏差,k为索引。
时钟控制电路201可根据第一数字信号和第二数字信号确定数据采样电路203的采样时钟偏差,并根据该采样时钟偏差。例如,时钟控制电路201根据I′[k]和I
k之间的第一偏差信号
例如,时钟控制电路201根据Q′[k]和Q
k之间的第二偏差信号
其中,m为预设的一个整数。
时钟控制电路201确定第一偏差信号和第二偏差信号之后,可根据第一偏差信号和第二偏差信号确定采样时钟偏差err_clock=error_s_I+j×error_s_Q。进而根据采样时钟偏差生成时钟控制信号err_clock。时钟控制信号err_clock可以是偏差信号err_clock的线性函数,例如,error_s=k×(err_clock),k大于0。可以理解的是,当error_s最小时,err_clock也最小。因此可根据error_s来调节err_clock的大小和方向。
可以理解的是,经过时钟恢复电路202的多次调整可使得数据采样电路203的采样时钟偏差逐渐减小,即error_s逐渐减小。相应的,时钟控制信号所指示时钟恢复电路202对 于采样时钟的调整量也减小。即通过不同次数调整,时钟恢复电路202所生成的时钟控制信号不同。为方便描述,可将时钟控制电路201首次确定的时钟控制信号称为第一时钟控制信号。下面以时钟控制电路201生成的时钟控制信号为第一时钟控制信号介绍时钟恢复电路202如何根据时钟控制电路201反馈的时钟控制信号调整数据采样电路203的采样时钟。
在本申请实施例中,可将数据采样电路203的采样时钟锁定在最佳采样时钟。例如,通过时钟恢复电路202对输入数据采样电路203的模拟信号的采样时钟进行处理,根据处理结果判断数据采样电路203的采样时钟是否是最佳采样时钟。例如,时钟恢复电路通过将输入的模拟信号分为两路,并通过控制这两路的延迟时长来达到调整数据采样电路的采样时钟。
在可能的设计中,时钟恢复电路202可以包括分路器2021、第一延迟器2022、第二延迟器2023和乘法器2024。其中,分路器2021用于将第一模拟信号分为第一模拟子信号r
IF(t)和第二模拟子信号r
IF(t)。r
IF(t)满足:r
IF(t)=real(A(t)×exp(j×2×π×f0×t))。其中,A(t)为第一模拟信号,f0为载波频率,t为时间,real表示求取复数的实部,exp为指数函数。第一模拟子信号r
IF(t)输出给第一延迟器2022,第二模拟子信号r
IF(t)输出给第二延迟器2023。第一时钟控制信号分别反馈到第一延迟器2022和第二延迟器2023的输入端。需要说明的是,分路器2021也可以是功分器,只要可以将一路信号分为两路信号即可,例如,分路器2021可以是二功分器。
第一延迟器2022可根据第一时钟控制信号延迟第一模拟子信号r
IF(t),第二延迟器2023可根据第一时钟控制信号延迟第二模拟子信号r
IF(t)。假设第一模拟子信号r
IF(t)延迟时长τ
1,第二模拟子信号r
IF(t)延迟时长τ
2,延迟后的第一模拟子信号r
IF(t)记为r
IF(t-τ
1),延迟后的第二模拟子信号r
IF(t)记为r
IF(t-τ
2)。r
IF(t-τ
1)和r
IF(t-τ
2)经过乘法器2024之后得到第一信号S
1(t)=r
IF(t-τ
1)×r
IF(t-τ
2)。第一信号S
1(t)经过低通滤波器滤除高频成分可得:
其中,Ts为数据采样电路203期望的采样时钟,A
n中的A为信号的幅度,n为级数,n的取值范围从很小的负数到很大的正整数,函数g表示整型函数,函数g′表示等效的整形函数,t表示时间,τ表示π,f
IF表示载波频率。
S
2(t)的功率谱S
2(f)满足:
其中,Ts为数据采样电路203的最佳采样时钟。请参见图3,示出了功率谱S
2(f)。图3中纵坐标为S
2(f)。从图3中可以看出,当(τ
2-τ
1)=T
s时,
最大,因此,当τ
2-τ
1=T
s,可以确定时钟恢复电路202已经将数据采样电路203的采样时钟调整为期望的采样时钟。当τ
2-τ
1≠T
s时,数据采样电路203的采样时钟调整还没有达到期望的采样时钟,时钟恢复电路202需要继续调整数据采样电路203的采样时钟,即时钟恢复电路202需要通过第一延迟器2022和第二延迟器2023继续延迟所接收的信号。
应理解,第一延迟器2022和第二延迟器2023对所接收的信号进行延迟,实际上是对所接收的信号在时域上进行移位。在本申请实施例中,第一延迟器2022和第二延迟器2023 对所接收的信号在时域上的移位是相反的,即τ
1为正数时,τ
2为负数;τ
1为负数时,τ
2为正数。时钟恢复电路202经过多次调整可使得数据采样电路203的采样时钟偏差逐渐减小,直到将数据采样电路203的采样时钟调整为期望的采样时钟。由于多次调整过程中,数据采样电路203的采样时钟偏差会逐渐减小,因此,时钟恢复电路202通过第一延迟器2022对所接收到信号延迟时长也应该适应性减小,同理,第二延迟器2023对所接收的信号延迟时长也应该适应性减小。
在可能的设计中,针对第一延迟器2022和第二延迟器2023可分别预定义多个延时步长。时钟恢复电路202接收到来自时钟控制电路201的时钟控制信号,可根据该时钟控制信号指示的采样时钟偏差的大小选择与第一延迟器2022匹配的延迟步长,以及与第二延迟器2023匹配的延迟步长。以第一延迟器2022为例,可预定义第一延时步长、第二延迟步长和第三延迟步长。其中,第一延迟步长大于第二延迟步长,第二延迟步长大于第三延迟步长。如果第一延迟器2022从时钟控制电路201接收的时钟控制信号指示采样时钟偏差大于或等于第一取值,第一延迟器2022按照第一延迟步长τ
11延迟第一模拟子信号,获得延迟信号,记为r
IF(t-τ
11)。如果第一延迟器2022从时钟控制电路201接收的时钟控制信号指示采样时钟偏差大于或等于第二取值,第一延迟器2022按照第二延迟步长τ
12延迟第一模拟子信号,获得延迟信号,记为r
IF(t-τ
12)。其中,第一取值大于第二取值。
类似地,针对第二延迟器2023,也可以预定义第四延时步长、第五延迟步长和第六延迟步长。其中,第四延迟步长大于第五延迟步长,第五延迟步长大于第六延迟步长。如果第二延迟器2023从时钟控制电路201接收的时钟控制信号指示采样时钟偏差大于或等于第一取值,第二延迟器2023按照第四延迟步长τ
21延迟第一模拟子信号,获得延迟信号,记为r
IF(t-τ
21)。如果第二延迟器2023从时钟控制电路201接收的时钟控制信号指示采样时钟偏差大于或等于第二取值,第二延迟器2023按照第五延迟步长τ
22延迟第一模拟子信号,获得延迟信号,记为r
IF(t-τ
22)。可以理解的是,第一延迟步长、第二延迟步长和第三延迟步长为正数,第四延时步长、第五延迟步长和第六延迟步长为负数;或者,第一延迟步长、第二延迟步长和第三延迟步长为负数,第四延时步长、第五延迟步长和第六延迟步长为正数。本申请实施例对第一延迟步长、第二延迟步长和第三延迟步长的大小不作限制,以及对第四延时步长、第五延迟步长和第六延迟步长的大小也不作限制。
需要说明的是,分路器2021、第一延迟器2022、第二延迟器2023和乘法器2024中的部分器件或者全部器件可以是集成在一起的。例如,第一延迟器2022和第二延迟器2023可以集成在一起,作为一个器件。
第一延迟器2022和第二延迟器2023将生成的信号反馈给时钟控制电路201,由时钟控制电路201确定第一延迟器2022和第二延迟器2023是否已经将数据采样电路203当前的采样时钟调整为期望的采样时钟。为方便描述,将第一延迟器2022生成的信号称为第一延迟信号,将第二延迟器2023生成的信号称为第二延迟信号。
时钟控制电路201从第一延迟器2022接收第一延迟信号,从第二延迟器2023接收第二延迟信号,确定时钟恢复电路202是否已经将数据采样电路203当前的采样时钟调整为期望的采样时钟。例如,时钟控制电路201包括判决器2012,通过判决器2012根据第一延迟信号确定第一模拟子信号被延迟的第一时长,以及根据第二延迟信号确定第二模拟子信号被延迟的第二时长。如果第一时长和第二时长之差与数据采样电路203期望的采样时钟Ts之间的偏差大于第一阈值,乘法器2024对第一延迟信号和第二延迟信号进行相乘处 理获得的第一信号,即时钟恢复电路202生成的时钟信号不是目标时钟信号,也就是时钟恢复电路202不能生成目标时钟信号。
这种情况下,时钟控制电路201继续根据从数据采样电路203接收的I信号和Q信号计算采样时钟偏差,并根据该采样时钟偏差生成新的时钟控制信号,例如称为第二时钟控制信号。例如,时钟控制电路201中的处理器2011根据从数据采样电路203接收的I信号和Q信号计算采样时钟偏差,并根据该采样时钟偏差生成第二时钟控制信号。该第二时钟控制信号可指示数据采用电路203的采样时钟偏差低于第二阈值。该第二时钟控制信号反馈给第一延迟器2022和第二延迟器2023,第一延迟器2022和第二延迟器2023根据第二时钟控制信号分别对所接收的信号进行延迟,并将所生成的延迟信号再次反馈给时钟控制电路201,以此类推。直到时钟控制电路201确定第一延迟信号对应的延迟时长和第二延迟信号对应的延迟时长之间的差值与数据采样电路203期望的采样时钟Ts之间的偏差小于或等于第一阈值。此时,时钟控制电路201向第一延迟器2022和第二延迟器2023反馈的指示信号,该指示信号指示数据采样电路203的采样时钟偏差低于第一阈值。乘法器2024对第一延迟信号和第二延迟信号进行相乘处理获得的第一信号为目标时钟信号。应理解,指示信号为时钟控制信号的特例,其具体实现形式同时钟控制信号。可以理解的是,如果数据采样电路203的采样时钟经过调整达到期望的采样时钟,但是后续使用过程中,数据采样电路203的实际采样时钟与期望的采样时钟出现偏差,那么可继续使用前述的方法调整数据采样电路203的采样时钟,以尽量使得数据采样电路203的实际采样时钟为期望的采样时钟。
考虑到乘法器2024输出的第一信号包含的高频分量可能会造成干扰,在可能的设计中,时钟恢复电路202还可以用于滤除第一信号的高频分量的功能模块。例如,请参见图4,时钟恢复电路202除了包括乘法器2024,还可以包括与乘法器2024连接的低通滤波器2025。低通滤波器2025可滤除第一信号中的高频分量,从而降低第一信号可能会造成的干扰。
如果第一信号的幅度过大,可能会因为饱和引起目标时钟信号的不准确。为此,时钟恢复电路202还可以包括与低通滤波器2025连接的限幅放大器2026。例如,时钟恢复电路202可包括乘法器2024、低通滤波器2025和限幅放大器2026,如图4所示。该限幅放大器2026可滤除低通滤波器2025输出的信号中幅度高于预设幅度的分量,以降低第一信号造成幅度饱和的概率。
如果限幅放大器2026输出的信号的频率无法固定,那么采样时钟可能无法收敛,即采样时钟不稳定。为此,时钟恢复电路202还可以包括与限幅放大器2026连接的锁相环2027。例如,时钟恢复电路202可包括乘法电路2024、低通滤波器2025、限幅放大器2026和锁相环2027,如图4所示。该锁相环2027可以使得目标时钟信号的频率与乘法电路2024输出的第一信号的频率一致,以降低由于相位不稳定造成采样时钟不稳定的概率。
请参见图5,本申请实施例提供的通信装置还可以包括相位锁定模块204,例如,通信装置包括时钟控制电路201、时钟恢复电路202、数据采样电路203以及相位锁定模块204。其中,时钟控制电路201可用于消除数据采样电路203的采样相位偏差。具体的,相位锁定模块204可包括鉴相器2041、压控振荡器2042和低通滤波器2043。其中,鉴相器2041的输入端与时钟控制电路201连接,鉴相器2041的输出端与压控振荡器2042的输入端连接。压控振荡器2042的输出端与低通滤波器2043的输入端连接,低通滤波器2043 的输出端与数据采样电路连接。
时钟控制电路201中的处理器2011可根据从数据采样电路203接收的第一数字信号和第二数字信号来确定数据采样电路的采样相位偏差。为方便描述,将第一数字信号记为I′(k),第二数字信号记为Q′(k)。假设不存在采样相位偏差,那么数字采样电路203输出的信号为I
k+jQ
k。有:
其中,Δf为频率偏差,θ
0为采样相位偏差,即期望的采样时钟和实际采样时钟之间的偏差,如图6所示。
时钟控制电路201中的处理器2011可以提取I
k+jQ
k与I′(k)+Q′(k)之间的偏差信号error。如前述可知:
处理器2011将该偏差信号反馈给鉴相器2041,经过压控振荡器2042确定采样相位偏差。压控振荡器2042根据该采样相位偏差生成第三控制信号,经过低通滤波器2043滤除第三控制信号中的高频分量,输出给数据采样电路203。为节省资源,该第三控制信号可以指示采样相位调大或调小,从而保证数据采样电路203的采样相位稳定。
通过本申请实施例提供的通信装置,可将数据采样电路203(即ADC)的采样时钟锁定在期望的采样时钟(最佳采样时钟)。由于ADC被锁定工作在最佳的采用时钟,因此无需对原始模拟信号进行过采样,也能够使得采样后的数字信号保留原始模拟信号的有用信息。由于ADC的采样频率与原始模拟信号所在带宽大小无关,因此可实现对各种带宽下的模拟信号的采样。且由于ADC无需对原始模拟信号进行过采样,即使在大带宽场景下,也不会增加ADC的复杂度以及接收机中滤波器的复杂度。
所述本申请提供的实施例中,从通信装置包括的各个电路(或者器件或者功能模块)之间信号的处理以及传输路径对本申请实施例提供的通信装置进行了介绍。该通信装置包括的各个功能模块可以是硬件结构和/或软件模块,以硬件结构、软件模块、或硬件结构加软件模块的形式来实现上述各功能。上述各功能中的某个功能以硬件结构、软件模块、还是硬件结构加软件模块的方式来执行,取决于技术方案的特定应用和设计约束条件。
例如,该通信装置包括的各个电路(或者器件或者功能模块)可以是独立的,也可以是集成在一起的,或者相互耦合。例如,该通信装置可以为芯片***。本申请实施例中,芯片***可以由芯片构成,也可以包含芯片和其他分立器件。具体的功能可以参见上述实施例中的说明。
又例如,处理器2011和判决器2012可以独立,也可以耦合在一起。耦合后的处理器2011和判决器2012,也可以称为处理器,该处理器也可以称为处理单元或处理模块,可以实现一定的控制功能。处理器可以是通用处理器或者专用处理器等。例如,包括:中央处理器,应用处理器,调制解调处理器,图形处理器,图像信号处理器,数字信号处理器,视频编解码处理器,控制器,存储器,和/或神经网络处理器等。所述中央处理器可以用于对通信装置进行控制,执行软件程序和/或处理数据。不同的处理器可以是独立的器件,也可以是集成在一个或多个处理器中,例如,集成在一个或多个专用集成电路上。
本申请实施例中的耦合是装置、单元或模块之间的间接耦合或通信连接,可以是电性,机械或其它的形式,用于装置、单元或模块之间的信息交互。耦合的多个模块可以协同操作。
需要说明的是,上述实施例中的通信装置也可以是电路,也可以是应用于设备中的芯 片或者其他具有上述通信装置功能的组合器件、部件等。
本申请实施例还提供了一种接收机,该接收机包括前述实施例中的通信装置。该接收机还包括其他必须的功能器件,例如,收发器以及天线。所述收发器可以称为收发单元,收发模块、收发机、收发电路、收发器,输入输出接口等,用于通过天线实现接收机的收发功能。
实现本文描述的通信装置,可以是独立设备(例如,独立的集成电路,手机等),或者可以是较大设备中的一部分(例如,可嵌入在其他设备内的模块),具体可以参照前述关于终端设备,以及网络设备的说明,在此不再赘述。
可选地,通信装置还可以包括以下一个或多个部件:无线通信模块,音频模块,外部存储器接口,内部存储器,通用串行总线(universal serial bus,USB)接口,电源管理模块,天线,扬声器,麦克风,输入输出模块,传感器模块,马达,摄像头,或显示屏等等。可以理解,在一些实施例中,通信装置可以包括更多或更少部件,或者某些部件集成,或者某些部件拆分。这些部件可以是硬件,软件,或者软件和硬件的组合实现。
基于与上述同样的发明构思,本申请实施例还提供一种信号采样方法,应用于接收机,该接收机包括通信装置,该通信装置包括时钟控制电路201、时钟恢复电路202和数据采样电路203。该方法包括:通过时钟控制电路201确定数据采样电路203的采样时钟偏差,根据采样时钟偏差生成第一时钟控制信号,该第一时钟控制信号用于调整数据采样电路203的采样时钟;通过时钟恢复电路202根据第一时钟控制信号调整数据采样电路203的采样时钟,并向数据采样电路203发送时钟信号;通过数据采样电路203根据时钟信号对输入的模拟信号进行采样。
在一种可能的实现方式中,第一时钟控制信号指示数据采用电路203的采样时钟偏差低于第一阈值,时钟信号为目标时钟信号,该目标时钟信号能够产生数据采样电路203期望的采样时钟。
在一种可能的实现方式中,时钟恢复电路202包括分路器2021、第一延迟器2022、第二延迟器2023和乘法电路2024。第一延迟器2022与分路器2021以及时钟控制电路201连接,第二延迟器2023与分路器2021以及时钟控制电路201连接。其中,分路器2021将输入的模拟信号分为第一模拟子信号和第二模拟子信号。第一延迟器2022根据第一时钟控制信号延迟第一模拟子信号,获得第一延迟信号,并将第一延迟信号输出给乘法电路2024以及时钟控制电路201。第二延迟器2023根据第一时钟控制信号延迟第二模拟字信号,获得第二延迟信号,并将第二延迟信号输出给乘法电路2024以及时钟控制电路201。乘法电路2024对第一延迟信号和第二延迟信号进行相乘处理,获得第一信号,并将第一信号输出给数据采样电路203。
在一种可能的实现方式中,时钟控制电路201包括处理器2011和延迟器2012,其中,处理器2011根据数据采样电路203输出的第一数字信号和第二数字信号确定采样时钟偏差,并根据采样时钟偏差,生成第一时钟控制信号。第一数字信号为数据采样电路203对输入的模拟信号进行采样得到的实部分量,第二数字信号为数据采样电路203对输入的模拟信号进行采样得到的虚部分量。判决器2012根据第一延迟信号和第二延迟信号确定时钟恢复电路202不能生成目标时钟信号,向时钟恢复电路202输出第二时钟控制信号。
在一种可能的实现方式中,判决器2012还根据第一延迟信号和第二延迟信号确定时钟恢复电路202能够生成目标时钟信号,向时钟恢复电路202输出指示信号。该指示信息 指示无需调整数据采样电路203的采样时钟。
在一种可能的实现方式中,判决器2012具体用于:根据第一延迟信号确定第一模拟子信号被延迟的第一时长,根据第二延迟信号确定第二模拟子信号被延迟的第二时长,当第一时长和第二时长之差与所述数据采样电路203期望的采样时钟之间的偏差大于第一阈值,确定时钟恢复电路202不能生成目标时钟信号。
在一种可能的实现方式中,当第一时钟控制信号指示采样时钟偏差大于或等于第一取值,第一延迟器2022按照第一延迟步长延迟第一模拟子信号,当第一时钟控制信号指示采样时钟偏差小于第一取值,第一延迟器2022按照第二延迟步长延迟第一模拟子信号,其中,第一延迟步长大于第二延迟步长。当第一时钟控制信号指示采样时钟偏差大于或等于第一取值,第二延迟器2023按照第三延迟步长延迟第二模拟子信号,当第一时钟控制信号指示所述采样时钟偏差小于第一取值,第二延迟器2023按照第四延迟步长延迟第二模拟子信号,其中,第三延迟步长大于第四延迟步长。
在一种可能的实现方式中,时钟恢复电路202还包括与乘法电路2024连接的第一低通滤波器2025,该第一低通滤波器2025用于滤除第一信号中的高频分量。
在一种可能的实现方式中,时钟恢复电路202还包括与第一低通滤波器2025连接的限幅放大器2026,该限幅放大器2026用于滤除第一低通滤波器2025输出的信号中幅度高于第一幅度的分量。
在一种可能的实现方式中,时钟恢复电路202还包括与限幅放大器2026连接的锁相环2027,该锁相环2027用于使得目标时钟信号的频率与第一信号的频率一致。
在一种可能的实现方式中,所述通信装置还包括相位锁定模块204,该相位锁定模块204与时钟控制电路201和数据采样电路203分别连接,所述方法还包括:通过相位锁定电路204根据误差信号确定数据采样电路203的采样相位偏差,并根据采样相位偏差生成第三控制信号,以及向数据采样电路203输出所述第三控制信号。其中,误差信号为数据采集电路203输出的第一数字信号和第二数字信号之间的误差信号。第三控制信号用于指示数据采样电路203对采样相位进行调整。
在一种可能的实现方式中,相位锁定模块包括与时钟控制电路201依次连接的鉴相器2041、压控振荡器2042和第二低通滤波器2043。其中,第二低通滤波器2043的输入端与压控振荡器2042连接,输出端与数据采样电路203连接。
本申请实施例还提供一种通信***,具体的,通信***包括图2-图5任一所述的通信装置和发送装置。具体请参考上述方法实施例中的相关描述,这里不再赘述。
本申请实施例中还提供一种计算机可读存储介质,包括指令,当其在计算机上运行时,使得计算机实现如图2-图5任一所述的通信装置的功能。
本申请实施例中还提供一种计算机程序产品,包括指令,当其在计算机上运行时,使得计算机实现如图2-图5任一所述的通信装置的功能。
本申请实施例提供了一种芯片***,该芯片***包括处理器,还可以包括存储器,使得安装有该芯片***的设备实现如图2-图5任一所述的通信装置的功能。该芯片***可以由芯片构成,也可以包含芯片和其他分立器件。
应理解,在本申请的各种实施例中,上述各过程的序号的大小并不意味着执行顺序的先后,各过程的执行顺序应以其功能和内在逻辑确定,而不应对本申请实施例的实施过程构成任何限定。
本领域普通技术人员可以意识到,结合本文中所公开的实施例描述的各种说明性逻辑块(illustrative logical block)和步骤(step),能够以电子硬件、或者计算机软件和电子硬件的结合来实现。这些功能究竟以硬件还是软件方式来执行,取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能,但是这种实现不应认为超出本申请的范围。
所属领域的技术人员可以清楚地了解到,为描述的方便和简洁,上述描述的***、装置和单元的具体工作过程,可以参考前述方法实施例中的对应过程,在此不再赘述。
在本申请所提供的几个实施例中,应该理解到,所揭露的***、装置和方法,可以通过其它的方式实现。例如,以上所描述的装置实施例仅仅是示意性的,例如,所述单元的划分,仅仅为一种逻辑功能划分,实际实现时可以有另外的划分方式,例如多个单元或组件可以结合或者可以集成到另一个***,或一些特征可以忽略,或不执行。另一点,所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口,装置或单元的间接耦合或通信连接,可以是电性,机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的,作为单元显示的部件可以是或者也可以不是物理单元,即可以位于一个地方,或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
所述功能如果以软件功能单元的形式实现并作为独立的产品销售或使用时,可以存储在一个计算机可读取存储介质中。基于这样的理解,本申请的技术方案本质上做出贡献的部分或者该技术方案的部分可以以软件产品的形式体现出来,该计算机软件产品存储在一个存储介质中,包括若干指令用以使得一台计算机设备(可以是个人计算机,服务器,或者网络设备等)执行本申请各个实施例所述方法的全部或部分步骤。而前述的存储介质包括:U盘、移动硬盘、只读存储器(read-only memory,ROM)、随机存储存储器(random access memory,RAM)、磁碟或者光盘等各种可以存储程序代码的介质。
需要说明的是,本申请中所涉及的连接,描述两个对象的连接关系,可以表示两种连接关系,例如,A和B连接,可以表示:A与B直接连接,A通过C和B连接这两种情况。另外,需要理解的是,在本申请的描述中,“第一”、“第二”等词汇,仅用于区分描述的目的,而不能理解为指示或暗示相对重要性,也不能理解为指示或暗示顺序。此外,本申请实施例中提供的***结构和业务场景主要是为了解释本申请的技术方案的一些可能的实施方式,不应被解读为对本申请的技术方案的唯一性限定。本领域普通技术人员可以知晓,随着***的演进,以及更新的业务场景的出现,本申请提供的技术方案对于相同或类似的技术问题仍然可以适用。
显然,本领域的技术人员可以对本申请进行各种改动和变型而不脱离本申请的保护范围。这样,倘若本申请的这些修改和变型属于本申请权利要求及其等同技术的范围之内,则本申请也意图包含这些改动和变型在内。
Claims (28)
- 一种通信装置,其特征在于,包括时钟控制电路、数据采样电路和时钟恢复电路;其中,所述时钟控制电路,用于确定所述数据采样电路的采样时钟偏差,根据所述采样时钟偏差生成第一时钟控制信号,所述第一时钟控制信号用于调整所述数据采样电路的采样时钟;所述时钟恢复电路,用于根据所述第一时钟控制信号调整所述数据采样电路的采样时钟,并向所述数据采样电路发送时钟信号;所述数据采样电路,用于根据所述时钟信号对输入的模拟信号进行采样。
- [根据细则91更正 18.10.2022]
如权利要求1所述的装置,其特征在于,当所述第一时钟控制信号指示所述数据采样电路的采样时钟偏差低于第一阈值,所述时钟信号为目标时钟信号,所述目标时钟信号能够产生所述数据采样电路期望的采样时钟。 - 如权利要求1或2所述的装置,其特征在于,所述时钟恢复电路包括:分路器,用于将输入的模拟信号分为第一模拟子信号和第二模拟子信号;第一延迟器,与所述分路器以及所述时钟控制电路连接,用于根据所述第一时钟控制信号延迟所述第一模拟子信号,获得第一延迟信号,并将所述第一延迟信号输出给乘法电路以及所述时钟控制电路;第二延迟器,与所述分路器以及所述时钟控制电路连接,用于根据所述第一时钟控制信号延迟所述第二模拟字信号,获得第二延迟信号,并将所述第二延迟信号输出给所述乘法电路以及所述时钟控制电路;所述乘法电路,用于对所述第一延迟信号和所述第二延迟信号进行相乘处理,获得第一信号,并将所述第一信号输出给所述数据采样电路。
- 如权利要求2-3任一项所述的装置,其特征在于,所述时钟控制电路包括:处理器,用于根据所述数据采样电路输出的第一数字信号和第二数字信号确定所述采样时钟偏差,并根据所述采样时钟偏差,生成所述第一时钟控制信号;其中,所述第一数字信号为所述数据采样电路对输入的模拟信号进行采样得到的实部分量,所述第二数字信号为所述数据采样电路对所述模拟信号进行采样得到的虚部分量;判决器,用于根据所述第一延迟信号和所述第二延迟信号确定所述时钟恢复电路不能生成所述目标时钟信号,向所述时钟恢复电路输出第二时钟控制信号。
- 如权利要求4所述的装置,其特征在于,判决器还用于:根据所述第一延迟信号和所述第二延迟信号确定所述时钟恢复电路能够生成所述目标时钟信号,向所述时钟恢复电路输出指示信号,所述指示信息指示无需调整所述数据采样电路的采样时钟。
- 如权利要求4所述的装置,其特征在于,所述判决器具体用于:根据所述第一延迟信号确定所述第一模拟子信号被延迟的第一时长;根据所述第二延迟信号确定所述第二模拟子信号被延迟的第二时长;当所述第一时长和所述第二时长之差与所述数据采样电路期望的采样时钟之间的偏差大于所述第一阈值,确定所述时钟恢复电路不能生成所述目标时钟信号。
- 如权利要求3所述的装置,其特征在于,所述第一延迟器根据所述第一时钟控制信 号延迟所述第一模拟子信号,包括:当所述第一时钟控制信号指示所述采样时钟偏差大于或等于第一取值,所述第一延迟器按照第一延迟步长延迟所述第一模拟子信号,当所述第一时钟控制信号指示所述采样时钟偏差小于所述第一取值,所述第一延迟器按照第二延迟步长延迟所述第一模拟子信号,其中,所述第一延迟步长大于所述第二延迟步长;所述第二延迟器根据所述第一时钟控制信号延迟所述第二模拟子信号,包括:当所述第一时钟控制信号指示所述采样时钟偏差大于或等于第一取值,所述第二延迟器按照第三延迟步长延迟所述第二模拟子信号,当所述第一时钟控制信号指示所述采样时钟偏差小于所述第一取值,所述第二延迟器按照第四延迟步长延迟所述第二模拟子信号,其中,所述第三延迟步长大于所述第四延迟步长。
- [根据细则91更正 18.10.2022]
如权利要求2-7任一项所述的装置,其特征在于,所述时钟恢复电路还包括:第一低通滤波器,与所述乘法电路连接,用于滤除所述第一信号中的高频分量。 - 如权利要求8所述的装置,其特征在于,所述时钟恢复电路还包括:限幅放大器,与所述第一低通滤波器连接,用于滤除所述第一低通滤波器输出的信号中幅度高于第一幅度的分量。
- 如权利要求9所述的装置,其特征在于,所述时钟恢复电路还包括:锁相环,与所述限幅放大器连接,用于使得所述目标时钟信号的频率与所述第一信号的频率一致。
- [根据细则91更正 18.10.2022]
如权利要求1-10任一项所述的装置,其特征在于,所述装置还包括相位锁定模块,所述相位锁定模块与所述时钟控制电路和所述数据采样电路分别连接;其中,所述相位锁定电路用于:根据误差信号确定所述数据采样电路的采样相位偏差,根据所述采样相位偏差生成第三控制信号,所述误差信号为所述数据采样电路输出的第一数字信号和第二数字信号之间的误差信号;向所述数据采样电路输出所述第三控制信号,所述第三控制信号用于指示所述数据采样电路对采样相位进行调整。 - 如权利要求11所述的装置,其特征在于,所述相位锁定模块包括:鉴相器,与所述时钟控制电路连接;压控振荡器,与所述鉴相器连接;第二低通滤波器,其输入端与所述压控振荡器连接,输出端与所述数据采样电路连接。
- 一种信号采样方法,其特征在于,应用于一种通信装置,所述通信装置包括时钟控制电路、数据采样电路和时钟恢复电路;其中,所述时钟控制电路确定所述数据采样电路的采样时钟偏差,根据所述采样时钟偏差生成第一时钟控制信号,所述第一时钟控制信号用于调整所述数据采样电路的采样时钟;所述时钟恢复电路根据所述第一时钟控制信号调整所述数据采样电路的采样时钟,并向所述数据采样电路发送时钟信号;所述数据采样电路根据所述时钟信号对输入的模拟信号进行采样。
- [根据细则91更正 18.10.2022]
如权利要求13所述的方法,其特征在于,当所述第一时钟控制信号指示所述数据采样电路的采样时钟偏差低于第一阈值,所述时钟信号为目标时钟信号,所述目标时钟信号能够产生所述数据采样电路期望的采样时钟。 - [根据细则91更正 18.10.2022]
如权利要求13或14所述的方法,其特征在于,所述时钟恢复电路包括分路器、第一延迟器、第二延迟器和乘法电路,所述第一延迟器与所述分路器以及所述时钟控制电路连接,所述第二延迟器与所述分路器以及所述时钟控制电路连接;其中,所述分路器将输入的模拟信号分为第一模拟子信号和第二模拟子信号;所述第一延迟器根据所述第一时钟控制信号延迟所述第一模拟子信号,获得第一延迟信号,并将所述第一延迟信号输出给乘法电路以及所述时钟控制电路;所述第二延迟器根据所述第一时钟控制信号延迟所述第二模拟字信号,获得第二延迟信号,并将所述第二延迟信号输出给所述乘法电路以及所述时钟控制电路;所述乘法电路对所述第一延迟信号和所述第二延迟信号进行相乘处理,获得第一信号,并将所述第一信号输出给所述数据采样电路。 - 如权利要求14-15任一项所述的方法,其特征在于,所述时钟控制电路包括处理器和延迟器,其中,所述处理器根据所述数据采样电路输出的第一数字信号和第二数字信号确定所述采样时钟偏差,并根据所述采样时钟偏差,生成所述第一时钟控制信号;其中,所述第一数字信号为所述数据采样电路对输入的模拟信号进行采样得到的实部分量,所述第二数字信号为所述数据采样电路对所述模拟信号进行采样得到的虚部分量;所述判决器根据所述第一延迟信号和所述第二延迟信号确定所述时钟恢复电路不能生成所述目标时钟信号,向所述时钟恢复电路输出第二时钟控制信号。
- 如权利要求16所述的方法,其特征在于,所述判决器还根据所述第一延迟信号和所述第二延迟信号确定所述时钟恢复电路能够生成所述目标时钟信号,向所述时钟恢复电路输出指示信号,所述指示信息指示无需调整所述数据采样电路的采样时钟。
- 如权利要求16所述的方法,其特征在于,所述判决器具体用于:根据所述第一延迟信号确定所述第一模拟子信号被延迟的第一时长;根据所述第二延迟信号确定所述第二模拟子信号被延迟的第二时长;当所述第一时长和所述第二时长之差与所述数据采样电路期望的采样时钟之间的偏差大于所述第一阈值,确定所述时钟恢复电路不能生成所述目标时钟信号。
- 如权利要求15所述的方法,其特征在于,当所述第一时钟控制信号指示所述采样时钟偏差大于或等于第一取值,所述第一延迟器按照第一延迟步长延迟所述第一模拟子信号,当所述第一时钟控制信号指示所述采样时钟偏差小于所述第一取值,所述第一延迟器按照第二延迟步长延迟所述第一模拟子信号,其中,所述第一延迟步长大于所述第二延迟步长;当所述第一时钟控制信号指示所述采样时钟偏差大于或等于第一取值,所述第二延迟器按照第三延迟步长延迟所述第二模拟子信号,当所述第一时钟控制信号指示所述采样时钟偏差小于所述第一取值,所述第二延迟器按照第四延迟步长延迟所述第二模拟子信号,其中,所述第三延迟步长大于所述第四延迟步长。
- [根据细则91更正 18.10.2022]
如权利要求14-19任一项所述的方法,其特征在于,所述时钟恢复电路还包括与所述乘法电路连接的第一低通滤波器,所述第一低通滤波器用于滤除所述第一信号中的高频分量。 - 如权利要求20所述的方法,其特征在于,所述时钟恢复电路还包括与所述第一低通滤波器连接的限幅放大器,所述限幅放大器用于滤除所述第一低通滤波器输出的信号中 幅度高于第一幅度的分量。
- 如权利要求21所述的方法,其特征在于,所述时钟恢复电路还包括与所述限幅放大器连接的锁相环,所述锁相环用于使得所述目标时钟信号的频率与所述第一信号的频率一致。
- [根据细则91更正 18.10.2022]
如权利要求13-22任一项所述的方法,其特征在于,所述通信装置还包括相位锁定模块,所述相位锁定模块与所述时钟控制电路和所述数据采样电路分别连接,所述方法还包括:通过所述相位锁定电路根据误差信号确定所述数据采样电路的采样相位偏差,并根据所述采样相位偏差生成第三控制信号,以及向所述数据采样电路输出所述第三控制信号;其中,所述误差信号为所述数据采样电路输出的第一数字信号和第二数字信号之间的误差信号,所述第三控制信号用于指示所述数据采样电路对采样相位进行调整。 - 如权利要求23所述的方法,其特征在于,所述相位锁定模块包括:鉴相器,与所述时钟控制电路连接;压控振荡器,与所述鉴相器连接;第二低通滤波器,其输入端与所述压控振荡器连接,输出端与所述数据采样电路连接。
- 一种芯片***,其特征在于,包括:通信接口,用于输入和/或输出信息;处理器,用于执行计算机程序,使得安装有所述芯片***的设备执行如权利要求13-24任一项所述的方法。
- 一种计算机可读存储介质,其特征在于,所述存储介质中存储有计算机程序或指令,当所述计算机程序或指令被执行时,实现如权利要求13-24任一项所述的方法。
- 一种发射机,其特征在于,包括:如权利要求1-12任一项所述的通信装置。
- 一种基站,其特征在于,包括:如权利要求1-12任一项所述的通信装置。
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