WO2024041217A1 - 像素电路及其驱动方法、显示面板、显示装置 - Google Patents

像素电路及其驱动方法、显示面板、显示装置 Download PDF

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Publication number
WO2024041217A1
WO2024041217A1 PCT/CN2023/105030 CN2023105030W WO2024041217A1 WO 2024041217 A1 WO2024041217 A1 WO 2024041217A1 CN 2023105030 W CN2023105030 W CN 2023105030W WO 2024041217 A1 WO2024041217 A1 WO 2024041217A1
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WIPO (PCT)
Prior art keywords
reset
circuit
transistor
node
light
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PCT/CN2023/105030
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English (en)
French (fr)
Inventor
刘苗
刘烺
陈腾
郝学光
乔勇
王景泉
吴新银
Original Assignee
京东方科技集团股份有限公司
北京京东方技术开发有限公司
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Publication of WO2024041217A1 publication Critical patent/WO2024041217A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element

Definitions

  • Embodiments of the present disclosure relate to a pixel circuit and a driving method thereof, a display panel, and a display device.
  • OLED display devices are gradually attracting attention due to their advantages such as wide viewing angle, high contrast, fast response speed, higher luminance and lower driving voltage than inorganic light-emitting display devices. extensive attention. Due to the above characteristics, organic light-emitting diodes (OLEDs) can be applied to devices with display functions such as mobile phones, monitors, laptops, digital cameras, instruments and meters.
  • Pixel circuits in OLED display devices generally adopt matrix driving methods, and are divided into active matrix (AM) driving and passive matrix (PM) driving according to whether switching components are introduced in each pixel unit.
  • AM active matrix
  • PM passive matrix
  • AMOLED integrates a set of thin film transistors and storage capacitors into the pixel circuit of each pixel. By driving and controlling the thin film transistors and storage capacitors, the current flowing through the OLED is controlled, so that the OLED can be controlled as needed. glow.
  • AMOLED Compared with PMOLED, AMOLED requires small driving current, low power consumption, and longer life, and can meet the needs of large-size display with high resolution and multiple grayscales. At the same time, AMOLED has obvious advantages in viewing angle, color reproduction, power consumption and response time, and is suitable for display devices with high information content and high resolution.
  • At least one embodiment of the present disclosure provides a driving method for a pixel circuit, wherein the pixel circuit includes a driving circuit, a data writing circuit, a threshold compensation circuit, a storage circuit, a first light emission control circuit and a first reset circuit;
  • the driving circuit includes a control end, a first end and a second end, and is equipped with Set to control a driving current flowing through the light-emitting element;
  • the data writing circuit is connected to a first end of the driving circuit, and is configured to write a data signal to the first end of the driving circuit in response to a first scan signal.
  • the threshold compensation circuit is connected between the control end of the drive circuit and the second end of the drive circuit, and is configured to write a compensation signal based on the data signal into the drive in response to a second scan signal.
  • the first reset circuit is connected to the threshold compensation circuit and is configured to apply a first reset voltage to a control end of the drive circuit in response to a first reset signal; control of the drive circuit
  • the terminal and the storage circuit are connected to the first node, the first terminal of the first light-emitting control circuit and the driving circuit is connected to the second node; the method includes: before the data writing stage, the first terminal The reset circuit is turned on in response to the first reset signal to apply the first reset voltage to the control terminal of the driving circuit to reset the first node, and the first lighting control circuit Turning on in response to the first lighting control signal to apply the first voltage to the first end of the driving circuit to reset the second node; during the data writing phase, the The data writing circuit is turned on in response to the first scan signal to write the data signal to the first end of the driving circuit; in the light-emitting phase, the first light-emitting control circuit responds to the first light-emitting The control signal is turned on, and the light-emitting element emits
  • the first reset circuit is turned on in response to the first reset signal to apply the first reset voltage to the control end of the driving circuit, thereby The first node is reset, including: the first reset circuit is turned on in response to the first reset signal, and the threshold compensation circuit is turned on in response to the second scan signal to reset the first node.
  • a voltage is applied to the control terminal of the driving circuit through the path formed by the first reset circuit and the threshold compensation circuit, thereby resetting the first node.
  • the pixel circuit further includes a second light-emitting control circuit and a second reset circuit; the second light-emitting control circuit and the second end of the driving circuit and the light-emitting circuit
  • the element is connected and configured to apply the voltage of the second end of the driving circuit to the light-emitting element in response to a second light-emitting control signal; the second reset circuit is connected to the second light-emitting control circuit and the light-emitting element.
  • the method further includes: before the data writing stage, while the first reset circuit resets the first node, the first reset circuit sets the first reset voltage to applied to the second terminal of the drive circuit, thereby resetting the third node; and/or, before the data writing phase, the second reset circuit is turned on in response to the second reset signal , to apply the second reset voltage to the light-emitting element, thereby resetting the fourth node.
  • the first node and the second node are reset at the same time or reset respectively in different periods.
  • the third node and the fourth node are reset before the data writing phase
  • the third node and the fourth node are reset. Nodes are reset at the same time or reset separately at different time periods.
  • the reset period of at least one of the third node and the fourth node is the same as that of the first node and the second node.
  • the reset periods of at least one of the nodes coincide.
  • the reset period of the first node, the reset period of the second node, the reset period of the third node, the The reset periods of the fourth node mentioned above do not overlap.
  • the method provided by an embodiment of the present disclosure further includes: after the data writing stage and before the light-emitting stage, the first light-emitting control circuit is turned on in response to the first light-emitting control signal to turn on the light-emitting control circuit.
  • the first voltage is applied to the first terminal of the driving circuit, thereby resetting the second node; and/or, after the data writing phase and before the light emitting phase, the first reset circuit Turning on in response to the first reset signal to apply the first reset voltage to the second end of the drive circuit to reset the third node; and/or, when the data is written After the stage and before the light-emitting stage, the second reset circuit is turned on in response to the second reset signal to apply the second reset voltage to the light-emitting element to reset the fourth node.
  • the driving circuit includes a driving transistor
  • the data writing circuit includes a data writing transistor
  • the threshold compensation circuit includes a threshold compensation transistor
  • the first lighting control circuit includes a first lighting control transistor
  • the first reset circuit includes a first reset transistor
  • the driving transistor, the data writing transistor, the first light emitting control transistor, and the first reset transistor are transistors of the first type
  • the threshold compensation transistor is a transistor of the second type
  • the first type is different from The second type.
  • the first type of transistor includes a P-type thin film transistor
  • the second type of transistor includes an N-type thin film transistor
  • the pixel circuit further includes an anti-leakage circuit, and the anti-leakage circuit is connected to the control end of the driving circuit, the threshold compensation circuit and the storage circuit, so The leakage prevention circuit is configured to suppress leakage of the control terminal of the drive circuit.
  • the anti-leakage circuit includes an anti-leakage transistor, and the anti-leakage transistor is the second type of transistor.
  • At least one embodiment of the present disclosure also provides a pixel circuit, including: a driving circuit, a data writing circuit, a threshold compensation circuit, a storage circuit, and a first reset circuit; wherein the driving circuit includes a control terminal, a first terminal, and a first reset circuit. Two terminals, and configured to control the driving current flowing through the light-emitting element; the data writing circuit is connected to the first terminal of the driving circuit, and is configured to write a data signal into the driving circuit in response to the first scanning signal.
  • the first end of the threshold compensation circuit is connected between the control end of the drive circuit and the second end of the drive circuit, and is configured to write a compensation signal based on the data signal in response to the second scan signal.
  • the storage circuit is connected to the control terminal of the driving circuit and the first voltage line, and is configured to store the compensation signal and maintain the compensation signal under the control of the driving circuit terminal, the control terminal of the driving circuit and the storage circuit are connected to the first node;
  • the first reset circuit is connected to the threshold compensation circuit and the second terminal of the driving circuit, and is configured to respond to the first The reset signal applies a first reset voltage to the second terminal of the drive circuit.
  • the driving circuit includes a driving transistor, the gate of the driving transistor serves as the control terminal of the driving circuit, and the first electrode of the driving transistor serves as the driving transistor.
  • the first end of the circuit, the second pole of the driving transistor serves as the second end of the driving circuit;
  • the data writing circuit includes a data writing transistor, the gate of the data writing transistor is connected to the first scan line connected to receive the first scan signal, the first pole of the data writing transistor is connected to the data line to receive the data signal, the second pole of the data writing transistor is connected to the first pole of the driving transistor connection;
  • the threshold compensation circuit includes a threshold compensation transistor, The gate of the threshold compensation transistor is connected to the second scan line to receive the second scan signal, the first electrode of the threshold compensation transistor is connected to the second electrode of the driving transistor, and the third electrode of the threshold compensation transistor is connected to the second scan line.
  • the diode is connected to the gate of the drive transistor;
  • the storage circuit includes a storage capacitor, a first pole of the storage capacitor is connected to the first voltage line, and a second pole of the storage capacitor is connected to the drive transistor.
  • the gate electrode is connected;
  • the first reset circuit includes a first reset transistor, the gate electrode of the first reset transistor is connected to the first reset line to receive the first reset signal, and the first reset transistor has a gate electrode connected to the first reset line.
  • the first reset transistor has a second pole connected to a first reset voltage line to receive the first reset voltage, and a second pole of the first reset transistor is connected to a second pole of the driving transistor.
  • a pixel circuit provided by an embodiment of the present disclosure further includes a first light-emitting control circuit and a second light-emitting control circuit; wherein the first light-emitting control circuit is connected to the first voltage line and the first terminal of the driving circuit. connected and configured to apply a first voltage provided by the first voltage line to a first end of the driving circuit in response to a first lighting control signal, the first lighting control circuit and the first terminal of the driving circuit
  • the second light-emitting control circuit is connected to the second end of the driving circuit and the light-emitting element, and is configured to change the voltage of the second end of the driving circuit in response to the second light-emitting control signal. Applying to the light-emitting element, the second terminals of the second light-emitting control circuit and the driving circuit are connected to a third node.
  • the first light-emitting control circuit includes a first light-emitting control transistor, and the gate of the first light-emitting control transistor is connected to the first light-emitting control line to receive the first light-emitting control transistor.
  • a light-emitting control signal the first pole of the first light-emitting control transistor is connected to the first voltage line, the second pole of the first light-emitting control transistor is connected to the first end of the driving circuit;
  • the third The second light-emitting control circuit includes a second light-emitting control transistor, the gate of the second light-emitting control transistor is connected to the second light-emitting control line to receive the second light-emitting control signal, and the first electrode of the second light-emitting control transistor is connected to the second light-emitting control line.
  • the second terminal of the driving circuit is connected, and the second pole of the second light-emitting control transistor is connected to the light-emitting element.
  • the pixel circuit provided by an embodiment of the present disclosure further includes a second reset circuit, wherein the second reset circuit is connected to the second light-emitting control circuit and the light-emitting element, and is configured to respond to a second reset signal.
  • a second reset voltage is applied to the light-emitting element; the second reset circuit, the second light-emitting control circuit and the light-emitting element are connected to a fourth node; the third node is reset by the first reset circuit The potential after is greater than the potential after the fourth node is reset by the second reset circuit.
  • the second reset circuit includes a third Two reset transistors, the gate of the second reset transistor is connected to the second reset line to receive the second reset signal, and the first electrode of the second reset transistor is connected to the second reset voltage line to receive the second reset voltage line.
  • Two reset voltages, the second pole of the second reset transistor is connected to the second pole of the second light emitting control transistor and the light emitting element.
  • the pixel circuit provided by an embodiment of the present disclosure further includes a third reset circuit, wherein the third reset circuit is connected to the control end of the threshold compensation circuit and the driving circuit, and the third reset circuit is configured as In response to a third reset signal, a third reset voltage is applied to the control end of the driving circuit; the potential of the first node after being reset by the third reset circuit is less than the potential of the third node after being reset by the first reset circuit.
  • the potential after reset; the potential of the first node after being reset by the third reset circuit is less than or equal to the potential of the fourth node after being reset by the second reset circuit.
  • the third reset circuit includes a third reset transistor, the gate of the third reset transistor is connected to a third reset line to receive the third reset signal, The first electrode of the third reset transistor is connected to the third reset voltage line to receive the third reset voltage, and the second electrode of the third reset transistor is connected to the control terminal of the driving circuit.
  • the pixel circuit provided by an embodiment of the present disclosure further includes a fourth reset circuit, wherein the fourth reset circuit is connected to the first end of the driving circuit, and the fourth reset circuit is configured to respond to the fourth reset.
  • the signal applies a fourth reset voltage to the first end of the driving circuit; the potential of the second node after being reset by the fourth reset circuit is greater than the potential of the first node after being reset by the third reset circuit ; The potential of the second node after being reset by the fourth reset circuit is greater than the potential of the third node after being reset by the first reset circuit; the potential of the second node after being reset by the fourth reset circuit The potential is greater than the potential of the fourth node after being reset by the second reset circuit.
  • the fourth reset circuit includes a fourth reset transistor, the gate of the fourth reset transistor is connected to the fourth reset line to receive the fourth reset signal, The first electrode of the fourth reset transistor is connected to the fourth reset voltage line to receive the fourth reset voltage, and the second electrode of the fourth reset transistor is connected to the first end of the driving circuit.
  • At least one embodiment of the present disclosure also provides a display panel including a plurality of pixel units, wherein each pixel unit includes the pixel circuit provided by any embodiment of the present disclosure.
  • At least one embodiment of the present disclosure further provides a display device, including the display panel provided by any embodiment of the present disclosure.
  • Figure 1A is a schematic diagram of a 2T1C pixel circuit
  • Figure 1B is a schematic diagram of another 2T1C pixel circuit
  • Figure 2 is a schematic block diagram of a pixel circuit provided by some embodiments of the present disclosure.
  • Figure 3 is a schematic block diagram of another pixel circuit provided by some embodiments of the present disclosure.
  • Figure 4 is a schematic block diagram of another pixel circuit provided by some embodiments of the present disclosure.
  • Figure 5 is a schematic block diagram of another pixel circuit provided by some embodiments of the present disclosure.
  • Figure 6 is a schematic flowchart of a driving method for a pixel circuit provided by some embodiments of the present disclosure
  • Figure 7 is a schematic diagram of the circuit structure of the pixel circuit shown in Figure 2;
  • Figure 8 is a timing diagram for the pixel circuit shown in Figure 7 provided by some embodiments of the present disclosure.
  • Figure 9 is a timing diagram of the first voltage provided by some embodiments of the present disclosure.
  • Figure 10 is another timing diagram for the pixel circuit shown in Figure 7 provided by some embodiments of the present disclosure.
  • Figure 11 is another timing diagram for the pixel circuit shown in Figure 7 provided by some embodiments of the present disclosure.
  • Figure 12 is a schematic diagram of the circuit structure of the pixel circuit shown in Figure 5;
  • Figure 13 is a timing diagram for the pixel circuit shown in Figure 12 provided by some embodiments of the present disclosure.
  • Figure 14 is another timing diagram for the pixel circuit shown in Figure 12 provided by some embodiments of the present disclosure.
  • Figure 15 is another timing diagram for the pixel circuit shown in Figure 12 provided by some embodiments of the present disclosure.
  • Figure 16 is another timing diagram for the pixel circuit shown in Figure 12 provided by some embodiments of the present disclosure.
  • Figure 17 is a schematic diagram of the circuit structure of the pixel circuit shown in Figure 3;
  • Figure 18 is a timing sequence for the pixel circuit shown in Figure 17 provided by some embodiments of the present disclosure. picture;
  • Figure 19 is another timing diagram for the pixel circuit shown in Figure 17 provided by some embodiments of the present disclosure.
  • Figure 20 is another timing diagram for the pixel circuit shown in Figure 17 provided by some embodiments of the present disclosure.
  • Figure 21 is a schematic diagram of the circuit structure of the pixel circuit shown in Figure 4.
  • Figure 22 is a timing diagram for the pixel circuit shown in Figure 21 provided by some embodiments of the present disclosure.
  • Figure 23 is a schematic circuit structure diagram of a pixel circuit provided by some embodiments of the present disclosure.
  • Figure 24 is a timing diagram for the pixel circuit shown in Figure 23 provided by some embodiments of the present disclosure.
  • Figure 25 is a schematic block diagram of a display panel provided by some embodiments of the present disclosure.
  • Figure 26 is a schematic block diagram of a display device provided by some embodiments of the present disclosure.
  • the basic pixel circuit used in AMOLED display devices is usually a 2T1C pixel circuit, which uses two thin-film transistors (TFTs) and a storage capacitor Cs to achieve the basic function of driving OLED to emit light.
  • TFTs thin-film transistors
  • Cs storage capacitors
  • a 2T1C pixel circuit includes a switching transistor T0, a driving transistor N0, and a storage capacitor Cs.
  • the gate of the switching transistor T0 is connected to the scan line to receive the scan signal Scan1
  • the source is connected to the data line to receive the data signal Vdata
  • the drain is connected to the gate of the driving transistor N0.
  • the source of the driving transistor N0 is connected to the first voltage terminal to receive the first voltage Vdd (eg, high voltage), and the drain is connected to the anode of the OLED.
  • One end of the storage capacitor Cs is connected to the drain of the switching transistor T0 and the gate of the driving transistor N0, and the other end is connected to the source of the driving transistor N0 and the first voltage terminal.
  • the cathode of the OLED is connected to the second voltage terminal to receive the second voltage Vss (low voltage, such as ground voltage).
  • the driving method of this 2T1C pixel circuit is to control the brightness (gray scale) of the pixel through two TFTs and the storage capacitor Cs.
  • the scan signal Scan1 is applied through the scan line to turn on the switching transistor T0
  • the data signal Vdata sent by the data driving circuit through the data line will charge the storage capacitor Cs via the switching transistor T0, thereby storing the data signal Vdata in the storage capacitor Cs.
  • the stored data signal Vdata controls the conduction degree of the driving transistor N0, thereby controlling the current flowing through the driving transistor to drive the OLED to emit light, that is, this current determines the grayscale of the pixel emitting light.
  • the switching transistor T0 is an N-type transistor and the driving transistor N0 is a P-type transistor.
  • another 2T1C pixel circuit also includes a switching transistor T0, a driving transistor N0, and a storage capacitor Cs, but its connection method is slightly changed, and the driving transistor N0 is an N-type transistor.
  • Changes in the pixel circuit of FIG. 1B relative to FIG. 1A include: the anode of the OLED is connected to the first voltage terminal to receive the first voltage Vdd (eg, high voltage), and the cathode is connected to the drain of the driving transistor N0.
  • the driving transistor N0 The source is connected to the second voltage terminal to receive the second voltage Vss (low voltage, such as ground voltage).
  • the working mode of the 2T1C pixel circuit is basically the same as the pixel circuit shown in Figure 1A, and will not be described again here.
  • the switching transistor T0 is not limited to an N-type transistor, and may also be a P-type transistor, thereby controlling the on or off of the scanning signal Scan1. Just change the polarity accordingly.
  • OLED display devices usually include a plurality of pixel units arranged in an array, and each pixel unit may include, for example, the above-mentioned pixel circuit.
  • the threshold voltage of the driving transistor in each pixel circuit may be different due to the manufacturing process, and due to the influence of temperature changes, for example, the threshold voltage of the driving transistor may drift. Therefore, the difference in the threshold voltage of each driving transistor may cause poor display (eg, uneven display), so the threshold voltage needs to be compensated. At the same time, when the transistor is in the off state, poor display may also occur due to the existence of leakage current.
  • the industry also provides other pixel circuits with compensation functions based on the above-mentioned basic pixel circuit of 2T1C.
  • the compensation function can be achieved through voltage compensation, current compensation or hybrid compensation.
  • the pixel circuit with compensation function can be, for example, 4T1C or 4T2C, etc. will not be described in detail here.
  • At least one embodiment of the present disclosure provides a pixel circuit and a driving method thereof, a display panel, and a display device.
  • the driving method of this pixel circuit can reduce or eliminate the influence of residual charge on the accuracy of writing data and the potential of the anode of the light-emitting device during the light-emitting phase, thereby optimizing the display effect.
  • At least one embodiment of the present disclosure provides a driving method of a pixel circuit.
  • the pixel circuit includes a driving circuit, a data writing circuit, a threshold compensation circuit, a storage circuit, a first light emission control circuit and a first reset circuit.
  • the driving circuit includes a control terminal, a first terminal and a second terminal, and is configured to control the driving current flowing through the light-emitting element; the data writing circuit is connected to the first terminal of the driving circuit, and is configured to write the data in response to the first scan signal.
  • the threshold compensation circuit is connected between the control end of the driving circuit and the second end of the driving circuit, and is configured to write a compensation signal based on the data signal into the driving circuit in response to the second scan signal
  • the control terminal the storage circuit is connected to the control terminal of the driving circuit and the first voltage line, and is configured to store the compensation signal and keep the compensation signal at the control terminal of the driving circuit
  • the first light-emitting control circuit is connected to the first voltage line and the driving circuit The first end is connected, and is configured to apply the first voltage provided by the first voltage line to the driving circuit in response to the first light emitting control signal.
  • the first reset circuit is connected to the threshold compensation circuit and is configured to apply a first reset voltage to the control end of the driving circuit in response to the first reset signal.
  • the control terminal of the driving circuit and the storage circuit are connected to the first node, and the first terminals of the first light-emitting control circuit and the driving circuit are connected to the second node.
  • the driving method of the pixel circuit includes: before the data writing stage, the first reset circuit is turned on in response to the first reset signal to apply the first reset voltage to the control terminal of the driving circuit to reset the first node, Moreover, the first light-emitting control circuit is turned on in response to the first light-emitting control signal to apply the first voltage to the first end of the driving circuit to reset the second node; in the data writing stage, the data writing circuit responds The first scanning signal is turned on to write the data signal to the first end of the driving circuit; in the light-emitting stage, the first light-emitting control circuit is turned on in response to the first light-emitting control signal, and the light-emitting element emits light according to the driving current.
  • FIG. 2 is a schematic block diagram of a pixel circuit provided by some embodiments of the present disclosure.
  • the driving method provided by the embodiment of the present disclosure can drive the pixel circuit shown in FIG. 2 .
  • the pixel circuit 10 includes a driving circuit 110 , a data writing circuit 120 , a threshold compensation circuit 130 , a storage circuit 140 , a first light emission control circuit 150 and a first reset circuit 160 .
  • the driving circuit 110 includes a first terminal 111 , a second terminal 112 and a control terminal 113 , and is configured to control the driving current flowing through the light emitting element 170 .
  • the driving circuit 110 can provide a driving current to the light-emitting element 170 to drive the light-emitting element 170 to emit light, and can emit light according to the required "grayscale".
  • the light-emitting element 170 can adopt any type of suitable device, which can include a variety of structures, which can be selected and arranged according to actual needs, and the embodiments of the present disclosure are not limited to this.
  • the light emitting element 170 can be an OLED, a quantum dot light emitting diode (Quantum Dot Light Emitting Diode, QLED), or a micro light emitting diode (Micro Light Emitting Diode, Micro LED), etc., which can be determined according to actual needs.
  • QLED Quantum Dot Light Emitting Diode
  • Micro LED Micro Light Emitting Diode
  • the data writing circuit 120 is connected to the first end 111 of the driving circuit 110 and is configured to write a data signal to the first end 111 of the driving circuit 110 in response to the first scanning signal.
  • the data writing circuit 120 is connected to the first scan line SC1 and the data line Vdata, the first scan line SC1 is used to provide the first scan signal, and the data line Vdata is used to provide the data signal.
  • the data writing circuit 120 is turned on in response to the first scanning signal provided by the first scanning line SC1, thereby writing the data signal provided by the data line Vdata into the first end 111 of the driving circuit 110.
  • the data signal is further written into the control terminal 113 of the driving circuit 110 through the driving circuit 110 and the threshold compensation circuit 130, and is stored in the storage circuit 140 to generate a driving current for driving the light-emitting element 170 to emit light according to the data signal during the light-emitting phase. .
  • the threshold compensation circuit 130 is connected between the control terminal 113 of the driving circuit 110 and the second terminal 112 of the driving circuit 110, and is configured to write a compensation signal based on the data signal into the control terminal 113 of the driving circuit 110 in response to the second scan signal.
  • the threshold compensation circuit 130 may be directly connected to the control terminal 113 and the second terminal 112 of the driving circuit 110 , that is, directly connected between the control terminal 113 and the second terminal 112 of the driving circuit 110 .
  • the threshold compensation circuit 130 can also be indirectly connected between the control terminal 113 and the second terminal 112 of the driving circuit 110 , that is, between the threshold compensation circuit 130 and the control terminal 113 of the driving circuit 110 , between the threshold compensation circuit 130
  • Other circuits such as the anti-leakage circuit 230 described below may also be provided between the second end 112 of the driving circuit 110 and the embodiments of the present disclosure are not limited thereto.
  • the threshold compensation circuit 130 is connected to the second scan line SC2, and the second scan line SC2 is used to provide the second scan signal.
  • the data writing circuit 120 and the threshold compensation circuit 130 are both turned on, and the driving circuit 110 is also turned on at this time.
  • the data signal is transmitted to the threshold compensation circuit 130 via the data writing circuit 120 and the driving circuit 110.
  • the threshold compensation circuit 130 generates a compensation signal based on the data signal, and writes the compensation signal to the control terminal 113 of the driving circuit 110.
  • the threshold compensation circuit 130 can electrically connect the control terminal 113 and the second terminal 112 of the driving circuit 110, so that the relevant information about the threshold voltage of the driving circuit 110 is also stored in the storage circuit 140 accordingly, Therefore, during the light-emitting phase, the stored voltage including the data signal and the threshold voltage can be used to control the driving circuit 110, so that the driving circuit 110 can be compensated.
  • the storage circuit 140 is connected to the control terminal 113 of the driving circuit 110 and the first voltage line VDD, and is configured to store the compensation signal and maintain the compensation signal at the control terminal 113 of the driving circuit 110 .
  • the first lighting control circuit 150 is connected to the first voltage line VDD and the first terminal 111 of the driving circuit 110, and is configured to apply the first voltage provided by the first voltage line VDD to the driving circuit 110 in response to the first lighting control signal.
  • First end 111 the first lighting control circuit 150 is connected to the first lighting control line EM1, and the first lighting control line EM1 is used to provide a first lighting control signal.
  • the first lighting control circuit 150 may be turned on in response to the first lighting control signal, so that the first terminal 111 of the driving circuit 110 is electrically connected to the first voltage line VDD, thereby applying the first voltage provided by the first voltage line VDD to the driving circuit 110 .
  • First terminal 111 of circuit 110 First terminal 111 of circuit 110 .
  • the first reset circuit 160 is connected to the threshold compensation circuit 130 and is configured to apply a first reset voltage to the control terminal 113 of the driving circuit 110 in response to the first reset signal.
  • the first reset circuit 160 is connected to the first reset line RST1 and the first reset voltage line VR1.
  • the first reset line RST1 The first reset voltage line VR1 is used to provide the first reset signal, and the first reset voltage line VR1 is used to provide the first reset voltage.
  • the first reset circuit 160 may be turned on in response to the first reset signal, thereby transmitting the first reset voltage to the second terminal 112 of the driving circuit 110 , and the first reset voltage is further transmitted to the control terminal of the driving circuit 110 through the threshold compensation circuit 130 113, thereby realizing the reset of the control terminal 113 of the driving circuit 110.
  • the anode of the light-emitting element 170 receives the driving current provided by the driving circuit 110, and the cathode of the light-emitting element 170 is connected to the second voltage line VSS, and the second voltage line VSS is used to provide the second voltage.
  • the first voltage line VDD in various embodiments of the present disclosure, for example, maintains an input DC high level signal, and the DC high level is called the first voltage;
  • the second voltage line VSS For example, the DC low level signal is kept input, and the DC low level is called the second voltage (which may be the ground voltage), and is lower than the first voltage.
  • the first voltage line VDD in various embodiments of the present disclosure, for example, maintains an input DC high level signal, and the DC high level is called the first voltage
  • the second voltage line VSS For example, the DC low level signal is kept input, and the DC low level is called the second voltage (which may be the ground voltage), and is lower than the first voltage.
  • the pixel circuit 10 further includes a second lighting control circuit 180 and a second reset circuit 190.
  • the second light emitting control circuit 180 is connected to the second terminal 112 of the driving circuit 110 and the light emitting element 170, and is configured to apply the voltage of the second end 112 of the driving circuit 110 to the light emitting element 170 in response to the second light emitting control signal.
  • the second lighting control circuit 180 is connected to the second lighting control line EM2, and the second lighting control line EM2 is used to provide a second lighting control signal.
  • the second light-emitting control circuit 180 may be turned on in response to the second light-emitting control signal to electrically connect the second terminal 112 of the driving circuit 110 to the light-emitting element 170 (eg, the anode of the light-emitting element 170), thereby connecting the second terminal 112 of the driving circuit 110 A voltage of 112 is applied to the light emitting element 170 .
  • the second reset circuit 190 is connected to the second light emitting control circuit 180 and the light emitting element 170, and is configured to apply a second reset voltage to the light emitting element 170 (eg, the anode of the light emitting element 170) in response to the second reset signal.
  • the second reset circuit 190 is connected to the second reset line RST2 and the second reset voltage line VR2.
  • the second reset line RST2 is used to provide the second reset signal
  • the second reset voltage line VR2 is used to provide the second reset voltage.
  • the second reset circuit 190 may be turned on in response to the second reset signal, thereby transmitting the second reset voltage to the connection between the second light emitting control circuit 180 and the light emitting element 170 , thereby resetting the light emitting element 170 .
  • the control terminal 113 of the driving circuit 110 and the storage circuit 140 are connected to the first node P1, the first lighting control circuit 150 and the first terminal 111 of the driving circuit 110 are connected to the second node P2, and the second lighting control circuit 180 is connected to the driving circuit 110.
  • the second terminal 112 of the circuit 110 is connected to the third node P3, and the second reset circuit 190, the second light-emitting control circuit 180 and the light-emitting element 170 are connected to the fourth node P4.
  • the potential of the third node P3 after being reset by the first reset circuit 160 is greater than the potential of the fourth node P4 after being reset by the second reset circuit 190 . This can achieve a better reset effect and better reduce or eliminate the impact of residual charges on the potential of the anode of the light-emitting device during the light-emitting stage.
  • FIG. 3 is a schematic block diagram of another pixel circuit provided by some embodiments of the present disclosure.
  • the driving method provided by the embodiments of the present disclosure can drive the pixel circuit shown in FIG. 3 .
  • the pixel circuit 10 may further include a third reset circuit 210 .
  • the third reset circuit 210 is connected to the threshold compensation circuit 130 and the control terminal 113 of the driving circuit 110, and is configured to apply a third reset voltage to the control terminal 113 of the driving circuit 110 in response to the third reset signal.
  • the third reset circuit 210 is connected to the third reset line RST3 and the third reset voltage line VR3.
  • the third reset line RST3 is used to provide the third reset signal
  • the third reset voltage line VR3 is used to provide the third reset voltage.
  • the third reset circuit 210 may be turned on in response to the third reset signal, thereby transmitting the third reset voltage to the control terminal 113 of the driving circuit 110 , thereby realizing resetting the control terminal 113 of the driving circuit 110 .
  • Other parts of the pixel circuit 10 are basically the same as the pixel circuit 10 shown in FIG. 2 and will not be described again here.
  • the potential of the third node P3 after being reset by the first reset circuit 160 is greater than the potential of the fourth node P4 after being reset by the second reset circuit 190; the potential of the first node P1 after being reset by the third reset circuit 210 The potential of the third node P3 is less than the potential of the third node P3 after being reset by the first reset circuit 160; the potential of the first node P1 after being reset by the third reset circuit 210 is less than or equal to the potential of the fourth node P4 after being reset by the second reset circuit 190.
  • This can achieve a better reset effect and better reduce or eliminate the impact of residual charges on the accuracy of writing data and the potential of the anode of the light-emitting device during the light-emitting phase.
  • FIG. 4 is a schematic block diagram of another pixel circuit provided by some embodiments of the present disclosure.
  • the driving method provided by the embodiment of the present disclosure can drive the pixel circuit shown in FIG. 4 .
  • the pixel circuit 10 may further include a fourth reset circuit 220 .
  • the fourth reset circuit 220 is connected to the first terminal 111 of the driving circuit 110, and the fourth reset circuit 220 is configured to apply a fourth reset voltage to the first terminal 111 of the driving circuit 110 in response to the fourth reset signal.
  • the fourth reset circuit 220 is connected to the fourth reset line RST4 and the fourth reset voltage line VR4.
  • the fourth reset line RST4 is used to provide the fourth reset signal
  • the fourth reset voltage line VR4 is used to provide the fourth reset voltage.
  • the fourth reset circuit 220 may be turned on in response to the fourth reset signal, thereby transmitting the fourth reset voltage to the first terminal 111 of the driving circuit 110 , thereby resetting the first terminal 111 of the driving circuit 110 .
  • Other parts of the pixel circuit 10 are basically the same as the pixel circuit 10 shown in FIG. 3 They are basically the same and will not be described again here.
  • the potential of the third node P3 after being reset by the first reset circuit 160 is greater than the potential of the fourth node P4 after being reset by the second reset circuit 190; the potential of the first node P1 after being reset by the third reset circuit 210
  • the potential of the third node P3 is less than the potential of the third node P3 after being reset by the first reset circuit 160; the potential of the first node P1 after being reset by the third reset circuit 210 is less than or equal to the potential of the fourth node P4 after being reset by the second reset circuit 190;
  • the potential of the second node P2 after being reset by the fourth reset circuit 220 is greater than the potential of the first node P1 after being reset by the third reset circuit 210; the potential of the second node P2 after being reset by the fourth reset circuit 220 is greater than the potential of the third node P3 after being reset by the third reset circuit 210.
  • FIG. 5 is a schematic block diagram of another pixel circuit provided by some embodiments of the present disclosure.
  • the driving method provided by the embodiments of the present disclosure can drive the pixel circuit shown in FIG. 5 .
  • the pixel circuit 10 may further include an anti-leakage circuit 230 .
  • the anti-leakage circuit 230 is connected to the control terminal 113 of the drive circuit 110 , the threshold compensation circuit 130 and the storage circuit 140 .
  • the anti-leakage circuit 230 is configured to suppress leakage of the control terminal 113 of the drive circuit 110 .
  • the anti-leakage circuit 230 is also connected to the third scan line SC3, and the third scan line SC3 is used to provide a third scan signal.
  • the anti-leakage circuit 230 can be turned on in response to the third scan signal, thereby facilitating the transmission of the required electrical signal to the control terminal 113 of the driving circuit 110 .
  • the first reset circuit 160 is connected to the threshold compensation circuit 130 and the anti-leakage circuit 230.
  • the first reset voltage can be applied to the first node P1 through the turned-on anti-leakage circuit 230, or through the turned-on threshold.
  • the compensation circuit 130 applies the first reset voltage to the third node P3.
  • Other parts of the pixel circuit 10 are basically the same as the pixel circuit 10 shown in FIG. 2 and will not be described again here.
  • FIG 6 is a schematic flowchart of a driving method for a pixel circuit provided by some embodiments of the present disclosure.
  • This driving method can be used, for example, in the pixel circuit 10 shown in Figures 2, 3, 4, and 5.
  • the driving method provided by the embodiment of the present disclosure may include the following operations.
  • Step S10 Before the data writing stage, the first reset circuit is turned on in response to the first reset signal to apply the first reset voltage to the control terminal of the driving circuit, thereby resetting the first node, and the first light emitting The control circuit is turned on in response to the first lighting control signal to apply a first voltage to the first terminal of the driving circuit to reset the second node;
  • Step S20 In the data writing stage, the data writing circuit is turned on in response to the first scanning signal to write the data signal to the first end of the driving circuit;
  • Step S30 In the light-emitting stage, the first light-emitting control circuit is turned on in response to the first light-emitting control signal, and the light-emitting element emits light according to the driving current.
  • the reset operation on the first node in step S10 may include: the first reset circuit 160 turns on in response to the first reset signal, and the threshold compensation circuit 130 responds The second scan signal is turned on to apply the first reset voltage to the control terminal 113 of the driving circuit 110 through the path formed by the first reset circuit 160 and the threshold compensation circuit 130, thereby resetting the first node P1.
  • the first reset circuit 160 is turned on in response to the first reset signal.
  • the threshold compensation circuit 130 is turned on in response to the second scan signal, thereby applying the first reset voltage to the driving circuit 110 .
  • the control terminal 113 is applied to the first node P1, thereby resetting the first node P1.
  • the first light emitting control circuit 150 is turned on in response to the first light emitting control signal to apply the first voltage to the first terminal 111 of the driving circuit 110, that is, to the second node P2, thereby operating the second node P2. reset.
  • step S10 for the pixel circuit 10 shown in FIG. 5, before the data writing stage, the first reset circuit 160 is turned on in response to the first reset signal, and at this time, the anti-leakage circuit 230 responds to the third scan signal is turned on, thereby applying the first reset voltage to the control terminal 113 of the driving circuit 110, that is, to the first node P1, thereby resetting the first node P1.
  • the first light emitting control circuit 150 is turned on in response to the first light emitting control signal to apply the first voltage to the first terminal 111 of the driving circuit 110, that is, to the second node P2, thereby operating the second node P2. reset.
  • step S20 during the data writing phase, the data writing circuit 120 is turned on in response to the first scanning signal to write the data signal to the first end 111 of the driving circuit 110, that is, to the second node P2. .
  • the driving circuit 110 and the threshold compensation circuit 130 are also turned on.
  • the leakage prevention circuit 230 is also turned on. Therefore, the data signal can be written from the second node P2 to the control terminal 113 of the driving circuit 110 , that is, written to the first node P1 , and thus stored in the storage circuit 140 .
  • information related to the threshold voltage of the driving circuit 110 is also stored in the storage circuit 140 accordingly, so that the stored voltage including the data signal and the threshold voltage can be used to control the driving circuit 110 during the light emitting phase, so that the driving circuit 110 can be compensated.
  • step S30 during the lighting phase, the first lighting control circuit 150 responds to the first The light-emitting control signal is turned on, and the light-emitting element 170 emits light according to the driving current.
  • the second light-emitting control circuit 180 is also turned on, thereby forming a current path in front of the first voltage line VDD and the second voltage line VSS.
  • the driving circuit 110 controls the size of the driving current so that the light-emitting element 170 adjusts to the required "gray scale". "Glow.
  • the driving method provided by the embodiment of the present disclosure may further include the following operations:
  • the first reset circuit Before the data writing stage, while the first reset circuit resets the first node, the first reset circuit applies the first reset voltage to the second terminal of the driving circuit, thereby resetting the third node; and/or
  • the second reset circuit is turned on in response to the second reset signal to apply the second reset voltage to the light emitting element to reset the fourth node.
  • the first reset voltage will first be written. Enter the second terminal 112 of the driving circuit 110 (ie, the third node P3), so that the third node P3 can be reset.
  • the threshold compensation circuit 130 can be turned on, thereby causing the first reset
  • the first reset voltage transmitted by the circuit 160 may be transmitted to the third node P3 through the threshold compensation circuit 130, thereby realizing the reset of the third node P3.
  • the second reset circuit 190 is turned on in response to the second reset signal to apply the second reset voltage to the light-emitting element 170 (eg, the anode of the light-emitting element 170), thereby performing the operation on the fourth node P4. reset.
  • the first node P1 and the second node P2 are reset at the same time, or the first node P1 and the second node P2 are reset respectively in different periods. That is to say, the first node P1 and the second node P2 can be reset at the same time, or the first node P1 and the second node P2 can be reset in sequence.
  • the first node P1 can be reset first, and then the second node can be reset. P2, you can also reset the second node P2 first, and then reset the first node P1.
  • the third node P3 and the fourth node P4 are reset at the same time or respectively at different periods of time. . That is to say, the third node P3 and the fourth node P4 can be reset at the same time, or the third node P3 and the fourth node P4 can be reset in sequence.
  • the third node P3 can be reset first, and then the fourth node can be reset. P4, you can also reset the fourth node P4 first, and then The third node P3 is reset.
  • the reset period of at least one of the third node P3 and the fourth node P4 coincides with the reset period of at least one of the first node P1 and the second node P2. That is, at least one of the third node P3 and the fourth node P4 is reset at the same time as at least one of the first node P1 and the second node P2.
  • the reset period of the first node P1, the reset period of the second node P2, the reset period of the third node P3, and the reset period of the fourth node P4 do not overlap. That is, the reset period of each node does not coincide with the reset period of other nodes, and only one node is reset in each reset period.
  • the reset period refers to the period during which the node is reset.
  • the reset period can be a continuous period of time or a short time point. This can be determined according to the length of time required for the reset operation. The implementation of the present disclosure There is no restriction on this.
  • the driving method provided by the embodiment of the present disclosure may further include the following operations:
  • the first light-emitting control circuit is turned on in response to the first light-emitting control signal to apply the first voltage to the first end of the driving circuit to reset the second node;
  • the first reset circuit is turned on in response to the first reset signal to apply the first reset voltage to the second end of the driving circuit to reset the third node;
  • the second reset circuit is turned on in response to the second reset signal to apply the second reset voltage to the light-emitting element to reset the fourth node.
  • the first light emitting control circuit 150 is turned on in response to the first light emitting control signal to The first voltage is applied to the first terminal 111 of the driving circuit 110, that is, to the second node P2, thereby resetting the second node P2.
  • the first reset circuit 160 is turned on in response to the first reset signal to apply the first reset voltage. to the second terminal 112 of the driving circuit 110, that is, applied to the third node P3, thereby resetting the third node P3.
  • the threshold compensation circuit 130 is also turned on, so that the threshold compensation circuit 130 can be turned on.
  • the first reset voltage is applied to the third node P3 via the threshold compensation circuit 130 to reset the third node P3.
  • the second reset circuit 190 is turned on in response to the second reset signal to apply the second reset voltage to the light emitting element 170 (eg, the anode of the light emitting element 170), that is, , is applied to the fourth node P4, thereby resetting the fourth node P4.
  • the light emitting element 170 eg, the anode of the light emitting element 170
  • the second node P2, the third node P3, and the fourth node P4 are reset at the same time, or the second node P2, the third node At least two nodes among P3 and the fourth node P4 are respectively reset in different time periods. That is to say, the second node P2, the third node P3, and the fourth node P4 can be reset separately in three different reset periods; the second node P2, the third node P3, and the fourth node P4 can also be reset.
  • any two nodes among them are reset at the same time, and the remaining node is reset in different time periods; the second node P2, the third node P3, and the fourth node P4 can also be reset simultaneously in the same time period. This can be determined according to actual needs, and the embodiments of the present disclosure do not limit this.
  • any one or more nodes among the first node P1, the second node P2, the third node P3, and the fourth node P4 can be reset.
  • the nodes that need to be reset can be reset at the same time, or the reset periods of each node can be staggered from each other. Therefore, before writing data, the anode of the OLED and/or the source, drain, and gate of the driving transistor can be initialized or reset by performing an initialization or reset operation on the nodes on the data writing path. Reset can reduce or eliminate the adverse effects caused by residual charges and optimize the display effect.
  • any one or more nodes among the second node P2, the third node P3, and the fourth node P4 can be reset after the data writing stage and before the lighting stage.
  • the nodes that need to be reset can be reset at the same time, or the reset periods of each node can be staggered from each other. Therefore, after writing data and before emitting light, an initialization or reset operation can be performed on the anode of the OLED and/or one or more of the source and drain of the driving transistor. By resetting the nodes on the light emitting path, The adverse effects caused by residual charges can be reduced or eliminated to optimize the display effect.
  • the nodes that need to be reset before the data writing phase and the nodes that need to be reset after the data writing phase and before the light emitting phase can be the same or different.
  • the nodes that need to be reset can be the same or different.
  • Reset operation and after the data writing phase and the lighting phase The previous reset operations may be the same or different, which may be determined according to actual requirements, and the embodiments of the present disclosure do not limit this.
  • FIG. 7 is a schematic diagram of the circuit structure of the pixel circuit shown in FIG. 2 .
  • the pixel circuit 10 includes: transistors M1 to M7 and a storage capacitor Cst.
  • the transistor M3 is used as a driving transistor, and the other transistors are used as switching transistors.
  • the light-emitting element 170 can be implemented as a light-emitting element EL, and the light-emitting element EL can be, for example, an OLED.
  • Embodiments of the present disclosure include but are not limited to this. The following embodiments take OLED as an example for description, and will not be described again.
  • the OLED can be of various types, such as top emission, bottom emission, etc., and can emit red light, green light, blue light, or white light, etc., and the embodiments of the present disclosure are not limited thereto.
  • the driving circuit 110 may be implemented as a driving transistor, that is, a transistor M3.
  • the gate of the driving transistor (transistor M3) serves as the control terminal 113 of the driving circuit 110
  • the first pole of the driving transistor (transistor M3) serves as the first terminal 111 of the driving circuit 110
  • the second pole of the driving transistor (transistor M3) serves as the driving Second terminal 112 of circuit 110 .
  • the data writing circuit 120 may be implemented as a data writing transistor, namely transistor M4.
  • the gate electrode of the data writing transistor (transistor M4) is connected to the first scan line (scan line S3) to receive the first scan signal, and the first electrode of the data writing transistor (transistor M4) is connected to the data line (data line DL).
  • the second electrode of the data writing transistor (transistor M4) and the first electrode of the driving transistor (transistor M3) are connected to the second node P2.
  • the threshold compensation circuit 130 may be implemented as a threshold compensation transistor, namely transistor M2.
  • the gate of the threshold compensation transistor (transistor M2) is connected to the second scan line (scan line S5) to receive the second scan signal, and the first electrode of the threshold compensation transistor (transistor M2) is connected to the second electrode of the driving transistor (transistor M3).
  • the second electrode of the threshold compensation transistor (transistor M2) and the gate of the driving transistor (transistor M3) are connected to the first node P1.
  • the storage circuit 140 may be implemented as a storage capacitor Cst, a first electrode of the storage capacitor Cst is connected to the first voltage line VDD, and a second electrode of the storage capacitor Cst is connected to the gate of the driving transistor (transistor M3) to the first node P1.
  • the first light emission control circuit 150 may be implemented as a first light emission control transistor, that is, the transistor M5.
  • the gate of the first light-emitting control transistor (transistor M5) is connected to the first light-emitting control line (scan line S1) to receive the first light-emitting control signal.
  • the gate of the first light-emitting control transistor (transistor M5) The first electrode is connected to the first voltage line VDD, and the second electrode of the first light-emitting control transistor (transistor M5) is connected to the first terminal of the driving circuit, that is, the first electrode of the driving transistor (transistor M3) is connected to the second terminal of the driving circuit. Node P2.
  • the first reset circuit 160 may be implemented as a first reset transistor, that is, transistor M1.
  • the gate electrode of the first reset transistor (transistor M1) is connected to the first reset line (scan line S4) to receive the first reset signal
  • the first electrode of the first reset transistor (transistor M1) is connected to the first reset voltage line (voltage line INIT1) is connected to receive the first reset voltage
  • the second electrode of the first reset transistor (transistor M1) and the second electrode of the driving transistor (transistor M3) are connected to the third node P3.
  • the second light emission control circuit 180 may be implemented as a second light emission control transistor, that is, the transistor M6.
  • the gate electrode of the second light-emitting control transistor (transistor M6) is connected to the second light-emitting control line (scan line S2) to receive the second light-emitting control signal.
  • the first electrode of the second light-emitting control transistor (transistor M6) is connected to the first electrode of the driving circuit.
  • a two-terminal connection is made, that is, the second electrode of the driving transistor (transistor M3) is connected to the third node P3, and the second electrode of the second light-emitting control transistor (transistor M6) is connected to the anode of the light-emitting element EL to the fourth node P4.
  • the second reset circuit 190 may be implemented as a second reset transistor, namely transistor M7.
  • the gate of the second reset transistor (transistor M7) is connected to the second reset line (scan line S6) to receive the second reset signal, and the first electrode of the second reset transistor (transistor M7) is connected to the second reset voltage line (voltage line INIT2) is connected to receive the second reset voltage, and the second electrode of the second reset transistor (transistor M7), the second electrode of the second light-emitting control transistor (transistor M6) and the light-emitting element EL are connected to the fourth node P4.
  • the driving transistor (transistor M3), the data writing transistor (transistor M4), the first light emitting control transistor (transistor M5), and the first reset transistor (transistor M1) are first type transistors;
  • the threshold compensation transistor (transistor M2) is a second type of transistor; the first type is different from the second type.
  • the first type of transistor includes a P-type thin film transistor
  • the second type of transistor includes an N-type thin film transistor, that is, a driving transistor (transistor M3), a data writing transistor (transistor M4), a third A light emission control transistor (transistor M5) and a first reset transistor (transistor M1) are P-type thin film transistors
  • the threshold compensation transistor (transistor M2) is an N-type transistor.
  • the embodiments of the present disclosure are not limited to this, and the types of some transistors used in the pixel circuit 10 can be changed according to actual needs, such as changing P-type thin film transistors to N-type thin film transistors, or changing N-type thin film transistors to P-type thin film transistors. type thin film transistor.
  • FIG. 8 is a timing diagram for the pixel circuit shown in FIG. 7 provided by some embodiments of the present disclosure.
  • the gate of the transistor M5 is connected to the scan line S1, S1 is at a low potential, the transistor M5 is turned on, and the high potential of the first voltage line VDD is written to The first pole of the transistor M3 is written to the second node P2.
  • the potential of the second node P2 is V1.
  • the potential of V1 can be VDD, or it can be greater than 0 and less than VDD, as shown in Figure 9.
  • the potential provided by the first voltage line VDD is constant; if the potential of V1 is greater than 0 and less than VDD, the potential provided by the first voltage line VDD changes.
  • the gate of transistor M1 is connected to scan line S4, S4 is low potential, transistor M1 is turned on, the gate of transistor M2 is connected to scan line S5, S5 is high potential, transistor M2 is turned on, and the low potential of voltage line INIT1 is written to the second electrode of the transistor M3 (that is, the third node P3) and the gate electrode of the transistor M3 (that is, the first node P1).
  • the gate of the transistor M7 is connected to the scan line S6.
  • the transistor M7 is turned on, and the low potential of the voltage line INIT2 is written to the anode of the light-emitting element EL (ie, the fourth node P4). Therefore, in the first stage T1, the anode of the light-emitting element EL and the first electrode, the second electrode, and the gate of the transistor M3 are reset, eliminating the residual charge displayed in the previous frame, which is beneficial to the second stage T2 data. Writing can be done accurately.
  • S3 and S5 are low level and high level respectively, transistor M4 and transistor M2 are turned on, and the data signal is written to the gate of transistor M3 through transistor M4, transistor M3, and transistor M2 in sequence.
  • the potential of the first node P1 is Vdata+
  • Vdata is the data signal, and Vth is the threshold voltage of transistor M3.
  • the transistor M7 is still turned on, and the low potential of the voltage line INIT2 is written to the fourth node P4. That is, the fourth node P4 is reset in both the first phase T1 and the second phase T2.
  • the potentials of S1 and S2 are low, the transistors M5 and M6 are turned on, and the light-emitting element EL emits light.
  • W/L is the width-to-length ratio of the transistor M3
  • Cox is the dielectric constant of the channel insulating layer of the transistor M3
  • ⁇ is the channel carrier mobility of the transistor M3.
  • VDD is 4.6V
  • VSS is -3V
  • Vinit that is, INIT1 and INIT2
  • Vdata is 3V
  • Vth is -2V.
  • better simulation effect means that the accuracy of writing data is higher, and the potential of the anode of the light-emitting device during the light-emitting phase is almost not affected by the residual charge.
  • the voltage of the first voltage line VDD bit is VDD; in the non-light-emitting phase, including the first phase T1 for resetting and the second phase T2 for data writing, in order to save power consumption, the potential of the first voltage line can be reduced to V1.
  • the potential of the second node P2 may be V1, that is, greater than 0 and less than or equal to VDD, thereby achieving the reset function.
  • S2 and S5 can be signals output by the same gate drive circuit (such as GOA); S3 and S4 can be provided by the same type of GOA.
  • S3 is provided by a certain level of shift register unit in the GOA.
  • Signal, S4 is the signal provided by the upper-level shift register unit in GOA. Therefore, for a row of pixel circuits, at least 4 GOA are needed, or the first-level shift register unit of GOA needs to output 4 shift signals (if the GOA used can output multiple signals, for example, one GOA can output two Signals with different pulse widths or two signals with different potentials).
  • FIG. 10 is another timing diagram for the pixel circuit shown in FIG. 7 provided by some embodiments of the present disclosure.
  • this example adds a period of time between the reset phase and the data writing phase of Figure 8, which is used as the drain and gate of the transistor M3 (also That is, the reset of the third node P3 and the first node P1).
  • this stage can also be incorporated into the T1 stage.
  • the source electrode of the transistor M3 that is, the second node P2
  • the drain electrode of the transistor M7 that is, the anode of the light-emitting element EL
  • the purpose of resetting the second node P2 is to eliminate the residual charge at the second node P2 after the data is written, thereby eliminating the impact on the current flowing into the driving transistor (transistor M3) during the light-emitting phase.
  • the fourth node P4 is reset again in order to eliminate the residual charge that may be generated at the fourth node P4 by the leakage current through the transistor M6 during the data writing stage.
  • the low-potential control transistor M7 of S6 is turned on.
  • S6 can be set to remain at a low potential during the four time periods from T1 to T4. Through simulation, good simulation results were obtained.
  • the simulation conditions are: VDD is 4.6V, VSS is -3V, Vinit (that is, INIT1 and INIT2) is -3V, and Vdata is 3V.
  • signals S3 and S4 can be provided by the same type of GOA.
  • S3 is a signal provided by a shift register unit of a certain level in the GOA
  • S4 is a signal provided by a shift register unit of the previous level in the GOA. Therefore, for a row of pixel circuits, at least 4 GOA are needed, or the first-level shift register unit of GOA needs to output 4 shift signals (if the GOA used can output multiple signals, for example, one GOA can output two Signals with different pulse widths or two signals with different potentials).
  • Figure 11 is another timing sequence for the pixel circuit shown in Figure 7 provided by some embodiments of the present disclosure. picture. As shown in Figure 11, compared with the example shown in Figure 10, the same point is: in the previous stage T2 and the subsequent stage T4 of the data writing stage T3, both the second node P2 and the fourth node P4 A reset operation is performed to ensure that data can be written accurately and that residual charges on the light-emitting path can be eliminated before emitting light. In this example, the reset operation of the first node P1 and the third node P3 is performed in the first phase T1.
  • S1 and S5 can be signals output by the same GOA; S3 and S4 can be provided by the same type of GOA.
  • S3 is a signal provided by a certain level of shift register unit in the GOA
  • S4 is a signal provided by the upper level shift register unit in the GOA. signal provided by the two-stage shift register unit. Therefore, for a row of pixel circuits, at least 4 GOA are needed, or the first-level shift register unit of GOA needs to output 4 shift signals.
  • FIG. 12 is a schematic diagram of the circuit structure of the pixel circuit shown in FIG. 5 .
  • the pixel circuit 10 includes: transistors M1 to M8 and a storage capacitor Cst.
  • the transistor M3 is used as a driving transistor, and the other transistors are used as switching transistors.
  • the light-emitting element 170 can be implemented as a light-emitting element EL, and the light-emitting element EL can be, for example, an OLED.
  • Embodiments of the present disclosure include but are not limited to this. The following embodiments take OLED as an example for description, and will not be described again.
  • the OLED can be of various types, such as top emission, bottom emission, etc., and can emit red light, green light, blue light, or white light, etc., and the embodiments of the present disclosure are not limited thereto.
  • the driving circuit 110 can be implemented as a driving transistor, that is, a transistor M3; the data writing circuit 120 can be implemented as a data writing transistor, that is, a transistor M4; and the threshold compensation circuit 130 can be implemented is a threshold compensation transistor, that is, transistor M2; the storage circuit 140 can be implemented as a storage capacitor Cst; the first lighting control circuit 150 can be implemented as a first lighting control transistor, that is, transistor M5; the second lighting control circuit 180 can be implemented as a Two light-emitting control transistors, that is, the transistor M6; the second reset circuit 190 can be implemented as a second reset transistor, that is, the transistor M7.
  • the connection method of these transistors and storage capacitors is similar to the circuit structure shown in Figure 7 and will not be described again here.
  • the first reset circuit 160 is connected in a different manner and also includes an anti-leakage circuit 230 .
  • the first reset circuit 160 may be implemented as a first reset transistor, that is, transistor M1.
  • the gate of the first reset transistor (transistor M1) is connected to the first reset line (scan line S4).
  • the first electrode of the first reset transistor (transistor M1) is connected to the first reset voltage line (voltage line INIT1).
  • the second pole of (transistor M1) is connected to the second pole of transistor M2.
  • the anti-leakage circuit 230 can be implemented as an anti-leakage transistor, also That is transistor M8.
  • the gate electrode of the anti-leakage transistor is connected to the third scan line (scan line S7)
  • the first electrode of the anti-leakage transistor is connected to the second electrode of the transistor M2
  • the gate electrode of the anti-leakage transistor is connected to the third scan line (scan line S7).
  • the second electrode and the gate of the transistor M3 are connected to the first node P1.
  • the anti-leakage transistor is a second type transistor, such as an N-type thin film transistor.
  • FIG. 13 is a timing diagram for the pixel circuit shown in FIG. 12 provided by some embodiments of the present disclosure.
  • the pixel circuit 10 used in this example contains two N-type thin film transistors (transistor M8 and transistor M2), so it can It plays a better role in preventing leakage at the first node P1, which is prone to leakage.
  • the two N-type thin film transistors M2 and M8 can enhance the flexibility of operation. For example, when only the first node P1 needs to be reset, the transistor M8 can be turned on.
  • the transistor M8 controlled by S7 is turned on, the transistor M1 controlled by S4 is turned on, and the first node P1 writes the reset voltage of INIT1 to reset the gate of the transistor M3, that is, The first node P1 is reset.
  • the transistor M5 controlled by S1 is turned on, the transistor M7 controlled by S6 is turned on, the high potential of VDD is written to the second node P2, thereby resetting the second node P2, and the potential of INIT2 is written to the anode of the light-emitting element EL, thus resetting the The fourth node P4 is reset.
  • a data writing operation is performed.
  • the transistor M4 controlled by S3 is turned on, and the transistor M2 controlled by S5 is turned on, and the data signal is written to the gate of the transistor M3 (that is, the first node P1).
  • the potential of the first node P1 is Vdata+
  • the transistor M7 controlled by S6 still remains on, so that the potential of the fourth node P4 is INIT2.
  • the potentials of S1 and S2 are low, the transistors M5 and M6 are turned on, and therefore the light-emitting element EL emits light.
  • FIG. 14 is another timing diagram for the pixel circuit shown in FIG. 12 provided by some embodiments of the present disclosure.
  • the difference between this example and the example shown in Figure 13 is that the reset operation before writing data is performed in two stages, that is, in the first stage T1, the second node P2 and the fourth node P4 is reset, and in the second stage T2, the first node P1 is reset.
  • the T1 and T2 stages in this example can also be combined into one stage.
  • the second node P2 and the fourth node P4 are reset again to eliminate the residual charge on the light-emitting path, and then enter the light-emitting stage.
  • S7 and S1 can be signals output by the same GOA; S3 and S4 can be output by the same GOA.
  • a type of GOA provides signals.
  • S3 is a signal provided by a shift register unit of a certain level in the GOA
  • S4 is a signal provided by a shift register unit of the previous level in the GOA. Therefore, for a row of pixel circuits, at least 5 GOA are needed, or the first-level shift register unit of GOA needs to output 5 shift signals.
  • FIG. 15 is another timing diagram for the pixel circuit shown in FIG. 12 provided by some embodiments of the present disclosure.
  • a reset operation is performed on both the second node P2 and the fourth node P4.
  • the reset operation on the first node P1 is performed in the first phase T1.
  • the conduction status of each transistor during the reset operation please refer to the above content and will not be repeated here.
  • FIG. 16 is another timing diagram for the pixel circuit shown in FIG. 12 provided by some embodiments of the present disclosure.
  • the reset operation is performed in two stages before writing data. Specifically, the first node P1 and the third node P3 are reset in the first phase T1, and the second node P2 and the fourth node P4 are reset in the second phase T2. After writing the data, the second node P2, the third node P3, and the fourth node P4 are reset.
  • the potential of the second node P2 is VDD
  • the potential of the third node P3 is INIT1
  • the potential of the fourth node P4 is INIT2.
  • the conduction status of each transistor during the reset operation please refer to the above content and will not be repeated here.
  • FIG. 17 is a schematic diagram of the circuit structure of the pixel circuit shown in FIG. 3 .
  • the pixel circuit 10 includes: transistors M1 to M8 and a storage capacitor Cst.
  • the transistor M3 is used as a driving transistor, and the other transistors are used as switching transistors.
  • the light-emitting element 170 can be implemented as a light-emitting element EL, and the light-emitting element EL can be, for example, an OLED.
  • Embodiments of the present disclosure include but are not limited to this. The following embodiments take OLED as an example for description, and will not be described again.
  • the OLED can be of various types, such as top emission, bottom emission, etc., and can emit red light, green light, blue light, or white light, etc., and the embodiments of the present disclosure are not limited thereto.
  • the driving circuit 110 can be implemented as a driving transistor, that is, the transistor M3; the data writing circuit 120 can be implemented as a data writing transistor, that is, the transistor M4; and the threshold compensation circuit 130 can be implemented is a threshold compensation transistor, that is, transistor M2; the storage circuit 140 can be implemented as a storage capacitor Cst; the first lighting control circuit 150 can be implemented as a first lighting control transistor, that is, transistor M5; the second lighting control circuit 180 can be implemented as a Two light-emitting control transistors, that is, transistor M6; the first reset circuit 160 can be implemented as a first reset transistor, that is, transistor M1; the second reset circuit 190 can be implemented as a second reset transistor, that is, transistor M7.
  • the connection of these transistors and storage capacitors is consistent with the circuit structure shown in Figure 7 Similar, will not be repeated here.
  • the third reset circuit 210 may be implemented as a third reset transistor, that is, transistor M8.
  • the gate of the third reset transistor (transistor M8) is connected to the third reset line (scan line S7) to receive the third reset signal
  • the first electrode of the third reset transistor (transistor M8) is connected to the third reset voltage line (voltage line INIT1 ) to receive the third reset voltage
  • the second electrode of the third reset transistor (transistor M8) is connected to the control terminal 113 of the driving circuit 110, that is, the gate electrode of the transistor M3 is connected to the first node P1.
  • the third reset transistor is a second type transistor, such as an N-type thin film transistor.
  • FIG. 18 is a timing diagram for the pixel circuit shown in FIG. 17 provided by some embodiments of the present disclosure.
  • the transistor M1 is used to reset the drain of the transistor M3 (ie, the third node P3).
  • the first stage T1 the first node P1, the second node P2, the third node P3, and the fourth node P4 are reset.
  • the second stage T2 a data writing operation is performed.
  • the third stage T3 the second node P2 is reset by the turned-on transistor M5, the third node P3 is reset by the turned-on transistor M1, and the fourth node P4 is reset by the turned-on transistor M7.
  • the light-emitting element EL emits light.
  • the conduction status of each transistor during the reset operation please refer to the above content and will not be repeated here.
  • FIG. 19 is another timing diagram for the pixel circuit shown in FIG. 17 provided by some embodiments of the present disclosure.
  • the first node P1, the second node P2, and the fourth node P4 are reset; in the second phase T2, the first node P1, the third node P3 and the fourth node P4 are reset.
  • the second node P2 can be reset through the turned-on transistor M5, the third node P3 can be reset through the turned-on transistor M1, the fourth node P4 can be reset through the turned-on transistor M7, and the turned-on transistor M7 can be used to reset the fourth node P4.
  • M8 resets the first node P1.
  • the third stage T3 the data writing operation is performed.
  • the fourth stage T4 the light-emitting element EL emits light.
  • the conduction status of each transistor during the reset operation please refer to the above content and will not be repeated here.
  • FIG. 20 is another timing diagram for the pixel circuit shown in FIG. 17 provided by some embodiments of the present disclosure.
  • the first phase T1 the first node P1, the second node P2, and the fourth node P4 are reset; in the second phase T2, the first node P1, the third node P3 and the fourth node P4 are reset.
  • the third stage T3 the data writing operation is performed.
  • the fourth phase T4 the third node P3 and the fourth node P4 are reset.
  • the conduction status of each transistor during the reset operation please refer to the above content and will not be repeated here.
  • FIG. 21 is a schematic diagram of the circuit structure of the pixel circuit shown in FIG. 4 .
  • the pixel circuit 10 includes: transistors M1 to M9 and a storage capacitor Cst.
  • the transistor M3 is used as a driving transistor, and the other transistors are used as switching transistors.
  • the light-emitting element 170 can be implemented as a light-emitting element EL, and the light-emitting element EL can be, for example, an OLED.
  • Embodiments of the present disclosure include but are not limited to this. The following embodiments take OLED as an example for description, and will not be described again.
  • the OLED can be of various types, such as top emission, bottom emission, etc., and can emit red light, green light, blue light, or white light, etc., and the embodiments of the present disclosure are not limited thereto.
  • the driving circuit 110 can be implemented as a driving transistor, that is, a transistor M3; the data writing circuit 120 can be implemented as a data writing transistor, that is, a transistor M4; and the threshold compensation circuit 130 can be implemented is a threshold compensation transistor, that is, transistor M2; the storage circuit 140 can be implemented as a storage capacitor Cst; the first lighting control circuit 150 can be implemented as a first lighting control transistor, that is, transistor M5; the second lighting control circuit 180 can be implemented as a Two light-emitting control transistors, that is, transistor M6; the first reset circuit 160 can be implemented as a first reset transistor, that is, transistor M1; the second reset circuit 190 can be implemented as a second reset transistor, that is, transistor M7; the third reset circuit 210 may be implemented as a third reset transistor, namely transistor M8.
  • the connection method of these transistors and storage capacitors is similar to the circuit structure shown in Figure 17, and will not be described again here.
  • the fourth reset circuit 220 may be implemented as a fourth reset transistor, that is, transistor M9.
  • the gate electrode of the fourth reset transistor (transistor M9) is connected to the fourth reset line (scan line S8) to receive the fourth reset signal
  • the first electrode of the fourth reset transistor (transistor M9) is connected to the fourth reset voltage line (voltage line INIT4) is connected to receive the fourth reset voltage
  • the second pole of the fourth reset transistor (transistor M9) is connected to the first terminal 111 of the driving circuit 110, that is, the first pole of the transistor M3 is connected to the second node P2.
  • FIG. 22 is a timing diagram for the pixel circuit shown in FIG. 21 provided by some embodiments of the present disclosure.
  • the first node P1 is reset by the turned-on transistor M8, and the second node P2 and the fourth node are reset by the turned-on transistor M9 and M7 respectively.
  • P4 is reset.
  • the third node P3 is reset by the turned-on transistor M1.
  • the data writing operation is performed.
  • the fourth stage T4 again The third node P3 and the fourth node P4 are respectively reset by the turned-on transistor M1 and the transistor M7.
  • the light-emitting element EL emits light.
  • the conduction status of each transistor during the reset operation please refer to the above content and will not be repeated here.
  • VINT4 is 6V
  • VINT1 is -3V or -4V
  • VINT2 is -3V
  • VINT3 is 0V, 1V, 2V, 3V, and 4V respectively.
  • the potential of VINT3 can be 0V, 1V, 2V, 3V, 4V, and its value can be selected according to actual needs. If you need a fast reset and apply it to a high-frequency scenario, you can choose a lower potential value, such as 0V; if you need a slower speed reset and apply it to a low-frequency scenario, you can choose a potential close to the data voltage, such as 3V or 4V. .
  • the potential of the third node P3 after being reset by the first reset transistor (transistor M1) is greater than the potential of the fourth node P4 after being reset by the second reset transistor (transistor M7); the first node P1 is reset by the third reset transistor (Transistor M8) The potential after reset is less than the potential of the third node P3 after being reset by the first reset transistor (transistor M1); the potential of the first node P1 after being reset by the third reset transistor (transistor M8) is less than or equal to the fourth node
  • the potential of P4 after being reset by the second reset transistor (transistor M7); the potential of the second node P2 after being reset by the fourth reset transistor (transistor M9) is greater than the potential of the first node P1 after being reset by the third reset transistor (transistor M8) ;
  • the potential of the second node P2 after being reset by the fourth reset transistor (transistor M9) is greater than the potential of the third node P3 after being reset by the first reset transistor (transist
  • the reset situation within one frame may be different.
  • a low-frequency situation such as 30 Hz and below
  • the four nodes of the first node P1, the second node P2, the third node P3, and the fourth node P4 are all reset. Since when operating at low frequency, there is more time to complete the reset, and at low frequency, the transistors in the pixel circuit are more likely to leak. Therefore, sufficient reset is conducive to improving the hysteresis effect and thereby improving the display quality.
  • a medium frequency situation such as 30Hz to 90Hz
  • you can choose to reset fewer nodes than the low-frequency state such as resetting the first node P1, the second node P2, and the fourth node P4, or resetting the first node P1 , the third node P3 and the fourth node P4.
  • high frequency working state such as 90Hz to 120Hz or even higher frequency
  • Nodes with fewer states such as resetting the first node P1 and the fourth node P4, or only resetting one of the two nodes.
  • fewer nodes are reset, which is conducive to rapid data writing in a short period of time, thereby achieving a high refresh rate.
  • the number of reset nodes is reduced, which is beneficial to further reducing power consumption.
  • a separately provided voltage generation circuit can be used to generate three voltage signals for use by the pixel circuit, that is, to generate VDD1, VDD2, VSS Three voltage signals, or two signal lines are connected at the first voltage line VDD to transmit VDD1 and VDD2 respectively.
  • the relationship between the three is: VDD1>VDD2>VSS.
  • the signal connected to the first voltage line VDD is VDD2; in the light-emitting phase, the signal connected to the first voltage line VDD is VDD1. Therefore, the transistor M9 in FIG. 21 can be omitted.
  • the first voltage transmitted on the first voltage line VDD may also be constant, and the embodiments of the present disclosure are not limited to this.
  • Figure 23 is a schematic circuit structure diagram of a pixel circuit provided by some embodiments of the present disclosure.
  • the pixel circuit 10 includes: transistors M1 to M9 and a storage capacitor Cst.
  • the transistor M3 is used as a driving transistor, and the other transistors are used as switching transistors.
  • the light-emitting element 170 can be implemented as a light-emitting element EL, and the light-emitting element EL can be, for example, an OLED.
  • Embodiments of the present disclosure include but are not limited to this.
  • the following embodiments take OLED as an example for description, and will not be described again.
  • the OLED can be of various types, such as top emission, bottom emission, etc., and can emit red light, green light, blue light, or white light, etc., and the embodiments of the present disclosure are not limited thereto.
  • the driving circuit 110 can be implemented as a driving transistor, that is, a transistor M3; the data writing circuit 120 can be implemented as a data writing transistor, that is, a transistor M4; and the threshold compensation circuit 130 can be implemented is a threshold compensation transistor, that is, transistor M2; the storage circuit 140 can be implemented as a storage capacitor Cst; the first lighting control circuit 150 can be implemented as a first lighting control transistor, that is, transistor M5; the second lighting control circuit 180 can be implemented as a Two light-emitting control transistors, that is, transistor M6; the first reset circuit 160 can be implemented as a first reset transistor, that is, transistor M1; the second reset circuit 190 can be implemented as a second reset transistor, that is, transistor M7; the third reset circuit 210 may be implemented as a third reset transistor, that is, transistor M8; the fourth reset circuit 220 may be implemented as a fourth reset transistor, that is, transistor M9.
  • the working principle of the pixel circuit 10 in this example is basically the same as the working principle of the pixel circuit 10 shown in FIG. 21 .
  • the difference is that all the transistors in the pixel circuit 10 in this example are N-type thin film transistors.
  • the transistors in the pixel circuit 10 in this example are N-type thin film transistors.
  • FIG. 24 is a timing diagram for the pixel circuit shown in FIG. 23 provided by some embodiments of the present disclosure.
  • the second node P2 is reset by the turned-on transistor M9.
  • the third node P3 is reset by the turned-on transistor M1
  • the fourth node P4 is reset by the turned-on transistor M7
  • the first node P1 is reset by the turned-on transistor M8.
  • the third phase T3 the data writing operation is performed.
  • the fourth node P4 and the second node P2 are respectively reset through the turned-on transistor M7 and the transistor M9.
  • the light-emitting element EL emits light.
  • one or more nodes among the first node P1, the second node P2, the third node P3, and the fourth node P4 may be selected for reset before and/or during the data writing phase. Reset is performed between the data writing stage and the light-emitting stage (that is, after the data writing stage and before the light-emitting stage).
  • the selected nodes can be reset in any applicable order and manner, and embodiments of the present disclosure do not limit this.
  • each node is described above for a specific circuit structure, this does not constitute a limitation on the embodiments of the present disclosure.
  • the driving method provided by the embodiments of the present disclosure can also be applied to other circuit structures. Not limited to the circuit structures shown in Figures 2 to 5, Figure 7, Figure 12, Figure 17, Figure 21, and Figure 23, and not limited to pixel circuits including 7 transistors/8 transistors/9 transistors, the driving method Can be applied to any applicable pixel circuit.
  • nodes on the data writing path are reset before data writing, which can eliminate the influence of residual charges in the previous stage (including residual charges due to leakage current), so that data can be accurately written into the gate of the drive transistor.
  • the storage capacitor Cst may be a capacitor device manufactured through a process, for example, the capacitor device is realized by manufacturing a special capacitor electrode.
  • the capacitor Cst Each electrode of can be realized by a metal layer, a semiconductor layer (such as doped polysilicon), etc., and the storage capacitor Cst can also be a parasitic capacitance between transistors, which can be realized by the transistor itself and other devices and circuits.
  • the first node P1, the second node P2, the third node P3, and the fourth node P4 do not represent actual existing components, but represent relevant electrical connections in the circuit diagram. meeting point.
  • the transistors used in the embodiments of the present disclosure may be thin film transistors, field effect transistors, or other switching devices with the same characteristics.
  • thin film transistors are used as examples for explanation.
  • the source and drain of the transistor used here can be symmetrical in structure, so there can be no structural difference between the source and drain.
  • one of the poles is directly described as the first pole and the other pole is the second pole.
  • the transistor when the transistor is an N-type transistor, the first electrode of the transistor is the drain electrode, and the second electrode is the source electrode; when the transistor is a P-type transistor, the first electrode of the transistor is the source electrode. , the second pole is the drain.
  • IGZO Indium Gallium Zinc Oxide
  • LTPS Low Temperature Polysilicon
  • amorphous silicon such as hydrogenated non-crystalline silicon
  • Crystalline silicon as the active layer of thin film transistors, can effectively reduce the size of the transistor and prevent leakage current.
  • At least one embodiment of the present disclosure also provides a pixel circuit.
  • the pixel circuit includes: a driving circuit, a data writing circuit, a threshold compensation circuit, a storage circuit, a first light emitting control circuit and a first reset circuit.
  • the driving circuit includes a control terminal, a first terminal and a second terminal, and is configured to control the driving current flowing through the light emitting element.
  • the data writing circuit is connected to the first end of the driving circuit and is configured to write the data signal to the first end of the driving circuit in response to the first scanning signal during the data writing phase.
  • the threshold compensation circuit is connected between the control terminal of the driving circuit and the second terminal of the driving circuit, and is configured to write a compensation signal based on the data signal into the control terminal of the driving circuit in response to the second scan signal.
  • the storage circuit is connected to the control terminal of the driving circuit and the first voltage line.
  • the storage circuit and the control terminal of the driving circuit are connected to the first node.
  • the storage circuit is configured to store the compensation signal and maintain the compensation signal at the control terminal of the driving circuit.
  • the first lighting control circuit is connected to the first voltage line and the first end of the driving circuit.
  • a first end of the control circuit and the driving circuit is connected to the second node, and the first lighting control circuit is configured to apply a first voltage provided by the first voltage line to the driving circuit in response to the first lighting control signal before the data writing stage. The first end, thereby resetting the second node.
  • the first reset circuit is connected to the threshold compensation circuit and is configured to apply a first reset voltage to the control terminal of the driving circuit in response to the first reset signal before the data writing phase, thereby resetting the first node.
  • the pixel circuit can reduce or eliminate the impact of residual charge on the accuracy of written data and the potential of the anode of the light-emitting device during the light-emitting phase, thereby optimizing the display effect.
  • the pixel circuit 10 shown in FIGS. 2 to 5 please refer to the above description of the pixel circuit 10 shown in FIGS. 2 to 5 , and will not be described again here.
  • At least one embodiment of the present disclosure also provides a pixel circuit.
  • the pixel circuit includes: a driving circuit, a data writing circuit, a threshold compensation circuit, a storage circuit and a first reset circuit.
  • the driving circuit includes a control terminal, a first terminal and a second terminal, and is configured to control the driving current flowing through the light-emitting element; the data writing circuit is connected to the first terminal of the driving circuit, and is configured to write the data in response to the first scan signal.
  • the threshold compensation circuit is connected between the control end of the driving circuit and the second end of the driving circuit, and is configured to write a compensation signal based on the data signal into the driving circuit in response to the second scan signal
  • the control end of the drive circuit is connected to the control end of the drive circuit and the first voltage line, and is configured to store the compensation signal and maintain the compensation signal at the control end of the drive circuit
  • the first reset circuit is connected to the threshold compensation circuit and the third drive circuit
  • the two terminals are connected and configured to apply a first reset voltage to the second terminal of the driving circuit in response to the first reset signal.
  • the pixel circuit is, for example, the pixel circuit 10 shown in FIGS. 2, 3, and 4.
  • driving circuit data writing circuit, threshold compensation circuit, storage circuit, and first reset circuit
  • the description of the driving circuit 110, the data writing circuit 120, the threshold compensation circuit 130, the storage circuit 140 and the first reset circuit 160 in the pixel circuit 10 shown in Figures 3 and 4 will not be described again here.
  • the driving circuit includes a driving transistor, the gate of the driving transistor serves as the control terminal of the driving circuit, the first pole of the driving transistor serves as the first terminal of the driving circuit, and the second pole of the driving transistor serves as the second terminal of the driving circuit.
  • the data writing circuit includes a data writing transistor, a gate electrode of the data writing transistor is connected to the first scan line to receive the first scan signal, a first electrode of the data writing transistor is connected to the data line to receive the data signal, and the data The second pole of the write transistor is connected to the first pole of the drive transistor.
  • the threshold compensation circuit includes a threshold compensation transistor, a gate electrode of the threshold compensation transistor is connected to the second scan line to receive the second scan signal, a first electrode of the threshold compensation transistor is connected to the second electrode of the driving transistor, and a third electrode of the threshold compensation transistor is connected to the second scan line.
  • the diode is connected to the gate of the drive transistor.
  • the storage circuit includes a storage capacitor, a first electrode of the storage capacitor is connected to the first voltage line, and a second electrode of the storage capacitor is connected to the gate electrode of the driving transistor.
  • the first reset circuit includes a first reset transistor, a gate of the first reset transistor is connected to the first reset line to receive the first reset signal, and a first electrode of the first reset transistor is connected to the first reset voltage line to receive the first reset voltage line.
  • a reset voltage, the second electrode of the first reset transistor is connected to the second electrode of the driving transistor.
  • connection methods of each transistor and the storage capacitor reference can be made to the connection methods of each transistor and the storage capacitor in the pixel circuit 10 shown in Figures 7, 17, and 21.
  • the driving transistor is, for example, the transistor M3, and the data writing transistor is, for example, The transistor M4, the threshold compensation transistor is, for example, the transistor M2, the storage capacitor is, for example, the storage capacitor Cst, and the first reset transistor is, for example, the transistor M1. The detailed description will not be repeated here.
  • the pixel circuit further includes a first lighting control circuit and a second lighting control circuit.
  • the first lighting control circuit is connected to the first voltage line and the first terminal of the driving circuit, and is configured to apply a first voltage provided by the first voltage line to the first terminal of the driving circuit in response to the first lighting control signal.
  • the second light emitting control circuit is connected to the second end of the driving circuit and the light emitting element, and is configured to apply the voltage of the second end of the driving circuit to the light emitting element in response to the second light emitting control signal.
  • first light-emitting control circuit and the second light-emitting control circuit please refer to the above description of the first light-emitting control circuit 150 and the second light-emitting control circuit 180 in the pixel circuit 10 shown in FIG. 2, FIG. 3, and FIG. 4. Description will not be repeated here.
  • the first light-emitting control circuit includes a first light-emitting control transistor.
  • the gate of the first light-emitting control transistor is connected to the first light-emitting control line to receive the first light-emitting control signal.
  • the first electrode of the first light-emitting control transistor is connected to the first voltage.
  • the second terminal of the first light-emitting control transistor is connected to the first terminal of the driving circuit.
  • the second light-emitting control circuit includes a second light-emitting control transistor.
  • the gate of the second light-emitting control transistor is connected to the second light-emitting control line to receive the second light-emitting control signal.
  • the first electrode of the second light-emitting control transistor is connected to the first electrode of the driving circuit.
  • the second terminal is connected, and the second pole of the second light-emitting control transistor is connected to the light-emitting element.
  • the first light emission control transistor is, for example, the transistor M5
  • the second light emission control transistor is, for example, the transistor M6. , the detailed description will not be repeated here.
  • the pixel circuit also includes a second reset circuit.
  • the second reset circuit is connected to the second light-emitting control circuit and the light-emitting element, and is configured to reset the second reset circuit in response to the second reset signal. Pressure is applied to the light emitting element.
  • the second reset circuit please refer to the above description of the second reset circuit 190 in the pixel circuit 10 shown in FIG. 2 , FIG. 3 , and FIG. 4 , and will not be described again here.
  • the second reset circuit includes a second reset transistor, a gate of the second reset transistor is connected to the second reset line to receive the second reset signal, and a first electrode of the second reset transistor is connected to the second reset voltage line to receive the second reset voltage line.
  • Two reset voltages, the second electrode of the second reset transistor is connected to the second electrode of the second light-emitting control transistor and the light-emitting element.
  • the second reset transistor is, for example, the transistor M7 , and the detailed description will not be repeated here.
  • the pixel circuit also includes a third reset circuit.
  • the third reset circuit is connected to the threshold compensation circuit and the control terminal of the driving circuit, and is configured to apply a third reset voltage to the control terminal of the driving circuit in response to the third reset signal.
  • the third reset circuit please refer to the above description of the third reset circuit 210 in the pixel circuit 10 shown in FIG. 3 and FIG. 4 , and will not be described again here.
  • the third reset circuit includes a third reset transistor, a gate of the third reset transistor is connected to the third reset line to receive the third reset signal, and a first electrode of the third reset transistor is connected to the third reset voltage line to receive the third reset voltage line.
  • Three reset voltages, the second pole of the third reset transistor is connected to the control terminal of the drive circuit.
  • the third reset transistor is, for example, the transistor M8, and the detailed description will not be repeated here.
  • the pixel circuit further includes a fourth reset circuit.
  • the fourth reset circuit is connected to the first end of the driving circuit, and the fourth reset circuit is configured to apply a fourth reset voltage to the first end of the driving circuit in response to the fourth reset signal.
  • the fourth reset circuit please refer to the above description of the fourth reset circuit 220 in the pixel circuit 10 shown in FIG. 4 , and will not be described again here.
  • the fourth reset circuit includes a fourth reset transistor, a gate of the fourth reset transistor is connected to the fourth reset line to receive the fourth reset signal, and a first electrode of the fourth reset transistor is connected to the fourth reset voltage line to receive the fourth reset voltage line.
  • the second pole of the fourth reset transistor is connected to the first terminal of the driving circuit.
  • the fourth reset transistor is, for example, the transistor M9, and the detailed description will not be repeated here.
  • At least one embodiment of the present disclosure also provides a display panel, the display panel including a plurality of pixels unit, each pixel unit includes a pixel circuit provided by any embodiment of the present disclosure.
  • the display panel can reduce or eliminate the impact of residual charges on the accuracy of writing data and the potential of the anode of the light-emitting device during the light-emitting phase, thereby optimizing the display effect.
  • FIG. 25 is a schematic block diagram of a display panel provided by some embodiments of the present disclosure.
  • the display panel 30 includes a plurality of pixel units 301 , and the plurality of pixel units 301 are arranged in an array, for example.
  • Each pixel unit 301 includes a pixel circuit 302 .
  • the pixel circuit 302 may be a pixel circuit provided by any embodiment of the present disclosure, such as the pixel circuit 10 described above.
  • the display panel 30 may be an organic light-emitting diode (OLED) display panel, a quantum dot light-emitting diode (QLED) display panel, or other suitable display panels.
  • OLED organic light-emitting diode
  • QLED quantum dot light-emitting diode
  • Each pixel unit 301 includes not only a pixel circuit 302 but also a light-emitting element (such as OLED, QLED, etc.).
  • the display panel 30 may be a rectangular panel, a circular panel, an oval panel, a polygonal panel, or the like.
  • the display panel 30 can be not only a flat panel, but also a curved panel, or even a spherical panel.
  • the display panel 30 may also have a touch function, that is, the display panel 30 may be a touch display panel.
  • the display panel 30 can be applied to any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, or the like.
  • the display panel 30 can be a flexible display panel, so that it can meet various practical application requirements.
  • the display panel 30 can be applied to a curved screen, etc.
  • the embodiments of the present disclosure do not show all the constituent units of the display panel 30 .
  • those skilled in the art can provide and set up other structures not shown according to specific needs, and the embodiments of the present disclosure do not limit this.
  • At least one embodiment of the present disclosure further provides a display device, which includes the display panel provided by any embodiment of the present disclosure.
  • the display device can reduce or eliminate the influence of residual charges on the accuracy of writing data and the potential of the anode of the light-emitting device during the light-emitting phase, thereby optimizing the display effect.
  • FIG. 26 is a schematic block diagram of a display device provided by some embodiments of the present disclosure.
  • the display device 40 includes a display panel 4000 , a gate driver 4010 , a timing controller 4020 and a data driver 4030 .
  • the display panel 4000 includes a plurality of pixel units P defined crosswise according to a plurality of scan lines GL and a plurality of data lines DL.
  • the display panel 4000 is, for example, a display panel provided by any embodiment of the present disclosure, such as the display panel 30 described above.
  • Multiple scan lines GL include the aforementioned The first scan line SC1, the second scan line SC2, the third scan line SC3, the first light emission control line EM1, the second light emission control line EM2, and so on.
  • the plurality of data lines DL include the aforementioned data line Vdata.
  • the gate driver 4010 is used to drive a plurality of scan lines GL; the data driver 4030 is used to drive a plurality of data lines DL; the timing controller 4020 is used to process the image data RGB input from outside the display device 40, and provide the processed data to the data driver 4030.
  • the image data RGB and the scan control signal GCS and the data control signal DCS are output to the gate driver 4010 and the data driver 4030 to control the gate driver 4010 and the data driver 4030 .
  • the gate driver 4010 can be implemented as a semiconductor chip, or can be integrated in the display panel 4000 to form a GOA circuit.
  • the data driver 4030 converts the digital image data RGB input from the timing controller 4020 into a data signal according to the plurality of data control signals DCS originating from the timing controller 4020 using the reference gamma voltage.
  • the data driver 4030 provides converted data signals to the plurality of data lines DL.
  • the data driver 4030 may be implemented as a semiconductor chip.
  • the timing controller 4020 processes the externally input image data RGB to match the size and resolution of the display panel 4000, and then provides the processed image data to the data driver 4030.
  • the timing controller 4020 uses synchronization signals (such as dot clock DCLK, data enable signal DE, horizontal synchronization signal Hsync, and vertical synchronization signal Vsync) input from outside the display device 40 to generate a plurality of scan control signals GCS and a plurality of data control signals DCS. .
  • the timing controller 4020 provides the generated scan control signal GCS and data control signal DCS to the gate driver 4010 and the data driver 4030 respectively for control of the gate driver 4010 and the data driver 4030.
  • the display device 40 may also include other components, such as a signal decoding circuit, a voltage conversion circuit, etc. These components may be, for example, existing conventional components, which will not be described in detail here.
  • the display device 40 can be applied to any product or component with a display function such as e-books, mobile phones, tablets, televisions, monitors, laptops, digital photo frames, and navigators.
  • a display function such as e-books, mobile phones, tablets, televisions, monitors, laptops, digital photo frames, and navigators.

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Abstract

一种像素电路及其驱动方法、显示面板、显示装置。在该像素电路（10）中，驱动电路（110）的控制端（113）与存储电路（140）连接于第一节点（P1），第一发光控制电路（150）与驱动电路（110）的第一端（111）连接于第二节点（P2）。该像素电路（10）的驱动方法包括：在数据写入阶段之前，第一复位电路（160）导通，以将第一复位电压施加至驱动电路（110）的控制端（113），从而对第一节点（P1）进行复位，第一发光控制电路（150）导通，以将第一电压施加至驱动电路（110）的第一端（111），从而对第二节点（P2）进行复位；在数据写入阶段，数据写入电路（120）导通，以将数据信号写入驱动电路（110）的第一端（111）；在发光阶段，第一发光控制电路（150）导通，发光元件（170）根据驱动电流发光。该方法可以降低或消除残余电荷对写入数据的精确度和发光阶段发光器件阳极的电位的影响，实现显示效果的优化。

Description

像素电路及其驱动方法、显示面板、显示装置
本申请要求于2022年8月23日递交的中国专利申请第202211012901.3号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开的实施例涉及一种像素电路及其驱动方法、显示面板、显示装置。
背景技术
有机发光二极管(Organic Light Emitting Diode，OLED)显示装置由于具有视角宽、对比度高、响应速度快以及相比于无机发光显示器件更高的发光亮度、更低的驱动电压等优势而逐渐受到人们的广泛关注。由于上述特点，有机发光二极管(OLED)可以适用于手机、显示器、笔记本电脑、数码相机、仪器仪表等具有显示功能的装置。
OLED显示装置中的像素电路一般采用矩阵驱动方式，根据每个像素单元中是否引入开关元器件分为有源矩阵(Active Matrix，AM)驱动和无源矩阵(Passive Matrix，PM)驱动。PMOLED虽然工艺简单、成本较低，但因存在交叉串扰、高功耗、低寿命等缺点，不能满足高分辨率大尺寸显示的需求。相比之下，AMOLED在每一个像素的像素电路中都集成了一组薄膜晶体管和存储电容，通过对薄膜晶体管和存储电容的驱动控制，实现对流过OLED的电流的控制，从而使OLED根据需要发光。相比PMOLED，AMOLED所需驱动电流小、功耗低、寿命更长，可以满足高分辨率多灰度的大尺寸显示需求。同时，AMOLED在可视角度、色彩的还原、功耗以及响应时间等方面具有明显的优势，适用于高信息含量、高分辨率的显示装置。
发明内容
本公开至少一个实施例提供一种像素电路的驱动方法，其中，所述像素电路包括驱动电路、数据写入电路、阈值补偿电路、存储电路、第一发光控制电路和第一复位电路；所述驱动电路包括控制端、第一端和第二端，且配 置为控制流经发光元件的驱动电流；所述数据写入电路与所述驱动电路的第一端连接，且配置为响应于第一扫描信号将数据信号写入所述驱动电路的第一端；所述阈值补偿电路连接在所述驱动电路的控制端和所述驱动电路的第二端之间，且配置为响应于第二扫描信号将基于所述数据信号的补偿信号写入所述驱动电路的控制端；所述存储电路与所述驱动电路的控制端和第一电压线连接，且配置为存储所述补偿信号并将所述补偿信号保持在所述驱动电路的控制端；所述第一发光控制电路与所述第一电压线和所述驱动电路的第一端连接，且配置为响应于第一发光控制信号将所述第一电压线提供的第一电压施加至所述驱动电路的第一端；所述第一复位电路与所述阈值补偿电路连接，且配置为响应于第一复位信号将第一复位电压施加至所述驱动电路的控制端；所述驱动电路的控制端与所述存储电路连接于第一节点，所述第一发光控制电路与所述驱动电路的第一端连接于第二节点；所述方法包括：在数据写入阶段之前，所述第一复位电路响应于所述第一复位信号导通，以将所述第一复位电压施加至所述驱动电路的控制端，从而对所述第一节点进行复位，并且，所述第一发光控制电路响应于所述第一发光控制信号导通，以将所述第一电压施加至所述驱动电路的第一端，从而对所述第二节点进行复位；在所述数据写入阶段，所述数据写入电路响应于所述第一扫描信号导通，以将所述数据信号写入所述驱动电路的第一端；在发光阶段，所述第一发光控制电路响应于所述第一发光控制信号导通，所述发光元件根据所述驱动电流发光。
例如，在本公开一实施例提供的方法中，所述第一复位电路响应于所述第一复位信号导通，以将所述第一复位电压施加至所述驱动电路的控制端，从而对所述第一节点进行复位，包括：所述第一复位电路响应于所述第一复位信号导通，所述阈值补偿电路响应于所述第二扫描信号导通，以将所述第一复位电压通过所述第一复位电路和所述阈值补偿电路形成的通路施加至所述驱动电路的控制端，从而对所述第一节点进行复位。
例如，在本公开一实施例提供的方法中，所述像素电路还包括第二发光控制电路和第二复位电路；所述第二发光控制电路与所述驱动电路的第二端和所述发光元件连接，且配置为响应于第二发光控制信号将所述驱动电路的第二端的电压施加至所述发光元件；所述第二复位电路与所述第二发光控制电路和所述发光元件连接，且配置为响应于第二复位信号将第二复位电压施 加至所述发光元件；所述第二发光控制电路与所述驱动电路的第二端连接于第三节点，所述第二复位电路与所述第二发光控制电路及所述发光元件连接于第四节点；所述方法还包括：在所述数据写入阶段之前，在所述第一复位电路对所述第一节点进行复位的同时，所述第一复位电路将所述第一复位电压施加至所述驱动电路的第二端，从而对所述第三节点进行复位；和/或，在所述数据写入阶段之前，所述第二复位电路响应于所述第二复位信号导通，以将所述第二复位电压施加至所述发光元件，从而对所述第四节点进行复位。
例如，在本公开一实施例提供的方法中，在所述数据写入阶段之前，所述第一节点和所述第二节点同时进行复位或者在不同的时段分别进行复位。
例如，在本公开一实施例提供的方法中，在所述数据写入阶段之前，在所述第三节点和所述第四节点均进行复位的情形，所述第三节点和所述第四节点同时进行复位或者在不同的时段分别进行复位。
例如，在本公开一实施例提供的方法中，在所述数据写入阶段之前，所述第三节点和所述第四节点至少之一的复位时段与所述第一节点和所述第二节点至少之一的复位时段重合。
例如，在本公开一实施例提供的方法中，在所述数据写入阶段之前，所述第一节点的复位时段、所述第二节点的复位时段、所述第三节点的复位时段、所述第四节点的复位时段均不重合。
例如，本公开一实施例提供的方法还包括：在所述数据写入阶段之后、所述发光阶段之前，所述第一发光控制电路响应于所述第一发光控制信号导通，以将所述第一电压施加至所述驱动电路的第一端，从而对所述第二节点进行复位；和/或，在所述数据写入阶段之后、所述发光阶段之前，所述第一复位电路响应于所述第一复位信号导通，以将所述第一复位电压施加至所述驱动电路的第二端，从而对所述第三节点进行复位；和/或，在所述数据写入阶段之后、所述发光阶段之前，所述第二复位电路响应于所述第二复位信号导通，以将所述第二复位电压施加至所述发光元件，从而对所述第四节点进行复位。
例如，在本公开一实施例提供的方法中，在所述数据写入阶段之后、所述发光阶段之前，所述第二节点、所述第三节点、所述第四节点中至少两个节点同时进行复位或者在不同的时段分别进行复位。
例如，在本公开一实施例提供的方法中，所述驱动电路包括驱动晶体管， 所述数据写入电路包括数据写入晶体管，所述阈值补偿电路包括阈值补偿晶体管，所述第一发光控制电路包括第一发光控制晶体管，所述第一复位电路包括第一复位晶体管；所述驱动晶体管、所述数据写入晶体管、所述第一发光控制晶体管、所述第一复位晶体管为第一类型的晶体管；所述阈值补偿晶体管为第二类型的晶体管；所述第一类型不同于所述第二类型。
例如，在本公开一实施例提供的方法中，所述第一类型的晶体管包括P型薄膜晶体管，所述第二类型的晶体管包括N型薄膜晶体管。
例如，在本公开一实施例提供的方法中，所述像素电路还包括防漏电电路，所述防漏电电路与所述驱动电路的控制端、所述阈值补偿电路和所述存储电路连接，所述防漏电电路配置为抑制所述驱动电路的控制端的漏电。
例如，在本公开一实施例提供的方法中，所述防漏电电路包括防漏电晶体管，所述防漏电晶体管为所述第二类型的晶体管。
本公开至少一个实施例还提供一种像素电路，包括：驱动电路、数据写入电路、阈值补偿电路、存储电路和第一复位电路；其中，所述驱动电路包括控制端、第一端和第二端，且配置为控制流经发光元件的驱动电流；所述数据写入电路与所述驱动电路的第一端连接，且配置为响应于第一扫描信号将数据信号写入所述驱动电路的第一端；所述阈值补偿电路连接在所述驱动电路的控制端和所述驱动电路的第二端之间，且配置为响应于第二扫描信号将基于所述数据信号的补偿信号写入所述驱动电路的控制端；所述存储电路与所述驱动电路的控制端和第一电压线连接，且配置为存储所述补偿信号并将所述补偿信号保持在所述驱动电路的控制端，所述驱动电路的控制端与所述存储电路连接于第一节点；所述第一复位电路与所述阈值补偿电路和所述驱动电路的第二端连接，且配置为响应于第一复位信号将第一复位电压施加至所述驱动电路的第二端。
例如，在本公开一实施例提供的像素电路中，所述驱动电路包括驱动晶体管，所述驱动晶体管的栅极作为所述驱动电路的控制端，所述驱动晶体管的第一极作为所述驱动电路的第一端，所述驱动晶体管的第二极作为所述驱动电路的第二端；所述数据写入电路包括数据写入晶体管，所述数据写入晶体管的栅极与第一扫描线连接以接收所述第一扫描信号，所述数据写入晶体管的第一极与数据线连接以接收所述数据信号，所述数据写入晶体管的第二极与所述驱动晶体管的第一极连接；所述阈值补偿电路包括阈值补偿晶体管， 所述阈值补偿晶体管的栅极与第二扫描线连接以接收所述第二扫描信号，所述阈值补偿晶体管的第一极与所述驱动晶体管的第二极连接，所述阈值补偿晶体管的第二极与所述驱动晶体管的栅极连接；所述存储电路包括存储电容，所述存储电容的第一极与所述第一电压线连接，所述存储电容的第二极与所述驱动晶体管的栅极连接；所述第一复位电路包括第一复位晶体管，所述第一复位晶体管的栅极与第一复位线连接以接收所述第一复位信号，所述第一复位晶体管的第一极与第一复位电压线连接以接收所述第一复位电压，所述第一复位晶体管的第二极与所述驱动晶体管的第二极连接。
例如，本公开一实施例提供的像素电路还包括第一发光控制电路和第二发光控制电路；其中，所述第一发光控制电路与所述第一电压线和所述驱动电路的第一端连接，且配置为响应于第一发光控制信号将所述第一电压线提供的第一电压施加至所述驱动电路的第一端，所述第一发光控制电路与所述驱动电路的第一端连接于第二节点；所述第二发光控制电路与所述驱动电路的第二端和所述发光元件连接，且配置为响应于第二发光控制信号将所述驱动电路的第二端的电压施加至所述发光元件，所述第二发光控制电路与所述驱动电路的第二端连接于第三节点。
例如，在本公开一实施例提供的像素电路中，所述第一发光控制电路包括第一发光控制晶体管，所述第一发光控制晶体管的栅极与第一发光控制线连接以接收所述第一发光控制信号，所述第一发光控制晶体管的第一极与所述第一电压线连接，所述第一发光控制晶体管的第二极与所述驱动电路的第一端连接；所述第二发光控制电路包括第二发光控制晶体管，所述第二发光控制晶体管的栅极与第二发光控制线连接以接收所述第二发光控制信号，所述第二发光控制晶体管的第一极与所述驱动电路的第二端连接，所述第二发光控制晶体管的第二极与所述发光元件连接。
例如，本公开一实施例提供的像素电路还包括第二复位电路，其中，所述第二复位电路与所述第二发光控制电路和所述发光元件连接，且配置为响应于第二复位信号将第二复位电压施加至所述发光元件；所述第二复位电路与所述第二发光控制电路及所述发光元件连接于第四节点；所述第三节点被所述第一复位电路复位后的电位大于所述第四节点被所述第二复位电路复位后的电位。
例如，在本公开一实施例提供的像素电路中，所述第二复位电路包括第 二复位晶体管，所述第二复位晶体管的栅极与第二复位线连接以接收所述第二复位信号，所述第二复位晶体管的第一极与第二复位电压线连接以接收所述第二复位电压，所述第二复位晶体管的第二极与所述第二发光控制晶体管的第二极和所述发光元件连接。
例如，本公开一实施例提供的像素电路还包括第三复位电路，其中，所述第三复位电路与所述阈值补偿电路和所述驱动电路的控制端连接，所述第三复位电路配置为响应于第三复位信号将第三复位电压施加至所述驱动电路的控制端；所述第一节点被所述第三复位电路复位后的电位小于所述第三节点被所述第一复位电路复位后的电位；所述第一节点被所述第三复位电路复位后的电位小于或等于所述第四节点被所述第二复位电路复位后的电位。
例如，在本公开一实施例提供的像素电路中，所述第三复位电路包括第三复位晶体管，所述第三复位晶体管的栅极与第三复位线连接以接收所述第三复位信号，所述第三复位晶体管的第一极与第三复位电压线连接以接收所述第三复位电压，所述第三复位晶体管的第二极与所述驱动电路的控制端连接。
例如，本公开一实施例提供的像素电路还包括第四复位电路，其中，所述第四复位电路与所述驱动电路的第一端连接，所述第四复位电路配置为响应于第四复位信号将第四复位电压施加至所述驱动电路的第一端；所述第二节点被所述第四复位电路复位后的电位大于所述第一节点被所述第三复位电路复位后的电位；所述第二节点被所述第四复位电路复位后的电位大于所述第三节点被所述第一复位电路复位后的电位；所述第二节点被所述第四复位电路复位后的电位大于所述第四节点被所述第二复位电路复位后的电位。
例如，在本公开一实施例提供的像素电路中，所述第四复位电路包括第四复位晶体管，所述第四复位晶体管的栅极与第四复位线连接以接收所述第四复位信号，所述第四复位晶体管的第一极与第四复位电压线连接以接收所述第四复位电压，所述第四复位晶体管的第二极与所述驱动电路的第一端连接。
本公开至少一个实施例还提供一种显示面板，包括多个像素单元，其中，每个像素单元包括本公开任一实施例提供的像素电路。
本公开至少一个实施例还提供一种显示装置，包括本公开任一实施例提供的显示面板。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1A为一种2T1C像素电路的示意图；
图1B为另一种2T1C像素电路的示意图；
图2为本公开一些实施例提供的一种像素电路的示意框图；
图3为本公开一些实施例提供的另一种像素电路的示意框图；
图4为本公开一些实施例提供的另一种像素电路的示意框图；
图5为本公开一些实施例提供的另一种像素电路的示意框图；
图6为本公开一些实施例提供的一种像素电路的驱动方法的流程示意图；
图7为图2所示的像素电路的电路结构示意图；
图8为本公开一些实施例提供的用于图7所示的像素电路的一种时序图；
图9为本公开一些实施例提供的第一电压的时序图；
图10为本公开一些实施例提供的用于图7所示的像素电路的另一种时序图；
图11为本公开一些实施例提供的用于图7所示的像素电路的另一种时序图；
图12为图5所示的像素电路的电路结构示意图；
图13为本公开一些实施例提供的用于图12所示的像素电路的一种时序图；
图14为本公开一些实施例提供的用于图12所示的像素电路的另一种时序图；
图15为本公开一些实施例提供的用于图12所示的像素电路的另一种时序图；
图16为本公开一些实施例提供的用于图12所示的像素电路的另一种时序图；
图17为图3所示的像素电路的电路结构示意图；
图18为本公开一些实施例提供的用于图17所示的像素电路的一种时序 图；
图19为本公开一些实施例提供的用于图17所示的像素电路的另一种时序图；
图20为本公开一些实施例提供的用于图17所示的像素电路的另一种时序图；
图21为图4所示的像素电路的电路结构示意图；
图22为本公开一些实施例提供的用于图21所示的像素电路的一种时序图；
图23为本公开一些实施例提供的一种像素电路的电路结构示意图；
图24为本公开一些实施例提供的用于图23所示的像素电路的一种时序图；
图25为本公开一些实施例提供的一种显示面板的示意框图；以及
图26为本公开一些实施例提供的一种显示装置的示意框图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
AMOLED显示装置中使用的基础像素电路通常为2T1C像素电路，即利用两个薄膜晶体管(Thin-film Transistor，TFT)和一个存储电容Cs来实现驱动OLED发光的基本功能。图1A和图1B分别为示出了两种2T1C像素电路的示意图。
如图1A所示，一种2T1C像素电路包括开关晶体管T0、驱动晶体管N0以及存储电容Cs。例如，该开关晶体管T0的栅极连接扫描线以接收扫描信号Scan1，例如源极连接到数据线以接收数据信号Vdata，漏极连接到驱动晶体管N0的栅极。驱动晶体管N0的源极连接到第一电压端以接收第一电压Vdd(例如高电压)，漏极连接到OLED的阳极。存储电容Cs的一端连接到开关晶体管T0的漏极以及驱动晶体管N0的栅极，另一端连接到驱动晶体管N0的源极以及第一电压端。OLED的阴极连接到第二电压端以接收第二电压Vss(低电压，例如接地电压)。
该2T1C像素电路的驱动方式是将像素的明暗(灰阶)经由两个TFT和存储电容Cs来控制。当通过扫描线施加扫描信号Scan1以开启开关晶体管T0时，数据驱动电路通过数据线送入的数据信号Vdata将经由开关晶体管T0对存储电容Cs充电，由此将数据信号Vdata存储在存储电容Cs中，且此存储的数据信号Vdata控制驱动晶体管N0的导通程度，由此控制流过驱动晶体管以驱动OLED发光的电流大小，即此电流决定该像素发光的灰阶。在图1A所示的2T1C像素电路中，开关晶体管T0为N型晶体管而驱动晶体管N0为P型晶体管。
如图1B所示，另一种2T1C像素电路也包括开关晶体管T0、驱动晶体管N0以及存储电容Cs，但是其连接方式略有改变，且驱动晶体管N0为N型晶体管。图1B的像素电路相对于图1A的变化之处包括：OLED的阳极连接到第一电压端以接收第一电压Vdd(例如高电压)，而阴极连接到驱动晶体管N0的漏极，驱动晶体管N0的源极连接到第二电压端以接收第二电压Vss(低电压，例如接地电压)。存储电容Cs的一端连接到开关晶体管T0的漏极以及驱动晶体管N0的栅极，另一端连接到驱动晶体管N0的源极以及第二电压端。该2T1C像素电路的工作方式与图1A所示的像素电路基本相同，这里不再赘述。
此外，对于图1A和图1B所示的像素电路，开关晶体管T0不限于N型晶体管，也可以为P型晶体管，由此控制其导通或截止的扫描信号Scan1的 极性进行相应地改变即可。
OLED显示装置通常包括多个按阵列排布的像素单元，每个像素单元例如可以包括上述像素电路。在OLED显示装置中，各个像素电路中的驱动晶体管的阈值电压由于制备工艺可能存在差异，而且由于例如温度变化的影响，驱动晶体管的阈值电压可能会产生漂移现象。因此，各个驱动晶体管的阈值电压的不同可能会导致显示不良(例如显示不均匀)，所以就需要对阈值电压进行补偿。同时，在晶体管处于关闭状态时，由于泄露电流的存在，也可能会导致显示不良。
因此，业界还在上述2T1C的基本像素电路的基础上提供了其他具有补偿功能的像素电路，补偿功能可以通过电压补偿、电流补偿或混合补偿来实现，具有补偿功能的像素电路例如可以为4T1C或4T2C等，这里不再详述。
对于目前的像素电路，尤其是应用在显示屏(例如手机、手表等)中的像素电路，在其工作过程中，在写数据之前和发光之前，由于存在残余电荷，这些残余电荷会对电路性能产生影响，进而会影响写入数据的精确度，并且影响发光阶段发光器件阳极的电位，特别是在改变频率后，这种不利影响更为明显。
本公开至少一个实施例提供一种像素电路及其驱动方法、显示面板、显示装置。利用该像素电路的驱动方法，可以降低或消除残余电荷对写入数据的精确度和发光阶段发光器件阳极的电位的影响，实现显示效果的优化。
下面，将参考附图详细地说明本公开的实施例。应当注意的是，不同的附图中相同的附图标记将用于指代已描述的相同的元件。
本公开至少一个实施例提供一种像素电路的驱动方法。像素电路包括驱动电路、数据写入电路、阈值补偿电路、存储电路、第一发光控制电路和第一复位电路。驱动电路包括控制端、第一端和第二端，且配置为控制流经发光元件的驱动电流；数据写入电路与驱动电路的第一端连接，且配置为响应于第一扫描信号将数据信号写入驱动电路的第一端；阈值补偿电路连接在驱动电路的控制端和驱动电路的第二端之间，且配置为响应于第二扫描信号将基于数据信号的补偿信号写入驱动电路的控制端；存储电路与驱动电路的控制端和第一电压线连接，且配置为存储补偿信号并将补偿信号保持在驱动电路的控制端；第一发光控制电路与第一电压线和驱动电路的第一端连接，且配置为响应于第一发光控制信号将第一电压线提供的第一电压施加至驱动电 路的第一端；第一复位电路与阈值补偿电路连接，且配置为响应于第一复位信号将第一复位电压施加至驱动电路的控制端。驱动电路的控制端与存储电路连接于第一节点，第一发光控制电路与驱动电路的第一端连接于第二节点。该像素电路的驱动方法包括：在数据写入阶段之前，第一复位电路响应于第一复位信号导通，以将第一复位电压施加至驱动电路的控制端，从而对第一节点进行复位，并且，第一发光控制电路响应于第一发光控制信号导通，以将第一电压施加至驱动电路的第一端，从而对第二节点进行复位；在数据写入阶段，数据写入电路响应于第一扫描信号导通，以将数据信号写入驱动电路的第一端；在发光阶段，第一发光控制电路响应于第一发光控制信号导通，发光元件根据驱动电流发光。
图2为本公开一些实施例提供的一种像素电路的示意框图，本公开实施例提供的驱动方法可以驱动图2所示的像素电路。
如图2所示，像素电路10包括驱动电路110、数据写入电路120、阈值补偿电路130、存储电路140、第一发光控制电路150和第一复位电路160。
例如，驱动电路110包括第一端111、第二端112和控制端113，驱动电路110配置为控制流经发光元件170的驱动电流。例如，在发光阶段，驱动电路110可以向发光元件170提供驱动电流以驱动发光元件170发光，且可以根据需要的“灰度”发光。例如，发光元件170可以采用任意类型的适用的器件，其可以包括多种结构，这可以根据实际需要选择设置，本公开的实施例对此不作限制。例如，发光元件170可以为OLED、量子点发光二极管(Quantum Dot Light Emitting Diode，QLED)或微发光二极管(Micro Light Emitting Diode，Micro LED)等，这可以根据实际需求而定。
数据写入电路120与驱动电路110的第一端111连接，且配置为响应于第一扫描信号将数据信号写入驱动电路110的第一端111。例如，数据写入电路120与第一扫描线SC1和数据线Vdata连接，第一扫描线SC1用于提供第一扫描信号，数据线Vdata用于提供数据信号。在数据写入阶段，数据写入电路120响应于第一扫描线SC1提供的第一扫描信号而开启，从而将数据线Vdata提供的数据信号写入驱动电路110的第一端111。数据信号进一步通过驱动电路110和阈值补偿电路130被写入驱动电路110的控制端113，并被存储在存储电路140中，以在发光阶段时根据该数据信号生成驱动发光元件170发光的驱动电流。
阈值补偿电路130连接在驱动电路110的控制端113和驱动电路110的第二端112之间，且配置为响应于第二扫描信号将基于数据信号的补偿信号写入驱动电路110的控制端113。例如，阈值补偿电路130可以直接与驱动电路110的控制端113和第二端112连接，也即，直接连接在驱动电路110的控制端113和第二端112之间。当然，阈值补偿电路130也可以间接连接在驱动电路110的控制端113和第二端112之间，也即，在阈值补偿电路130与驱动电路110的控制端113之间、在阈值补偿电路130与驱动电路110的第二端112之间也可以设置有其他电路(例如后文描述的防漏电电路230)，本公开的实施例对此不作限制。
例如，阈值补偿电路130与第二扫描线SC2连接，第二扫描线SC2用于提供第二扫描信号。当第一扫描线SC1提供的第一扫描信号、第二扫描线SC2提供的第二扫描信号均为有效电平时，数据写入电路120和阈值补偿电路130均开启，此时驱动电路110也开启，数据信号经由数据写入电路120、驱动电路110传输至阈值补偿电路130，阈值补偿电路130基于数据信号而产生补偿信号，并将补偿信号写入驱动电路110的控制端113。例如，在数据写入阶段，阈值补偿电路130可以将驱动电路110的控制端113和第二端112电连接，从而使驱动电路110的阈值电压的相关信息也相应地存储在存储电路140中，从而在发光阶段可以利用存储的包括数据信号以及阈值电压的电压对驱动电路110进行控制，使得驱动电路110可以得到补偿。
存储电路140与驱动电路110的控制端113和第一电压线VDD连接，且配置为存储补偿信号并将补偿信号保持在驱动电路110的控制端113。
第一发光控制电路150与第一电压线VDD和驱动电路110的第一端111连接，且配置为响应于第一发光控制信号将第一电压线VDD提供的第一电压施加至驱动电路110的第一端111。例如，第一发光控制电路150与第一发光控制线EM1连接，第一发光控制线EM1用于提供第一发光控制信号。第一发光控制电路150可以响应于第一发光控制信号而开启，使驱动电路110的第一端111与第一电压线VDD电连接，从而将第一电压线VDD提供的第一电压施加至驱动电路110的第一端111。
第一复位电路160与阈值补偿电路130连接，且配置为响应于第一复位信号将第一复位电压施加至驱动电路110的控制端113。例如，第一复位电路160与第一复位线RST1、第一复位电压线VR1连接，第一复位线RST1 用于提供第一复位信号，第一复位电压线VR1用于提供第一复位电压。第一复位电路160可以响应于第一复位信号而开启，从而将第一复位电压传输至驱动电路110的第二端112，第一复位电压进一步通过阈值补偿电路130传输至驱动电路110的控制端113，从而实现对驱动电路110的控制端113的复位。
发光元件170的阳极接收驱动电路110提供的驱动电流，发光元件170的阴极连接至第二电压线VSS，第二电压线VSS用于提供第二电压。
需要说明的是，出于描述的目的，本公开的各实施例中的第一电压线VDD例如保持输入直流高电平信号，将该直流高电平称为第一电压；第二电压线VSS例如保持输入直流低电平信号，将该直流低电平称为第二电压(可为接地电压)，且低于第一电压。以下各实施例与此相同，不再赘述。
例如，在一些示例中，像素电路10还包括第二发光控制电路180和第二复位电路190。
第二发光控制电路180与驱动电路110的第二端112和发光元件170连接，且配置为响应于第二发光控制信号将驱动电路110的第二端112的电压施加至发光元件170。例如，第二发光控制电路180与第二发光控制线EM2连接，第二发光控制线EM2用于提供第二发光控制信号。第二发光控制电路180可以响应于第二发光控制信号而开启，使驱动电路110的第二端112与发光元件170(例如发光元件170的阳极)电连接，从而将驱动电路110的第二端112的电压施加至发光元件170。
第二复位电路190与第二发光控制电路180和发光元件170连接，且配置为响应于第二复位信号将第二复位电压施加至发光元件170(例如发光元件170的阳极)。例如，第二复位电路190与第二复位线RST2、第二复位电压线VR2连接，第二复位线RST2用于提供第二复位信号，第二复位电压线VR2用于提供第二复位电压。第二复位电路190可以响应于第二复位信号而开启，从而将第二复位电压传输至第二发光控制电路180与发光元件170的连接处，从而实现对发光元件170的复位。
例如，驱动电路110的控制端113与存储电路140连接于第一节点P1，第一发光控制电路150与驱动电路110的第一端111连接于第二节点P2，第二发光控制电路180与驱动电路110的第二端112连接于第三节点P3，第二复位电路190与第二发光控制电路180及发光元件170连接于第四节点P4。 例如，第三节点P3被第一复位电路160复位后的电位大于第四节点P4被第二复位电路190复位后的电位。由此可以取得较好的复位效果，更好地降低或消除残余电荷对发光阶段发光器件阳极的电位的影响。
图3为本公开一些实施例提供的另一种像素电路的示意框图，本公开实施例提供的驱动方法可以驱动图3所示的像素电路。
如图3所示，在一些示例中，像素电路10还可以包括第三复位电路210。第三复位电路210与阈值补偿电路130和驱动电路110的控制端113连接，第三复位电路210配置为响应于第三复位信号将第三复位电压施加至驱动电路110的控制端113。例如，第三复位电路210与第三复位线RST3、第三复位电压线VR3连接，第三复位线RST3用于提供第三复位信号，第三复位电压线VR3用于提供第三复位电压。第三复位电路210可以响应于第三复位信号而开启，从而将第三复位电压传输至驱动电路110的控制端113，从而实现对驱动电路110的控制端113的复位。该像素电路10的其他部分与图2所示的像素电路10基本相同，此处不再赘述。
例如，在该示例中，第三节点P3被第一复位电路160复位后的电位大于第四节点P4被第二复位电路190复位后的电位；第一节点P1被第三复位电路210复位后的电位小于第三节点P3被第一复位电路160复位后的电位；第一节点P1被第三复位电路210复位后的电位小于或等于第四节点P4被第二复位电路190复位后的电位。由此可以取得较好的复位效果，更好地降低或消除残余电荷对写入数据的精确度和发光阶段发光器件阳极的电位的影响。
图4为本公开一些实施例提供的另一种像素电路的示意框图，本公开实施例提供的驱动方法可以驱动图4所示的像素电路。
如图4所示，在一些示例中，像素电路10还可以包括第四复位电路220。第四复位电路220与驱动电路110的第一端111连接，第四复位电路220配置为响应于第四复位信号将第四复位电压施加至驱动电路110的第一端111。例如，第四复位电路220与第四复位线RST4、第四复位电压线VR4连接，第四复位线RST4用于提供第四复位信号，第四复位电压线VR4用于提供第四复位电压。第四复位电路220可以响应于第四复位信号而开启，从而将第四复位电压传输至驱动电路110的第一端111，从而实现对驱动电路110的第一端111的复位。该像素电路10的其他部分与图3所示的像素电路10基 本相同，此处不再赘述。
例如，在该示例中，第三节点P3被第一复位电路160复位后的电位大于第四节点P4被第二复位电路190复位后的电位；第一节点P1被第三复位电路210复位后的电位小于第三节点P3被第一复位电路160复位后的电位；第一节点P1被第三复位电路210复位后的电位小于或等于第四节点P4被第二复位电路190复位后的电位；第二节点P2被第四复位电路220复位后的电位大于第一节点P1被第三复位电路210复位后的电位；第二节点P2被第四复位电路220复位后的电位大于第三节点P3被第一复位电路160复位后的电位；第二节点P2被第四复位电路220复位后的电位大于第四节点P4被第二复位电路190复位后的电位。由此可以取得较好的复位效果，更好地降低或消除残余电荷对写入数据的精确度和发光阶段发光器件阳极的电位的影响。
图5为本公开一些实施例提供的另一种像素电路的示意框图，本公开实施例提供的驱动方法可以驱动图5所示的像素电路。
如图5所示，在一些示例中，像素电路10还可以包括防漏电电路230。防漏电电路230与驱动电路110的控制端113、阈值补偿电路130和存储电路140连接，防漏电电路230配置为抑制驱动电路110的控制端113的漏电。防漏电电路230还与第三扫描线SC3连接，第三扫描线SC3用于提供第三扫描信号。防漏电电路230可以响应于第三扫描信号而开启，从而便于所需要的电信号传输至驱动电路110的控制端113。在该示例中，第一复位电路160与阈值补偿电路130和防漏电电路230连接，可以通过导通的防漏电电路230将第一复位电压施加至第一节点P1，也可以通过导通的阈值补偿电路130将第一复位电压施加至第三节点P3。该像素电路10的其他部分与图2所示的像素电路10基本相同，此处不再赘述。
图6为本公开一些实施例提供的一种像素电路的驱动方法的流程示意图，该驱动方法例如可以用于图2、图3、图4、图5所示的像素电路10。如图6所示，本公开实施例提供的驱动方法可以包括如下操作。
步骤S10：在数据写入阶段之前，第一复位电路响应于第一复位信号导通，以将第一复位电压施加至驱动电路的控制端，从而对第一节点进行复位，并且，第一发光控制电路响应于第一发光控制信号导通，以将第一电压施加至驱动电路的第一端，从而对第二节点进行复位；
步骤S20：在数据写入阶段，数据写入电路响应于第一扫描信号导通，以将数据信号写入驱动电路的第一端；
步骤S30：在发光阶段，第一发光控制电路响应于第一发光控制信号导通，发光元件根据驱动电流发光。
例如，对于图2、图3、图4所示的像素电路10，步骤S10中对第一节点的复位操作可以包括：第一复位电路160响应于第一复位信号导通，阈值补偿电路130响应于第二扫描信号导通，以将第一复位电压通过第一复位电路160和阈值补偿电路130形成的通路施加至驱动电路110的控制端113，从而对第一节点P1进行复位。例如，在数据写入阶段之前，第一复位电路160响应于第一复位信号导通，此时阈值补偿电路130响应于第二扫描信号导通，从而将第一复位电压施加至驱动电路110的控制端113，也即施加至第一节点P1，由此对第一节点P1进行复位。并且，第一发光控制电路150响应于第一发光控制信号导通，以将第一电压施加至驱动电路110的第一端111，也即施加至第二节点P2，从而对第二节点P2进行复位。
例如，在步骤S10中，对于图5所示的像素电路10，在数据写入阶段之前，第一复位电路160响应于第一复位信号导通，此时防漏电电路230响应于第三扫描信号导通，从而将第一复位电压施加至驱动电路110的控制端113，也即施加至第一节点P1，由此对第一节点P1进行复位。并且，第一发光控制电路150响应于第一发光控制信号导通，以将第一电压施加至驱动电路110的第一端111，也即施加至第二节点P2，从而对第二节点P2进行复位。
例如，在步骤S20中，在数据写入阶段，数据写入电路120响应于第一扫描信号导通，以将数据信号写入驱动电路110的第一端111，也即写入第二节点P2。此时，驱动电路110和阈值补偿电路130也导通。对于图5所示的像素电路10，防漏电电路230也导通。由此，数据信号可以从第二节点P2被写入到驱动电路110的控制端113，也即被写入第一节点P1，由此存储在存储电路140中。在该过程中，驱动电路110的阈值电压的相关信息也相应地存储在存储电路140中，从而在发光阶段可以利用存储的包括数据信号以及阈值电压的电压对驱动电路110进行控制，使得驱动电路110可以得到补偿。
例如，在步骤S30中，在发光阶段，第一发光控制电路150响应于第一 发光控制信号导通，发光元件170根据驱动电流发光。此时，第二发光控制电路180也导通，从而在第一电压线VDD与第二电压线VSS之前形成电流通路，驱动电路110控制驱动电流的大小，使得发光元件170根据需要的“灰阶”发光。
例如，本公开实施例提供的驱动方法还可以进一步包括如下操作：
在数据写入阶段之前，在第一复位电路对第一节点进行复位的同时，第一复位电路将第一复位电压施加至驱动电路的第二端，从而对第三节点进行复位；和/或
在数据写入阶段之前，第二复位电路响应于第二复位信号导通，以将第二复位电压施加至发光元件，从而对第四节点进行复位。
例如，对于图2、图3、图4所示的像素电路10，在数据写入阶段之前，在利用第一复位电路160对第一节点P1进行复位的同时，第一复位电压首先会被写入驱动电路110的第二端112(也即第三节点P3)，从而可以对第三节点P3进行复位。
例如，对于图5所示的像素电路10，在数据写入阶段之前，在利用第一复位电路160对第一节点P1进行复位的同时，可以使阈值补偿电路130开启，由此使得第一复位电路160传输的第一复位电压可以通过阈值补偿电路130而被传输至第三节点P3，由此实现对第三节点P3的复位。
例如，在数据写入阶段之前，第二复位电路190响应于第二复位信号导通，以将第二复位电压施加至发光元件170(例如发光元件170的阳极)，从而对第四节点P4进行复位。
例如，在一些示例中，在数据写入阶段之前，第一节点P1和第二节点P2同时进行复位，或者第一节点P1和第二节点P2在不同的时段分别进行复位。也即是，可以同时对第一节点P1和第二节点P2进行复位，也可以按照先后顺序对第一节点P1和第二节点P2进行复位，可以先复位第一节点P1、再复位第二节点P2，也可以先复位第二节点P2、再复位第一节点P1。
例如，在一些示例中，在数据写入阶段之前，在第三节点P3和第四节点P4均进行复位的情形，第三节点P3和第四节点P4同时进行复位或者在不同的时段分别进行复位。也即是，可以同时对第三节点P3和第四节点P4进行复位，也可以按照先后顺序对第三节点P3和第四节点P4进行复位，可以先复位第三节点P3、再复位第四节点P4，也可以先复位第四节点P4、再 复位第三节点P3。
例如，在一些示例中，在数据写入阶段之前，第三节点P3和第四节点P4至少之一的复位时段与第一节点P1和第二节点P2至少之一的复位时段重合。也即是，第三节点P3和第四节点P4中的至少一个节点与第一节点P1和第二节点P2中的至少一个节点同时复位。
例如，在一些示例中，在数据写入阶段之前，第一节点P1的复位时段、第二节点P2的复位时段、第三节点P3的复位时段、第四节点P4的复位时段均不重合。也即是，每个节点的复位时段均不与其他节点的复位时段重合，在每个复位时段中仅有一个节点被复位。需要说明的是，复位时段是指对节点进行复位的时段，复位时段可以是持续的一段时间，也可以是一个短暂的时间点，这可以根据复位操作所需要的时长而定，本公开的实施例对此不作限制。
例如，本公开实施例提供的驱动方法还可以进一步包括如下操作：
在数据写入阶段之后、发光阶段之前，第一发光控制电路响应于第一发光控制信号导通，以将第一电压施加至驱动电路的第一端，从而对第二节点进行复位；和/或
在数据写入阶段之后、发光阶段之前，第一复位电路响应于第一复位信号导通，以将第一复位电压施加至驱动电路的第二端，从而对第三节点进行复位；和/或
在数据写入阶段之后、发光阶段之前，第二复位电路响应于第二复位信号导通，以将第二复位电压施加至发光元件，从而对第四节点进行复位。
例如，对于图2、图3、图4、图5所示的像素电路10，在数据写入阶段之后、发光阶段之前，第一发光控制电路150响应于第一发光控制信号导通，以将第一电压施加至驱动电路110的第一端111，也即施加至第二节点P2，从而对第二节点P2进行复位。
例如，对于图2、图3、图4所示的像素电路10，在数据写入阶段之后、发光阶段之前，第一复位电路160响应于第一复位信号导通，以将第一复位电压施加至驱动电路110的第二端112，也即施加至第三节点P3，从而对第三节点P3进行复位。
例如，对于图5所示的像素电路10，在数据写入阶段之后、发光阶段之前，在第一复位电路160导通的同时，使阈值补偿电路130也导通，从而可 以将第一复位电压经由阈值补偿电路130施加至第三节点P3，以对第三节点P3进行复位。
例如，在数据写入阶段之后、发光阶段之前，第二复位电路190响应于第二复位信号导通，以将第二复位电压施加至发光元件170(例如发光元件170的阳极)，也即是，施加至第四节点P4，从而对第四节点P4进行复位。
例如，在一些示例中，在数据写入阶段之后、发光阶段之前，第二节点P2、第三节点P3、第四节点P4中至少两个节点同时进行复位，或者第二节点P2、第三节点P3、第四节点P4中至少两个节点在不同的时段分别进行复位。也即是，可以在三个不同的复位时段分别对第二节点P2、第三节点P3、第四节点P4分别单独进行复位；也可以对第二节点P2、第三节点P3、第四节点P4中任意两个节点同时进行复位，对余下的另一节点在不同的时段进行复位；也可以在同一时段对第二节点P2、第三节点P3、第四节点P4这三个节点进行同时复位。这可以根据实际需求而定，本公开的实施例对此不作限制。
在本公开实施例提供的驱动方法中，在数据写入阶段之前，可以对第一节点P1、第二节点P2、第三节点P3、第四节点P4中的任意一个节点或多个节点进行复位。对于需要进行复位的节点，可以同时进行复位，也可以使各个节点的复位时段彼此错开。由此，可以在写数据之前，对OLED的阳极和/或驱动晶体管的源极、漏极、栅极中的一个或多个进行初始化或者复位的操作，通过对数据写入路径上的节点进行复位，可以使残余电荷导致的不良影响降低或者消除，实现显示效果的优化。
在本公开实施例提供的驱动方法中，在数据写入阶段之后、发光阶段之前，可以对第二节点P2、第三节点P3、第四节点P4中的任意一个节点或多个节点进行复位。对于需要进行复位的节点，可以同时进行复位，也可以使各个节点的复位时段彼此错开。由此，可以在写数据之后、发光之前，对OLED的阳极和/或驱动晶体管的源极、漏极中的一个或多个进行初始化或者复位的操作，通过对发光路径上的节点进行复位，可以使残余电荷导致的不良影响降低或者消除，实现显示效果的优化。
在本公开实施例提供的驱动方法中，在数据写入阶段之前需要进行复位的节点与在数据写入阶段之后及发光阶段之前需要进行复位的节点可以相同或不同，在数据写入阶段之前的复位操作与在数据写入阶段之后及发光阶段 之前的复位操作可以相同或不同，这可以根据实际需求而定，本公开的实施例对此不作限制。
下面结合具体的电路结构对本公开实施例提供的驱动方法进行简要说明。
图7为图2所示的像素电路的电路结构示意图。如图7所示，该像素电路10包括：晶体管M1至晶体管M7以及存储电容Cst。例如，晶体管M3被用作驱动晶体管，其他的晶体管被用作开关晶体管。发光元件170可以实现为发光元件EL，发光元件EL例如可以采用OLED，本公开的实施例包括但不限于此，以下各实施例均以OLED为例进行说明，不再赘述。该OLED可以为各种类型，例如顶发射、底发射等，可以发红光、绿光、蓝光或白光等，本公开的实施例对此不作限制。
例如，如图7所示，更详细地，驱动电路110可以实现为驱动晶体管，也即晶体管M3。驱动晶体管(晶体管M3)的栅极作为驱动电路110的控制端113，驱动晶体管(晶体管M3)的第一极作为驱动电路110的第一端111，驱动晶体管(晶体管M3)的第二极作为驱动电路110的第二端112。
数据写入电路120可以实现为数据写入晶体管，也即晶体管M4。数据写入晶体管(晶体管M4)的栅极与第一扫描线(扫描线S3)连接以接收第一扫描信号，数据写入晶体管(晶体管M4)的第一极与数据线(数据线DL)连接以接收数据信号，数据写入晶体管(晶体管M4)的第二极与驱动晶体管(晶体管M3)的第一极连接于第二节点P2。
阈值补偿电路130可以实现为阈值补偿晶体管，也即晶体管M2。阈值补偿晶体管(晶体管M2)的栅极与第二扫描线(扫描线S5)连接以接收第二扫描信号，阈值补偿晶体管(晶体管M2)的第一极与驱动晶体管(晶体管M3)的第二极连接于第三节点P3，阈值补偿晶体管(晶体管M2)的第二极与驱动晶体管(晶体管M3)的栅极连接于第一节点P1。
存储电路140可以实现为存储电容Cst，存储电容Cst的第一极与第一电压线VDD连接，存储电容Cst的第二极与驱动晶体管(晶体管M3)的栅极连接于第一节点P1。
第一发光控制电路150可以实现为第一发光控制晶体管，也即晶体管M5。第一发光控制晶体管(晶体管M5)的栅极与第一发光控制线(扫描线S1)连接以接收第一发光控制信号，第一发光控制晶体管(晶体管M5)的 第一极与第一电压线VDD连接，第一发光控制晶体管(晶体管M5)的第二极与驱动电路的第一端连接，也即与驱动晶体管(晶体管M3)的第一极连接于第二节点P2。
第一复位电路160可以实现为第一复位晶体管，也即晶体管M1。第一复位晶体管(晶体管M1)的栅极与第一复位线(扫描线S4)连接以接收第一复位信号，第一复位晶体管(晶体管M1)的第一极与第一复位电压线(电压线INIT1)连接以接收第一复位电压，第一复位晶体管(晶体管M1)的第二极与驱动晶体管(晶体管M3)的第二极连接于第三节点P3。
第二发光控制电路180可以实现为第二发光控制晶体管，也即晶体管M6。第二发光控制晶体管(晶体管M6)的栅极与第二发光控制线(扫描线S2)连接以接收第二发光控制信号，第二发光控制晶体管(晶体管M6)的第一极与驱动电路的第二端连接，也即与驱动晶体管(晶体管M3)的第二极连接于第三节点P3，第二发光控制晶体管(晶体管M6)的第二极与发光元件EL的阳极连接于第四节点P4。
第二复位电路190可以实现为第二复位晶体管，也即晶体管M7。第二复位晶体管(晶体管M7)的栅极与第二复位线(扫描线S6)连接以接收第二复位信号，第二复位晶体管(晶体管M7)的第一极与第二复位电压线(电压线INIT2)连接以接收第二复位电压，第二复位晶体管(晶体管M7)的第二极与第二发光控制晶体管(晶体管M6)的第二极和发光元件EL连接于第四节点P4。
例如，驱动晶体管(晶体管M3)、数据写入晶体管(晶体管M4)、第一发光控制晶体管(晶体管M5)、第一复位晶体管(晶体管M1)为第一类型的晶体管；阈值补偿晶体管(晶体管M2)为第二类型的晶体管；第一类型不同于第二类型。例如，在一些示例中，第一类型的晶体管包括P型薄膜晶体管，第二类型的晶体管包括N型薄膜晶体管，也即是，驱动晶体管(晶体管M3)、数据写入晶体管(晶体管M4)、第一发光控制晶体管(晶体管M5)、第一复位晶体管(晶体管M1)为P型薄膜晶体管，而阈值补偿晶体管(晶体管M2)为N型晶体管。当然，本公开的实施例不限于此，可以根据实际需要改变像素电路10所采用的某些晶体管的类型，例如将P型薄膜晶体管变更为N型薄膜晶体管，或者将N型薄膜晶体管变更为P型薄膜晶体管。
图8为本公开一些实施例提供的用于图7所示的像素电路的一种时序图。如图8所示，在一些示例中，在第一阶段T1，晶体管M5的栅极连接到扫描线S1，S1为低电位，晶体管M5导通，第一电压线VDD的高电位被写入到晶体管M3的第一极，也即写入到第二节点P2，第二节点P2的电位为V1，V1的电位可以是VDD，也可以是大于0且小于VDD，如图9所示。如果V1的电位等于VDD，则第一电压线VDD提供的电位是恒定的；如果V1的电位大于0且小于VDD，则第一电压线VDD提供的电位是变化的。晶体管M1的栅极连接到扫描线S4，S4为低电位，晶体管M1导通，晶体管M2的栅极连接到扫描线S5，S5为高电位，晶体管M2导通，电压线INIT1的低电位写入到晶体管M3的第二极(也即第三节点P3)和晶体管M3的栅极(也即第一节点P1)。晶体管M7的栅极连接到扫描线S6，S6为低电位，晶体管M7导通，电压线INIT2的低电位写入到发光元件EL的阳极(也即第四节点P4)。由此，在第一阶段T1，进行了发光元件EL的阳极以及晶体管M3的第一极、第二极、栅极的复位，消除了上一帧显示的残余电荷，有利于第二阶段T2数据写入能够准确进行。
在第二阶段T2，S3和S5分别为低电平和高电平，晶体管M4和晶体管M2导通，数据信号依次经晶体管M4、晶体管M3、晶体管M2而被写入到晶体管M3的栅极，此时第一节点P1的电位为Vdata+|Vth|。Vdata为数据信号，Vth为晶体管M3的阈值电压。在此阶段，为了确保第四节点P4在发光前能保持稳定的低电位，因此，在第二阶段T2，晶体管M7依然导通，电压线INIT2的低电位写入到第四节点P4。也即是，在第一阶段T1和第二阶段T2这两个阶段均对第四节点P4进行复位。
在第三阶段T3，S1和S2的电位为低电位，晶体管M5和晶体管M6导通，发光元件EL发光。流经晶体管M3的电流为：I＝1/2μ*W/L*Cox(Vgs-Vth)2＝1/2μ*W/L*Cox(VDD-Vdata)2。其中，W/L为晶体管M3的宽长比，Cox为晶体管M3的沟道绝缘层的介电常数，μ为晶体管M3的沟道载流子迁移率。通过仿真，得到了较好的仿真效果，其中，仿真条件为：VDD为4.6V，VSS为-3V，Vinit(也即INIT1和INIT2)为-3V，Vdata为3V，Vth为-2V。这里，较好的仿真效果是指写入数据的精确度较高，发光阶段发光器件阳极的电位几乎不受残余电荷的影响。
如图9所示，在第三阶段T3，也即在发光阶段，第一电压线VDD的电 位为VDD；在非发光阶段，包括进行复位的第一阶段T1和进行数据写入的第二阶段T2，为了节省功耗，第一电压线的电位可以降低至V1。第二节点P2的电位可以是V1，即大于0且小于等于VDD，由此可以实现复位的作用。
在该示例中，S2和S5可以为同一栅极驱动电路(例如GOA)输出的信号；S3和S4可以由同一类的GOA提供信号，例如，S3是GOA中某一级移位寄存器单元提供的信号，S4是GOA中上一级移位寄存器单元提供的信号。由此，对于一行像素电路，至少需要4个GOA，或者，GOA的一级移位寄存器单元需要输出4个移位信号(若所采用的GOA能够输出多个信号，例如一个GOA可以输出两种脉宽不同的信号或者两种电位不同的信号)。
图10为本公开一些实施例提供的用于图7所示的像素电路的另一种时序图。如图10所示，该示例与图8所示的示例相比，是在图8的复位阶段与数据写入阶段之间增加了一个时间段，用作晶体管M3的漏极和栅极(也即第三节点P3和第一节点P1)的复位。当然，为了缩短复位的时间，在其他示例中，此阶段也可以并入T1阶段。
在图10所示的示例中，在数据写入之后、发光之前对晶体管M3的源极(也即第二节点P2)和晶体管M7的漏极(也即发光元件EL的阳极)进行再次复位，即增加了T4阶段。对于第二节点P2的再次复位，是为了消除在数据写入之后第二节点P2处的残余电荷，进而消除对发光阶段流入驱动晶体管(晶体管M3)电流的影响。对于第四节点P4的再次复位，是为了消除数据写入阶段可能经过晶体管M6的漏电流在第四节点P4可能产生的残余电荷。S6的低电位控制晶体管M7导通，为了使得第四节点P4的电位在非发光阶段能长期保持INIT2的电位，可以设置S6在T1-T4的4个时间段都保持为低电位。通过仿真，得到了较好的仿真效果，其中，仿真条件为：VDD为4.6V，VSS为-3V，Vinit(也即INIT1和INIT2)为-3V，Vdata为3V。
在该示例中，S3和S4可以由同一类的GOA提供信号，例如，S3是GOA中某一级移位寄存器单元提供的信号，S4是GOA中上一级移位寄存器单元提供的信号。由此，对于一行像素电路，至少需要4个GOA，或者，GOA的一级移位寄存器单元需要输出4个移位信号(若所采用的GOA能够输出多个信号，例如一个GOA可以输出两种脉宽不同的信号或者两种电位不同的信号)。
图11为本公开一些实施例提供的用于图7所示的像素电路的另一种时序 图。如图11所示，该示例与图10所示的示例相比，相同点是：在数据写入阶段T3的前一阶段T2和后一阶段T4，对第二节点P2和第四节点P4都进行复位操作，从而确保数据能准确写入，并且，在发光之前能消除发光路径上的残余电荷。在该示例中，第一节点P1和第三节点P3的复位操作在第一阶段T1进行。
在该示例中，S1和S5可以为同一GOA输出的信号；S3和S4可以由同一类的GOA提供信号，例如，S3是GOA中某一级移位寄存器单元提供的信号，S4是GOA中上两级移位寄存器单元提供的信号。由此，对于一行像素电路，至少需要4个GOA，或者，GOA的一级移位寄存器单元需要输出4个移位信号。
图12为图5所示的像素电路的电路结构示意图。如图12所示，该像素电路10包括：晶体管M1至晶体管M8以及存储电容Cst。例如，晶体管M3被用作驱动晶体管，其他的晶体管被用作开关晶体管。发光元件170可以实现为发光元件EL，发光元件EL例如可以采用OLED，本公开的实施例包括但不限于此，以下各实施例均以OLED为例进行说明，不再赘述。该OLED可以为各种类型，例如顶发射、底发射等，可以发红光、绿光、蓝光或白光等，本公开的实施例对此不作限制。
例如，如图12所示，更详细地，驱动电路110可以实现为驱动晶体管，也即晶体管M3；数据写入电路120可以实现为数据写入晶体管，也即晶体管M4；阈值补偿电路130可以实现为阈值补偿晶体管，也即晶体管M2；存储电路140可以实现为存储电容Cst；第一发光控制电路150可以实现为第一发光控制晶体管，也即晶体管M5；第二发光控制电路180可以实现为第二发光控制晶体管，也即晶体管M6；第二复位电路190可以实现为第二复位晶体管，也即晶体管M7。这些晶体管和存储电容的连接方式与图7所示的电路结构类似，此处不再赘述。
该示例与图7所示的电路结构的不同点在于：第一复位电路160的连接方式不同，并且还包括防漏电电路230。例如，第一复位电路160可以实现为第一复位晶体管，也即晶体管M1。第一复位晶体管(晶体管M1)的栅极连接第一复位线(扫描线S4)，第一复位晶体管(晶体管M1)的第一极连接第一复位电压线(电压线INIT1)，第一复位晶体管(晶体管M1)的第二极连接晶体管M2的第二极。防漏电电路230可以实现为防漏电晶体管，也 即晶体管M8。防漏电晶体管(晶体管M8)的栅极与第三扫描线(扫描线S7)连接，防漏电晶体管(晶体管M8)的第一极与晶体管M2的第二极连接，防漏电晶体管(晶体管M8)的第二极与晶体管M3的栅极连接于第一节点P1。例如，防漏电晶体管为第二类型的晶体管，例如为N型薄膜晶体管。
图13为本公开一些实施例提供的用于图12所示的像素电路的一种时序图。如图13所示，在一些示例中，与前述示例采用图7所示的电路结构相比，该示例采用的像素电路10中包含两个N型薄膜晶体管(晶体管M8和晶体管M2)，因此能够在容易漏电的第一节点P1起到更好的防漏电作用。并且，两个N型薄膜晶体管M2和M8可以增强操作的灵活性，例如需要仅复位第一节点P1时，将晶体管M8导通即可。
如图13所示，在第一阶段T1，S7控制的晶体管M8导通，S4控制的晶体管M1导通，第一节点P1写入INIT1的复位电压，对晶体管M3的栅极进行复位，也即对第一节点P1进行复位。S1控制的晶体管M5导通，S6控制的晶体管M7导通，VDD的高电位写入到第二节点P2，从而对第二节点P2复位，INIT2的电位写入到发光元件EL的阳极，从而对第四节点P4进行复位。
在第二阶段T2，进行写数据操作。S3控制的晶体管M4导通，S5控制的晶体管M2导通，将数据信号写入到晶体管M3的栅极(也即第一节点P1)，此时第一节点P1的电位为Vdata+|Vth|。同时，S6控制的晶体管M7依然保持导通，使得第四节点P4的电位为INIT2。
在第三阶段T3，S1和S2的电位为低，晶体管M5和晶体管M6导通，因此发光元件EL发光。
图14为本公开一些实施例提供的用于图12所示的像素电路的另一种时序图。如图14所示，该示例与图13所示的示例相比，区别在于写数据前的复位操作分两个阶段进行，也即是，在第一阶段T1对第二节点P2和第四节点P4进行复位，在第二阶段T2对第一节点P1进行复位。为了缩短时间，在其他示例中，也可以将本示例中的T1和T2阶段合并在一个阶段进行。在写数据之后，对第二节点P2和第四节点P4再次进行复位，以消除发光路径上的残余电荷，然后再进入发光阶段。
在该示例中，S7和S1可以为同一GOA输出的信号；S3和S4可以由同 一类的GOA提供信号，例如，S3是GOA中某一级移位寄存器单元提供的信号，S4是GOA中上一级移位寄存器单元提供的信号。由此，对于一行像素电路，至少需要5个GOA，或者，GOA的一级移位寄存器单元需要输出5个移位信号。
图15为本公开一些实施例提供的用于图12所示的像素电路的另一种时序图。如图15所示，在该示例中，在数据写入阶段(第三阶段T3)的前一阶段T2和后一阶段T4，对第二节点P2和第四节点P4都进行复位操作。对第一节点P1的复位操作在第一阶段T1进行。关于复位操作时各个晶体管的导通情况可以参考上文内容，此处不再赘述。
图16为本公开一些实施例提供的用于图12所示的像素电路的另一种时序图。如图16所示，在该示例中，在写数据前的两个阶段中进行复位操作。具体地，在第一阶段T1对第一节点P1和第三节点P3进行复位，在第二阶段T2对第二节点P2和第四节点P4进行复位。在写数据之后，对第二节点P2、第三节点P3、第四节点P4进行复位，第二节点P2的电位为VDD，第三节点P3的电位为INIT1，第四节点P4的电位为INIT2。关于复位操作时各个晶体管的导通情况可以参考上文内容，此处不再赘述。
图17为图3所示的像素电路的电路结构示意图。如图17所示，该像素电路10包括：晶体管M1至晶体管M8以及存储电容Cst。例如，晶体管M3被用作驱动晶体管，其他的晶体管被用作开关晶体管。发光元件170可以实现为发光元件EL，发光元件EL例如可以采用OLED，本公开的实施例包括但不限于此，以下各实施例均以OLED为例进行说明，不再赘述。该OLED可以为各种类型，例如顶发射、底发射等，可以发红光、绿光、蓝光或白光等，本公开的实施例对此不作限制。
例如，如图17所示，更详细地，驱动电路110可以实现为驱动晶体管，也即晶体管M3；数据写入电路120可以实现为数据写入晶体管，也即晶体管M4；阈值补偿电路130可以实现为阈值补偿晶体管，也即晶体管M2；存储电路140可以实现为存储电容Cst；第一发光控制电路150可以实现为第一发光控制晶体管，也即晶体管M5；第二发光控制电路180可以实现为第二发光控制晶体管，也即晶体管M6；第一复位电路160可以实现为第一复位晶体管，也即晶体管M1；第二复位电路190可以实现为第二复位晶体管，也即晶体管M7。这些晶体管和存储电容的连接方式与图7所示的电路结构 类似，此处不再赘述。
该示例与图7所示的电路结构的不同点在于：还包括第三复位电路210。例如，第三复位电路210可以实现为第三复位晶体管，也即晶体管M8。第三复位晶体管(晶体管M8)的栅极连接第三复位线(扫描线S7)以接收第三复位信号，第三复位晶体管(晶体管M8)的第一极连接第三复位电压线(电压线INIT1)以接收第三复位电压，第三复位晶体管(晶体管M8)的第二极与驱动电路110的控制端113连接，也即与晶体管M3的栅极连接于第一节点P1。例如，第三复位晶体管为第二类型的晶体管，例如为N型薄膜晶体管。
图18为本公开一些实施例提供的用于图17所示的像素电路的一种时序图。如图18所示，在该示例中，晶体管M1用作给晶体管M3的漏极(也即第三节点P3)复位。在第一阶段T1，对第一节点P1、第二节点P2、第三节点P3、第四节点P4进行复位。然后，在第二阶段T2，进行数据写入操作。在第三阶段T3，通过导通的晶体管M5对第二节点P2进行复位，通过导通的晶体管M1对第三节点P3进行复位，通过导通的晶体管M7对第四节点P4进行复位。在第四阶段T4，发光元件EL发光。关于复位操作时各个晶体管的导通情况可以参考上文内容，此处不再赘述。
图19为本公开一些实施例提供的用于图17所示的像素电路的另一种时序图。如图19所示，在该示例中，在第一阶段T1，对第一节点P1、第二节点P2、第四节点P4进行复位；在第二阶段T2，对第一节点P1、第三节点P3、第四节点P4进行复位。例如，可以通过导通的晶体管M5对第二节点P2进行复位，通过导通的晶体管M1对第三节点P3进行复位，通过导通的晶体管M7对第四节点P4进行复位，通过导通的晶体管M8对第一节点P1进行复位。在第三阶段T3，进行数据写入操作。然后，在第四阶段T4，发光元件EL发光。关于复位操作时各个晶体管的导通情况可以参考上文内容，此处不再赘述。
图20为本公开一些实施例提供的用于图17所示的像素电路的另一种时序图。如图20所示，在该示例中，在第一阶段T1，对第一节点P1、第二节点P2、第四节点P4进行复位；在第二阶段T2，对第一节点P1、第三节点P3、第四节点P4进行复位。在第三阶段T3，进行数据写入操作。在第四阶段T4，对第三节点P3和第四节点P4进行复位。在第五阶段T5，发光元件 EL发光。关于复位操作时各个晶体管的导通情况可以参考上文内容，此处不再赘述。
图21为图4所示的像素电路的电路结构示意图。如图21所示，该像素电路10包括：晶体管M1至晶体管M9以及存储电容Cst。例如，晶体管M3被用作驱动晶体管，其他的晶体管被用作开关晶体管。发光元件170可以实现为发光元件EL，发光元件EL例如可以采用OLED，本公开的实施例包括但不限于此，以下各实施例均以OLED为例进行说明，不再赘述。该OLED可以为各种类型，例如顶发射、底发射等，可以发红光、绿光、蓝光或白光等，本公开的实施例对此不作限制。
例如，如图21所示，更详细地，驱动电路110可以实现为驱动晶体管，也即晶体管M3；数据写入电路120可以实现为数据写入晶体管，也即晶体管M4；阈值补偿电路130可以实现为阈值补偿晶体管，也即晶体管M2；存储电路140可以实现为存储电容Cst；第一发光控制电路150可以实现为第一发光控制晶体管，也即晶体管M5；第二发光控制电路180可以实现为第二发光控制晶体管，也即晶体管M6；第一复位电路160可以实现为第一复位晶体管，也即晶体管M1；第二复位电路190可以实现为第二复位晶体管，也即晶体管M7；第三复位电路210可以实现为第三复位晶体管，也即晶体管M8。这些晶体管和存储电容的连接方式与图17所示的电路结构类似，此处不再赘述。
该示例与图17所示的电路结构的不同点在于：还包括第四复位电路220。例如，第四复位电路220可以实现为第四复位晶体管，也即晶体管M9。第四复位晶体管(晶体管M9)的栅极与第四复位线(扫描线S8)连接以接收第四复位信号，第四复位晶体管(晶体管M9)的第一极与第四复位电压线(电压线INIT4)连接以接收第四复位电压，第四复位晶体管(晶体管M9)的第二极与驱动电路110的第一端111连接，也即与晶体管M3的第一极连接于第二节点P2。
图22为本公开一些实施例提供的用于图21所示的像素电路的一种时序图。如图22所示，在该示例中，在第一阶段T1，通过导通的晶体管M8对第一节点P1进行复位，通过导通的晶体管M9和晶体管M7分别对第二节点P2和第四节点P4进行复位。在第二阶段T2，通过导通的晶体管M1对第三节点P3进行复位。在第三阶段T3，进行写数据操作。在第四阶段T4，再次 通过导通的晶体管M1和晶体管M7分别对第三节点P3和第四节点P4进行复位。在第五阶段T5，发光元件EL发光。关于复位操作时各个晶体管的导通情况可以参考上文内容，此处不再赘述。
对该时序进行仿真，仿真条件为：VINT4为6V，VINT1为-3V或-4V，VINT2为-3V，VINT3分别为0V、1V、2V、3V、4V。在VINT3取不同电压值时，均能得到较好的仿真效果。例如，VINT3的电位可以为0V、1V、2V、3V、4V，其数值可以根据实际的需要进行选择。如果需要快速复位，应用于高频场景，则可以选择电位较低的数值，例如0V；如果需要较慢的速度复位，应用于低频场景，则可以选择与数据电压接近的电位，例如3V或4V。
在该示例中，第三节点P3被第一复位晶体管(晶体管M1)复位后的电位大于第四节点P4被第二复位晶体管(晶体管M7)复位后的电位；第一节点P1被第三复位晶体管(晶体管M8)复位后的电位小于第三节点P3被第一复位晶体管(晶体管M1)复位后的电位；第一节点P1被第三复位晶体管(晶体管M8)复位后的电位小于或等于第四节点P4被第二复位晶体管(晶体管M7)复位后的电位；第二节点P2被第四复位晶体管(晶体管M9)复位后的电位大于第一节点P1被第三复位晶体管(晶体管M8)复位后的电位；第二节点P2被第四复位晶体管(晶体管M9)复位后的电位大于第三节点P3被第一复位晶体管(晶体管M1)复位后的电位；第二节点P2被第四复位晶体管(晶体管M9)复位后的电位大于第四节点P4被第二复位晶体管(晶体管M7)复位后的电位。由此可以得到较好的复位效果，更好地降低残余电荷的影响。
例如，对于图22所示的时序，在不同的工作频率下，一帧时间内的复位情形可以不同。例如，在低频情形，例如30Hz及以下，对第一节点P1、第二节点P2、第三节点P3、第四节点P4这4个节点都进行复位。由于在低频工作时，有更充足的时间完成复位，且在低频状态下，像素电路中的晶体管更容易发生漏电，因此充分的复位有利于改善迟滞效应，进而提升显示画质。例如，在中等频率情形，例如30Hz至90Hz，可以选择复位比低频状态更少的节点，例如复位第一节点P1、第二节点P2、第四节点P4这3个节点，或者复位第一节点P1、第三节点P3、第四节点P4这3个节点。在高频工作状态，例如90Hz至120Hz甚至更高的频率，可以选择复位比中频状态/低频状 态更少的节点，例如复位第一节点P1、第四节点P4这2个节点，或仅复位二者中的一个节点。在越高的频率下，复位的节点越少，有利于实现在短时间内的数据快速写入，进而实现高刷新率。而且，在高频工作状态下，复位的节点个数减少，有利于进一步降低功耗。
例如，为了既减少像素电路中的晶体管数量，又能实现第二节点P2的复位，可以采用另行提供的电压生成电路来生成三种电压信号以供像素电路使用，也即生成VDD1、VDD2、VSS三种电压信号，或者在第一电压线VDD处连接两根信号线以分别传输VDD1和VDD2。三者的大小关系是：VDD1>VDD2>VSS。在非发光阶段，第一电压线VDD连接的信号是VDD2；在发光阶段，第一电压线VDD连接的信号是VDD1。由此，可以省略图21中的晶体管M9。当然，本公开的实施例不限于此，第一电压线VDD上传输的第一电压也可以是恒定的，本公开的实施例对此不作限制。
图23为本公开一些实施例提供的一种像素电路的电路结构示意图。在一些示例中，如图23所示，该像素电路10包括：晶体管M1至晶体管M9以及存储电容Cst。例如，晶体管M3被用作驱动晶体管，其他的晶体管被用作开关晶体管。发光元件170可以实现为发光元件EL，发光元件EL例如可以采用OLED，本公开的实施例包括但不限于此，以下各实施例均以OLED为例进行说明，不再赘述。该OLED可以为各种类型，例如顶发射、底发射等，可以发红光、绿光、蓝光或白光等，本公开的实施例对此不作限制。
例如，如图23所示，更详细地，驱动电路110可以实现为驱动晶体管，也即晶体管M3；数据写入电路120可以实现为数据写入晶体管，也即晶体管M4；阈值补偿电路130可以实现为阈值补偿晶体管，也即晶体管M2；存储电路140可以实现为存储电容Cst；第一发光控制电路150可以实现为第一发光控制晶体管，也即晶体管M5；第二发光控制电路180可以实现为第二发光控制晶体管，也即晶体管M6；第一复位电路160可以实现为第一复位晶体管，也即晶体管M1；第二复位电路190可以实现为第二复位晶体管，也即晶体管M7；第三复位电路210可以实现为第三复位晶体管，也即晶体管M8；第四复位电路220可以实现为第四复位晶体管，也即晶体管M9。该示例的像素电路10的工作原理与图21所示的像素电路10的工作原理基本相同，区别在于该示例的像素电路10中所有的晶体管均为N型薄膜晶体管，相关原理可参考上文内容，此处不再赘述。
图24为本公开一些实施例提供的用于图23所示的像素电路的一种时序图。在该示例中，在第一阶段T1，通过导通的晶体管M9对第二节点P2进行复位。在第二阶段T2，通过导通的晶体管M1对第三节点P3进行复位，通过导通的晶体管M7对第四节点P4进行复位，通过导通的晶体管M8对第一节点P1进行复位。在第三阶段T3，进行写数据操作。在第四阶段T4，再次通过导通的晶体管M7和晶体管M9分别对第四节点P4和第二节点P2进行复位。在第五阶段T5，发光元件EL发光。
需要说明的是，上文结合图7至图24描述了多个示例，虽然在这些示例中对第一节点P1、第二节点P2、第三节点P3、第四节点P4的复位操作以特定的顺序进行了描述，但这并不构成对本公开实施例的限制。对第一节点P1、第二节点P2、第三节点P3、第四节点P4的复位操作的顺序可以不限于本公开实施例所描述的情形，可以根据实际情况进行调整和更改，本公开的实施例对此不作限制。在本公开的实施例中，可以选择第一节点P1、第二节点P2、第三节点P3、第四节点P4中的一个或多个节点进行复位，可以在数据写入阶段之前和/或在数据写入阶段与发光阶段之间(也即数据写入阶段后、发光阶段前)进行复位，可以采用任意适用的顺序和方式对选择的节点进行复位，本公开的实施例对此不作限制。
需要说明的是，虽然上文针对具体的电路结构描述了对各个节点的复位操作，但是这并不构成对本公开实施例的限制，本公开实施例提供的驱动方法还可以应用于其他电路结构，不限于图2至图5、图7、图12、图17、图21、图23所示出的电路结构，不限于包含7个晶体管/8个晶体管/9个晶体管的像素电路，该驱动方法可以应用于任意适用的像素电路。
在本公开的实施例中，在数据写入之前对数据写入路径上的节点进行复位，这样可以消除前一阶段残余电荷(包括由于漏电流造成的残余电荷)的影响，使得数据可以准确写入到驱动晶体管的栅极。在发光之前对发光路径上的节点进行复位，由于发光阶段是在数据写入之后，数据写入后会在发光路径上产生残余电荷，一些晶体管的漏电也会在发光路径上产生残余电荷，在发光之前对可能有残余电荷的位置或者节点进行复位，能显著提升发光路径上的发光电流准确度，进而提升显示品质。
需要说明的是，本公开的各实施例中，存储电容Cst可以是通过工艺制程制作的电容器件，例如通过制作专门的电容电极来实现电容器件，该电容 的各个电极可以通过金属层、半导体层(例如掺杂多晶硅)等实现，并且，存储电容Cst也可以是晶体管之间的寄生电容，可以通过晶体管本身与其他器件、线路来实现。
需要注意的是，在本公开的各个实施例的说明中，第一节点P1、第二节点P2、第三节点P3、第四节点P4并非表示实际存在的部件，而是表示电路图中相关电连接的汇合点。
需要说明的是，本公开的实施例中采用的晶体管均可以为薄膜晶体管、场效应晶体管或其他特性相同的开关器件，本公开的实施例中均以薄膜晶体管为例进行说明。这里采用的晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的。在本公开的实施例中，为了区分晶体管除栅极之外的两极，直接描述了其中一极为第一极，另一极为第二极。
另外，在本公开的实施例中，当晶体管采用N型晶体管时，晶体管的第一极是漏极，第二极是源极；当晶体管采用P型晶体管时，晶体管的第一极是源极，第二极是漏极。当改变晶体管的类型时，只需将选定类型的晶体管的各极参照本公开的实施例中的相应晶体管的各极相应连接，并且使相应的电压端提供对应的高电压或低电压即可。当采用N型晶体管时，可以采用氧化铟镓锌(Indium Gallium Zinc Oxide，IGZO)作为薄膜晶体管的有源层，相对于采用低温多晶硅(Low Temperature Poly Silicon，LTPS)或非晶硅(例如氢化非晶硅)作为薄膜晶体管的有源层，可以有效减小晶体管的尺寸以及防止漏电流。
本公开至少一个实施例还提供一种像素电路。该像素电路包括：驱动电路、数据写入电路、阈值补偿电路、存储电路、第一发光控制电路和第一复位电路。驱动电路包括控制端、第一端和第二端，且配置为控制流经发光元件的驱动电流。数据写入电路与驱动电路的第一端连接，且配置为在数据写入阶段响应于第一扫描信号将数据信号写入驱动电路的第一端。阈值补偿电路连接在驱动电路的控制端和驱动电路的第二端之间，且配置为响应于第二扫描信号将基于数据信号的补偿信号写入驱动电路的控制端。存储电路与驱动电路的控制端和第一电压线连接，存储电路与驱动电路的控制端连接于第一节点，存储电路配置为存储补偿信号并将补偿信号保持在驱动电路的控制端。第一发光控制电路与第一电压线和驱动电路的第一端连接，第一发光控 制电路与驱动电路的第一端连接于第二节点，第一发光控制电路配置为在数据写入阶段之前响应于第一发光控制信号将第一电压线提供的第一电压施加至驱动电路的第一端，从而对第二节点进行复位。第一复位电路与阈值补偿电路连接，且配置为在数据写入阶段之前响应于第一复位信号将第一复位电压施加至驱动电路的控制端，从而对第一节点进行复位。该像素电路可以降低或消除残余电荷对写入数据的精确度和发光阶段发光器件阳极的电位的影响，实现显示效果的优化。关于该像素电路的详细说明可以参考上文关于图2至图5所示的像素电路10的说明，此处不再赘述。
本公开至少一个实施例还提供一种像素电路。该像素电路包括：驱动电路、数据写入电路、阈值补偿电路、存储电路和第一复位电路。驱动电路包括控制端、第一端和第二端，且配置为控制流经发光元件的驱动电流；数据写入电路与驱动电路的第一端连接，且配置为响应于第一扫描信号将数据信号写入驱动电路的第一端；阈值补偿电路连接在驱动电路的控制端和驱动电路的第二端之间，且配置为响应于第二扫描信号将基于数据信号的补偿信号写入驱动电路的控制端；存储电路与驱动电路的控制端和第一电压线连接，且配置为存储补偿信号并将补偿信号保持在驱动电路的控制端；第一复位电路与阈值补偿电路和驱动电路的第二端连接，且配置为响应于第一复位信号将第一复位电压施加至驱动电路的第二端。该像素电路例如为图2、图3、图4所示的像素电路10，关于驱动电路、数据写入电路、阈值补偿电路、存储电路和第一复位电路的详细说明可参考上文中关于图2、图3、图4所示的像素电路10中的驱动电路110、数据写入电路120、阈值补偿电路130、存储电路140和第一复位电路160的说明，此处不再赘述。
例如，驱动电路包括驱动晶体管，驱动晶体管的栅极作为驱动电路的控制端，驱动晶体管的第一极作为驱动电路的第一端，驱动晶体管的第二极作为驱动电路的第二端。
例如，数据写入电路包括数据写入晶体管，数据写入晶体管的栅极与第一扫描线连接以接收第一扫描信号，数据写入晶体管的第一极与数据线连接以接收数据信号，数据写入晶体管的第二极与驱动晶体管的第一极连接。
例如，阈值补偿电路包括阈值补偿晶体管，阈值补偿晶体管的栅极与第二扫描线连接以接收第二扫描信号，阈值补偿晶体管的第一极与驱动晶体管的第二极连接，阈值补偿晶体管的第二极与驱动晶体管的栅极连接。
例如，存储电路包括存储电容，存储电容的第一极与第一电压线连接，存储电容的第二极与驱动晶体管的栅极连接。
例如，第一复位电路包括第一复位晶体管，第一复位晶体管的栅极与第一复位线连接以接收第一复位信号，第一复位晶体管的第一极与第一复位电压线连接以接收第一复位电压，第一复位晶体管的第二极与驱动晶体管的第二极连接。
关于各个晶体管及存储电容的具体连接方式，可以参考图7、图17、图21所示的像素电路10中各个晶体管及存储电容的连接方式，驱动晶体管例如为晶体管M3，数据写入晶体管例如为晶体管M4，阈值补偿晶体管例如为晶体管M2，存储电容例如为存储电容Cst，第一复位晶体管例如为晶体管M1，详细说明此处不再赘述。
在一些示例中，该像素电路还包括第一发光控制电路和第二发光控制电路。第一发光控制电路与第一电压线和驱动电路的第一端连接，且配置为响应于第一发光控制信号将第一电压线提供的第一电压施加至驱动电路的第一端。第二发光控制电路与驱动电路的第二端和发光元件连接，且配置为响应于第二发光控制信号将驱动电路的第二端的电压施加至发光元件。关于第一发光控制电路和第二发光控制电路的详细说明可参考上文中关于图2、图3、图4所示的像素电路10中的第一发光控制电路150和第二发光控制电路180的说明，此处不再赘述。
例如，第一发光控制电路包括第一发光控制晶体管，第一发光控制晶体管的栅极与第一发光控制线连接以接收第一发光控制信号，第一发光控制晶体管的第一极与第一电压线连接，第一发光控制晶体管的第二极与驱动电路的第一端连接。例如，第二发光控制电路包括第二发光控制晶体管，第二发光控制晶体管的栅极与第二发光控制线连接以接收第二发光控制信号，第二发光控制晶体管的第一极与驱动电路的第二端连接，第二发光控制晶体管的第二极与发光元件连接。关于各个晶体管的具体连接方式，可以参考图7、图17、图21所示的像素电路10中各个晶体管的连接方式，第一发光控制晶体管例如为晶体管M5，第二发光控制晶体管例如为晶体管M6，详细说明此处不再赘述。
在一些示例中，该像素电路还包括第二复位电路。第二复位电路与第二发光控制电路和发光元件连接，且配置为响应于第二复位信号将第二复位电 压施加至发光元件。关于第二复位电路的详细说明可参考上文中关于图2、图3、图4所示的像素电路10中的第二复位电路190的说明，此处不再赘述。
例如，第二复位电路包括第二复位晶体管，第二复位晶体管的栅极与第二复位线连接以接收第二复位信号，第二复位晶体管的第一极与第二复位电压线连接以接收第二复位电压，第二复位晶体管的第二极与第二发光控制晶体管的第二极和发光元件连接。关于各个晶体管的具体连接方式，可以参考图7、图17、图21所示的像素电路10中各个晶体管的连接方式，第二复位晶体管例如为晶体管M7，详细说明此处不再赘述。
在一些示例中，该像素电路还包括第三复位电路。第三复位电路与阈值补偿电路和驱动电路的控制端连接，第三复位电路配置为响应于第三复位信号将第三复位电压施加至驱动电路的控制端。关于第三复位电路的详细说明可参考上文中关于图3、图4所示的像素电路10中的第三复位电路210的说明，此处不再赘述。
例如，第三复位电路包括第三复位晶体管，第三复位晶体管的栅极与第三复位线连接以接收第三复位信号，第三复位晶体管的第一极与第三复位电压线连接以接收第三复位电压，第三复位晶体管的第二极与驱动电路的控制端连接。关于各个晶体管的具体连接方式，可以参考图17、图21所示的像素电路10中各个晶体管的连接方式，第三复位晶体管例如为晶体管M8，详细说明此处不再赘述。
例如，在一些示例中，该像素电路还包括第四复位电路。第四复位电路与驱动电路的第一端连接，第四复位电路配置为响应于第四复位信号将第四复位电压施加至驱动电路的第一端。关于第四复位电路的详细说明可参考上文中关于图4所示的像素电路10中的第四复位电路220的说明，此处不再赘述。
例如，第四复位电路包括第四复位晶体管，第四复位晶体管的栅极与第四复位线连接以接收第四复位信号，第四复位晶体管的第一极与第四复位电压线连接以接收第四复位电压，第四复位晶体管的第二极与驱动电路的第一端连接。关于各个晶体管的具体连接方式，可以参考图21所示的像素电路10中各个晶体管的连接方式，第四复位晶体管例如为晶体管M9，详细说明此处不再赘述。
本公开至少一个实施例还提供一种显示面板，该显示面板包括多个像素 单元，每个像素单元包括本公开任一实施例提供的像素电路。该显示面板可以降低或消除残余电荷对写入数据的精确度和发光阶段发光器件阳极的电位的影响，实现显示效果的优化。
图25为本公开一些实施例提供的一种显示面板的示意框图。如图25所示，在一些实施例中，该显示面板30包括多个像素单元301，多个像素单元301例如阵列排布。每个像素单元301包括像素电路302。像素电路302可以是本公开任一实施例提供的像素电路，例如上文描述的像素电路10。
例如，显示面板30可以为有机发光二极管(OLED)显示面板、量子点发光二极管(Quantum Dot Light-Emitting Diode，QLED)显示面板或其他适用的显示面板。每个像素单元301不仅包括像素电路302，还包括发光元件(例如OLED、QLED等)。
例如，显示面板30可以为矩形面板、圆形面板、椭圆形面板或多边形面板等。另外，显示面板30不仅可以为平面面板，也可以为曲面面板，甚至球面面板等。例如，显示面板30还可以具备触控功能，即显示面板30可以为触控显示面板。例如，显示面板30可以应用于手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件中。例如，该显示面板30可以为柔性显示面板，从而可以满足各种实际应用需求，例如，该显示面板30可以应用于曲面屏等。
为表示清楚、简洁，本公开的实施例并没有给出该显示面板30的全部组成单元。为实现该显示面板30的基本功能，本领域技术人员可以根据具体需要提供、设置其他未示出的结构，本公开的实施例对此不作限制。
关于上述实施例提供的显示面板30的技术效果可以参考本公开的实施例中提供的像素电路10的技术效果，这里不再赘述。
本公开至少一个实施例还提供一种显示装置，该显示装置包括本公开任一实施例提供的显示面板。该显示装置可以降低或消除残余电荷对写入数据的精确度和发光阶段发光器件阳极的电位的影响，实现显示效果的优化。
图26为本公开一些实施例提供的一种显示装置的示意框图。如图26所示，显示装置40包括显示面板4000、栅极驱动器4010、定时控制器4020和数据驱动器4030。显示面板4000包括根据多条扫描线GL和多条数据线DL交叉限定的多个像素单元P。显示面板4000例如为本公开任一实施例提供的显示面板，例如为上文描述的显示面板30。多条扫描线GL包括前述的 第一扫描线SC1、第二扫描线SC2、第三扫描线SC3、第一发光控制线EM1、第二发光控制线EM2等。多条数据线DL包括前述的数据线Vdata。栅极驱动器4010用于驱动多条扫描线GL；数据驱动器4030用于驱动多条数据线DL；定时控制器4020用于处理从显示装置40外部输入的图像数据RGB，向数据驱动器4030提供处理的图像数据RGB以及向栅极驱动器4010和数据驱动器4030输出扫描控制信号GCS和数据控制信号DCS，以对栅极驱动器4010和数据驱动器4030进行控制。
例如，栅极驱动器4010可以实现为半导体芯片，也可以集成在显示面板4000中以构成GOA电路。
例如，数据驱动器4030使用参考伽玛电压根据源自定时控制器4020的多个数据控制信号DCS将从定时控制器4020输入的数字图像数据RGB转换成数据信号。数据驱动器4030向多条数据线DL提供转换的数据信号。例如，数据驱动器4030可以实现为半导体芯片。
例如，定时控制器4020对外部输入的图像数据RGB进行处理以匹配显示面板4000的大小和分辨率，然后向数据驱动器4030提供处理后的图像数据。定时控制器4020使用从显示装置40外部输入的同步信号(例如点时钟DCLK、数据使能信号DE、水平同步信号Hsync以及垂直同步信号Vsync)产生多条扫描控制信号GCS和多条数据控制信号DCS。定时控制器4020分别向栅极驱动器4010和数据驱动器4030提供产生的扫描控制信号GCS和数据控制信号DCS，以用于栅极驱动器4010和数据驱动器4030的控制。
该显示装置40还可以包括其他部件，例如信号解码电路、电压转换电路等，这些部件例如可以采用已有的常规部件，这里不再详述。显示装置40可以应用于电子书、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件中。关于该显示装置40的详细描述可以参考本公开的实施例中对于像素电路10和显示面板30的描述，此处不再赘述。
有以下几点需要说明：
(1)本公开实施例附图只涉及到本公开实施例涉及到的结构，其他结构可参考通常设计。
(2)在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (25)

  1. 一种像素电路的驱动方法，其中，
    所述像素电路包括驱动电路、数据写入电路、阈值补偿电路、存储电路、第一发光控制电路和第一复位电路；
    所述驱动电路包括控制端、第一端和第二端，且配置为控制流经发光元件的驱动电流；
    所述数据写入电路与所述驱动电路的第一端连接，且配置为响应于第一扫描信号将数据信号写入所述驱动电路的第一端；
    所述阈值补偿电路连接在所述驱动电路的控制端和所述驱动电路的第二端之间，且配置为响应于第二扫描信号将基于所述数据信号的补偿信号写入所述驱动电路的控制端；
    所述存储电路与所述驱动电路的控制端和第一电压线连接，且配置为存储所述补偿信号并将所述补偿信号保持在所述驱动电路的控制端；
    所述第一发光控制电路与所述第一电压线和所述驱动电路的第一端连接，且配置为响应于第一发光控制信号将所述第一电压线提供的第一电压施加至所述驱动电路的第一端；
    所述第一复位电路与所述阈值补偿电路连接，且配置为响应于第一复位信号将第一复位电压施加至所述驱动电路的控制端；
    所述驱动电路的控制端与所述存储电路连接于第一节点，所述第一发光控制电路与所述驱动电路的第一端连接于第二节点；
    所述方法包括：
    在数据写入阶段之前，所述第一复位电路响应于所述第一复位信号导通，以将所述第一复位电压施加至所述驱动电路的控制端，从而对所述第一节点进行复位，并且，所述第一发光控制电路响应于所述第一发光控制信号导通，以将所述第一电压施加至所述驱动电路的第一端，从而对所述第二节点进行复位；
    在所述数据写入阶段，所述数据写入电路响应于所述第一扫描信号导通，以将所述数据信号写入所述驱动电路的第一端；
    在发光阶段，所述第一发光控制电路响应于所述第一发光控制信号导通，所述发光元件根据所述驱动电流发光。
  2. 根据权利要求1所述的方法，其中，所述第一复位电路响应于所述第一复位信号导通，以将所述第一复位电压施加至所述驱动电路的控制端，从而对所述第一节点进行复位，包括：
    所述第一复位电路响应于所述第一复位信号导通，所述阈值补偿电路响应于所述第二扫描信号导通，以将所述第一复位电压通过所述第一复位电路和所述阈值补偿电路形成的通路施加至所述驱动电路的控制端，从而对所述第一节点进行复位。
  3. 根据权利要求1或2所述的方法，其中，所述像素电路还包括第二发光控制电路和第二复位电路；
    所述第二发光控制电路与所述驱动电路的第二端和所述发光元件连接，且配置为响应于第二发光控制信号将所述驱动电路的第二端的电压施加至所述发光元件；
    所述第二复位电路与所述第二发光控制电路和所述发光元件连接，且配置为响应于第二复位信号将第二复位电压施加至所述发光元件；
    所述第二发光控制电路与所述驱动电路的第二端连接于第三节点，所述第二复位电路与所述第二发光控制电路及所述发光元件连接于第四节点；
    所述方法还包括：
    在所述数据写入阶段之前，在所述第一复位电路对所述第一节点进行复位的同时，所述第一复位电路将所述第一复位电压施加至所述驱动电路的第二端，从而对所述第三节点进行复位；和/或
    在所述数据写入阶段之前，所述第二复位电路响应于所述第二复位信号导通，以将所述第二复位电压施加至所述发光元件，从而对所述第四节点进行复位。
  4. 根据权利要求1-3任一项所述的方法，其中，在所述数据写入阶段之前，所述第一节点和所述第二节点同时进行复位或者在不同的时段分别进行复位。
  5. 根据权利要求3所述的方法，其中，在所述数据写入阶段之前，在所述第三节点和所述第四节点均进行复位的情形，所述第三节点和所述第四节点同时进行复位或者在不同的时段分别进行复位。
  6. 根据权利要求5所述的方法，其中，在所述数据写入阶段之前，所述第三节点和所述第四节点至少之一的复位时段与所述第一节点和所述第二节 点至少之一的复位时段重合。
  7. 根据权利要求5所述的方法，其中，在所述数据写入阶段之前，所述第一节点的复位时段、所述第二节点的复位时段、所述第三节点的复位时段、所述第四节点的复位时段均不重合。
  8. 根据权利要求3所述的方法，还包括：
    在所述数据写入阶段之后、所述发光阶段之前，所述第一发光控制电路响应于所述第一发光控制信号导通，以将所述第一电压施加至所述驱动电路的第一端，从而对所述第二节点进行复位；和/或
    在所述数据写入阶段之后、所述发光阶段之前，所述第一复位电路响应于所述第一复位信号导通，以将所述第一复位电压施加至所述驱动电路的第二端，从而对所述第三节点进行复位；和/或
    在所述数据写入阶段之后、所述发光阶段之前，所述第二复位电路响应于所述第二复位信号导通，以将所述第二复位电压施加至所述发光元件，从而对所述第四节点进行复位。
  9. 根据权利要求8所述的方法，其中，在所述数据写入阶段之后、所述发光阶段之前，所述第二节点、所述第三节点、所述第四节点中至少两个节点同时进行复位或者在不同的时段分别进行复位。
  10. 根据权利要求1-9任一项所述的方法，其中，所述驱动电路包括驱动晶体管，所述数据写入电路包括数据写入晶体管，所述阈值补偿电路包括阈值补偿晶体管，所述第一发光控制电路包括第一发光控制晶体管，所述第一复位电路包括第一复位晶体管；
    所述驱动晶体管、所述数据写入晶体管、所述第一发光控制晶体管、所述第一复位晶体管为第一类型的晶体管；
    所述阈值补偿晶体管为第二类型的晶体管；
    所述第一类型不同于所述第二类型。
  11. 根据权利要求10所述的方法，其中，所述第一类型的晶体管包括P型薄膜晶体管，所述第二类型的晶体管包括N型薄膜晶体管。
  12. 根据权利要求10或11所述的方法，其中，所述像素电路还包括防漏电电路，所述防漏电电路与所述驱动电路的控制端、所述阈值补偿电路和所述存储电路连接，所述防漏电电路配置为抑制所述驱动电路的控制端的漏电。
  13. 根据权利要求12所述的方法，其中，所述防漏电电路包括防漏电晶体管，所述防漏电晶体管为所述第二类型的晶体管。
  14. 一种像素电路，包括：驱动电路、数据写入电路、阈值补偿电路、存储电路和第一复位电路；其中，
    所述驱动电路包括控制端、第一端和第二端，且配置为控制流经发光元件的驱动电流；
    所述数据写入电路与所述驱动电路的第一端连接，且配置为响应于第一扫描信号将数据信号写入所述驱动电路的第一端；
    所述阈值补偿电路连接在所述驱动电路的控制端和所述驱动电路的第二端之间，且配置为响应于第二扫描信号将基于所述数据信号的补偿信号写入所述驱动电路的控制端；
    所述存储电路与所述驱动电路的控制端和第一电压线连接，且配置为存储所述补偿信号并将所述补偿信号保持在所述驱动电路的控制端，所述驱动电路的控制端与所述存储电路连接于第一节点；
    所述第一复位电路与所述阈值补偿电路和所述驱动电路的第二端连接，且配置为响应于第一复位信号将第一复位电压施加至所述驱动电路的第二端。
  15. 根据权利要求14所述的像素电路，其中，
    所述驱动电路包括驱动晶体管，所述驱动晶体管的栅极作为所述驱动电路的控制端，所述驱动晶体管的第一极作为所述驱动电路的第一端，所述驱动晶体管的第二极作为所述驱动电路的第二端；
    所述数据写入电路包括数据写入晶体管，所述数据写入晶体管的栅极与第一扫描线连接以接收所述第一扫描信号，所述数据写入晶体管的第一极与数据线连接以接收所述数据信号，所述数据写入晶体管的第二极与所述驱动晶体管的第一极连接；
    所述阈值补偿电路包括阈值补偿晶体管，所述阈值补偿晶体管的栅极与第二扫描线连接以接收所述第二扫描信号，所述阈值补偿晶体管的第一极与所述驱动晶体管的第二极连接，所述阈值补偿晶体管的第二极与所述驱动晶体管的栅极连接；
    所述存储电路包括存储电容，所述存储电容的第一极与所述第一电压线连接，所述存储电容的第二极与所述驱动晶体管的栅极连接；
    所述第一复位电路包括第一复位晶体管，所述第一复位晶体管的栅极与第一复位线连接以接收所述第一复位信号，所述第一复位晶体管的第一极与第一复位电压线连接以接收所述第一复位电压，所述第一复位晶体管的第二极与所述驱动晶体管的第二极连接。
  16. 根据权利要求14或15所述的像素电路，还包括第一发光控制电路和第二发光控制电路；其中，
    所述第一发光控制电路与所述第一电压线和所述驱动电路的第一端连接，且配置为响应于第一发光控制信号将所述第一电压线提供的第一电压施加至所述驱动电路的第一端，所述第一发光控制电路与所述驱动电路的第一端连接于第二节点；
    所述第二发光控制电路与所述驱动电路的第二端和所述发光元件连接，且配置为响应于第二发光控制信号将所述驱动电路的第二端的电压施加至所述发光元件，所述第二发光控制电路与所述驱动电路的第二端连接于第三节点。
  17. 根据权利要求16所述的像素电路，其中，
    所述第一发光控制电路包括第一发光控制晶体管，所述第一发光控制晶体管的栅极与第一发光控制线连接以接收所述第一发光控制信号，所述第一发光控制晶体管的第一极与所述第一电压线连接，所述第一发光控制晶体管的第二极与所述驱动电路的第一端连接；
    所述第二发光控制电路包括第二发光控制晶体管，所述第二发光控制晶体管的栅极与第二发光控制线连接以接收所述第二发光控制信号，所述第二发光控制晶体管的第一极与所述驱动电路的第二端连接，所述第二发光控制晶体管的第二极与所述发光元件连接。
  18. 根据权利要求17所述的像素电路，还包括第二复位电路，其中，所述第二复位电路与所述第二发光控制电路和所述发光元件连接，且配置为响应于第二复位信号将第二复位电压施加至所述发光元件；
    所述第二复位电路与所述第二发光控制电路及所述发光元件连接于第四节点；
    所述第三节点被所述第一复位电路复位后的电位大于所述第四节点被所述第二复位电路复位后的电位。
  19. 根据权利要求18所述的像素电路，其中，所述第二复位电路包括第 二复位晶体管，所述第二复位晶体管的栅极与第二复位线连接以接收所述第二复位信号，所述第二复位晶体管的第一极与第二复位电压线连接以接收所述第二复位电压，所述第二复位晶体管的第二极与所述第二发光控制晶体管的第二极和所述发光元件连接。
  20. 根据权利要求18或19所述的像素电路，还包括第三复位电路，其中，所述第三复位电路与所述阈值补偿电路和所述驱动电路的控制端连接，所述第三复位电路配置为响应于第三复位信号将第三复位电压施加至所述驱动电路的控制端；
    所述第一节点被所述第三复位电路复位后的电位小于所述第三节点被所述第一复位电路复位后的电位；
    所述第一节点被所述第三复位电路复位后的电位小于或等于所述第四节点被所述第二复位电路复位后的电位。
  21. 根据权利要求20所述的像素电路，其中，所述第三复位电路包括第三复位晶体管，所述第三复位晶体管的栅极与第三复位线连接以接收所述第三复位信号，所述第三复位晶体管的第一极与第三复位电压线连接以接收所述第三复位电压，所述第三复位晶体管的第二极与所述驱动电路的控制端连接。
  22. 根据权利要求20或21所述的像素电路，还包括第四复位电路，其中，所述第四复位电路与所述驱动电路的第一端连接，所述第四复位电路配置为响应于第四复位信号将第四复位电压施加至所述驱动电路的第一端；
    所述第二节点被所述第四复位电路复位后的电位大于所述第一节点被所述第三复位电路复位后的电位；
    所述第二节点被所述第四复位电路复位后的电位大于所述第三节点被所述第一复位电路复位后的电位；
    所述第二节点被所述第四复位电路复位后的电位大于所述第四节点被所述第二复位电路复位后的电位。
  23. 根据权利要求22所述的像素电路，其中，所述第四复位电路包括第四复位晶体管，所述第四复位晶体管的栅极与第四复位线连接以接收所述第四复位信号，所述第四复位晶体管的第一极与第四复位电压线连接以接收所述第四复位电压，所述第四复位晶体管的第二极与所述驱动电路的第一端连接。
  24. 一种显示面板，包括多个像素单元，其中，每个像素单元包括权利要求14-23任一项所述的像素电路。
  25. 一种显示装置，包括权利要求24所述的显示面板。
PCT/CN2023/105030 2022-08-23 2023-06-30 像素电路及其驱动方法、显示面板、显示装置 WO2024041217A1 (zh)

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