WO2024034359A1 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
WO2024034359A1
WO2024034359A1 PCT/JP2023/026762 JP2023026762W WO2024034359A1 WO 2024034359 A1 WO2024034359 A1 WO 2024034359A1 JP 2023026762 W JP2023026762 W JP 2023026762W WO 2024034359 A1 WO2024034359 A1 WO 2024034359A1
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WO
WIPO (PCT)
Prior art keywords
terminal
semiconductor device
electrode
conductive member
sealing resin
Prior art date
Application number
PCT/JP2023/026762
Other languages
French (fr)
Japanese (ja)
Inventor
敦司 山口
洋平 中村
尚孝 黒田
Original Assignee
ローム株式会社
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Publication of WO2024034359A1 publication Critical patent/WO2024034359A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads

Definitions

  • the present disclosure relates to a semiconductor device.
  • Patent Document 1 discloses an example of a semiconductor device equipped with a MOSFET.
  • the semiconductor device includes a drain terminal to which a power supply voltage is applied, a gate terminal for inputting an electrical signal to the MOSFET, and a terminal for converting the converted power after the power corresponding to the power supply voltage is converted based on the electrical signal. and a source terminal from which is output.
  • a MOSFET has a drain electrode electrically connected to a drain terminal and a source electrode electrically connected to a source terminal.
  • the drain electrode is bonded to a die pad connected to the drain terminal by a first conductive bonding material.
  • the source electrode is bonded to the metal clip by a second conductive bonding material. Additionally, the metal clip is also bonded to the source terminal. Both the first conductive bonding material and the second conductive bonding material are solder. This allows a larger current to flow through the semiconductor device.
  • An object of the present disclosure is to provide a semiconductor device that is improved over conventional ones.
  • an object of the present disclosure is to provide a semiconductor device that can reduce switching loss of a semiconductor element.
  • a semiconductor device provided by a first aspect of the present disclosure includes a semiconductor element having a first electrode and a gate electrode, a first terminal electrically connected to the first electrode, and a second terminal electrically connected to the gate electrode. and a third terminal electrically connected to the first electrode.
  • the direction of the current flowing through each of the first terminal and the third terminal is opposite to the direction of the current flowing through the second terminal.
  • the second terminal is located next to the first terminal.
  • the third terminal is located on the opposite side of the first terminal with respect to the second terminal.
  • FIG. 1 is a perspective view of a semiconductor device according to a first embodiment of the present disclosure.
  • FIG. 2 is a plan view of the semiconductor device shown in FIG. 1.
  • FIG. 3 is a plan view corresponding to FIG. 2, in which the sealing resin is seen through.
  • FIG. 4 is a bottom view of the semiconductor device shown in FIG. 1.
  • FIG. 5 is a front view of the semiconductor device shown in FIG. 1.
  • FIG. 6 is a cross-sectional view taken along line VI-VI in FIG.
  • FIG. 7 is a sectional view taken along line VII-VII in FIG. 3.
  • FIG. 8 is a cross-sectional view taken along line VIII-VIII in FIG. 3.
  • FIG. 9 is a partially enlarged view of FIG. 6.
  • FIG. 6 is a cross-sectional view taken along line VI-VI in FIG.
  • FIG. 7 is a sectional view taken along line VII-VII in FIG. 3.
  • FIG. 8 is a cross-sectional view taken along line VIII-VIII
  • FIG. 10 is a plan view illustrating the effects of the semiconductor device shown in FIG. 1, and corresponds to FIG. 3.
  • FIG. 11 is a plan view of a semiconductor device according to a second embodiment of the present disclosure, through which the sealing resin is seen.
  • FIG. 12 is a bottom view of the semiconductor device shown in FIG. 11.
  • FIG. 13 is a front view of the semiconductor device shown in FIG. 11.
  • FIG. 14 is a rear view of the semiconductor device shown in FIG. 11.
  • FIG. 15 is a right side view of the semiconductor device shown in FIG. 11.
  • FIG. 16 is a cross-sectional view taken along line XVI-XVI in FIG. 11.
  • FIG. 17 is a cross-sectional view taken along line XVII-XVII in FIG. 11.
  • FIG. 11 is a plan view of a semiconductor device according to a second embodiment of the present disclosure, through which the sealing resin is seen.
  • FIG. 12 is a bottom view of the semiconductor device shown in FIG. 11.
  • FIG. 13 is a
  • FIG. 18 is a cross-sectional view taken along line XVIII-XVIII in FIG. 11.
  • FIG. 19 is a partially enlarged view of FIG. 16.
  • FIG. 20 is a plan view illustrating the function and effect of the semiconductor device shown in FIG. 11, and corresponds to FIG.
  • a semiconductor device A10 according to a first embodiment of the present disclosure will be described based on FIGS. 1 to 10.
  • the semiconductor device A10 is used in a power conversion circuit such as an inverter.
  • the package format of the semiconductor device A10 is TO (Transistor Outline).
  • the semiconductor device A10 includes a semiconductor element 10, a die pad 20, a first terminal 21, a second terminal 22, a third terminal 23, a fourth terminal 24, a conductive bonding layer 29, a first conductive member 31, a second conductive member 32, and a third conductive member 32.
  • 3 conductive member 33 and sealing resin 40.
  • the sealing resin 40 is shown.
  • the transparent sealing resin 40 is shown by an imaginary line (two-dot chain line).
  • first direction z the normal direction of the mounting surface 201 of the die pad 20, which will be described later, will be referred to as a "first direction z.”
  • second direction x One direction perpendicular to the first direction z is called a "second direction x.”
  • third direction y A direction perpendicular to both the first direction z and the second direction x is referred to as a "third direction y.”
  • the semiconductor element 10 is, for example, a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor).
  • the semiconductor element 10 may be a field effect transistor including a MISFET (Metal-Insulator-Semiconductor Field-Effect Transistor) or a bipolar transistor such as an IGBT (Insulated Gate Bipolar Transistor).
  • the semiconductor element 10 is an n-channel type MOSFET with a vertical structure.
  • the plurality of semiconductor elements 10 include a compound semiconductor substrate.
  • the composition of the compound semiconductor substrate includes silicon carbide (SiC).
  • the semiconductor element 10 has a first electrode 11, a gate electrode 12, and a second electrode 13.
  • the first electrode 11 is located on one side of the semiconductor element 10 in the first direction z. A current corresponding to the power converted by the semiconductor element 10 flows through the first electrode 11 . That is, the first electrode 11 corresponds to the source electrode of the semiconductor element 10.
  • the first electrode 11 includes a first part 111 and two second parts 112.
  • the two second parts 112 are located on one side of the first part 111 in the second direction x.
  • the two second parts 112 are separated from each other in the third direction y.
  • the area of each of the two second parts 112 is smaller than the area of the first part 111 when viewed in the first direction z.
  • the second electrode 13 is located on the opposite side from the first electrode 11 in the first direction z. A current corresponding to the power before being converted by the semiconductor element 10 flows through the second electrode 13 . That is, the second electrode 13 corresponds to the drain electrode of the semiconductor element 10.
  • the gate electrode 12 is located on the same side as the first electrode 11 in the first direction z.
  • the gate electrode 12 is located between the two second parts 112 of the first electrode 11 in the third direction y.
  • a gate voltage for driving the semiconductor element 10 is applied to the gate electrode 12 .
  • the area of the gate electrode 12 is smaller than the area of the first portion 111 of the first electrode 11 when viewed in the first direction z.
  • the die pad 20 is a conductive member on which the semiconductor element 10 is mounted, as shown in FIG. 3 and FIGS. 6 to 8.
  • the die pad 20, together with the first terminal 21, the second terminal 22, the third terminal 23, and the fourth terminal 24, are constructed from the same lead frame.
  • the lead frame is made of copper (Cu) or a copper alloy. Therefore, the composition of each of the die pad 20, the first terminal 21, the second terminal 22, the third terminal 23, and the fourth terminal 24 includes copper.
  • the die pad 20 has a mounting surface 201, a back surface 202, and a through hole 203.
  • the mounting surface 201 faces in the first direction z.
  • the mounting surface 201 faces the second electrode 13 of the semiconductor element 10.
  • the back surface 202 faces the opposite side from the mounting surface 201 in the first direction z.
  • the back surface 202 is plated with tin (Sn), for example.
  • the through hole 203 extends through the die pad 20 from the mounting surface 201 to the back surface 202 in the first direction z.
  • the through hole 203 has a circular shape when viewed in the first direction z.
  • the conductive bonding layer 29 bonds the die pad 20 and the semiconductor element 10, as shown in FIGS. 6 and 7.
  • the conductive bonding layer 29 conductively bonds the mounting surface 201 of the die pad 20 and the second electrode 13 of the semiconductor element 10. Thereby, the second electrode 13 is electrically connected to the die pad 20.
  • the conductive bonding layer 29 is, for example, solder.
  • the conductive bonding layer 29 may be made of sintered metal.
  • the first terminal 21 is located away from the die pad 20, as shown in FIGS. 3 and 6.
  • the first terminal 21 extends in the third direction y.
  • the first terminal 21 is electrically connected to the first portion 111 of the first electrode 11 of the semiconductor element 10 . Therefore, the first terminal 21 corresponds to the source terminal of the semiconductor device A10.
  • the first terminal 21 has a covering portion 211, an exposed portion 212, and a first bonding surface 213.
  • the covering portion 211 is covered with a sealing resin 40.
  • the exposed portion 212 is connected to the covering portion 211 and exposed from the sealing resin 40 .
  • the exposed portion 212 extends away from the die pad 20 in the third direction y.
  • the surface of the exposed portion 212 is plated with tin, for example.
  • the first bonding surface 213 faces the same side as the mounting surface 201 of the die pad 20 in the first direction z.
  • the first bonding surface 213 is included in a part of the covering portion 211.
  • the first bonding surface 213 is located on the side where the semiconductor element 10 is located with respect to the mounting surface 201 in the first direction z.
  • the second terminal 22 is located away from the die pad 20, as shown in FIGS. 3 and 7.
  • the second terminal 22 extends in the third direction y.
  • the second terminal 22 is located next to the first terminal 21.
  • the second terminal 22 is electrically connected to the gate electrode 12 of the semiconductor element 10 . Therefore, the second terminal 22 corresponds to the gate terminal of the semiconductor device A10.
  • the direction of the current flowing through the second terminal 22 is opposite to the direction of the current flowing through the first terminal 21.
  • the second terminal 22 has a covering portion 221, an exposed portion 222, and a second bonding surface 223.
  • the covering portion 221 is covered with a sealing resin 40.
  • the exposed portion 222 is connected to the covering portion 221 and exposed from the sealing resin 40 .
  • the exposed portion 222 extends away from the die pad 20 in the third direction y.
  • the surface of the exposed portion 222 is plated with tin.
  • the second bonding surface 223 faces the same side as the mounting surface 201 of the die pad 20 in the first direction z.
  • the second bonding surface 223 is included in a part of the covering portion 221. In the first direction z, the position of the second joint surface 223 is the same as the position of the first joint surface 213 of the first terminal 21 .
  • the third terminal 23 is located away from the die pad 20, as shown in FIG.
  • the second terminal 22 and the third terminal 23 extend in the third direction y.
  • the third terminal 23 is located on the opposite side of the first terminal 21 with respect to the second terminal 22.
  • the third terminal 23 is located next to the second terminal 22.
  • the third terminal 23 is electrically connected to either of the two second portions 112 of the first electrode 11 of the semiconductor element 10 . Therefore, a voltage having the same potential as the voltage applied to the first terminal 21 is applied to the third terminal 23 .
  • the direction of the current flowing through the third terminal 23 is the same as the direction of the current flowing through the first terminal 21.
  • the third terminal 23 has a covering portion 231, an exposed portion 232, and a third bonding surface 233.
  • the covering portion 231 is covered with a sealing resin 40.
  • the exposed portion 232 is connected to the covering portion 231 and exposed from the sealing resin 40 .
  • the exposed portion 232 extends away from the die pad 20 in the third direction y.
  • the surface of the exposed portion 232 is plated with tin.
  • the third bonding surface 233 faces the same side as the mounting surface 201 of the die pad 20 in the first direction z.
  • the third joint surface 233 is included in a part of the covering portion 231. In the first direction z, the position of the third joint surface 233 is the same as the position of the first joint surface 213 of the first terminal 21 .
  • the fourth terminal 24 is located on the opposite side of the second terminal 22 with respect to the first terminal 21 in the second direction x.
  • the fourth terminal 24 includes a portion extending in the third direction y, and is connected to the die pad 20. Thereby, the fourth terminal 24 is electrically connected to the second electrode 13 of the semiconductor element 10. Therefore, the fourth terminal 24 corresponds to the drain terminal of the semiconductor device A10.
  • the direction of the current flowing through the fourth terminal 24 is opposite to the direction of the current flowing through the first terminal 21.
  • the fourth terminal 24 has a covering portion 241 and an exposed portion 242.
  • the covering portion 241 is connected to the die pad 20 and covered with the sealing resin 40 .
  • the covering portion 241 is bent when viewed in the second direction x.
  • the exposed portion 242 is connected to the covering portion 241 and exposed from the sealing resin 40 .
  • the exposed portion 242 extends away from the die pad 20 in the third direction y.
  • the surface of the exposed portion 242 is plated with tin.
  • the first terminal 21, second terminal 22, third terminal 23, and fourth terminal 24 are arranged along the second direction x.
  • the minimum distance d1 between the portions of the first terminal 21 and the fourth terminal 24 exposed from the sealing resin 40 (the exposed portion 212 and the exposed portion 242) is It is larger than the minimum interval d2 between the portions of the second terminals 22 exposed from the sealing resin 40 (the exposed portions 212 and the exposed portions 222).
  • the height h of the portion of each of the first terminal 21, second terminal 22, third terminal 23, and fourth terminal 24 exposed from the sealing resin 40 is as follows: Both are equal.
  • the first conductive member 31 is electrically conductively bonded to the first portion 111 of the first electrode 11 of the semiconductor element 10 and the first bonding surface 213 of the first terminal 21, as shown in FIGS. 3 and 6. Thereby, the first terminal 21 is electrically connected to the first portion 111 of the first electrode 11 .
  • the first conductive member 31 is a plurality of wires containing aluminum (Al).
  • the first conductive member 31 may be a plurality of wires containing copper or a metal clip containing copper.
  • the second conductive member 32 is electrically bonded to the gate electrode 12 of the semiconductor element 10 and the second bonding surface 223 of the second terminal 22, as shown in FIGS. 3 and 7. Thereby, the second terminal 22 is electrically connected to the gate electrode 12.
  • the second conductive member 32 is, for example, a wire containing either aluminum or gold (Au).
  • the third conductive member 33 is conductively bonded to one of the two second parts 112 of the first electrode 11 of the semiconductor element 10 and the third bonding surface 233 of the third terminal 23. . Thereby, the third terminal 23 is electrically connected to either of the two second portions 112 of the first electrode 11 .
  • the third conductive member 33 is, for example, a wire containing either aluminum or gold.
  • the second conductive member 32 is located next to the first conductive member 31. Further, the second conductive member 32 includes a section located between the first conductive member 31 and the third conductive member 33. As shown in FIG. 3, in the semiconductor device A10, the dimension of the first terminal 21 in the third direction y is larger than the conductive path length of the first conductive member 31. Additionally, the dimension of the second terminal 22 in the third direction y is larger than the length of the conductive path of the second conductive member 32.
  • the sealing resin 40 covers the semiconductor element 10, the first conductive member 31, and the second conductive member 32, as shown in FIGS. 3, 6, and 7. As shown in FIGS. 6 to 8, the sealing resin 40 partially covers each of the die pad 20, the first terminal 21, the second terminal 22, and the fourth terminal 24. As shown in FIGS. Further, the sealing resin 40 covers the third conductive member 33 and also partially covers the third terminal 23 .
  • the sealing resin 40 has electrical insulation properties.
  • the sealing resin 40 is made of a material containing, for example, a black epoxy resin.
  • the sealing resin 40 has a top surface 41 , a bottom surface 42 , two first side surfaces 43 , two second side surfaces 44 , two openings 45 , and a mounting hole 46 .
  • the top surface 41 faces the same side as the mounting surface 201 of the die pad 20 in the first direction z.
  • the bottom surface 42 faces opposite to the top surface 41 in the first direction z.
  • the back surface 202 of the die pad 20 is exposed from the bottom surface 42.
  • the two first side surfaces 43 are located apart from each other in the third direction y. Each of the two first side surfaces 43 is connected to the top surface 41 and the bottom surface 42. From one of the two first side surfaces 43, the exposed portion 212 of the first terminal 21, the exposed portion 222 of the second terminal 22, and the exposed portion 232 of the fourth terminal 24 are exposed.
  • the two second side surfaces 44 are located apart from each other in the second direction x.
  • Each of the two second side surfaces 44 is connected to the top surface 41 and the bottom surface 42.
  • the two openings 45 are located apart from each other in the second direction x.
  • Each of the two openings 45 is recessed inward from the sealing resin 40 from both the top surface 41 and one of the two second side surfaces 44 .
  • a portion of the mounting surface 201 of the die pad 20 is exposed from each of the two openings 45.
  • the attachment hole 46 penetrates the sealing resin 40 from the top surface 41 to the bottom surface 42 in the first direction z.
  • the attachment hole 46 is included in the through hole 203 of the die pad 20 when viewed in the first direction z.
  • the peripheral surface of the die pad 20 that defines the through hole 203 is covered with a sealing resin 40 .
  • the maximum dimension of the attachment hole 46 is smaller than the dimension of the through hole 203 when viewed in the first direction z.
  • the semiconductor device A10 includes a semiconductor element 10 having a first electrode 11 and a gate electrode 12, a first terminal 21 electrically connected to the first electrode 11, a second terminal 22 electrically connected to the gate electrode 12, and a semiconductor element 10 having a first electrode 11 and a gate electrode 12.
  • the third terminal 23 is electrically connected. The direction of the current flowing through each of the first terminal 21 and the third terminal 23 is opposite to the direction of the current flowing through the second terminal 22.
  • the second terminal 22 is located next to the first terminal 21.
  • the third terminal 23 is located on the opposite side of the first terminal 21 with respect to the second terminal 22.
  • an output current I d flows through the first terminal 21 as the first electrode 11 is driven.
  • the output current I d is a so-called unsteady current whose magnitude changes over time. Therefore, a magnetic flux M is formed around the first terminal 21. Therefore, by adopting this configuration, an induced electromotive force V M acts on the second terminal 22 due to electromagnetic induction caused by the magnetic flux M.
  • the direction of the induced electromotive force V M is equal to the direction of the current flowing through the second terminal 22. Therefore, the current flowing to the second terminal 22 is accelerated by the induced electromotive force V M .
  • the semiconductor device A10 further includes a first conductive member 31, a second conductive member 32, and a third conductive member 33 covered with a sealing resin 40.
  • the second conductive member 32 is located next to the first conductive member 31.
  • the induced electromotive force V M also acts on the second conductive member 32 due to the output current I d flowing through the first conductive member 31 (see FIG. 10). This further accelerates the current flowing through the second terminal 22, making it possible to effectively reduce the switching loss of the semiconductor element 10.
  • the second conductive member 32 includes a section located between the first conductive member 31 and the third conductive member 33.
  • the third conductive member 33 is located further away from the first conductive member 31 than the second conductive member 32. Thereby, inhibition of the current in the second conductive member 32 due to mutual induction between the first conductive member 31 and the third conductive member 33 can be suppressed.
  • the dimension of the first terminal 21 in the third direction y is larger than the conductive path length of the first conductive member 31. Furthermore, the dimension of the second terminal 22 in the third direction y is larger than the length of the conductive path of the second conductive member 32. Therefore, in the semiconductor device A10, the effect of the induced electromotive force V M shown in FIG. . Therefore, in the semiconductor device A10, it is preferable to further reduce the distance between the first terminal 21 and the second terminal 22.
  • the semiconductor element 10 has a second electrode 13 located on the opposite side to the first electrode 11 in the first direction z.
  • the semiconductor device A10 further includes a fourth terminal 24 electrically connected to the second electrode 13.
  • the fourth terminal 24 is located on the opposite side of the second terminal 22 with respect to the first terminal 21 in the second direction x. As shown in FIG. 3, the distance d1 between the first terminal 21 and the fourth terminal 24 is larger than the distance d2 between the first terminal 21 and the second terminal 22.
  • the semiconductor device A10 further includes a die pad 20 to which the second electrode 13 of the semiconductor element 10 is conductively bonded.
  • the fourth terminal 24 is connected to the die pad 20.
  • the die pad 20 can have both heat dissipation and conduction functions. In this case, by exposing the die pad 20 from the sealing resin 40, the heat dissipation of the semiconductor device A10 can be improved.
  • FIGS. 11 to 20 A semiconductor device A20 according to a second embodiment of the present disclosure will be described based on FIGS. 11 to 20.
  • the same or similar elements as those of the semiconductor device A10 described above are denoted by the same reference numerals, and redundant explanation will be omitted.
  • the sealing resin 40 is shown.
  • the transparent sealing resin 40 is shown with imaginary lines.
  • the semiconductor device A20 differs from the semiconductor device A10 in that it does not include the die pad 20 and in the configurations of the semiconductor element 10, the first terminal 21, the second terminal 22, the third terminal 23, and the fourth terminal 24.
  • the package format of the semiconductor device A20 is QFN (Quad Flat Non-leaded).
  • the first electrode 11 of the semiconductor element 10 does not include a first part 111 separated from each other and two second parts 112, and is single.
  • Each of the first conductive member 31 and the third conductive member 33 is electrically connected to the first electrode 11 .
  • FIG. 11 As shown in FIG. 11, FIG. 12, FIG. 13, and FIG. It has a hanging part 218.
  • the two mounting surfaces 214 face opposite to the first bonding surface 213 in the first direction z. As shown in FIG. 12, the mounting surfaces 214 are separated from each other in the second direction x. The two mounting surfaces 214 are exposed from the bottom surface 42 of the sealing resin 40. As shown in FIGS. 13 and 16, the two side surfaces 215 are individually connected to the two mounting surfaces 214 and face the third direction y. The two side surfaces 215 are also connected to the first joint surface 213. The two side surfaces 215 are exposed from either of the two first side surfaces 43 of the sealing resin 40.
  • the two inner circumferential surfaces 216 are individually connected to the two mounting surfaces 214 and face in a direction perpendicular to the first direction z.
  • Inner peripheral surface 216 is covered with sealing resin 40.
  • the eaves portion 217 protrudes from the two inner peripheral surfaces 216 in a direction perpendicular to the first direction z.
  • the first joint surface 213 is included in a part of the eaves section 217.
  • the eaves portion 217 is covered with a sealing resin 40.
  • the hanging portion 218 protrudes outward from the sealing resin 40 from the eaves portion 217 in the second direction x.
  • the first joint surface 213 is included in a part of the hanging portion 218. As shown in FIG. 15, the hanging portion 218 has an end surface 218A facing in the second direction x. The end surface 218A is exposed from either of the two second side surfaces 44 of the sealing resin 40.
  • the second terminal 22 has a second bonding surface 223, a mounting surface 224, a side surface 225, an inner peripheral surface 226, and an eaves portion 227.
  • the mounting surface 224 faces the opposite side from the second bonding surface 223 in the first direction z. As shown in FIG. 12, the mounting surface 224 is exposed from the bottom surface 42 of the sealing resin 40. As shown in FIGS. 13 and 17, the side surface 225 is connected to the second bonding surface 223 and the mounting surface 224, and faces in the third direction y. The side surface 225 is exposed from the first side surface 43 of the two first side surfaces 43 of the sealing resin 40 where the side surface 215 of the first terminal 21 is exposed.
  • the inner peripheral surface 226 is connected to the mounting surface 224 and faces in a direction perpendicular to the first direction z. Inner peripheral surface 226 is covered with sealing resin 40. As shown in FIGS. 11, 12, 13, and 17, the eaves portion 227 protrudes from the inner peripheral surface 226 in a direction perpendicular to the first direction z. The second joint surface 223 is included in a part of the eaves section 227. The eaves portion 227 is covered with a sealing resin 40.
  • the third terminal 23 has a third bonding surface 233, a mounting surface 234, a side surface 235, an inner peripheral surface 236, an eaves portion 237, and a hanging portion 238.
  • the mounting surface 234 faces the opposite side from the third bonding surface 233 in the first direction z. As shown in FIG. 12, the mounting surface 234 is exposed from the bottom surface 42 of the sealing resin 40. As shown in FIG. 13, the side surface 235 is connected to the third bonding surface 233 and the mounting surface 234, and faces in the third direction y. The side surface 235 is exposed from the first side surface 43 of the two first side surfaces 43 of the sealing resin 40 where the side surface 215 of the first terminal 21 is exposed.
  • the inner peripheral surface 236 is connected to the mounting surface 234 and faces in a direction perpendicular to the first direction z.
  • Inner peripheral surface 236 is covered with sealing resin 40.
  • the eaves portion 237 protrudes from the inner peripheral surface 236 in a direction perpendicular to the first direction z.
  • the third joint surface 233 is included in a part of the eaves section 237.
  • the eaves portion 237 is covered with a sealing resin 40.
  • the hanging portion 238 protrudes outward from the sealing resin 40 from the eaves portion 237 in the second direction x.
  • the third joint surface 233 is included in a part of the hanging portion 238.
  • the hanging portion 218 has an end surface 218A facing in the second direction x.
  • the end surface 218A is exposed from the second side surface 44 of the two second side surfaces 44 of the sealing resin 40 from which the end surface 218A of the hanging portion 218 of the first terminal 21 is not exposed.
  • the fourth terminal 24 is separated from the first terminal 21, second terminal 22, and third terminal 23 in the third direction y.
  • the fourth terminal 24 includes a mounting surface 243, a mounting surface 244, a plurality of side surfaces 245, an inner peripheral surface 246, an eaves portion 247, and two It has a hanging part 248.
  • the mounting surface 243 and the mounting surface 244 face oppositely to each other in the first direction z.
  • the mounting surface 243 faces the semiconductor element 10.
  • the second electrode 13 of the semiconductor element 10 is electrically bonded to the mounting surface 243 via the electrically conductive bonding layer 29 . Thereby, the second electrode 13 of the semiconductor element 10 is electrically connected to the fourth terminal 24.
  • the mounting surface 234 is exposed from the bottom surface 42 of the sealing resin 40.
  • the area of the mounting surface 234 is larger than the area of each of the two mounting surfaces 214 of the first terminal 21 , the mounting surface 224 of the second terminal 22 , and the mounting surface 234 of the third terminal 23 .
  • the semiconductor element 10 overlaps the mounting surface 234 when viewed in the first direction z.
  • the plurality of side surfaces 235 are connected to the mounting surface 243 and the mounting surface 244, and face the third direction y.
  • the plurality of side surfaces 235 are exposed from the first side surface 43 of the two first side surfaces 43 of the sealing resin 40 from which the two side surfaces 215 of the first terminal 21 are not exposed.
  • the plurality of side surfaces 235 are arranged along the second direction x.
  • the inner peripheral surface 246 is connected to the mounting surface 244 and faces in a direction perpendicular to the first direction z. Inner peripheral surface 246 is covered with sealing resin 40.
  • the semiconductor element 10 is surrounded by an inner circumferential surface 236 and a plurality of side surfaces 235 when viewed in the first direction z.
  • the eaves portion 237 protrudes from the inner peripheral surface 236 in a direction perpendicular to the first direction z.
  • the mounting surface 243 is included in a part of the eaves section 237.
  • the eaves portion 237 is covered with a sealing resin 40. As shown in FIGS.
  • the two hanging parts 248 protrude outward from the sealing resin 40 from the eaves part 217 in the second direction x.
  • the two hanging parts 248 are located on opposite sides of the eaves part 237 in the second direction x.
  • the mounting surface 243 is included in a part of each of the two hanging parts 218.
  • Each of the two hanging portions 248 has an end surface 248A facing in the second direction x. End surfaces 248A of each of the two hanging portions 248 are individually exposed from the two second side surfaces 44 of the sealing resin 40.
  • the first conductive member 31 is a metal clip. One end of the first conductive member 31 is electrically bonded to the first electrode 11 of the semiconductor element 10 via the electrically conductive bonding layer 29 . The other end of the first conductive member 31 is electrically bonded to the first bonding surface 213 of the first terminal 21 via the electrically conductive bonding layer 29 .
  • the second conductive member 32 is located next to the first conductive member 31 in the semiconductor device A20 as well. Further, the second conductive member 32 includes a section located between the first conductive member 31 and the third conductive member 33. As shown in FIG. 11, in the semiconductor device A20, the dimension of the first terminal 21 in the third direction y is smaller than the conductive path length of the first conductive member 31. Additionally, the dimension of the second terminal 22 in the third direction y is smaller than the length of the conductive path of the second conductive member 32.
  • the semiconductor device A20 includes a semiconductor element 10 having a first electrode 11 and a gate electrode 12, a first terminal 21 electrically connected to the first electrode 11, a second terminal 22 electrically connected to the gate electrode 12, and a semiconductor element 10 having a first electrode 11 and a gate electrode 12.
  • the third terminal 23 is electrically connected. The direction of the current flowing through each of the first terminal 21 and the third terminal 23 is opposite to the direction of the current flowing through the second terminal 22.
  • the second terminal 22 is located next to the first terminal 21.
  • the third terminal 23 is located on the opposite side of the first terminal 21 with respect to the second terminal 22.
  • the direction of the induced electromotive force V M is equal to the direction of the current flowing through the second terminal 22. Therefore, the current flowing to the second terminal 22 is accelerated by the induced electromotive force V M . Therefore, according to this configuration, it is possible to reduce the switching loss of the semiconductor element 10 also in the semiconductor device A20. Further, the semiconductor device A20 has the same configuration as the semiconductor element 10, so that the same effects as the semiconductor element 10 can be achieved.
  • the dimension of the first terminal 21 in the third direction y is smaller than the conductive path length of the first conductive member 31. Furthermore, the dimension of the second terminal 22 in the third direction y is smaller than the length of the conductive path of the second conductive member 32. Therefore, in the semiconductor device A20, the effect of the induced electromotive force V M shown in FIG. . Therefore, in the semiconductor device A20, it is preferable to make the distance between the first conductive member 31 and the second conductive member 32 smaller.
  • the second electrode 13 of the semiconductor element 10 is conductively bonded to the fourth terminal 24.
  • the sealing resin 40 has a bottom surface 42 facing in the first direction z.
  • the first terminal 21 , the second terminal 22 , the third terminal 23 , and the fourth terminal 24 are exposed from the bottom surface 42 .
  • the sealing resin 40 has two first side surfaces 43 facing oppositely to each other in the third direction y.
  • the first terminal 21, the second terminal 22, the third terminal 23, and the fourth terminal 24 are exposed from either of the two first side surfaces 43.
  • a semiconductor element having a first electrode and a gate electrode; a first terminal electrically connected to the first electrode; a second terminal electrically connected to the gate electrode; a third terminal electrically connected to the first electrode; The direction of the current flowing through each of the first terminal and the third terminal is opposite to the direction of the current flowing through the second terminal, The second terminal is located next to the first terminal, In the semiconductor device, the third terminal is located on the opposite side of the first terminal with respect to the second terminal. Appendix 2.
  • the semiconductor element has a second electrode located on the opposite side of the first electrode in the first direction, The gate electrode is located on the same side as the first electrode in the first direction,
  • the semiconductor device according to supplementary note 1 further comprising a fourth terminal electrically connected to the second electrode.
  • Appendix 3. The first terminal, the second terminal, and the third terminal are arranged along a second direction orthogonal to the first direction, The semiconductor device according to appendix 2, wherein the third terminal is located next to the second terminal.
  • Appendix 4. further comprising a sealing resin that covers the semiconductor element, The semiconductor device according to appendix 3, wherein the first terminal, the second terminal, the third terminal, and the fourth terminal are exposed from the sealing resin.
  • the minimum interval between the parts of each of the first terminal and the fourth terminal exposed from the sealing resin is smaller than the minimum interval between the parts of each of the first terminal and the second terminal exposed from the sealing resin.
  • Appendix 11. Also equipped with a die pad, the second electrode is electrically conductively bonded to the die pad; The semiconductor device according to appendix 9 or 10, wherein the fourth terminal is connected to the die pad.
  • Appendix 12 The semiconductor device according to appendix 11, wherein the die pad is exposed from the sealing resin.
  • Appendix 14. the fourth terminal is separated from the first terminal in the third direction, The semiconductor device according to attachment 13, wherein the second electrode is conductively bonded to the fourth terminal.
  • the sealing resin has a bottom surface facing the first direction, The semiconductor device according to appendix 14, wherein the first terminal, the second terminal, the third terminal, and the fourth terminal are exposed from the bottom surface.
  • the sealing resin has two first side surfaces facing opposite to each other in the third direction, The semiconductor device according to appendix 15, wherein the first terminal, the second terminal, the third terminal, and the fourth terminal are exposed from either of the two first side surfaces.

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Abstract

The present invention provides a semiconductor device which is provided with a semiconductor element that has a first electrode and a gate electrode. This semiconductor device is additionally provided with: a first terminal that is electrically connected to the first electrode; a second terminal that is electrically connected to the gate electrode; and a third terminal that is electrically connected to the first electrode. The direction of the electric current flowing through the first terminal and the third terminal is opposite to the direction of the electric current flowing through the second terminal. The second terminal is positioned adjacent to the first terminal. The third terminal is positioned opposite to the first terminal with respect to the second terminal.

Description

半導体装置semiconductor equipment
　本開示は、半導体装置に関する。 The present disclosure relates to a semiconductor device.
　特許文献１には、ＭＯＳＦＥＴが搭載された半導体装置の一例が開示されている。当該半導体装置は、電源電圧が印加されるドレイン端子と、ＭＯＳＦＥＴに電気信号を入力するためのゲート端子と、当該電源電圧に対応した電力が当該電気信号に基づき変換された後、変換された電力が出力されるソース端子とを備える。ＭＯＳＦＥＴは、ドレイン端子に導通するドレイン電極と、ソース端子に導通するソース電極とを有する。ドレイン電極は、第１導電性接合材によりドレイン端子につながるダイパッドに接合されている。ソース電極は、第２導電性接合材により金属クリップに接合されている。さらに金属クリップは、ソース端子にも接合されている。第１導電性接合材および第２導電性接合材は、ともにハンダである。これにより、当該半導体装置に、より大きな電流を流すことが可能となっている。 Patent Document 1 discloses an example of a semiconductor device equipped with a MOSFET. The semiconductor device includes a drain terminal to which a power supply voltage is applied, a gate terminal for inputting an electrical signal to the MOSFET, and a terminal for converting the converted power after the power corresponding to the power supply voltage is converted based on the electrical signal. and a source terminal from which is output. A MOSFET has a drain electrode electrically connected to a drain terminal and a source electrode electrically connected to a source terminal. The drain electrode is bonded to a die pad connected to the drain terminal by a first conductive bonding material. The source electrode is bonded to the metal clip by a second conductive bonding material. Additionally, the metal clip is also bonded to the source terminal. Both the first conductive bonding material and the second conductive bonding material are solder. This allows a larger current to flow through the semiconductor device.
　ここで、特許文献１に開示されている半導体装置においては、ゲート端子に流れる電流の速度に対応して、ＭＯＳＦＥＴにスイッチング損失が生じる。スイッチング損失が大きくなるほど、ＭＯＳＦＥＴに電力が入力されてからソース端子に電力が出力されるまでの時間が長くなり、かつＭＯＳＦＥＴの電力消費量が増加する。このことは、当該半導体装置を用いた電力変換において、その変換効率の低下を招く要因となる。したがって、ＭＯＳＦＥＴのスイッチング損失を低減することが望まれる。 Here, in the semiconductor device disclosed in Patent Document 1, switching loss occurs in the MOSFET corresponding to the speed of the current flowing to the gate terminal. As the switching loss increases, the time from when power is input to the MOSFET until the power is output to the source terminal becomes longer, and the power consumption of the MOSFET increases. This becomes a factor that causes a decrease in conversion efficiency in power conversion using the semiconductor device. Therefore, it is desirable to reduce the switching loss of MOSFETs.
特開２０１６－１９２４５０号公報Japanese Patent Application Publication No. 2016-192450
　本開示は、従来よりも改良が施された半導体装置を提供することを一の課題とする。特に本開示は、上記事情に鑑み、半導体素子のスイッチング損失を低減することが可能な半導体装置を提供することを一の課題とする。 An object of the present disclosure is to provide a semiconductor device that is improved over conventional ones. In particular, in view of the above circumstances, an object of the present disclosure is to provide a semiconductor device that can reduce switching loss of a semiconductor element.
　本開示の第１の側面によって提供される半導体装置は、第１電極およびゲート電極を有する半導体素子と、前記第１電極に導通する第１端子と、前記ゲート電極に導通する第２端子と、前記第１電極に導通する第３端子と、を備える。前記第１端子および前記第３端子の各々に流れる電流の向きは、前記第２端子に流れる電流の向きとは逆である。前記第２端子は、前記第１端子の隣に位置している。前記第３端子は、前記第２端子を基準として前記第１端子とは反対側に位置する。 A semiconductor device provided by a first aspect of the present disclosure includes a semiconductor element having a first electrode and a gate electrode, a first terminal electrically connected to the first electrode, and a second terminal electrically connected to the gate electrode. and a third terminal electrically connected to the first electrode. The direction of the current flowing through each of the first terminal and the third terminal is opposite to the direction of the current flowing through the second terminal. The second terminal is located next to the first terminal. The third terminal is located on the opposite side of the first terminal with respect to the second terminal.
　上記構成によれば、半導体装置において半導体素子のスイッチング損失を低減することが可能となる。 According to the above configuration, it is possible to reduce the switching loss of the semiconductor element in the semiconductor device.
　本開示のその他の特徴および利点は、添付図面に基づき以下に行う詳細な説明によって、より明らかとなろう。 Other features and advantages of the present disclosure will become more apparent from the detailed description given below with reference to the accompanying drawings.
図１は、本開示の第１実施形態にかかる半導体装置の斜視図である。FIG. 1 is a perspective view of a semiconductor device according to a first embodiment of the present disclosure. 図２は、図１に示す半導体装置の平面図である。FIG. 2 is a plan view of the semiconductor device shown in FIG. 1. 図３は、図２に対応する平面図であり、封止樹脂を透過している。FIG. 3 is a plan view corresponding to FIG. 2, in which the sealing resin is seen through. 図４は、図１に示す半導体装置の底面図である。FIG. 4 is a bottom view of the semiconductor device shown in FIG. 1. 図５は、図１に示す半導体装置の正面図である。FIG. 5 is a front view of the semiconductor device shown in FIG. 1. 図６は、図３のＶＩ－ＶＩ線に沿う断面図である。FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. 図７は、図３のＶＩＩ－ＶＩＩ線に沿う断面図である。FIG. 7 is a sectional view taken along line VII-VII in FIG. 3. 図８は、図３のＶＩＩＩ－ＶＩＩＩ線に沿う断面図である。FIG. 8 is a cross-sectional view taken along line VIII-VIII in FIG. 3. 図９は、図６の部分拡大図である。FIG. 9 is a partially enlarged view of FIG. 6. 図１０は、図１に示す半導体装置の作用効果を説明する平面図であり、図３に対応している。FIG. 10 is a plan view illustrating the effects of the semiconductor device shown in FIG. 1, and corresponds to FIG. 3. 図１１は、本開示の第２実施形態にかかる半導体装置の平面図であり、封止樹脂を透過している。FIG. 11 is a plan view of a semiconductor device according to a second embodiment of the present disclosure, through which the sealing resin is seen. 図１２は、図１１に示す半導体装置の底面図である。FIG. 12 is a bottom view of the semiconductor device shown in FIG. 11. 図１３は、図１１に示す半導体装置の正面図である。FIG. 13 is a front view of the semiconductor device shown in FIG. 11. 図１４は、図１１に示す半導体装置の背面図である。FIG. 14 is a rear view of the semiconductor device shown in FIG. 11. 図１５は、図１１に示す半導体装置の右側面図である。FIG. 15 is a right side view of the semiconductor device shown in FIG. 11. 図１６は、図１１のＸＶＩ－ＸＶＩ線に沿う断面図である。FIG. 16 is a cross-sectional view taken along line XVI-XVI in FIG. 11. 図１７は、図１１のＸＶＩＩ－ＸＶＩＩ線に沿う断面図である。FIG. 17 is a cross-sectional view taken along line XVII-XVII in FIG. 11. 図１８は、図１１のＸＶＩＩＩ－ＸＶＩＩＩ線に沿う断面図である。FIG. 18 is a cross-sectional view taken along line XVIII-XVIII in FIG. 11. 図１９は、図１６の部分拡大図である。FIG. 19 is a partially enlarged view of FIG. 16. 図２０は、図１１に示す半導体装置の作用効果を説明する平面図であり、図１１に対応している。FIG. 20 is a plan view illustrating the function and effect of the semiconductor device shown in FIG. 11, and corresponds to FIG.
　本開示を実施するための形態について、添付図面に基づいて説明する。 A mode for carrying out the present disclosure will be described based on the accompanying drawings.
　第１実施形態：
　図１～図１０に基づき、本開示の第１実施形態にかかる半導体装置Ａ１０について説明する。一般的に半導体装置Ａ１０は、インバータなどの電力変換回路に用いられる。半導体装置Ａ１０のパッケージ形式は、ＴＯ（Transistor Outline）である。半導体装置Ａ１０は、半導体素子１０、ダイパッド２０、第１端子２１、第２端子２２、第３端子２３、第４端子２４、導電接合層２９、第１導通部材３１、第２導通部材３２、第３導通部材３３および封止樹脂４０を備える。ここで、図３は、理解の便宜上、封止樹脂４０を透過している。図３では、透過した封止樹脂４０を想像線（二点鎖線）で示している。 First embodiment:
A semiconductor device A10 according to a first embodiment of the present disclosure will be described based on FIGS. 1 to 10. Generally, the semiconductor device A10 is used in a power conversion circuit such as an inverter. The package format of the semiconductor device A10 is TO (Transistor Outline). The semiconductor device A10 includes a semiconductor element 10, a die pad 20, a first terminal 21, a second terminal 22, a third terminal 23, a fourth terminal 24, a conductive bonding layer 29, a first conductive member 31, a second conductive member 32, and a third conductive member 32. 3 conductive member 33 and sealing resin 40. Here, in FIG. 3, for convenience of understanding, the sealing resin 40 is shown. In FIG. 3, the transparent sealing resin 40 is shown by an imaginary line (two-dot chain line).
　半導体装置Ａ１０の説明においては、便宜上、後述するダイパッド２０の搭載面２０１の法線方向を「第１方向ｚ」と呼ぶ。第１方向ｚに対して直交する１つの方向を「第２方向ｘ」と呼ぶ。第１方向ｚおよび第２方向ｘの双方に対して直交する方向を「第３方向ｙ」と呼ぶ。 In the description of the semiconductor device A10, for convenience, the normal direction of the mounting surface 201 of the die pad 20, which will be described later, will be referred to as a "first direction z." One direction perpendicular to the first direction z is called a "second direction x." A direction perpendicular to both the first direction z and the second direction x is referred to as a "third direction y."
　半導体素子１０は、たとえばＭＯＳＦＥＴ（Metal-Oxide-Semiconductor Field-Effect Transistor）である。この他、半導体素子１０は、ＭＩＳＦＥＴ（Metal-Insulator-Semiconductor Field-Effect Transistor）を含む電界効果トランジスタや、ＩＧＢＴ（Insulated Gate Bipolar Transistor）のようなバイポーラトランジスタでもよい。半導体装置Ａ１０の説明においては、半導体素子１０は、ｎチャネル型であり、かつ縦型構造のＭＯＳＦＥＴを対象とする。複数の半導体素子１０は、化合物半導体基板を含む。当該化合物半導体基板の組成は、炭化ケイ素（ＳｉＣ）を含む。 The semiconductor element 10 is, for example, a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). In addition, the semiconductor element 10 may be a field effect transistor including a MISFET (Metal-Insulator-Semiconductor Field-Effect Transistor) or a bipolar transistor such as an IGBT (Insulated Gate Bipolar Transistor). In the description of the semiconductor device A10, the semiconductor element 10 is an n-channel type MOSFET with a vertical structure. The plurality of semiconductor elements 10 include a compound semiconductor substrate. The composition of the compound semiconductor substrate includes silicon carbide (SiC).
　図３および図９に示すように、半導体素子１０は、第１電極１１、ゲート電極１２および第２電極１３を有する。 As shown in FIGS. 3 and 9, the semiconductor element 10 has a first electrode 11, a gate electrode 12, and a second electrode 13.
　図３および図９に示すように、第１電極１１は、半導体素子１０の第１方向ｚの一方側に位置する。第１電極１１には、半導体素子１０により変換された後の電力に対応する電流が流れる。すなわち、第１電極１１は、半導体素子１０のソース電極に相当する。 As shown in FIGS. 3 and 9, the first electrode 11 is located on one side of the semiconductor element 10 in the first direction z. A current corresponding to the power converted by the semiconductor element 10 flows through the first electrode 11 . That is, the first electrode 11 corresponds to the source electrode of the semiconductor element 10.
　図３に示すように、第１電極１１は、第１部１１１、および２つの第２部１１２を含む。２つの第２部１１２は、第１部１１１の第２方向ｘの一方側に位置する。２つの第２部１１２は、第３方向ｙにおいて互いに離れている。第１方向ｚに視て、２つの第２部１１２の各々の面積は、第１部１１１の面積よりも小さい。 As shown in FIG. 3, the first electrode 11 includes a first part 111 and two second parts 112. The two second parts 112 are located on one side of the first part 111 in the second direction x. The two second parts 112 are separated from each other in the third direction y. The area of each of the two second parts 112 is smaller than the area of the first part 111 when viewed in the first direction z.
　図９に示すように、第２電極１３は、第１方向ｚにおいて第１電極１１とは反対側に位置する。第２電極１３には、半導体素子１０により変換される前の電力に対応する電流が流れる。すなわち、第２電極１３は、半導体素子１０のドレイン電極に相当する。 As shown in FIG. 9, the second electrode 13 is located on the opposite side from the first electrode 11 in the first direction z. A current corresponding to the power before being converted by the semiconductor element 10 flows through the second electrode 13 . That is, the second electrode 13 corresponds to the drain electrode of the semiconductor element 10.
　図３に示すように、ゲート電極１２は、第１方向ｚにおいて第１電極１１と同じ側に位置する。ゲート電極１２は、第３方向ｙにおいて第１電極１１の２つの第２部１１２の間に位置する。ゲート電極１２には、半導体素子１０を駆動するためのゲート電圧が印加される。第１方向ｚに視て、ゲート電極１２の面積は、第１電極１１の第１部１１１の面積よりも小さい。 As shown in FIG. 3, the gate electrode 12 is located on the same side as the first electrode 11 in the first direction z. The gate electrode 12 is located between the two second parts 112 of the first electrode 11 in the third direction y. A gate voltage for driving the semiconductor element 10 is applied to the gate electrode 12 . The area of the gate electrode 12 is smaller than the area of the first portion 111 of the first electrode 11 when viewed in the first direction z.
　ダイパッド２０は、図３、および図６～図８に示すように、半導体素子１０を搭載する導電部材である。ダイパッド２０は、第１端子２１、第２端子２２、第３端子２３および第４端子２４とともに、同一のリードフレームから構成されている。当該リードフレームは、銅（Ｃｕ）、または銅合金である。このため、ダイパッド２０、第１端子２１、第２端子２２、第３端子２３および第４端子２４の各々の組成は、銅を含む。図６に示すように、ダイパッド２０は、搭載面２０１、裏面２０２および貫通孔２０３を有する。搭載面２０１は、第１方向ｚを向く。搭載面２０１は、半導体素子１０の第２電極１３に対向している。裏面２０２は、第１方向ｚにおいて搭載面２０１とは反対側を向く。裏面２０２には、たとえば錫（Ｓｎ）めっきが施されている。貫通孔２０３は、第１方向ｚにおいて搭載面２０１から裏面２０２に至ってダイパッド２０を貫通している。貫通孔２０３は、第１方向ｚに視て円形状である。 The die pad 20 is a conductive member on which the semiconductor element 10 is mounted, as shown in FIG. 3 and FIGS. 6 to 8. The die pad 20, together with the first terminal 21, the second terminal 22, the third terminal 23, and the fourth terminal 24, are constructed from the same lead frame. The lead frame is made of copper (Cu) or a copper alloy. Therefore, the composition of each of the die pad 20, the first terminal 21, the second terminal 22, the third terminal 23, and the fourth terminal 24 includes copper. As shown in FIG. 6, the die pad 20 has a mounting surface 201, a back surface 202, and a through hole 203. The mounting surface 201 faces in the first direction z. The mounting surface 201 faces the second electrode 13 of the semiconductor element 10. The back surface 202 faces the opposite side from the mounting surface 201 in the first direction z. The back surface 202 is plated with tin (Sn), for example. The through hole 203 extends through the die pad 20 from the mounting surface 201 to the back surface 202 in the first direction z. The through hole 203 has a circular shape when viewed in the first direction z.
　導電接合層２９は、図６および図７に示すように、ダイパッド２０と半導体素子１０とを接合している。半導体装置Ａ１０においては、導電接合層２９は、ダイパッド２０の搭載面２０１と、半導体素子１０の第２電極１３とを導電接合している。これにより、第２電極１３がダイパッド２０に導通している。導電接合層２９は、たとえばハンダである。この他、導電接合層２９は、焼結金属でもよい。 The conductive bonding layer 29 bonds the die pad 20 and the semiconductor element 10, as shown in FIGS. 6 and 7. In the semiconductor device A10, the conductive bonding layer 29 conductively bonds the mounting surface 201 of the die pad 20 and the second electrode 13 of the semiconductor element 10. Thereby, the second electrode 13 is electrically connected to the die pad 20. The conductive bonding layer 29 is, for example, solder. In addition, the conductive bonding layer 29 may be made of sintered metal.
　第１端子２１は、図３および図６に示すように、ダイパッド２０から離れて位置する。第１端子２１は、第３方向ｙに延びている。第１端子２１は、半導体素子１０の第１電極１１の第１部１１１に導通している。したがって、第１端子２１は、半導体装置Ａ１０のソース端子に相当する。 The first terminal 21 is located away from the die pad 20, as shown in FIGS. 3 and 6. The first terminal 21 extends in the third direction y. The first terminal 21 is electrically connected to the first portion 111 of the first electrode 11 of the semiconductor element 10 . Therefore, the first terminal 21 corresponds to the source terminal of the semiconductor device A10.
　図３および図６に示すように、第１端子２１は、被覆部２１１、露出部２１２および第１接合面２１３を有する。被覆部２１１は、封止樹脂４０に覆われている。露出部２１２は、被覆部２１１につながり、かつ封止樹脂４０から露出している。露出部２１２は、第３方向ｙにおいてダイパッド２０から遠ざかる側に延びている。露出部２１２の表面には、たとえば錫めっきが施されている。第１接合面２１３は、第１方向ｚにおいてダイパッド２０の搭載面２０１と同じ側を向く。第１接合面２１３は、被覆部２１１の一部に含まれる。第１接合面２１３は、搭載面２０１に対して第１方向ｚにおいて半導体素子１０が位置する側に位置する。 As shown in FIGS. 3 and 6, the first terminal 21 has a covering portion 211, an exposed portion 212, and a first bonding surface 213. The covering portion 211 is covered with a sealing resin 40. The exposed portion 212 is connected to the covering portion 211 and exposed from the sealing resin 40 . The exposed portion 212 extends away from the die pad 20 in the third direction y. The surface of the exposed portion 212 is plated with tin, for example. The first bonding surface 213 faces the same side as the mounting surface 201 of the die pad 20 in the first direction z. The first bonding surface 213 is included in a part of the covering portion 211. The first bonding surface 213 is located on the side where the semiconductor element 10 is located with respect to the mounting surface 201 in the first direction z.
　第２端子２２は、図３および図７に示すように、ダイパッド２０から離れて位置する。第２端子２２は、第３方向ｙに延びている。第２端子２２は、第１端子２１の隣に位置する。第２端子２２は、半導体素子１０のゲート電極１２に導通している。したがって、第２端子２２は、半導体装置Ａ１０のゲート端子に相当する。第２端子２２に流れる電流の向きは、第１端子２１に流れる電流の向きとは逆である。 The second terminal 22 is located away from the die pad 20, as shown in FIGS. 3 and 7. The second terminal 22 extends in the third direction y. The second terminal 22 is located next to the first terminal 21. The second terminal 22 is electrically connected to the gate electrode 12 of the semiconductor element 10 . Therefore, the second terminal 22 corresponds to the gate terminal of the semiconductor device A10. The direction of the current flowing through the second terminal 22 is opposite to the direction of the current flowing through the first terminal 21.
　図３および図７に示すように、第２端子２２は、被覆部２２１、露出部２２２および第２接合面２２３を有する。被覆部２２１は、封止樹脂４０に覆われている。露出部２２２は、被覆部２２１につながり、かつ封止樹脂４０から露出している。露出部２２２は、第３方向ｙにおいてダイパッド２０から遠ざかる側に延びている。露出部２２２の表面には、錫めっきが施されている。第２接合面２２３は、第１方向ｚにおいてダイパッド２０の搭載面２０１と同じ側を向く。第２接合面２２３は、被覆部２２１の一部に含まれる。第１方向ｚにおいて、第２接合面２２３の位置は、第１端子２１の第１接合面２１３の位置と同一である。 As shown in FIGS. 3 and 7, the second terminal 22 has a covering portion 221, an exposed portion 222, and a second bonding surface 223. The covering portion 221 is covered with a sealing resin 40. The exposed portion 222 is connected to the covering portion 221 and exposed from the sealing resin 40 . The exposed portion 222 extends away from the die pad 20 in the third direction y. The surface of the exposed portion 222 is plated with tin. The second bonding surface 223 faces the same side as the mounting surface 201 of the die pad 20 in the first direction z. The second bonding surface 223 is included in a part of the covering portion 221. In the first direction z, the position of the second joint surface 223 is the same as the position of the first joint surface 213 of the first terminal 21 .
　第３端子２３は、図３に示すように、ダイパッド２０から離れて位置する。第２端子２２は、第３端子２３は、第３方向ｙに延びている。第３端子２３は、第２端子２２を基準として第１端子２１とは反対側に位置する。第３端子２３は、第２端子２２の隣に位置する。第３端子２３は、半導体素子１０の第１電極１１の２つの第２部１１２のいずれかに導通している。したがって、第３端子２３には、第１端子２１に印加される電圧と等電位の電圧が印加される。第３端子２３に流れる電流の向きは、第１端子２１に流れる電流の向きと同じである。 The third terminal 23 is located away from the die pad 20, as shown in FIG. The second terminal 22 and the third terminal 23 extend in the third direction y. The third terminal 23 is located on the opposite side of the first terminal 21 with respect to the second terminal 22. The third terminal 23 is located next to the second terminal 22. The third terminal 23 is electrically connected to either of the two second portions 112 of the first electrode 11 of the semiconductor element 10 . Therefore, a voltage having the same potential as the voltage applied to the first terminal 21 is applied to the third terminal 23 . The direction of the current flowing through the third terminal 23 is the same as the direction of the current flowing through the first terminal 21.
　図３に示すように、第３端子２３は、被覆部２３１、露出部２３２および第３接合面２３３を有する。被覆部２３１は、封止樹脂４０に覆われている。露出部２３２は、被覆部２３１につながり、かつ封止樹脂４０から露出している。露出部２３２は、第３方向ｙにおいてダイパッド２０から遠ざかる側に延びている。露出部２３２の表面には、錫めっきが施されている。第３接合面２３３は、第１方向ｚにおいてダイパッド２０の搭載面２０１と同じ側を向く。第３接合面２３３は、被覆部２３１の一部に含まれる。第１方向ｚにおいて、第３接合面２３３の位置は、第１端子２１の第１接合面２１３の位置と同一である。 As shown in FIG. 3, the third terminal 23 has a covering portion 231, an exposed portion 232, and a third bonding surface 233. The covering portion 231 is covered with a sealing resin 40. The exposed portion 232 is connected to the covering portion 231 and exposed from the sealing resin 40 . The exposed portion 232 extends away from the die pad 20 in the third direction y. The surface of the exposed portion 232 is plated with tin. The third bonding surface 233 faces the same side as the mounting surface 201 of the die pad 20 in the first direction z. The third joint surface 233 is included in a part of the covering portion 231. In the first direction z, the position of the third joint surface 233 is the same as the position of the first joint surface 213 of the first terminal 21 .
　第４端子２４は、図３および図８に示すように、第２方向ｘにおいて第１端子２１を基準として第２端子２２とは反対側に位置する。第４端子２４は、第３方向ｙに延びる部分を含むとともに、ダイパッド２０につながっている。これにより、第４端子２４は、半導体素子１０の第２電極１３に導通している。したがって、第４端子２４は、半導体装置Ａ１０のドレイン端子に相当する。第４端子２４に流れる電流の向きは、第１端子２１に流れる電流の向きとは逆である。 As shown in FIGS. 3 and 8, the fourth terminal 24 is located on the opposite side of the second terminal 22 with respect to the first terminal 21 in the second direction x. The fourth terminal 24 includes a portion extending in the third direction y, and is connected to the die pad 20. Thereby, the fourth terminal 24 is electrically connected to the second electrode 13 of the semiconductor element 10. Therefore, the fourth terminal 24 corresponds to the drain terminal of the semiconductor device A10. The direction of the current flowing through the fourth terminal 24 is opposite to the direction of the current flowing through the first terminal 21.
　図３および図８に示すように、第４端子２４は、被覆部２４１および露出部２４２を有する。被覆部２４１は、ダイパッド２０につながり、かつ封止樹脂４０に覆われている。第２方向ｘに視て、被覆部２４１は、屈曲している。露出部２４２は、被覆部２４１につながり、かつ封止樹脂４０から露出している。露出部２４２は、第３方向ｙにおいてダイパッド２０から遠ざかる側に延びている。露出部２４２の表面には、錫めっきが施されている。 As shown in FIGS. 3 and 8, the fourth terminal 24 has a covering portion 241 and an exposed portion 242. The covering portion 241 is connected to the die pad 20 and covered with the sealing resin 40 . The covering portion 241 is bent when viewed in the second direction x. The exposed portion 242 is connected to the covering portion 241 and exposed from the sealing resin 40 . The exposed portion 242 extends away from the die pad 20 in the third direction y. The surface of the exposed portion 242 is plated with tin.
　図３に示すように、第１端子２１、第２端子２２、第３端子２３および第４端子２４は、第２方向ｘに沿って配列されている。図３および図５に示すように、第１端子２１および第４端子２４の各々の封止樹脂４０から露出した部分（露出部２１２および露出部２４２）の最小間隔ｄ１は、第１端子２１および第２端子２２の各々の封止樹脂４０から露出した部分（露出部２１２および露出部２２２）の最小間隔ｄ２よりも大きい。図５に示すように、封止樹脂４０から露出した第１端子２１、第２端子２２、第３端子２３および第４端子２４の各々の封止樹脂４０から露出した部分の高さｈは、いずれも等しい。 As shown in FIG. 3, the first terminal 21, second terminal 22, third terminal 23, and fourth terminal 24 are arranged along the second direction x. As shown in FIGS. 3 and 5, the minimum distance d1 between the portions of the first terminal 21 and the fourth terminal 24 exposed from the sealing resin 40 (the exposed portion 212 and the exposed portion 242) is It is larger than the minimum interval d2 between the portions of the second terminals 22 exposed from the sealing resin 40 (the exposed portions 212 and the exposed portions 222). As shown in FIG. 5, the height h of the portion of each of the first terminal 21, second terminal 22, third terminal 23, and fourth terminal 24 exposed from the sealing resin 40 is as follows: Both are equal.
　第１導通部材３１は、図３および図６に示すように、半導体素子１０の第１電極１１の第１部１１１と、第１端子２１の第１接合面２１３とに導電接合されている。これにより、第１端子２１は、第１電極１１の第１部１１１に導通している。半導体装置Ａ１０においては、第１導通部材３１は、アルミニウム（Ａｌ）を含有する複数のワイヤである。この他、第１導通部材３１は、銅を含有する複数のワイヤ、あるいは銅を含有する金属クリップでもよい。 The first conductive member 31 is electrically conductively bonded to the first portion 111 of the first electrode 11 of the semiconductor element 10 and the first bonding surface 213 of the first terminal 21, as shown in FIGS. 3 and 6. Thereby, the first terminal 21 is electrically connected to the first portion 111 of the first electrode 11 . In the semiconductor device A10, the first conductive member 31 is a plurality of wires containing aluminum (Al). In addition, the first conductive member 31 may be a plurality of wires containing copper or a metal clip containing copper.
　第２導通部材３２は、図３および図７に示すように、半導体素子１０のゲート電極１２と、第２端子２２の第２接合面２２３とに導電接合されている。これにより、第２端子２２は、ゲート電極１２に導通している。第２導通部材３２は、たとえば、アルミニウムおよび金（Ａｕ）のいずれかを含有するワイヤである。 The second conductive member 32 is electrically bonded to the gate electrode 12 of the semiconductor element 10 and the second bonding surface 223 of the second terminal 22, as shown in FIGS. 3 and 7. Thereby, the second terminal 22 is electrically connected to the gate electrode 12. The second conductive member 32 is, for example, a wire containing either aluminum or gold (Au).
　第３導通部材３３は、図３に示すように、半導体素子１０の第１電極１１の２つの第２部１１２のいずれかと、第３端子２３の第３接合面２３３とに導電接合されている。これにより、第３端子２３は、第１電極１１の２つの第２部１１２のいずれかに導通している。第３導通部材３３は、たとえば、アルミニウムおよび金のいずれかを含有するワイヤである。 As shown in FIG. 3, the third conductive member 33 is conductively bonded to one of the two second parts 112 of the first electrode 11 of the semiconductor element 10 and the third bonding surface 233 of the third terminal 23. . Thereby, the third terminal 23 is electrically connected to either of the two second portions 112 of the first electrode 11 . The third conductive member 33 is, for example, a wire containing either aluminum or gold.
　図３に示すように、第２導通部材３２は、第１導通部材３１の隣に位置する。さらに第２導通部材３２は、第１導通部材３１と第３導通部材３３との間に位置する区間を含む。図３に示すように、半導体装置Ａ１０においては、第１端子２１の第３方向ｙの寸法は、第１導通部材３１の導電経路長よりも大きい。あわせて第２端子２２の第３方向ｙの寸法は、第２導通部材３２の導電経路長よりも大きい。 As shown in FIG. 3, the second conductive member 32 is located next to the first conductive member 31. Further, the second conductive member 32 includes a section located between the first conductive member 31 and the third conductive member 33. As shown in FIG. 3, in the semiconductor device A10, the dimension of the first terminal 21 in the third direction y is larger than the conductive path length of the first conductive member 31. Additionally, the dimension of the second terminal 22 in the third direction y is larger than the length of the conductive path of the second conductive member 32.
　封止樹脂４０は、図３、図６および図７に示すように、半導体素子１０、第１導通部材３１および第２導通部材３２を覆っている。図６～図８に示すように、封止樹脂４０は、ダイパッド２０、第１端子２１、第２端子２２および第４端子２４の各々の一部を覆っている。さらに封止樹脂４０は、第３導通部材３３を覆うとともに、第３端子２３の一部を覆っている。封止樹脂４０は、電気絶縁性を有する。封止樹脂４０は、たとえば黒色のエポキシ樹脂を含む材料からなる。封止樹脂４０は、頂面４１、底面４２、２つの第１側面４３、２つの第２側面４４、２つの開口４５、および取付け孔４６を有する。 The sealing resin 40 covers the semiconductor element 10, the first conductive member 31, and the second conductive member 32, as shown in FIGS. 3, 6, and 7. As shown in FIGS. 6 to 8, the sealing resin 40 partially covers each of the die pad 20, the first terminal 21, the second terminal 22, and the fourth terminal 24. As shown in FIGS. Further, the sealing resin 40 covers the third conductive member 33 and also partially covers the third terminal 23 . The sealing resin 40 has electrical insulation properties. The sealing resin 40 is made of a material containing, for example, a black epoxy resin. The sealing resin 40 has a top surface 41 , a bottom surface 42 , two first side surfaces 43 , two second side surfaces 44 , two openings 45 , and a mounting hole 46 .
　図６～図８に示すように、頂面４１は、第１方向ｚにおいてダイパッド２０の搭載面２０１と同じ側を向く。図６～図８に示すように、底面４２は、第１方向ｚにおいて頂面４１とは反対側を向く。底面４２からダイパッド２０の裏面２０２が露出している。 As shown in FIGS. 6 to 8, the top surface 41 faces the same side as the mounting surface 201 of the die pad 20 in the first direction z. As shown in FIGS. 6 to 8, the bottom surface 42 faces opposite to the top surface 41 in the first direction z. The back surface 202 of the die pad 20 is exposed from the bottom surface 42.
　図２および図４に示すように、２つの第１側面４３は、第３方向ｙにおいて互いに離れて位置する。２つの第１側面４３の各々は、頂面４１および底面４２につながっている。２つの第１側面４３のうち一方の当該第１側面４３から、第１端子２１の露出部２１２、第２端子２２の露出部２２２、および第４端子２４の露出部２３２が露出している。 As shown in FIGS. 2 and 4, the two first side surfaces 43 are located apart from each other in the third direction y. Each of the two first side surfaces 43 is connected to the top surface 41 and the bottom surface 42. From one of the two first side surfaces 43, the exposed portion 212 of the first terminal 21, the exposed portion 222 of the second terminal 22, and the exposed portion 232 of the fourth terminal 24 are exposed.
　図２および図４に示すように、２つの第２側面４４は、第２方向ｘにおいて互いに離れて位置する。２つの第２側面４４の各々は、頂面４１および底面４２につながっている。図２に示すように、２つの開口４５は、第２方向ｘにおいて互いに離れて位置する。２つの開口４５の各々は、頂面４１と、２つの第２側面４４のいずれかとの双方から封止樹脂４０の内方に向けて凹んでいる。２つの開口４５の各々から、ダイパッド２０の搭載面２０１の一部が露出している。図２、図４および図８に示すように、取付け孔４６は、第１方向ｚにおいて頂面４１から底面４２に至って封止樹脂４０を貫通している。第１方向ｚに視て、取付け孔４６は、ダイパッド２０の貫通孔２０３に内包されている。貫通孔２０３を規定するダイパッド２０の周面は、封止樹脂４０に覆われている。これにより、第１方向ｚに視て、取付け孔４６の最大寸法は、貫通孔２０３の寸法よりも小さい。 As shown in FIGS. 2 and 4, the two second side surfaces 44 are located apart from each other in the second direction x. Each of the two second side surfaces 44 is connected to the top surface 41 and the bottom surface 42. As shown in FIG. 2, the two openings 45 are located apart from each other in the second direction x. Each of the two openings 45 is recessed inward from the sealing resin 40 from both the top surface 41 and one of the two second side surfaces 44 . A portion of the mounting surface 201 of the die pad 20 is exposed from each of the two openings 45. As shown in FIGS. 2, 4, and 8, the attachment hole 46 penetrates the sealing resin 40 from the top surface 41 to the bottom surface 42 in the first direction z. The attachment hole 46 is included in the through hole 203 of the die pad 20 when viewed in the first direction z. The peripheral surface of the die pad 20 that defines the through hole 203 is covered with a sealing resin 40 . As a result, the maximum dimension of the attachment hole 46 is smaller than the dimension of the through hole 203 when viewed in the first direction z.
　次に、半導体装置Ａ１０の作用効果について説明する。 Next, the effects of the semiconductor device A10 will be explained.
　半導体装置Ａ１０は、第１電極１１およびゲート電極１２を有する半導体素子１０と、第１電極１１に導通する第１端子２１と、ゲート電極１２に導通する第２端子２２と、第１電極１１に導通する第３端子２３とを備える。第１端子２１および第３端子２３の各々に流れる電流の向きは、第２端子２２に流れる電流の向きとは逆である。第２端子２２は、第１端子２１の隣に位置する。第３端子２３は、第２端子２２を基準として第１端子２１とは反対側に位置する。 The semiconductor device A10 includes a semiconductor element 10 having a first electrode 11 and a gate electrode 12, a first terminal 21 electrically connected to the first electrode 11, a second terminal 22 electrically connected to the gate electrode 12, and a semiconductor element 10 having a first electrode 11 and a gate electrode 12. The third terminal 23 is electrically connected. The direction of the current flowing through each of the first terminal 21 and the third terminal 23 is opposite to the direction of the current flowing through the second terminal 22. The second terminal 22 is located next to the first terminal 21. The third terminal 23 is located on the opposite side of the first terminal 21 with respect to the second terminal 22.
　ここで、半導体装置Ａ１０においては、図１０に示すように、第１電極１１の駆動に伴い、第１端子２１には出力電流Ｉdが流れる。出力電流Ｉdは、その大きさが時間変化するいわゆる非定常電流である。したがって、第１端子２１の周りには、磁束Ｍが形成される。そこで、本構成をとることにより、第２端子２２には、磁束Ｍに起因した電磁誘導により誘導起電力ＶMが作用する。誘導起電力ＶMの向きは、第２端子２２に流れる電流の向きに等しい。このため、第２端子２２に流れる電流は、誘導起電力ＶMにより加速される。これにより、半導体素子１０のオン・オフのそれぞれにかかる所要時間が短縮されるとともに、オン・オフに必要な電力消費量が縮減される。さらに、第１端子２１と第３端子２３との相互誘導に起因した、第２端子２２に作用する誘導起電力ＶMの低下が抑制される。したがって、本構成によれば、半導体装置Ａ１０においては、半導体素子１０のスイッチング損失を低減することが可能となる。 Here, in the semiconductor device A10, as shown in FIG. 10, an output current I d flows through the first terminal 21 as the first electrode 11 is driven. The output current I d is a so-called unsteady current whose magnitude changes over time. Therefore, a magnetic flux M is formed around the first terminal 21. Therefore, by adopting this configuration, an induced electromotive force V M acts on the second terminal 22 due to electromagnetic induction caused by the magnetic flux M. The direction of the induced electromotive force V M is equal to the direction of the current flowing through the second terminal 22. Therefore, the current flowing to the second terminal 22 is accelerated by the induced electromotive force V M . As a result, the time required to turn on and off the semiconductor element 10 is shortened, and the power consumption required for turning on and off is reduced. Furthermore, a decrease in the induced electromotive force V M acting on the second terminal 22 due to mutual induction between the first terminal 21 and the third terminal 23 is suppressed. Therefore, according to this configuration, in the semiconductor device A10, it is possible to reduce the switching loss of the semiconductor element 10.
　半導体装置Ａ１０は、封止樹脂４０に覆われた第１導通部材３１、第２導通部材３２および第３導通部材３３をさらに備える。第２導通部材３２は、第１導通部材３１の隣に位置する。本構成をとることにより、第１導通部材３１に流れる出力電流Ｉdによって、第２導通部材３２にも誘導起電力ＶMが作用する（図１０参照）。これにより、第２端子２２に流れる電流がさらに加速されるため、半導体素子１０のスイッチング損失を効果的に低減することが可能となる。 The semiconductor device A10 further includes a first conductive member 31, a second conductive member 32, and a third conductive member 33 covered with a sealing resin 40. The second conductive member 32 is located next to the first conductive member 31. With this configuration, the induced electromotive force V M also acts on the second conductive member 32 due to the output current I d flowing through the first conductive member 31 (see FIG. 10). This further accelerates the current flowing through the second terminal 22, making it possible to effectively reduce the switching loss of the semiconductor element 10.
　第２導通部材３２は、第１導通部材３１と第３導通部材３３との間に位置する区間を含む。本構成をとることにより、第３導通部材３３は、第１導通部材３１に対して第２導通部材３２よりも遠くに位置する構成となる。これにより、第１導通部材３１と第３導通部材３３との相互誘導に起因した、第２導通部材３２における電流の阻害を抑制することができる。 The second conductive member 32 includes a section located between the first conductive member 31 and the third conductive member 33. By adopting this configuration, the third conductive member 33 is located further away from the first conductive member 31 than the second conductive member 32. Thereby, inhibition of the current in the second conductive member 32 due to mutual induction between the first conductive member 31 and the third conductive member 33 can be suppressed.
　半導体装置Ａ１０においては、第１端子２１の第３方向ｙの寸法は、第１導通部材３１の導電経路長よりも大きい。さらに第２端子２２の第３方向ｙの寸法は、第２導通部材３２の導電経路長よりも大きい。したがって、半導体装置Ａ１０においては、図１０に示す誘導起電力ＶMの作用は、第１導通部材３１および第２導通部材３２よりも第１端子２１および第２端子２２の方が支配的となる。したがって、半導体装置Ａ１０においては、第１端子２１と第２端子２２との間隔をより小さくすることが好ましい。 In the semiconductor device A10, the dimension of the first terminal 21 in the third direction y is larger than the conductive path length of the first conductive member 31. Furthermore, the dimension of the second terminal 22 in the third direction y is larger than the length of the conductive path of the second conductive member 32. Therefore, in the semiconductor device A10, the effect of the induced electromotive force V M shown in FIG. . Therefore, in the semiconductor device A10, it is preferable to further reduce the distance between the first terminal 21 and the second terminal 22.
　半導体素子１０は、第１方向ｚにおいて第１電極１１とは反対側に位置する第２電極１３を有する。半導体装置Ａ１０は、第２電極１３に導通する第４端子２４をさらに備える。第４端子２４は、第２方向ｘにおいて第１端子２１を基準として第２端子２２とは反対側に位置する。図３に示すように、第１端子２１と第４端子２４との間隔ｄ１は、第１端子２１と第２端子２２との間隔ｄ２よりも大きい。本構成をとることにより、半導体素子１０のスイッチング損失を低減しつつ、図１０に示す磁束Ｍの影響により第４端子２４に過電流が流れることを抑制できる。 The semiconductor element 10 has a second electrode 13 located on the opposite side to the first electrode 11 in the first direction z. The semiconductor device A10 further includes a fourth terminal 24 electrically connected to the second electrode 13. The fourth terminal 24 is located on the opposite side of the second terminal 22 with respect to the first terminal 21 in the second direction x. As shown in FIG. 3, the distance d1 between the first terminal 21 and the fourth terminal 24 is larger than the distance d2 between the first terminal 21 and the second terminal 22. By adopting this configuration, it is possible to reduce the switching loss of the semiconductor element 10 and to suppress the flow of overcurrent to the fourth terminal 24 due to the influence of the magnetic flux M shown in FIG. 10.
　半導体装置Ａ１０は、半導体素子１０の第２電極１３が導電接合されたダイパッド２０をさらに備える。第４端子２４は、ダイパッド２０につながっている。本構成をとることにより、ダイパッド２０に放熱および導電の両者の機能を持たせることができる。この場合において、ダイパッド２０が封止樹脂４０から露出することにより、半導体装置Ａ１０の放熱性を向上させることができる。 The semiconductor device A10 further includes a die pad 20 to which the second electrode 13 of the semiconductor element 10 is conductively bonded. The fourth terminal 24 is connected to the die pad 20. With this configuration, the die pad 20 can have both heat dissipation and conduction functions. In this case, by exposing the die pad 20 from the sealing resin 40, the heat dissipation of the semiconductor device A10 can be improved.
　第２実施形態：
　図１１～図２０に基づき、本開示の第２実施形態にかかる半導体装置Ａ２０について説明する。これらの図において、先述した半導体装置Ａ１０と同一または類似の要素には同一の符号を付して、重複する説明を省略する。ここで、ここで、図１１は、理解の便宜上、封止樹脂４０を透過している。図１１では、透過した封止樹脂４０を想像線で示している。 Second embodiment:
A semiconductor device A20 according to a second embodiment of the present disclosure will be described based on FIGS. 11 to 20. In these figures, the same or similar elements as those of the semiconductor device A10 described above are denoted by the same reference numerals, and redundant explanation will be omitted. Here, in FIG. 11, for convenience of understanding, the sealing resin 40 is shown. In FIG. 11, the transparent sealing resin 40 is shown with imaginary lines.
　半導体装置Ａ２０においては、ダイパッド２０を具備しないことと、半導体素子１０、第１端子２１、第２端子２２、第３端子２３および第４端子２４の構成とが、半導体装置Ａ１０の場合と異なる。半導体装置Ａ２０のパッケージ形式は、ＱＦＮ（Quad Flat Non-leaded）である。 The semiconductor device A20 differs from the semiconductor device A10 in that it does not include the die pad 20 and in the configurations of the semiconductor element 10, the first terminal 21, the second terminal 22, the third terminal 23, and the fourth terminal 24. The package format of the semiconductor device A20 is QFN (Quad Flat Non-leaded).
　図１１に示すように、半導体素子１０の第１電極１１は、互いに離れた第１部１１１、および２つの第２部１１２を含まず、単一である。第１導通部材３１および第３導通部材３３の各々は、第１電極１１に導電接合されている。 As shown in FIG. 11, the first electrode 11 of the semiconductor element 10 does not include a first part 111 separated from each other and two second parts 112, and is single. Each of the first conductive member 31 and the third conductive member 33 is electrically connected to the first electrode 11 .
　図１１、図１２、図１３および図１６に示すように、第１端子２１は、第１接合面２１３、２つの実装面２１４、２つの側面２１５、２つの内周面２１６、庇部２１７および吊部２１８を有する。 As shown in FIG. 11, FIG. 12, FIG. 13, and FIG. It has a hanging part 218.
　図１６に示すように、２つの実装面２１４は、第１方向ｚにおいて第１接合面２１３とは反対側を向く。図１２に示すように、実装面２１４は、第２方向ｘにおいて互いに離れている。２つの実装面２１４は、封止樹脂４０の底面４２から露出している。図１３および図１６に示すように、２つの側面２１５は、２つの実装面２１４に個別につながり、かつ第３方向ｙを向く。２つの側面２１５は、第１接合面２１３にもつながっている。２つの側面２１５は、封止樹脂４０の２つの第１側面４３のいずれかから露出している。 As shown in FIG. 16, the two mounting surfaces 214 face opposite to the first bonding surface 213 in the first direction z. As shown in FIG. 12, the mounting surfaces 214 are separated from each other in the second direction x. The two mounting surfaces 214 are exposed from the bottom surface 42 of the sealing resin 40. As shown in FIGS. 13 and 16, the two side surfaces 215 are individually connected to the two mounting surfaces 214 and face the third direction y. The two side surfaces 215 are also connected to the first joint surface 213. The two side surfaces 215 are exposed from either of the two first side surfaces 43 of the sealing resin 40.
　図１１、図１２および図１６に示すように、２つの内周面２１６は、２つの実装面２１４に個別につながり、かつ第１方向ｚに対して直交する方向を向く。内周面２１６は、封止樹脂４０に覆われている。図１１、図１２、図１３および図１６に示すように、庇部２１７は、２つの内周面２１６から第１方向ｚに対して直交する方向に張り出している。第１接合面２１３は、庇部２１７の一部に含まれる。庇部２１７は、封止樹脂４０に覆われている。図１１および図１２に示すように、吊部２１８は、庇部２１７から第２方向ｘにおいて封止樹脂４０の外方に突出している。第１接合面２１３は、吊部２１８の一部に含まれる。図１５に示すように、吊部２１８は、第２方向ｘを向く端面２１８Ａを有する。端面２１８Ａは、封止樹脂４０の２つの第２側面４４のいずれかから露出している。 As shown in FIGS. 11, 12, and 16, the two inner circumferential surfaces 216 are individually connected to the two mounting surfaces 214 and face in a direction perpendicular to the first direction z. Inner peripheral surface 216 is covered with sealing resin 40. As shown in FIGS. 11, 12, 13, and 16, the eaves portion 217 protrudes from the two inner peripheral surfaces 216 in a direction perpendicular to the first direction z. The first joint surface 213 is included in a part of the eaves section 217. The eaves portion 217 is covered with a sealing resin 40. As shown in FIGS. 11 and 12, the hanging portion 218 protrudes outward from the sealing resin 40 from the eaves portion 217 in the second direction x. The first joint surface 213 is included in a part of the hanging portion 218. As shown in FIG. 15, the hanging portion 218 has an end surface 218A facing in the second direction x. The end surface 218A is exposed from either of the two second side surfaces 44 of the sealing resin 40.
　図１１、図１２、図１３および図１７に示すように、第２端子２２は、第２接合面２２３、実装面２２４、側面２２５、内周面２２６および庇部２２７を有する。 As shown in FIGS. 11, 12, 13, and 17, the second terminal 22 has a second bonding surface 223, a mounting surface 224, a side surface 225, an inner peripheral surface 226, and an eaves portion 227.
　図１７に示すように、実装面２２４は、第１方向ｚにおいて第２接合面２２３とは反対側を向く。図１２に示すように、実装面２２４は、封止樹脂４０の底面４２から露出している。図１３および図１７に示すように、側面２２５は、第２接合面２２３および実装面２２４につながり、かつ第３方向ｙを向く。側面２２５は、封止樹脂４０の２つの第１側面４３のうち、第１端子２１の側面２１５が露出している第１側面４３から露出している。 As shown in FIG. 17, the mounting surface 224 faces the opposite side from the second bonding surface 223 in the first direction z. As shown in FIG. 12, the mounting surface 224 is exposed from the bottom surface 42 of the sealing resin 40. As shown in FIGS. 13 and 17, the side surface 225 is connected to the second bonding surface 223 and the mounting surface 224, and faces in the third direction y. The side surface 225 is exposed from the first side surface 43 of the two first side surfaces 43 of the sealing resin 40 where the side surface 215 of the first terminal 21 is exposed.
　図１１、図１２および図１７に示すように、内周面２２６は、実装面２２４につながり、かつ第１方向ｚに対して直交する方向を向く。内周面２２６は、封止樹脂４０に覆われている。図１１、図１２、図１３および図１７に示すように、庇部２２７は、内周面２２６から第１方向ｚに対して直交する方向に張り出している。第２接合面２２３は、庇部２２７の一部に含まれる。庇部２２７は、封止樹脂４０に覆われている。 As shown in FIGS. 11, 12, and 17, the inner peripheral surface 226 is connected to the mounting surface 224 and faces in a direction perpendicular to the first direction z. Inner peripheral surface 226 is covered with sealing resin 40. As shown in FIGS. 11, 12, 13, and 17, the eaves portion 227 protrudes from the inner peripheral surface 226 in a direction perpendicular to the first direction z. The second joint surface 223 is included in a part of the eaves section 227. The eaves portion 227 is covered with a sealing resin 40.
　図１１、図１２および図１３に示すように、第３端子２３は、第３接合面２３３、実装面２３４、側面２３５、内周面２３６、庇部２３７および吊部２３８を有する。 As shown in FIGS. 11, 12, and 13, the third terminal 23 has a third bonding surface 233, a mounting surface 234, a side surface 235, an inner peripheral surface 236, an eaves portion 237, and a hanging portion 238.
　図１１および図１２に示すように、実装面２３４は、第１方向ｚにおいて第３接合面２３３とは反対側を向く。図１２に示すように、実装面２３４は、封止樹脂４０の底面４２から露出している。図１３に示すように、側面２３５は、第３接合面２３３および実装面２３４につながり、かつ第３方向ｙを向く。側面２３５は、封止樹脂４０の２つの第１側面４３のうち、第１端子２１の側面２１５が露出している第１側面４３から露出している。 As shown in FIGS. 11 and 12, the mounting surface 234 faces the opposite side from the third bonding surface 233 in the first direction z. As shown in FIG. 12, the mounting surface 234 is exposed from the bottom surface 42 of the sealing resin 40. As shown in FIG. 13, the side surface 235 is connected to the third bonding surface 233 and the mounting surface 234, and faces in the third direction y. The side surface 235 is exposed from the first side surface 43 of the two first side surfaces 43 of the sealing resin 40 where the side surface 215 of the first terminal 21 is exposed.
　図１１および図１２に示すように、内周面２３６は、実装面２３４につながり、かつ第１方向ｚに対して直交する方向を向く。内周面２３６は、封止樹脂４０に覆われている。図１１、図１２および図１３に示すように、庇部２３７は、内周面２３６から第１方向ｚに対して直交する方向に張り出している。第３接合面２３３は、庇部２３７の一部に含まれる。庇部２３７は、封止樹脂４０に覆われている。図１１および図１２に示すように、吊部２３８は、庇部２３７から第２方向ｘにおいて封止樹脂４０の外方に突出している。第３接合面２３３は、吊部２３８の一部に含まれる。図１１に示すように、吊部２１８は、第２方向ｘを向く端面２１８Ａを有する。端面２１８Ａは、封止樹脂４０の２つの第２側面４４のうち、第１端子２１の吊部２１８の端面２１８Ａが露出していない第２側面４４から露出している。 As shown in FIGS. 11 and 12, the inner peripheral surface 236 is connected to the mounting surface 234 and faces in a direction perpendicular to the first direction z. Inner peripheral surface 236 is covered with sealing resin 40. As shown in FIGS. 11, 12, and 13, the eaves portion 237 protrudes from the inner peripheral surface 236 in a direction perpendicular to the first direction z. The third joint surface 233 is included in a part of the eaves section 237. The eaves portion 237 is covered with a sealing resin 40. As shown in FIGS. 11 and 12, the hanging portion 238 protrudes outward from the sealing resin 40 from the eaves portion 237 in the second direction x. The third joint surface 233 is included in a part of the hanging portion 238. As shown in FIG. 11, the hanging portion 218 has an end surface 218A facing in the second direction x. The end surface 218A is exposed from the second side surface 44 of the two second side surfaces 44 of the sealing resin 40 from which the end surface 218A of the hanging portion 218 of the first terminal 21 is not exposed.
　図１１に示すように、第４端子２４は、第３方向ｙにおいて第１端子２１、第２端子２２および第３端子２３から離れている。図１１、図１２、図１４、および図１６～図１８に示すように、第４端子２４は、搭載面２４３、実装面２４４、複数の側面２４５、内周面２４６、庇部２４７および２つの吊部２４８を有する。 As shown in FIG. 11, the fourth terminal 24 is separated from the first terminal 21, second terminal 22, and third terminal 23 in the third direction y. As shown in FIGS. 11, 12, 14, and 16 to 18, the fourth terminal 24 includes a mounting surface 243, a mounting surface 244, a plurality of side surfaces 245, an inner peripheral surface 246, an eaves portion 247, and two It has a hanging part 248.
　図１６～図１８に示すように、搭載面２４３および実装面２４４は、第１方向ｚにおいて互いに反対側を向く。搭載面２４３は、半導体素子１０に対向している。半導体素子１０の第２電極１３は、導電接合層２９を介して搭載面２４３に導電接合されている。これにより、半導体素子１０の第２電極１３は、第４端子２４に導通している。実装面２３４は、封止樹脂４０の底面４２から露出している。実装面２３４の面積は、第１端子２１の２つの実装面２１４、第２端子２２の実装面２２４、および第３端子２３の実装面２３４の各々の面積よりも大きい。第１方向ｚに視て、半導体素子１０は、実装面２３４に重なっている。図１４および図１６に示すように、複数の側面２３５は、搭載面２４３および実装面２４４につながり、かつ第３方向ｙを向く。複数の側面２３５は、封止樹脂４０の２つの第１側面４３のうち、第１端子２１の２つの側面２１５が露出していない第１側面４３から露出している。複数の側面２３５は、第２方向ｘに沿って配列されている。 As shown in FIGS. 16 to 18, the mounting surface 243 and the mounting surface 244 face oppositely to each other in the first direction z. The mounting surface 243 faces the semiconductor element 10. The second electrode 13 of the semiconductor element 10 is electrically bonded to the mounting surface 243 via the electrically conductive bonding layer 29 . Thereby, the second electrode 13 of the semiconductor element 10 is electrically connected to the fourth terminal 24. The mounting surface 234 is exposed from the bottom surface 42 of the sealing resin 40. The area of the mounting surface 234 is larger than the area of each of the two mounting surfaces 214 of the first terminal 21 , the mounting surface 224 of the second terminal 22 , and the mounting surface 234 of the third terminal 23 . The semiconductor element 10 overlaps the mounting surface 234 when viewed in the first direction z. As shown in FIGS. 14 and 16, the plurality of side surfaces 235 are connected to the mounting surface 243 and the mounting surface 244, and face the third direction y. The plurality of side surfaces 235 are exposed from the first side surface 43 of the two first side surfaces 43 of the sealing resin 40 from which the two side surfaces 215 of the first terminal 21 are not exposed. The plurality of side surfaces 235 are arranged along the second direction x.
　図１１、図１２、および図１６～図１８に示すように、内周面２４６は、実装面２４４につながり、かつ第１方向ｚに対して直交する方向を向く。内周面２４６は、封止樹脂４０に覆われている。第１方向ｚに視て、半導体素子１０は、内周面２３６および複数の側面２３５により囲まれている。図１１、図１２、図１４、および図１６～図１８に示すように、庇部２３７は、内周面２３６から第１方向ｚに対して直交する方向に張り出している。搭載面２４３は、庇部２３７の一部に含まれる。庇部２３７は、封止樹脂４０に覆われている。図１１、図１２および図１８に示すように、２つの吊部２４８は、庇部２１７から第２方向ｘにおいて封止樹脂４０の外方に突出している。２つの吊部２４８は、第２方向ｘにおいて庇部２３７を基準として互いに反対側に位置する。搭載面２４３は、２つの吊部２１８の各々の一部に含まれる。２つの吊部２４８の各々は、第２方向ｘを向く端面２４８Ａを有する。２つの吊部２４８の各々の端面２４８Ａは、封止樹脂４０の２つの第２側面４４から個別に露出している。 As shown in FIGS. 11, 12, and 16 to 18, the inner peripheral surface 246 is connected to the mounting surface 244 and faces in a direction perpendicular to the first direction z. Inner peripheral surface 246 is covered with sealing resin 40. The semiconductor element 10 is surrounded by an inner circumferential surface 236 and a plurality of side surfaces 235 when viewed in the first direction z. As shown in FIGS. 11, 12, 14, and 16 to 18, the eaves portion 237 protrudes from the inner peripheral surface 236 in a direction perpendicular to the first direction z. The mounting surface 243 is included in a part of the eaves section 237. The eaves portion 237 is covered with a sealing resin 40. As shown in FIGS. 11, 12, and 18, the two hanging parts 248 protrude outward from the sealing resin 40 from the eaves part 217 in the second direction x. The two hanging parts 248 are located on opposite sides of the eaves part 237 in the second direction x. The mounting surface 243 is included in a part of each of the two hanging parts 218. Each of the two hanging portions 248 has an end surface 248A facing in the second direction x. End surfaces 248A of each of the two hanging portions 248 are individually exposed from the two second side surfaces 44 of the sealing resin 40.
　図１１および図１６に示すように、半導体装置Ａ２０においては、第１導通部材３１は、金属クリップである。第１導通部材３１の一端は、導電接合層２９を介して半導体素子１０の第１電極１１に導電接合されている。第１導通部材３１の他端は、導電接合層２９を介して第１端子２１の第１接合面２１３に導電接合されている。 As shown in FIGS. 11 and 16, in the semiconductor device A20, the first conductive member 31 is a metal clip. One end of the first conductive member 31 is electrically bonded to the first electrode 11 of the semiconductor element 10 via the electrically conductive bonding layer 29 . The other end of the first conductive member 31 is electrically bonded to the first bonding surface 213 of the first terminal 21 via the electrically conductive bonding layer 29 .
　図１１に示すように、半導体装置Ａ２０においても第２導通部材３２は、第１導通部材３１の隣に位置する。さらに第２導通部材３２は、第１導通部材３１と第３導通部材３３との間に位置する区間を含む。図１１に示すように、半導体装置Ａ２０においては、第１端子２１の第３方向ｙの寸法は、第１導通部材３１の導電経路長よりも小さい。あわせて第２端子２２の第３方向ｙの寸法は、第２導通部材３２の導電経路長よりも小さい。 As shown in FIG. 11, the second conductive member 32 is located next to the first conductive member 31 in the semiconductor device A20 as well. Further, the second conductive member 32 includes a section located between the first conductive member 31 and the third conductive member 33. As shown in FIG. 11, in the semiconductor device A20, the dimension of the first terminal 21 in the third direction y is smaller than the conductive path length of the first conductive member 31. Additionally, the dimension of the second terminal 22 in the third direction y is smaller than the length of the conductive path of the second conductive member 32.
　次に、半導体装置Ａ２０の作用効果について説明する。 Next, the effects of the semiconductor device A20 will be explained.
　半導体装置Ａ２０は、第１電極１１およびゲート電極１２を有する半導体素子１０と、第１電極１１に導通する第１端子２１と、ゲート電極１２に導通する第２端子２２と、第１電極１１に導通する第３端子２３とを備える。第１端子２１および第３端子２３の各々に流れる電流の向きは、第２端子２２に流れる電流の向きとは逆である。第２端子２２は、第１端子２１の隣に位置する。第３端子２３は、第２端子２２を基準として第１端子２１とは反対側に位置する。本構成をとることにより、図２０に示すように、第２端子２２には、磁束Ｍに起因した電磁誘導により誘導起電力ＶMが作用する。誘導起電力ＶMの向きは、第２端子２２に流れる電流の向きに等しい。このため、第２端子２２に流れる電流は、誘導起電力ＶMにより加速される。したがって、本構成によれば、半導体装置Ａ２０においても、半導体素子１０のスイッチング損失を低減することが可能となる。さらに半導体装置Ａ２０においては、半導体素子１０と共通する構成を具備することにより、半導体素子１０と同等の作用効果を奏する。 The semiconductor device A20 includes a semiconductor element 10 having a first electrode 11 and a gate electrode 12, a first terminal 21 electrically connected to the first electrode 11, a second terminal 22 electrically connected to the gate electrode 12, and a semiconductor element 10 having a first electrode 11 and a gate electrode 12. The third terminal 23 is electrically connected. The direction of the current flowing through each of the first terminal 21 and the third terminal 23 is opposite to the direction of the current flowing through the second terminal 22. The second terminal 22 is located next to the first terminal 21. The third terminal 23 is located on the opposite side of the first terminal 21 with respect to the second terminal 22. With this configuration, as shown in FIG. 20, an induced electromotive force V M acts on the second terminal 22 due to electromagnetic induction caused by the magnetic flux M. The direction of the induced electromotive force V M is equal to the direction of the current flowing through the second terminal 22. Therefore, the current flowing to the second terminal 22 is accelerated by the induced electromotive force V M . Therefore, according to this configuration, it is possible to reduce the switching loss of the semiconductor element 10 also in the semiconductor device A20. Further, the semiconductor device A20 has the same configuration as the semiconductor element 10, so that the same effects as the semiconductor element 10 can be achieved.
　半導体装置Ａ２０においては、第１端子２１の第３方向ｙの寸法は、第１導通部材３１の導電経路長よりも小さい。さらに第２端子２２の第３方向ｙの寸法は、第２導通部材３２の導電経路長よりも小さい。したがって、半導体装置Ａ２０においては、図２０に示す誘導起電力ＶMの作用は、第１端子２１および第２端子２２よりも第１導通部材３１および第２導通部材３２の方が支配的となる。したがって、半導体装置Ａ２０においては、第１導通部材３１と第２導通部材３２との間隔をより小さくすることが好ましい。 In the semiconductor device A20, the dimension of the first terminal 21 in the third direction y is smaller than the conductive path length of the first conductive member 31. Furthermore, the dimension of the second terminal 22 in the third direction y is smaller than the length of the conductive path of the second conductive member 32. Therefore, in the semiconductor device A20, the effect of the induced electromotive force V M shown in FIG. . Therefore, in the semiconductor device A20, it is preferable to make the distance between the first conductive member 31 and the second conductive member 32 smaller.
　半導体装置Ａ２０においては、半導体素子１０の第２電極１３は、第４端子２４に導電接合されている。封止樹脂４０は、第１方向ｚを向く底面４２を有する。第１端子２１、第２端子２２、第３端子２３および第４端子２４は、底面４２から露出している。本構成をとることにより、半導体装置Ａ２０を配線基板に表面実装することが可能となる。この場合において、底面４２から露出する第４端子２４の面積をより大きく設定することにより、半導体装置Ａ２０の放熱性の向上を図ることができる。 In the semiconductor device A20, the second electrode 13 of the semiconductor element 10 is conductively bonded to the fourth terminal 24. The sealing resin 40 has a bottom surface 42 facing in the first direction z. The first terminal 21 , the second terminal 22 , the third terminal 23 , and the fourth terminal 24 are exposed from the bottom surface 42 . By adopting this configuration, it becomes possible to surface-mount the semiconductor device A20 on the wiring board. In this case, by setting the area of the fourth terminal 24 exposed from the bottom surface 42 to be larger, it is possible to improve the heat dissipation performance of the semiconductor device A20.
　封止樹脂４０は、第３方向ｙにおいて互いに反対側を向く２つの第１側面４３を有する。第１端子２１、第２端子２２、第３端子２３および第４端子２４は、２つの第１側面４３のいずれかから露出している。本構成をとることにより、半導体装置Ａ２０を配線基板に実装する際、第１端子２１、第２端子２２、第３端子２３および第４端子２４の各々に付着するハンダの体積が増加する。これにより、配線基板に対する半導体装置Ａ２０の接合強度を増加させることができる。 The sealing resin 40 has two first side surfaces 43 facing oppositely to each other in the third direction y. The first terminal 21, the second terminal 22, the third terminal 23, and the fourth terminal 24 are exposed from either of the two first side surfaces 43. By adopting this configuration, when mounting the semiconductor device A20 on a wiring board, the volume of solder adhering to each of the first terminal 21, second terminal 22, third terminal 23, and fourth terminal 24 increases. Thereby, the bonding strength of the semiconductor device A20 to the wiring board can be increased.
　本開示は、先述した実施形態に限定されるものではない。本開示の各部の具体的な構成は、種々に設計変更自在である。 The present disclosure is not limited to the embodiments described above. The specific configuration of each part of the present disclosure can be modified in various ways.
　本開示は、以下の付記に記載した実施形態を含む。
　付記１．
　第１電極およびゲート電極を有する半導体素子と、
　前記第１電極に導通する第１端子と、
　前記ゲート電極に導通する第２端子と、
　前記第１電極に導通する第３端子と、を備え、
　前記第１端子および前記第３端子の各々に流れる電流の向きは、前記第２端子に流れる電流の向きとは逆であり、
　前記第２端子は、前記第１端子の隣に位置しており、
　前記第３端子は、前記第２端子を基準として前記第１端子とは反対側に位置する、半導体装置。
　付記２．
　前記半導体素子は、第１方向において前記第１電極とは反対側に位置する第２電極を有し、
　前記ゲート電極は、前記第１方向において前記第１電極と同じ側に位置しており、
　前記第２電極に導通する第４端子をさらに備える、付記１に記載の半導体装置。
　付記３．
　前記第１端子、前記第２端子および前記第３端子は、前記第１方向に対して直交する第２方向に沿って配列されており、
　前記第３端子は、前記第２端子の隣に位置する、付記２に記載の半導体装置。
　付記４．
　前記半導体素子を覆う封止樹脂をさらに備え、
　前記第１端子、前記第２端子、前記第３端子および前記第４端子は、前記封止樹脂から露出している、付記３に記載の半導体装置。
　付記５．
　前記第１電極と前記第１端子とに導電接合された第１導通部材と、
　前記ゲート電極と前記第２端子とに導電接合された第２導通部材と、
　前記第１電極と前記第３端子とに導電接合された第３導通部材と、をさらに備え、
　前記第１導通部材、前記第２導通部材および前記第３導通部材は、前記封止樹脂に覆われており、
　前記第２導通部材は、前記第１導通部材の隣に位置する、付記４に記載の半導体装置。
　付記６．
　前記第２導通部材は、前記第１導通部材と前記第３導通部材との間に位置する区間を含む、付記５に記載の半導体装置。
　付記７．
　前記第１端子の前記第１方向および前記第２方向に直交する第３方向の寸法は、前記第１導通部材の導電経路長よりも大きい、付記５または６に記載の半導体装置。
　付記８．
　前記第１方向に視て、前記封止樹脂から露出した前記第１端子、前記第２端子、前記第３端子および前記第４端子の各々の部分は、前記第３方向に延びている、付記７に記載の半導体装置。
　付記９．
　前記第４端子は、前記第２方向において前記第１端子を基準として前記第２端子とは反対側に位置する、付記８に記載の半導体装置。
　付記１０．
　　前記第１端子および前記第４端子の各々の前記封止樹脂から露出した部分の最小間隔は、前記第１端子および前記第２端子の各々の前記封止樹脂から露出した部分の最小間隔よりも大きい、付記９に記載の半導体装置。
　付記１１．
　ダイパッドをさらに備え、
　前記第２電極は、前記ダイパッドに導電接合されており、
　前記第４端子は、前記ダイパッドにつながっている、付記９または１０に記載の半導体装置。
　付記１２．
　前記ダイパッドは、前記封止樹脂から露出している、付記１１に記載の半導体装置。
　付記１３．
　前記第１端子の前記第１方向および前記第２方向に直交する第３方向の寸法は、前記第１導通部材の導電経路長よりも小さい、付記５または６に記載の半導体装置。
　付記１４．
　前記第４端子は、前記第３方向において前記第１端子から離れており、
　前記第２電極は、前記第４端子に導電接合されている、付記１３に記載の半導体装置。
　付記１５．
　前記封止樹脂は、前記第１方向を向く底面を有し、
　前記第１端子、前記第２端子、前記第３端子および前記第４端子は、前記底面から露出している、付記１４に記載の半導体装置。
　付記１６．
　前記封止樹脂は、前記第３方向において互いに反対側を向く２つの第１側面を有し、
　前記第１端子、前記第２端子、前記第３端子および前記第４端子は、前記２つの第１側面のいずれかから露出している、付記１５に記載の半導体装置。 The present disclosure includes the embodiments described in the appendix below.
Additional note 1.
a semiconductor element having a first electrode and a gate electrode;
a first terminal electrically connected to the first electrode;
a second terminal electrically connected to the gate electrode;
a third terminal electrically connected to the first electrode;
The direction of the current flowing through each of the first terminal and the third terminal is opposite to the direction of the current flowing through the second terminal,
The second terminal is located next to the first terminal,
In the semiconductor device, the third terminal is located on the opposite side of the first terminal with respect to the second terminal.
Appendix 2.
The semiconductor element has a second electrode located on the opposite side of the first electrode in the first direction,
The gate electrode is located on the same side as the first electrode in the first direction,
The semiconductor device according to supplementary note 1, further comprising a fourth terminal electrically connected to the second electrode.
Appendix 3.
The first terminal, the second terminal, and the third terminal are arranged along a second direction orthogonal to the first direction,
The semiconductor device according to appendix 2, wherein the third terminal is located next to the second terminal.
Appendix 4.
further comprising a sealing resin that covers the semiconductor element,
The semiconductor device according to appendix 3, wherein the first terminal, the second terminal, the third terminal, and the fourth terminal are exposed from the sealing resin.
Appendix 5.
a first conductive member electrically connected to the first electrode and the first terminal;
a second conductive member electrically connected to the gate electrode and the second terminal;
further comprising a third conductive member electrically connected to the first electrode and the third terminal,
The first conductive member, the second conductive member, and the third conductive member are covered with the sealing resin,
The semiconductor device according to appendix 4, wherein the second conductive member is located next to the first conductive member.
Appendix 6.
The semiconductor device according to appendix 5, wherein the second conductive member includes a section located between the first conductive member and the third conductive member.
Appendix 7.
7. The semiconductor device according to appendix 5 or 6, wherein a dimension of the first terminal in a third direction perpendicular to the first direction and the second direction is larger than a conductive path length of the first conductive member.
Appendix 8.
Supplementary note, when viewed in the first direction, each portion of the first terminal, the second terminal, the third terminal, and the fourth terminal exposed from the sealing resin extends in the third direction. 7. The semiconductor device according to 7.
Appendix 9.
The semiconductor device according to appendix 8, wherein the fourth terminal is located on the opposite side of the second terminal with respect to the first terminal in the second direction.
Appendix 10.
The minimum interval between the parts of each of the first terminal and the fourth terminal exposed from the sealing resin is smaller than the minimum interval between the parts of each of the first terminal and the second terminal exposed from the sealing resin. The semiconductor device according to appendix 9, which is large.
Appendix 11.
Also equipped with a die pad,
the second electrode is electrically conductively bonded to the die pad;
The semiconductor device according to appendix 9 or 10, wherein the fourth terminal is connected to the die pad.
Appendix 12.
The semiconductor device according to appendix 11, wherein the die pad is exposed from the sealing resin.
Appendix 13.
7. The semiconductor device according to appendix 5 or 6, wherein a dimension of the first terminal in a third direction perpendicular to the first direction and the second direction is smaller than a conductive path length of the first conductive member.
Appendix 14.
the fourth terminal is separated from the first terminal in the third direction,
The semiconductor device according to attachment 13, wherein the second electrode is conductively bonded to the fourth terminal.
Appendix 15.
The sealing resin has a bottom surface facing the first direction,
The semiconductor device according to appendix 14, wherein the first terminal, the second terminal, the third terminal, and the fourth terminal are exposed from the bottom surface.
Appendix 16.
The sealing resin has two first side surfaces facing opposite to each other in the third direction,
The semiconductor device according to appendix 15, wherein the first terminal, the second terminal, the third terminal, and the fourth terminal are exposed from either of the two first side surfaces.
Ａ１０，Ａ２０：半導体素子　　　　１０：半導体素子
１１：第１電極　　　　１２：ゲート電極
１３：第２電極　　　　２０：ダイパッド
２０１：搭載面　　　　２０２：裏面
２０３：貫通孔　　　　２１：第１端子
２１１：被覆部　　　　２１２：露出部
２１３：第１接合面　　　　２１４：実装面
２１５：側面　　　　２１６：内周面
２１７：庇部　　　　２１８：吊部
２１８Ａ：端面　　　　２２：第２端子
２２１：被覆部　　　　２２２：露出部
２２３：第２接合面　　　　２２４：実装面
２２５：側面　　　　２２６：内周面
２２７：庇部　　　　２３：第３端子
２３１：被覆部　　　　２３２：露出部
２３３：第３接合面　　　　２３４：実装面
２３５：側面　　　　２３６：内周面
２３７：庇部　　　　２３８：吊部
２３８Ａ：端面　　　　２４：第４端子
２４１：被覆部　　　　２４２：露出部
２４３：搭載面　　　　２４４：実装面
２４５：側面　　　　２４６：内周面
２４７：庇部　　　　２４８：吊部
２４８Ａ：端面　　　　２９：導電接合層
３１：第１導通部材　　　　３２：第２導通部材
３３：第３導通部材　　　　４０：封止樹脂
４１：頂面　　　　４２：底面
４３：第１側面　　　　４４：第２側面
４５：開口　　　　４６：取付け孔
ｚ：第１方向　　　　ｘ：第２方向
ｙ：第３方向 A10, A20: Semiconductor element 10: Semiconductor element 11: First electrode 12: Gate electrode 13: Second electrode 20: Die pad 201: Mounting surface 202: Back surface 203: Through hole 21: First terminal 211: Covering part 212: Exposed Part 213: First joint surface 214: Mounting surface 215: Side surface 216: Inner peripheral surface 217: Eaves portion 218: Hanging portion 218A: End surface 22: Second terminal 221: Covering portion 222: Exposed portion 223: Second joint surface 224 : Mounting surface 225: Side surface 226: Inner peripheral surface 227: Eaves section 23: Third terminal 231: Covering section 232: Exposed section 233: Third bonding surface 234: Mounting surface 235: Side surface 236: Inner peripheral surface 237: Eaves section 238: Hanging portion 238A: End surface 24: Fourth terminal 241: Covering portion 242: Exposed portion 243: Mounting surface 244: Mounting surface 245: Side surface 246: Inner peripheral surface 247: Eaves portion 248: Hanging portion 248A: End surface 29: Conductive Bonding layer 31: First conductive member 32: Second conductive member 33: Third conductive member 40: Sealing resin 41: Top surface 42: Bottom surface 43: First side surface 44: Second side surface 45: Opening 46: Mounting hole z : 1st direction x: 2nd direction y: 3rd direction

Claims (16)

  1. 　第１電極およびゲート電極を有する半導体素子と、
    　前記第１電極に導通する第１端子と、
    　前記ゲート電極に導通する第２端子と、
    　前記第１電極に導通する第３端子と、を備え、
    　前記第１端子および前記第３端子の各々に流れる電流の向きは、前記第２端子に流れる電流の向きとは逆であり、
    　前記第２端子は、前記第１端子の隣に位置しており、
    　前記第３端子は、前記第２端子を基準として前記第１端子とは反対側に位置する、半導体装置。     a semiconductor element having a first electrode and a gate electrode;
    a first terminal electrically connected to the first electrode;
    a second terminal electrically connected to the gate electrode;
    a third terminal electrically connected to the first electrode;
    The direction of the current flowing through each of the first terminal and the third terminal is opposite to the direction of the current flowing through the second terminal,
    The second terminal is located next to the first terminal,
    In the semiconductor device, the third terminal is located on the opposite side of the first terminal with respect to the second terminal.
  2. 　前記半導体素子は、第１方向において前記第１電極とは反対側に位置する第２電極を有し、
    　前記ゲート電極は、前記第１方向において前記第１電極と同じ側に位置しており、
    　前記第２電極に導通する第４端子をさらに備える、請求項１に記載の半導体装置。     The semiconductor element has a second electrode located on the opposite side of the first electrode in the first direction,
    The gate electrode is located on the same side as the first electrode in the first direction,
    The semiconductor device according to claim 1, further comprising a fourth terminal electrically connected to the second electrode.
  3. 　前記第１端子、前記第２端子および前記第３端子は、前記第１方向に対して直交する第２方向に沿って配列されており、
    　前記第３端子は、前記第２端子の隣に位置する、請求項２に記載の半導体装置。     The first terminal, the second terminal, and the third terminal are arranged along a second direction orthogonal to the first direction,
    3. The semiconductor device according to claim 2, wherein the third terminal is located next to the second terminal.
  4. 　前記半導体素子を覆う封止樹脂をさらに備え、
    　前記第１端子、前記第２端子、前記第３端子および前記第４端子は、前記封止樹脂から露出している、請求項３に記載の半導体装置。     further comprising a sealing resin that covers the semiconductor element,
    4. The semiconductor device according to claim 3, wherein the first terminal, the second terminal, the third terminal, and the fourth terminal are exposed from the sealing resin.
  5. 　前記第１電極と前記第１端子とに導電接合された第１導通部材と、
    　前記ゲート電極と前記第２端子とに導電接合された第２導通部材と、
    　前記第１電極と前記第３端子とに導電接合された第３導通部材と、をさらに備え、
    　前記第１導通部材、前記第２導通部材および前記第３導通部材は、前記封止樹脂に覆われており、
    　前記第２導通部材は、前記第１導通部材の隣に位置する、請求項４に記載の半導体装置。     a first conductive member electrically connected to the first electrode and the first terminal;
    a second conductive member electrically connected to the gate electrode and the second terminal;
    further comprising a third conductive member electrically connected to the first electrode and the third terminal,
    The first conductive member, the second conductive member, and the third conductive member are covered with the sealing resin,
    5. The semiconductor device according to claim 4, wherein the second conductive member is located next to the first conductive member.
  6. 　前記第２導通部材は、前記第１導通部材と前記第３導通部材との間に位置する区間を含む、請求項５に記載の半導体装置。 The semiconductor device according to claim 5, wherein the second conductive member includes a section located between the first conductive member and the third conductive member.
  7. 　前記第１端子の前記第１方向および前記第２方向に直交する第３方向の寸法は、前記第１導通部材の導電経路長よりも大きい、請求項５または６に記載の半導体装置。 7. The semiconductor device according to claim 5, wherein a dimension of the first terminal in a third direction perpendicular to the first direction and the second direction is larger than a conductive path length of the first conductive member.
  8. 　前記第１方向に視て、前記封止樹脂から露出した前記第１端子、前記第２端子、前記第３端子および前記第４端子の各々の部分は、前記第３方向に延びている、請求項７に記載の半導体装置。 When viewed in the first direction, each portion of the first terminal, the second terminal, the third terminal, and the fourth terminal exposed from the sealing resin extends in the third direction. The semiconductor device according to item 7.
  9. 　前記第４端子は、前記第２方向において前記第１端子を基準として前記第２端子とは反対側に位置する、請求項８に記載の半導体装置。 The semiconductor device according to claim 8, wherein the fourth terminal is located on the opposite side of the second terminal with respect to the first terminal in the second direction.
  10. 　前記第１端子および前記第４端子の各々の前記封止樹脂から露出した部分の最小間隔は、前記第１端子および前記第２端子の各々の前記封止樹脂から露出した部分の最小間隔よりも大きい、請求項９に記載の半導体装置。 The minimum interval between the parts of each of the first terminal and the fourth terminal exposed from the sealing resin is smaller than the minimum interval between the parts of each of the first terminal and the second terminal exposed from the sealing resin. The semiconductor device according to claim 9, wherein the semiconductor device is large.
  11. 　ダイパッドをさらに備え、
    　前記第２電極は、前記ダイパッドに導電接合されており、
    　前記第４端子は、前記ダイパッドにつながっている、請求項９または１０に記載の半導体装置。     Also equipped with a die pad,
    the second electrode is electrically conductively bonded to the die pad;
    11. The semiconductor device according to claim 9, wherein the fourth terminal is connected to the die pad.
  12. 　前記ダイパッドは、前記封止樹脂から露出している、請求項１１に記載の半導体装置。 The semiconductor device according to claim 11, wherein the die pad is exposed from the sealing resin.
  13. 　前記第１端子の前記第１方向および前記第２方向に直交する第３方向の寸法は、前記第１導通部材の導電経路長よりも小さい、請求項５または６に記載の半導体装置。 7. The semiconductor device according to claim 5, wherein a dimension of the first terminal in a third direction perpendicular to the first direction and the second direction is smaller than a conductive path length of the first conductive member.
  14. 　前記第４端子は、前記第３方向において前記第１端子から離れており、
    　前記第２電極は、前記第４端子に導電接合されている、請求項１３に記載の半導体装置。     the fourth terminal is separated from the first terminal in the third direction,
    14. The semiconductor device according to claim 13, wherein the second electrode is conductively bonded to the fourth terminal.
  15. 　前記封止樹脂は、前記第１方向を向く底面を有し、
    　前記第１端子、前記第２端子、前記第３端子および前記第４端子は、前記底面から露出している、請求項１４に記載の半導体装置。     The sealing resin has a bottom surface facing the first direction,
    15. The semiconductor device according to claim 14, wherein the first terminal, the second terminal, the third terminal, and the fourth terminal are exposed from the bottom surface.
  16. 　前記封止樹脂は、前記第３方向において互いに反対側を向く２つの第１側面を有し、
    　前記第１端子、前記第２端子、前記第３端子および前記第４端子は、前記２つの第１側面のいずれかから露出している、請求項１５に記載の半導体装置。     The sealing resin has two first side surfaces facing opposite to each other in the third direction,
    16. The semiconductor device according to claim 15, wherein the first terminal, the second terminal, the third terminal, and the fourth terminal are exposed from either of the two first side surfaces.
PCT/JP2023/026762 2022-08-10 2023-07-21 Semiconductor device WO2024034359A1 (en)

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JP2012146998A (en) * 2012-03-12 2012-08-02 Renesas Electronics Corp Semiconductor device
WO2014050278A1 (en) * 2012-09-26 2014-04-03 日立オートモティブシステムズ株式会社 Power semiconductor module
JP2017147433A (en) * 2015-12-16 2017-08-24 ローム株式会社 Semiconductor device
WO2018043535A1 (en) * 2016-09-02 2018-03-08 ローム株式会社 Power module, power module with drive circuit, industrial equipment, electric automobile and hybrid car
JP2020188177A (en) * 2019-05-16 2020-11-19 ローム株式会社 Semiconductor device

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012146998A (en) * 2012-03-12 2012-08-02 Renesas Electronics Corp Semiconductor device
WO2014050278A1 (en) * 2012-09-26 2014-04-03 日立オートモティブシステムズ株式会社 Power semiconductor module
JP2017147433A (en) * 2015-12-16 2017-08-24 ローム株式会社 Semiconductor device
WO2018043535A1 (en) * 2016-09-02 2018-03-08 ローム株式会社 Power module, power module with drive circuit, industrial equipment, electric automobile and hybrid car
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