WO2024032403A1 - 显示面板和显示装置 - Google Patents

显示面板和显示装置 Download PDF

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Publication number
WO2024032403A1
WO2024032403A1 PCT/CN2023/110110 CN2023110110W WO2024032403A1 WO 2024032403 A1 WO2024032403 A1 WO 2024032403A1 CN 2023110110 W CN2023110110 W CN 2023110110W WO 2024032403 A1 WO2024032403 A1 WO 2024032403A1
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WIPO (PCT)
Prior art keywords
area
data lines
flexible substrate
sub
pixel driving
Prior art date
Application number
PCT/CN2023/110110
Other languages
English (en)
French (fr)
Inventor
田学伟
刘畅畅
陈立强
石佳凡
张云鹏
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Publication of WO2024032403A1 publication Critical patent/WO2024032403A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a display panel and a display device.
  • an embodiment of the present disclosure provides a display panel, including a display area
  • the display panel also includes a first flexible substrate, a second flexible substrate and a plurality of first data lines,
  • the plurality of first data lines are located between the stacked first flexible substrate and the second flexible substrate; the plurality of first data lines are distributed in the display area;
  • the display panel also includes a plurality of pixel driving circuits and a plurality of second data lines located in the display area, and the plurality of pixel driving circuits and the plurality of second data lines are located on the second flexible substrate. The side facing away from the first data line;
  • the plurality of pixel driving circuits are arranged in an array; the plurality of first data lines and the plurality of second data lines are connected in one-to-one correspondence;
  • the plurality of first data lines include portions routed along the column direction of the pixel driving circuit array
  • the pixel driving circuit includes driving transistors
  • at least portions of the plurality of first data lines are routed along the columns of the pixel driving circuit array.
  • the orthographic projection of the portion of the directional wiring on the first flexible substrate does not overlap with the orthographic projection of the channel region of the driving transistor on the first flexible substrate.
  • the display area includes a first area and a second area, and the first area and the second area are connected;
  • the display panel also includes a non-display area, the non-display area includes a bending area, the bending area is located on a side of the first area away from the second area, the bending area, the first district and The second areas are arranged sequentially along a second direction; the second direction is the column direction of the pixel driving circuit array;
  • the first area includes a first sub-area, a second sub-area and a third sub-area, and the first sub-area, the second sub-area and the third sub-area are sequentially arranged along the first direction and mutually exclusive. Connection; the first direction is the row direction of the pixel driving circuit array;
  • the bending area is connected to the second sub-area
  • the first flexible substrate, the plurality of first data lines and the second flexible substrate extend from the second sub-region to the bending region;
  • the plurality of first data lines in the second sub-area include a first part, a second part and a third part; the first part, the second part and the third part are sequentially along the first direction. arrangement; arrangement;
  • the first part extends from the second sub-area to the first sub-area
  • the third part extends from the second sub-area to the third sub-area
  • the second part extends from the second sub-area to the third sub-area.
  • the second sub-area extends and distributes toward the second area.
  • the first part, the second part and the third part distributed in the second sub-area extend along the second direction, and any two adjacent parts of the first part A data line is symmetrically distributed on opposite sides of the channel region of one of the driving transistors;
  • any one of the pixel driving circuits has two first data lines distributed in the orthographic projection area on the first flexible substrate.
  • the first sub-region includes a first partition and a second partition
  • the third sub-region includes a first partition and a second partition
  • the first partition and the second partition are arranged sequentially along the first direction and connected to each other; the second partition is located on a side of the first partition away from the second sub-region;
  • the first portion extends to the first subarea of the first subarea
  • the third portion extends to the first partition of the third sub-region
  • the first part includes a plurality of the first data lines
  • the third part includes a plurality of the first data lines.
  • the first portion and the third portion distributed in the first partition extend along the first direction, and the first data line is located in two adjacent rows of the pixel driving circuits. between;
  • first data lines are distributed between any two adjacent rows of the pixel driving circuits; and the first data lines are connected to the channels of the switching transistors in the pixel driving circuits. Orthographic projections of the regions on the first flexible substrate do not overlap.
  • a plurality of redundant traces are also included, located in the first partition and arranged in an array;
  • the plurality of redundant traces extend along the second direction, and any two adjacent redundant traces along the first direction are symmetrically distributed on opposite sides of one of the driving transistor channel regions;
  • any one of the pixel driving circuits has two redundant traces distributed in the front projection area on the first flexible substrate;
  • Each row of redundant traces is connected to one of the first data lines extending along the first direction; each row of redundant traces is connected to other first data lines extending along the first direction. Orthographic projections on the first flexible substrate do not overlap;
  • each of the redundant traces does not exceed the length of the orthographic projection area of the pixel driving circuit on the first flexible substrate along the second direction.
  • the first portion also extends to the second partition distributed to the first sub-region
  • the third portion also extends to the second subarea of the third subarea.
  • the first part and the third part distributed in the second partition extend along the second direction, and any two adjacent first parts along the first direction Data lines are symmetrically distributed on opposite sides of the channel region of one of the driving transistors;
  • any one of the pixel driving circuits has two first data lines distributed in the orthographic projection area on the first flexible substrate.
  • the width of the connecting portion of the first region and the second region is equal to the width of the second region along the first direction
  • the first portion also extends to the second area
  • the third portion also extends to the second area.
  • the first part, the second part and the third part distributed in the second area are arranged sequentially along the first direction, and the first part, the third part The two parts and the third part respectively extend along the second direction;
  • the plurality of second data lines are arranged sequentially along the first direction, and the plurality of second data lines extend along the second direction;
  • any one of the pixel driving circuits has one first data line distributed in the orthographic projection area on the first flexible substrate; and the plurality of first data lines are connected to the first data line.
  • the orthographic projections of the plurality of second data lines on the first flexible substrate overlap in one-to-one correspondence.
  • the non-display area further includes an upper frame area located on a side of the second area away from the first area, and the upper frame area is connected to the second area;
  • the first flexible substrate, the plurality of first data lines and the second flexible substrate also extend from the second area to the upper frame area;
  • the pixel driving circuit includes a first conductive layer and a second conductive layer, the first conductive layer and the second conductive layer are arranged away from the second flexible substrate in turn; the first conductive layer and the second conductive layer An insulating layer is provided between the conductive layers;
  • the first conductive layer includes a plurality of first graphics, and orthographic projections of the plurality of first graphics on the first flexible substrate extend from the upper frame area to the second area;
  • the plurality of first data lines located in the upper frame area are connected to the plurality of first patterns in one-to-one correspondence through first via holes opened in the second flexible substrate;
  • the second conductive layer includes the plurality of second data lines
  • the plurality of first patterns located in the second area are respectively connected to the plurality of second data lines in one-to-one correspondence through second via holes opened in the insulating layer.
  • multiple light emitting units and packaging layers are also included.
  • the plurality of light-emitting units are located in the display area and on a side of the pixel driving circuit away from the second flexible substrate;
  • the plurality of light-emitting units are arranged in an array, and the plurality of light-emitting units are connected to the plurality of pixel driving circuits in a one-to-one correspondence;
  • the encapsulation layer is located on a side of the light-emitting unit away from the pixel driving circuit and is used to encapsulate the light-emitting unit;
  • the upper boundary of the encapsulation layer is located in the upper frame area
  • the first via hole does not overlap with an orthographic projection of the encapsulation layer on the first flexible substrate.
  • the first conductive layer further includes a plurality of second patterns located in the display area, and the plurality of second patterns are respectively used as one plate of a storage capacitor in each of the pixel driving circuits;
  • the second pattern does not overlap with orthographic projections of the plurality of first data lines on the first flexible substrate.
  • an embodiment of the present disclosure further provides a display device, which includes the above-mentioned display panel.
  • FIG. 1a is a schematic structural top view of a display panel in which a fan-shaped wiring area is arranged in the display area in an embodiment of the present disclosure.
  • Figure 1b is an enlarged schematic diagram of the P position in Figure 1a.
  • Figure 1c is a further enlarged view of the front side of the data signal access area shown in Figure 1b.
  • Figure 1d is a further enlarged view of the back side of the data signal access area shown in Figure 1b.
  • Figure 1e is a structural cross-sectional view along the EE' section line in Figure 1c.
  • Figure 2 is a schematic diagram of the mura pattern appearing on the display panel during the lighting test through the pixel driving circuit.
  • Figure 3 is a schematic diagram of a display panel without mura phenomenon when the OLED light-emitting unit is lit without driving the pixel circuit.
  • FIG. 4 is a schematic structural top view of the display side of another display panel in an embodiment of the present disclosure.
  • FIG. 5 is a partially enlarged schematic diagram of the first area in FIG. 4 .
  • Figure 6 is a structural cross-sectional view along the AA' section line in Figure 4.
  • Figure 7 is a structural cross-sectional view along the BB' line in Figure 4.
  • Figure 8 is a structural cross-sectional view along the CC' section line in Figure 4.
  • FIG. 9 is a schematic top view of the distribution of first data lines in the second sub-region in an embodiment of the present disclosure.
  • FIG. 10 is an enlarged schematic diagram of the third part of the first data line extending and distributed to the first partition in the embodiment of the present disclosure.
  • FIG. 11 is a schematic top view of the distribution of first data lines in the first partition in an embodiment of the present disclosure.
  • FIG. 12 is a circuit diagram of an exemplary pixel driving circuit.
  • FIG. 13 is a schematic top view of the distribution of the third part of the first data lines in the second partition in the embodiment of the present disclosure.
  • Figure 14 is a structural cross-sectional view along the DD' line in Figure 4.
  • first and second are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of indicated technical features. Therefore, features defined as “first” and “second” may explicitly or implicitly include one or more of these features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.
  • display panels usually have fan-shaped wiring areas (Fanout wiring areas), located in the non-display area, used to lead data signal lines from the driving terminals to the display area to provide corresponding data signals for the pixel driving circuits in the display area.
  • this design method will significantly increase the size of the lower frame, which is not conducive to the realization of extremely narrow frames.
  • an embodiment of the present disclosure provides a display panel.
  • FIG. 1a is a schematic structural top view of a display panel in an embodiment of the present disclosure in which a fan-shaped wiring area is arranged in the display area.
  • the fan-shaped wiring area of the display panel can be set in the display area. It is beneficial to set the fan-shaped wiring area 110 of the display panel (i.e., the fanout wiring area, that is, the divergent wiring area like a trumpet) in the display area 100. Achieve extremely narrow bezels for display panels.
  • the fan-shaped wiring area 110 can be provided in the display area 100 by adding a layer of metal wiring (ie, SDO layer wiring 9) on the bottom layer of the backplane of the display area 100 of the display panel.
  • the SD0 layer trace 9 introduces the display data signal of the display panel from the bending area 103 outside the display area 100 (bent to the back of the display panel to be bound and connected to the peripheral circuits located on the back of the display panel) to the display area 100.
  • the display area 100SD0 layer wiring 9 implements fan-shaped expansion to connect the display data signal to each data line 10.
  • the data line 10 inputs the display data signal into each column of pixels, thereby realizing the display of each column of pixels.
  • the access area 111 of the display data signal (that is, the connection area between the SD0 layer trace and the data line) is designed to be in the display area 100
  • the display area 100 is provided with M rows of pixels.
  • the area where the middle row of pixels is located can be the area where the middle row of pixels is located, such as the area where the M/2th (an integer) row of pixels is located, or it can be the area where the middle rows of pixels are located, such as The area where the pixels of row M/2-2 (is an integer), row M/2-1 (is an integer), row M/2 (is an integer), and row M/2+1 (is an integer) are located.
  • Figure 1b is an enlarged schematic diagram of the P position in Figure 1a;
  • Figure 1c is a further enlarged view of the front of the data signal access area shown in Figure 1b;
  • Figure 1d is an enlarged view of the data signal access area shown in Figure 1b Further enlarged view of the back side of the entry area; it can be seen from Figure 1c and Figure 1d that the SD0 layer trace 9 located on the bottom layer is connected to the data line 10 through the via 11 (the data line 10 is covered by the SD0 layer trace 9).
  • Figure 1e is a cross-sectional view of the structure along the EE' section line in Figure 1c.
  • Figure 1e is a cross-sectional view of the structure along the EE' section line in Figure 1c.
  • the various film layers of the transistor are schematically shown in Figure 1e. The location is also shown.
  • the first flexible substrate 1, the SDO layer traces 9, and the second flexible substrate 2 are stacked in sequence.
  • the active layer 13 On the side of the second flexible substrate 2 away from the SDO layer traces 9, the active layer 13, the first Gate insulation layer 14, first gate layer 15, second gate insulation layer 16, second gate layer 17, intermediate dielectric layer 18, SD1 conductive layer 19 and flat layer 21; active layer 13, first gate insulation
  • the layer 14 , the first gate layer 15 , the second gate insulating layer 16 , the second gate layer 17 , the intermediate dielectric layer 18 , the SD1 conductive layer 19 and the flat layer 21 are arranged away from the second flexible substrate 2 in sequence.
  • the data line 10 is located on the SD1 conductive layer 19; the SD0 layer trace 9 is opened on the second flexible substrate 2, the first gate insulating layer 14, the second gate
  • the via hole in the insulating layer 16 is connected to the second gate layer 17; the second gate layer 17 is connected to the data line 10 located in the SD1 conductive layer 19 through the via hole opened in the intermediate dielectric layer 18; thus realizing the SD0 layer routing Connection between line 9 and data line 10.
  • the via holes opened in the second flexible substrate 2, the first gate insulating layer 14, the second gate insulating layer 16 and the via holes opened in the intermediate dielectric layer 18 together constitute the S0 layer trace 9 and the data line 10. via 11 connecting between them.
  • the range of the access area 111 displaying the data signal may be the area where the 3-4 rows of pixels are located in the middle.
  • the via holes 11 for connecting the multiple SD0 layer traces 9 and the multiple data lines 10 are not in a straight line, because the setting position of each via hole 11 needs to be in In the orthographic projection direction, avoid overlapping with other conductive film layers except the second gate layer; and the placement of each conductive film layer in each pixel area is different, so any row in the middle where the access area 111 of the display data signal is located In the area where the pixel is located, the via holes 11 for connecting the plurality of SD0 layer traces 9 and the plurality of data lines 10 are not in a straight line.
  • the display panel also includes a reference power trace 22, located in the display area 100; the reference power trace 22 is located on the same layer as the S0 layer trace 9, and the reference power trace 22 is located in the SD0 The area outside the distribution area of layer traces 9, and the two are insulated from each other; the reference power traces 22 are in a grid shape, and the grid-shaped reference power traces 22 are all over the display area 100 outside the distribution area of SD0 layer traces 9 Area.
  • the display panel also includes an anode layer, a pixel defining layer, a luminescent functional layer and a cathode layer.
  • the anode layer, pixel defining layer and cathode layer are stacked on the flat layer in sequence; the pixel defining layer has an opening, and the luminescent functional layer is located in the opening;
  • the reference power trace 22 is connected to the cathode layer through the connection leads in the peripheral frame area of the display area 100 to provide a reference power supply for the cathode layer; this can reduce the load and power consumption of the display panel.
  • FIG 2 which is a schematic diagram of the above-mentioned display panel showing mura pattern when the pixel driving circuit is used for lighting test
  • Figure 3 which is a schematic diagram of the above-mentioned display panel showing no mura phenomenon when the OLED light-emitting unit is not lit by driving the pixel circuit
  • the appearance of mura pattern is not caused by the uneven anode of the OLED light-emitting unit, but because the SD0 layer wiring is irregularly arranged in the drive transistor channel area of the pixel drive circuit.
  • the channel area of the driving transistor becomes uneven, which in turn causes the width-to-length ratio of the channel area of the driving transistor to change, causing the driving current of the driving transistor to change, ultimately leading to the mura phenomenon.
  • the display panel includes a display area 100; the display panel also includes a first flexible substrate 1 and a second flexible substrate 2 and a plurality of first data lines (i.e., SD0 layer traces 9), the plurality of first data lines are located between the stacked first flexible substrate 1 and the second flexible substrate 2; a plurality of first data lines The data lines are distributed in the display area 100; the display panel also includes a plurality of pixel driving circuits and a plurality of second data lines (ie, the data lines 10 located on the SD1 conductive layer) located in the display area 100, and a plurality of pixel driving circuits and a plurality of second data lines.
  • the second data line is located on the side of the second flexible substrate 2 away from the first data line; a plurality of pixel driving circuits are arranged in an array; a plurality of first data lines and a plurality of second data lines are connected in a one-to-one correspondence; wherein, The plurality of first data lines include portions 90 that are routed along the column direction of the pixel driving circuit array.
  • the pixel driving circuit includes driving transistors. The portions 90 of the plurality of first data lines that are routed along the column direction of the pixel driving circuit array are at The orthographic projection on a flexible substrate 1 does not overlap with the orthographic projection of the channel region 41 of the driving transistor on the first flexible substrate 1 .
  • an embodiment of the present disclosure provides another display panel.
  • Figure 4 is a schematic top view of the structure of the display side of another display panel in an embodiment of the present disclosure
  • Figure 5 is a first area in Figure 4 A partial enlarged schematic diagram
  • Figure 6 is a structural cross-sectional view along the AA' section line in Figure 4
  • Figure 7 is a structural cross-sectional view along the BB' section line in Figure 4
  • Figure 8 is a structural cross-sectional view along the CC' section line in Figure 4
  • the display panel includes a display area 100; the display panel also includes a first flexible substrate 1, a second flexible substrate 2 and a plurality of first data lines 3.
  • the plurality of first data lines 3 are located on the stacked first flexible substrate 1 and second flexible substrate 1. Between the flexible substrate 2; a plurality of first data lines 3 are distributed in the display area 100; the display panel also includes a plurality of pixel driving circuits 4 and a plurality of second data lines 5, located in the display area 100, and the plurality of pixel driving circuits 4 and a plurality of second data lines 5 located on the side of the second flexible substrate 2 away from the first data lines 3; a plurality of pixel driving circuits 4 arranged in an array; a plurality of first data lines 3 and a plurality of second data lines 5 are connected in a one-to-one correspondence; wherein, the pixel driving circuit 4 includes a driving transistor, the orthographic projection of the plurality of first data lines 3 on the first flexible substrate 1 and the orthographic projection of the channel region of the driving transistor on the first flexible substrate 1 No overlap.
  • the display panel may be an organic electroluminescent display panel.
  • the display panel includes multiple light-emitting units, and the light-emitting units may be OLED (Organic Light Emitting Diode, organic electroluminescent diode) light-emitting units.
  • the OLED light-emitting unit is a top-emission type, and the pixel driving circuit 4 is arranged in the entire display area 100 .
  • the pixel driving circuit 4 may be a 7T1C (ie, seven transistors and one capacitor) circuit, a 7T2C circuit, a 6T1C circuit, or a 6T2C circuit. Or 9T2C circuit.
  • the first data lines 3 can be prevented from being irregularly
  • the wiring is routed under the channel area of the driving transistor to avoid unevenness in the channel area of the driving transistor, thereby avoiding changes in the width-to-length ratio of the channel area of the driving transistor, to avoid changes in the driving current of the driving transistor, and ultimately to avoid When displaying mura defects, the quality of the display panel is ensured.
  • the display area 100 includes a first area 101 and a second area 102, which are connected; a plurality of first data lines 3 are connected by the first area 101 Extends to the second area 102; the display panel also includes a non-display area, the non-display area includes a bending area 103, the bending area 103 is located on the side of the first area 101 away from the second area 102, the bending area 103, the first Region 101 and second region 102 are arranged sequentially along the second direction Y; the second direction Y is the column direction of the pixel driving circuit array; the first region 101 includes a first sub-region 104, a second sub-region 105 and a third sub-region 106, the first sub-region 104, the second sub-region 105 and the third sub-region 106 are sequentially arranged and connected to each other along the first direction X; the first direction X is the row direction of the pixel driving circuit array; the bending region 103 and
  • the first part 31 , the second part 32 and the third part 33 respectively include a plurality of first data lines 3 .
  • first data lines 3 in Figure 4 only the two first data lines 3 in the first part 31, the two first data lines 3 in the second part 32 and the two first data lines 3 in the third part 33 are schematically drawn.
  • the two first data lines 3 in the first part 31, the second part 32 and the third part 33 can representatively illustrate the direction and distribution of the first data lines 3 in each part.
  • connection width between the bending area 103 and the first area 101 is smaller than the connection width between the first area 101 and the bending area 103, the plurality of first data lines connected to the first area 101 are connected from the bending area 103.
  • 3 traces are fan-shaped distribution (i.e. fanout distribution, that is, divergent distribution like a bell mouth).
  • fan-shaped distribution i.e. fanout distribution, that is, divergent distribution like a bell mouth.
  • the fan-shaped distribution spreads to Evenly distributed.
  • the plurality of first data lines 3 distributed in the first area 101 realize fan-shaped wiring distributed in the display area 100. Compared with the situation in the public technology where the fan-shaped wiring is distributed in the frame area, the width of the frame area is greatly reduced, and there is Conducive to achieving extremely narrow borders.
  • the display area 100 is composed of a first area 101 and a second area 102. Compared with the situation in FIG. The whole surface is arranged inside, which avoids the uneven wiring caused by the fan-shaped wiring being only distributed in part of the display area, improves the uniformity of the distribution of the fan-shaped wiring in the display area 100, thereby improving the display panel Effect.
  • FIG. 9 is a schematic top view of the distribution of the first data lines in the second sub-region in an embodiment of the present disclosure; the driving transistors in multiple pixel driving circuits are arranged at the same position; distributed in the second sub-region 105
  • the first part 31, the second part 32 and the third part 33 extend along the second direction Y, and any two adjacent first data lines 3 are symmetrically distributed on opposite sides of a driving transistor channel region 41; in In the second sub-region 105, any pixel driving circuit has two first data lines 3 distributed in the orthographic projection area on the first flexible substrate.
  • the orthographic projection area of the pixel driving circuit on the first flexible substrate includes an area surrounded by two adjacent gate lines and two adjacent second data lines 5 , the two adjacent The orthographic projection of the second data line 5 on the first flexible substrate may also fall within the orthographic projection area of the pixel driving circuit.
  • the symmetrical distribution refers to the symmetrical arrangement of the two first data lines 3. Due to the limitations of the manufacturing process, the symmetrical distribution not only includes the physically symmetrical arrangement of the two first data lines 3, but also includes the two first data lines 3. A case of incomplete physical symmetry of data line 3 graphics.
  • first sub-region 104 includes first partition 107 and The second sub-area 108; the third sub-area 106 includes the first sub-area 107 and the second sub-area 108; the first sub-area 107 and the second sub-area 108 are arranged sequentially and connected to each other along the first direction X; the second sub-area 108 is located in the first sub-area 107 on the side away from the second sub-area 105; the first part 31 extends to the first sub-area 107 of the first sub-area 104; refer to Figure 10, which is an enlargement of the third part extending to the first sub-area in the embodiment of the present disclosure.
  • Schematic diagram; the third part 33 extends to the first partition 107 of the third sub-area 106; the first part 31 includes a plurality of first data lines 3; the third part 33 includes a plurality of first data lines 3.
  • Figure 11 is a schematic top view of the distribution of the first data lines in the first partition in an embodiment of the present disclosure; the first data lines 3 located in different partitions extend in different directions, for example: distribution The first part and the third part in the first partition 107 extend along the first direction X, and the first data line 3 is located between two adjacent rows of pixel driving circuits 4; in the first partition 107, any two adjacent rows Two first data lines 3 are distributed between row pixel driving circuits 4; and the orthographic projections of the first data lines 3 and the channel regions 42 of the switching transistors in the pixel driving circuit 4 on the first flexible substrate do not overlap.
  • the pixel driving circuit is a 7T1C circuit.
  • the pixel driving circuit includes a first reset transistor T1, a threshold compensation transistor T2, a driving transistor T3, a data writing transistor T4, first light emission control transistor T5, second light emission control transistor T6, second reset transistor T7 and storage capacitor Cst.
  • the drain of the data writing transistor T4 is electrically connected to the source of the driving transistor T3, and the source of the data writing transistor T4 is configured to be electrically connected to the data line Data (ie, the second data line in the embodiment of the present disclosure) to receive data signal, the gate of the data writing transistor T4 is configured to be electrically connected to the first scanning signal line Ga1 to receive the scanning signal; the second plate of the storage capacitor Cst is electrically connected to the first power supply voltage line VDD, and the second plate of the storage capacitor Cst is electrically connected to the first power supply voltage line VDD.
  • the first plate is electrically connected to the gate of the driving transistor T3; the source of the threshold compensation transistor T2 is electrically connected to the gate of the driving transistor T3; the drain of the threshold compensation transistor T2 is electrically connected to the drain of the driving transistor T3; threshold compensation The gate of the transistor T2 is configured to be electrically connected to the second scanning signal line Ga2 to receive the compensation control signal; the gate of the first reset transistor T1 The source is configured to be electrically connected to the first reset power terminal Vinit1 to receive the first reset signal, the drain of the first reset transistor T1 is electrically connected to the gate of the driving transistor T3, and the gate of the first reset transistor T1 is configured to The drain of the second reset transistor T7 is electrically connected to the first reset control signal line Rst1 to receive the first reset control signal; the drain of the second reset transistor T7 is configured to be electrically connected to the second reset power supply terminal Vinit2 to receive the first reset signal.
  • the second reset transistor T7 The source of the second reset transistor T7 is electrically connected to the first electrode of the light-emitting unit D, and the gate of the second reset transistor T7 is configured to be electrically connected to the second reset control signal line Rst2 to receive the second reset control signal; the first light-emitting control transistor T5 The source is electrically connected to the first power supply voltage line VDD, the drain of the first light-emitting control transistor T5 is electrically connected to the source of the driving transistor T3, and the gate of the first light-emitting control transistor T5 is configured to be connected to the first light-emitting control signal line.
  • the EM1 is electrically connected to receive the first light-emitting control signal; the source of the second light-emitting control transistor T6 is electrically connected with the drain of the driving transistor T3, and the drain of the second light-emitting control transistor T6 is electrically connected with the first electrode D1 of the light-emitting unit D.
  • the gate of the second light-emitting control transistor T6 is configured to be electrically connected to the second light-emitting control signal line EM2 to receive the second light-emitting control signal; the second electrode of the light-emitting unit D is connected to the second power supply terminal VSS (ie, the embodiment of the present disclosure Reference power traces in ) electrical connections.
  • the first reset transistor T1, the threshold compensation transistor T2, the data writing transistor T4, the first light emission control transistor T5, the second light emission control transistor T6 and the second reset transistor T7 are all switching transistors.
  • the switching transistors in the pixel driving circuit 4 may refer to the first reset transistor T1, the threshold compensation transistor T2, the data writing transistor T4, the first light emission control transistor T5, The second light emission control transistor T6 and the second reset transistor T7.
  • the channel region 42 of the first reset transistor T1, the threshold compensation transistor T2, the first emission control transistor T5 and the second emission control transistor T6 is located close to the junction region of two adjacent rows of pixel driving circuits 4, so try to avoid the first
  • the data line 3 overlaps with the orthographic projection of the channel region 42 of the switching transistors T5, T6, T1, and T2 in the pixel driving circuit 4 on the first flexible substrate.
  • the first data line 3 By preventing the first data line 3 from overlapping the orthographic projection of the channel region 42 of the switching transistor in the pixel driving circuit 4 on the first flexible substrate, the first data line 3 can be prevented from being irregularly routed to the switching transistor. Below the channel region 42, thereby avoiding unevenness in the channel region 42 of the switching transistor, thereby avoiding changes in the width-to-length ratio of the channel region 42 of the switching transistor, thereby avoiding changes in the switching performance of the switching transistor, and ultimately preventing the display panel from being The quality of the display panel is ensured by mura defects when the drive transistor is turned on without threshold compensation and when the display panel is tested for lighting.
  • the display panel further includes a plurality of redundant traces 6 located in the first partition 107 and arranged in an array; the plurality of redundant traces 6 extend along the second direction Y, along Any two adjacent redundant traces 6 in the first direction There are two redundant traces 6 distributed in the orthographic projection area; each row of redundant traces 6 is connected to a first data line 3 extending along the first direction X; each row of redundant traces 6 is connected to other lines along the first direction X
  • the orthographic projections of the extended first data lines 3 on the first flexible substrate do not overlap; the length of each redundant trace 6 does not exceed the orthographic projection area of the pixel driving circuit 4 on the first flexible substrate along the second direction Y length.
  • the first data line 3 in the first partition 107 is a lateral wiring extending along the first direction
  • the vertical wiring of the first data line 3 extending along the second direction Y is vertical, which will cause the first data line 3 to appear uneven in the overall appearance of the first area 101; by setting the first data line 3 in the first partition 107 Redundant wiring 6, that is, adding vertical redundant wiring 6 on the basis of the horizontal wiring in the first partition 107, can reduce the uneven wiring in the overall appearance of the first zone 101, and the redundant wiring
  • the line 6 is similar to the wiring of the second sub-region 105 and also avoids the channel area 41 of the driving transistor, and is symmetrically distributed on the opposite sides of the channel area 41 of the driving transistor, thereby avoiding mura defects during the lighting test.
  • Each row of redundant traces 6 is connected to a first data line 3 extending along the first direction X to prevent signal crosstalk on the first data line 3 when the redundant traces 6 are suspended.
  • Figure 13 is a schematic top view of the distribution of the third part of the first data lines in the second partition in the embodiment of the present disclosure; the first part 31 also extends to the first sub-area. The second subarea 108 of the area 104; the third part 33 also extends to the third subarea 106 The second partition 108.
  • the first part 31 and the third part 33 distributed in the second partition 108 extend along the second direction Y, and any two adjacent first data lines 3 along the first direction X are symmetrically distributed in a On opposite sides of the drive transistor channel region 41; in the second partition 108, any one pixel drive circuit 4 has two first data lines 3 distributed in the orthographic projection area on the first flexible substrate.
  • the width of the connecting portion of the first area 101 and the second area 102 is equal to the width of the second area 102 along the first direction X; the first portion 31 also extends to the second area 102; The third part 33 also extends to the second area 102.
  • the first part 31 , the second part 32 and the third part 33 distributed in the second area 102 are arranged sequentially along the first direction X, and the first part 31 , the second part 32 and the third part 33 respectively extend along the second direction Y; a plurality of second data lines 5 are arranged in sequence along the first direction
  • the circuit 4 has a first data line 3 distributed in the orthographic projection area on the first flexible substrate; and the orthographic projections of the plurality of first data lines 3 and the plurality of second data lines 5 on the first flexible substrate are one-to-one. should overlap. This facilitates the connection between the first data line 3 located on the lower layer and the second data line 5 located on the upper layer.
  • the distribution density of the first data lines 3 in the first area 101 is greater than that of the first data lines 3 in the second area 102 Distribution density.
  • Figure 14 is a structural cross-sectional view along the DD' section line in Figure 4; the non-display area also includes an upper frame area 109, located in the second area 102 away from the first area 101. One side, and the upper frame area 109 is connected to the second area 102; the first flexible substrate 1, the plurality of first data lines 3 and the second flexible substrate 2 also extend from the second area 102 to the upper frame area 109; the pixel driving circuit 4 It includes a first conductive layer and a second conductive layer, and the first conductive layer and the second conductive layer are arranged away from the second flexible substrate 2 in sequence; an insulating layer 7 is arranged between the first conductive layer and the second conductive layer; A conductive layer includes a plurality of first graphics 8, and the orthographic projection of the plurality of first graphics 8 on the first flexible substrate 1 extends from the upper frame area 109 to the second area 102; a plurality of first patterns located in the upper frame area 109
  • the data lines 3 are connected
  • the first conductive layer also includes a plurality of second patterns (not shown in the figure) located in the display area, and the plurality of second patterns are respectively used as one plate of the storage capacitor in each pixel driving circuit;
  • the orthographic projections of the two graphics and the plurality of first data lines on the first flexible substrate do not overlap.
  • the pixel driving circuit includes an active layer, a first gate layer, a first conductive layer and a second conductive layer, the active layer, the first gate layer, the first conductive layer and the second conductive layer in order They are arranged away from the second flexible substrate, and any two adjacent ones are insulated from each other by an inorganic insulating layer.
  • the active layer includes the channel region of the driving transistor and the pattern of the channel region of the switching transistor;
  • the first gate layer includes the gate line, the gate electrode of the driving transistor and the pattern of the gate electrode of the switching transistor; wherein, the gate electrode of the driving transistor Used as one plate of the storage capacitor in the pixel drive circuit;
  • the first conductive layer includes a first pattern 8 and a second pattern, wherein the second pattern is used as another plate of the storage capacitor in the pixel drive circuit, that is, the second pattern Overlapping with the orthographic projection of the gate of the driving transistor on the first flexible substrate, the second pattern and the gate of the driving transistor form a storage capacitor.
  • the second conductive layer includes patterns of a plurality of second data lines 5 and patterns of source and drain electrodes of the driving transistors and switching transistors in the pixel driving circuit.
  • the display panel further includes a plurality of light-emitting units and an encapsulation layer 12.
  • the plurality of light-emitting units are located in the display area 100 and are located on the side of the pixel driving circuit away from the second flexible substrate;
  • the light-emitting units are arranged in an array, and the plurality of light-emitting units are connected to the plurality of pixel driving circuits in a one-to-one correspondence;
  • the packaging layer 12 is located on the side of the light-emitting unit away from the pixel driving circuit.
  • the upper boundary S of the encapsulation layer 12 is located in the upper frame area 109; the first via hole 20 does not overlap with the orthographic projection of the encapsulation layer on the first flexible substrate. That is, the first via hole 20 is located outside the upper boundary S of the packaging layer.
  • the light-emitting unit is an organic electroluminescent unit, that is, an OLED (Organic Light Emitting Diode) light-emitting unit.
  • OLED Organic Light Emitting Diode
  • the portions of the plurality of first data lines that are routed along the column direction of the pixel driving circuit array are orthogonally projected on the first flexible substrate and the channel region of the driving transistor is positioned on the first flexible substrate.
  • the orthographic projection on a flexible substrate does not overlap, which can improve or avoid the irregular routing of the first data line under the channel area of the driving transistor, thereby improving or avoiding unevenness in the channel area of the driving transistor, thereby improving or Avoid changes in the width-to-length ratio of the channel region of the drive transistor to improve or avoid changes in the drive current of the drive transistor, ultimately improving or avoiding mura defects in the display panel when the drive transistor does not perform threshold compensation and during the display panel lighting test , ensuring the quality of the display panel.
  • an embodiment of the present disclosure also provides a display device, including the display panel in the above embodiment.
  • the display device can be: an OLED panel, an OLED TV, a mobile phone, a tablet computer, a notebook computer, a monitor, a digital photo frame, a navigator, or any other product or component with a display function.

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Abstract

一种显示面板，包括显示区；显示面板还包括第一柔性基底、第二柔性基底和多条第一数据线，多条第一数据线位于叠置的第一柔性基底和第二柔性基底之间；多条第一数据线分布于显示区；显示面板还包括多个像素驱动电路和多条第二数据线，位于显示区，且多个像素驱动电路和多条第二数据线位于第二柔性基底的背离第一数据线的一侧；多个像素驱动电路呈阵列排布；多条第一数据线与多条第二数据线一一对应连接；其中，多条第一数据线包括沿像素驱动电路阵列的列方向走线的部分，像素驱动电路包括驱动晶体管，多条第一数据线的至少沿像素驱动电路阵列的列方向走线的部分在第一柔性基底上的正投影与驱动晶体管的沟道区在第一柔性基底上的正投影不交叠。

Description

显示面板和显示装置 技术领域
本公开涉及显示技术领域，具体涉及一种显示面板和显示装置。
背景技术
近几年全面屏的发展十分迅速，这对屏幕的形态提出了新的需求，显示屏走向全面屏时代，为了增大屏占比，窄边框产品越来越受到广大关注。
发明内容
第一方面，本公开实施例提供一种显示面板，包括显示区；
所述显示面板还包括第一柔性基底、第二柔性基底和多条第一数据线，
所述多条第一数据线位于叠置的所述第一柔性基底和所述第二柔性基底之间；所述多条第一数据线分布于所述显示区；
所述显示面板还包括多个像素驱动电路和多条第二数据线，位于所述显示区，且所述多个像素驱动电路和所述多条第二数据线位于所述第二柔性基底的背离所述第一数据线的一侧；
所述多个像素驱动电路呈阵列排布；所述多条第一数据线与所述多条第二数据线一一对应连接；
其中，所述多条第一数据线包括沿像素驱动电路阵列的列方向走线的部分，所述像素驱动电路包括驱动晶体管，所述多条第一数据线的至少沿像素驱动电路阵列的列方向走线的部分在所述第一柔性基底上的正投影与所述驱动晶体管的沟道区在所述第一柔性基底上的正投影不交叠。
在一些实施例中，所述显示区包括第一区和第二区，所述第一区和所述第二区连接；
所述显示面板还包括非显示区，所述非显示区包括弯折区，所述弯折区位于所述第一区的远离所述第二区的一侧，所述弯折区、所述第一区和 所述第二区沿第二方向依次排布；所述第二方向为像素驱动电路阵列的列方向；
所述第一区包括第一子区、第二子区和第三子区，所述第一子区、所述第二子区和所述第三子区沿第一方向依次排布且彼此连接；所述第一方向为像素驱动电路阵列的行方向；
所述弯折区与所述第二子区连接；
所述第一柔性基底、所述多条第一数据线和所述第二柔性基底由所述第二子区延伸至所述弯折区；
所述第二子区内所述多条第一数据线包括第一部分、第二部分和第三部分；所述第一部分、所述第二部分和所述第三部分沿所述第一方向依次排布；
所述第一部分由所述第二子区向所述第一子区延伸分布，所述第三部分由所述第二子区向所述第三子区延伸分布，所述第二部分由所述第二子区向所述第二区延伸分布。
在一些实施例中，分布在所述第二子区内的所述第一部分、所述第二部分和所述第三部分沿所述第二方向延伸，且任意相邻的两条所述第一数据线对称分布于一个所述驱动晶体管沟道区的相对两侧；
在所述第二子区内，任意一个所述像素驱动电路在所述第一柔性基底上的正投影区域内分布有两条所述第一数据线。
在一些实施例中，所述第一子区包括第一分区和第二分区；所述第三子区包括第一分区和第二分区；
所述第一分区和所述第二分区沿所述第一方向依次排布且相互连接；所述第二分区位于所述第一分区的远离所述第二子区的一侧；
所述第一部分延伸分布至所述第一子区的所述第一分区；
所述第三部分延伸分布至所述第三子区的所述第一分区；
所述第一部分包括多条所述第一数据线；
所述第三部分包括多条所述第一数据线。
在一些实施例中，分布在所述第一分区内的所述第一部分和所述第三部分沿所述第一方向延伸，且所述第一数据线位于相邻两行所述像素驱动电路之间；
在所述第一分区内，任意相邻两行所述像素驱动电路之间分布有两条所述第一数据线；且所述第一数据线与所述像素驱动电路中开关晶体管的沟道区在所述第一柔性基底上的正投影不交叠。
在一些实施例中，还包括多条冗余走线，位于所述第一分区内，且排布呈阵列；
所述多条冗余走线沿所述第二方向延伸，沿所述第一方向任意相邻的两条所述冗余走线对称分布于一个所述驱动晶体管沟道区的相对两侧；
在所述第一分区内，任意一个所述像素驱动电路在所述第一柔性基底上的正投影区域内分布有两条所述冗余走线；
每行所述冗余走线连接一条沿所述第一方向延伸的所述第一数据线；每行所述冗余走线与其他沿所述第一方向延伸的所述第一数据线在所述第一柔性基底上的正投影不交叠；
每条所述冗余走线的长度不超过所述像素驱动电路在所述第一柔性基底上的正投影区域沿所述第二方向的长度。
在一些实施例中，所述第一部分还延伸分布至所述第一子区的所述第二分区；
所述第三部分还延伸分布至所述第三子区的所述第二分区。
在一些实施例中，分布在所述第二分区内的所述第一部分和所述第三部分沿所述第二方向延伸，且沿所述第一方向任意相邻的两条所述第一数据线对称分布于一个所述驱动晶体管沟道区的相对两侧；
在所述第二分区内，任意一个所述像素驱动电路在所述第一柔性基底上的正投影区域内分布有两条所述第一数据线。
在一些实施例中，所述第一区与所述第二区的连接部分的宽度等于所述第二区沿第一方向的宽度；
所述第一部分还延伸分布至所述第二区；
所述第三部分还延伸分布至所述第二区。
在一些实施例中，分布在所述第二区内的所述第一部分、所述第二部分和所述第三部分沿所述第一方向依次排布，且所述第一部分、所述第二部分和所述第三部分分别沿所述第二方向延伸；
所述多条第二数据线沿所述第一方向依次排布，且所述多条第二数据线沿所述第二方向延伸；
在所述第二区内，任意一个所述像素驱动电路在所述第一柔性基底上的正投影区域内分布有一条所述第一数据线；且所述多条第一数据线与所述多条第二数据线在所述第一柔性基底上的正投影一一对应交叠。
在一些实施例中，所述非显示区还包括上边框区，位于所述第二区的远离所述第一区的一侧，且所述上边框区与所述第二区连接；
所述第一柔性基底、所述多条第一数据线和所述第二柔性基底还由所述第二区延伸至所述上边框区；
所述像素驱动电路包括第一导电层和第二导电层，所述第一导电层和所述第二导电层依次远离所述第二柔性基底设置；所述第一导电层和所述第二导电层之间设置有绝缘层；
所述第一导电层包括多个第一图形，所述多个第一图形在所述第一柔性基底上的正投影由所述上边框区延伸至所述第二区；
位于所述上边框区内的所述多条第一数据线通过开设在所述第二柔性基底中的第一过孔分别一一对应地连接所述多个第一图形；
所述第二导电层包括所述多条第二数据线；
位于所述第二区内的所述多个第一图形通过开设在所述绝缘层中的第二过孔分别一一对应地连接所述多条第二数据线。
在一些实施例中，还包括多个发光单元和封装层，
所述多个发光单元位于所述显示区，且位于所述像素驱动电路背离所述第二柔性基底的一侧；
所述多个发光单元排布呈阵列，所述多个发光单元与所述多个像素驱动电路一一对应连接；
所述封装层位于所述发光单元的背离所述像素驱动电路的一侧，用于对所述发光单元进行封装；
所述封装层的上边界位于所述上边框区；
所述第一过孔与所述封装层在所述第一柔性基底上的正投影不交叠。
在一些实施例中，所述第一导电层还包括多个第二图形，位于所述显示区，所述多个第二图形分别用作各所述像素驱动电路中存储电容的一个极板；
所述第二图形与所述多条第一数据线在所述第一柔性基底上的正投影不交叠。
第二方面，本公开实施例还提供一种显示装置，其中，包括上述显示面板。
附图说明
附图用来提供对本公开实施例的进一步理解，并且构成说明书的一部分，与本公开实施例一起用于解释本公开，并不构成对本公开的限制。通过参考附图对详细示例实施例进行描述，以上和其它特征和优点对本领域技术人员将变得更加显而易见，在附图中：
图1a为本公开实施例中一种显示面板的扇形走线区设置在显示区的结构俯视示意图。
图1b为图1a中P位置的放大示意图。
图1c为图1b中显示数据信号接入区正面的进一步放大图。
图1d为图1b中显示数据信号接入区背面的进一步放大图。
图1e为沿图1c中EE＇剖切线的结构剖视图。
图2为显示面板在通过像素驱动电路点亮测试时出现mura纹的示意图。
图3为显示面板在不通过驱动像素电路点亮OLED发光单元时未出现mura现象的示意图。
图4为本公开实施例中另一种显示面板显示侧的结构俯视示意图。
图5为图4中第一区的局部放大示意图。
图6为沿图4中AA＇剖切线的结构剖视图。
图7为沿图4中BB＇剖切线的结构剖视图。
图8为沿图4中CC＇剖切线的结构剖视图。
图9为本公开实施例中第二子区内第一数据线的分布俯视示意图。
图10为本公开实施例中第三部分第一数据线延伸分布至第一分区的放大示意图。
图11为本公开实施例中第一分区内第一数据线的分布俯视示意图。
图12为一种示例性的像素驱动电路的电路图。
图13为本公开实施例中第二分区内第三部分第一数据线的分布俯视示意图。
图14为沿图4中DD＇剖切线的结构剖视图。
具体实施方式
为使本领域技术人员更好地理解本公开实施例的技术方案，下面结合附图和具体实施方式对本公开实施例提供的显示面板和显示装置作进一步详细描述。
在下文中将参考附图更充分地描述本公开实施例，但是所示的实施例可以以不同形式来体现，且不应当被解释为限于本公开阐述的实施例。反之，提供这些实施例的目的在于使本公开透彻和完整，并将使本领域技术人员充分理解本公开的范围。
本公开实施例不限于附图中所示的实施例，而是包括基于制造工艺而形成的配置的修改。因此，附图中例示的区具有示意性属性，并且图中所示区的形状例示了区的具体形状，但并不是旨在限制性的。
以下，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。
相关技术中，显示面板通常具有扇形走线区(Fanout走线区)，位于非显示区，用于将数据信号线从驱动端子处引出至显示区，为显示区像素驱动电路提供相应的数据信号，但相关技术中这种设计方式会显著增大下边框的尺寸，不利于极窄边框的实现。
为了解决上述问题，第一方面，本公开实施例提供一种显示面板，参照图1a，为本公开实施例中一种显示面板的扇形走线区设置在显示区的结构俯视示意图。可以将显示面板的扇形走线区设置在显示区，将显示面板的扇形走线区110(即fanout走线区，也即似喇叭口一样的发散式走线区)设置在显示区100有利于实现显示面板的极窄边框。扇形走线区110设置在显示区100可以通过在显示面板显示区100的背板底层增设一层金属走线(即SD0层走线9)实现。SD0层走线9将显示面板的显示数据信号从显示区100以外的弯折区103(弯折到显示面板背面，以与位于显示面板背面的***电路绑定连接)引入到显示区100，在显示区100SD0层走线9实现扇形展开以便将显示数据信号接入每一条数据线10中，数据线10将显示数据信号输入每一列像素中，从而实现每一列像素的显示。
参照图1a，为了保证数据线传输的显示数据信号在靠近驱动端和远离驱动端相近，设计显示数据信号的接入区111(即SD0层走线与数据线的连接区)在显示区100的沿数据线10延伸方向的中间行像素所在区域。假设 显示区100内设置有M行像素，中间行像素所在区域可以为中间的一行像素所在区域，如第M/2(为整数)行像素所在区域，也可以为中间的多行像素所在区域，如第M/2-2(为整数)行、第M/2-1(为整数)行、第M/2(为整数)行和第M/2+1(为整数)行像素所在区域。参照图1b，图1c和图1d，图1b为图1a中P位置的放大示意图；图1c为图1b中显示数据信号接入区正面的进一步放大图；图1d为图1b中显示数据信号接入区背面的进一步放大图；从图1c和图1d中可见，位于底层的SD0层走线9通过过孔11与数据线10(数据线10被SD0层走线9覆盖)实现连接。
在一些实施例中，参照图1e，为沿图1c中EE＇剖切线的结构剖视图。实际沿图1c中的EE＇剖切线的剖切面上只能显示出过孔11的剖面结构，为了说明像素驱动电路中晶体管各膜层的位置，图1e中示意性的将晶体管的各膜层位置也示出。显示区100内，第一柔性基底1、SD0层走线9、第二柔性基底2依次叠置，在第二柔性基底2背离SD0层走线9的一侧设置有有源层13、第一栅绝缘层14、第一栅极层15、第二栅绝缘层16、第二栅极层17、中间介电层18、SD1导电层19和平坦层21；有源层13、第一栅绝缘层14、第一栅极层15、第二栅绝缘层16、第二栅极层17、中间介电层18、SD1导电层19和平坦层21依次远离第二柔性基底2设置。在显示数据信号的接入区111所在的中间行像素所在区域，数据线10位于SD1导电层19；SD0层走线9通过开设在第二柔性基底2、第一栅绝缘层14、第二栅绝缘层16中的过孔连接第二栅极层17；第二栅极层17通过开设在中间介电层18中的过孔连接位于SD1导电层19的数据线10；从而实现了SD0层走线9与数据线10之间的连接。开设在第二柔性基底2、第一栅绝缘层14、第二栅绝缘层16中的过孔和开设在中间介电层18中的过孔共同构成了实现SD0层走线9与数据线10之间连接的过孔11。
在一些实施例中，参照图1b，图1c和图1d，显示数据信号的接入区111范围可以为中间的3-4行像素所在区域。在显示数据信号的接入区111 所在的中间任一行像素所在区域，多条SD0层走线9与多条数据线10之间分别一一对应实现连接的过孔11并不在一条直线上，因为各个过孔11的设置位置需要在正投影方向上避免与除第二栅极层以外的其他导电膜层交叠；而各像素区域内各导电膜层的设置位置不同，所以在显示数据信号的接入区111所在的中间任一行像素所在区域，多条SD0层走线9与多条数据线10之间分别一一对应实现连接的过孔11并不在一条直线上。
在一些实施例中，参照图1a和图1b，显示面板还包括参考电源走线22，位于显示区100；参考电源走线22与SD0层走线9位于同一层，参考电源走线22位于SD0层走线9分布区域以外的区域，且二者之间相互绝缘；参考电源走线22为网格状，网格状参考电源走线22布满显示区100内SD0层走线9分布区域以外的区域。显示面板还包括阳极层、像素界定层、发光功能层和阴极层，阳极层、像素界定层和阴极层依次叠置于平坦层上；像素界定层中开设有开口，发光功能层位于开口中；参考电源走线22通过显示区100***四周边框区的连接引线连接阴极层，以为阴极层提供参考电源；如此能降低显示面板的负载和功耗。
参照图2，为上述显示面板在通过像素驱动电路点亮测试时出现mura纹的示意图；参照图3，为上述显示面板在不通过驱动像素电路点亮OLED发光单元时未出现mura现象的示意图；从图2和图3中的测试结果可以判断，mura纹的出现不是由OLED发光单元的阳极不平坦引起的，而是由于SD0层走线不规则地设置于像素驱动电路的驱动晶体管沟道区下方，使驱动晶体管沟道区出现不平整，继而导致驱动晶体管沟道区的宽长比发生变化，以致驱动晶体管的驱动电流发生变化，最终导致mura现象。
为了解决上述mura不良的问题，本公开实施例提供一种显示面板，参照图1c、图1d和图1e，显示面板包括显示区100；显示面板还包括第一柔性基底1、第二柔性基底2和多条第一数据线(即SD0层走线9)，多条第一数据线位于叠置的第一柔性基底1和第二柔性基底2之间；多条第一数 据线分布于显示区100；显示面板还包括多个像素驱动电路和多条第二数据线(即位于SD1导电层的数据线10)，位于显示区100，且多个像素驱动电路和多条第二数据线位于第二柔性基底2的背离第一数据线的一侧；多个像素驱动电路呈阵列排布；多条第一数据线与多条第二数据线一一对应连接；其中，多条第一数据线包括沿像素驱动电路阵列的列方向走线的部分90，像素驱动电路包括驱动晶体管，多条第一数据线的沿像素驱动电路阵列的列方向走线的部分90在第一柔性基底1上的正投影与驱动晶体管的沟道区41在第一柔性基底1上的正投影不交叠。
为了解决上述mura不良的问题，本公开实施例提供另一种显示面板，参照图4，为本公开实施例中另一种显示面板显示侧的结构俯视示意图；图5为图4中第一区的局部放大示意图；图6为沿图4中AA＇剖切线的结构剖视图；图7为沿图4中BB＇剖切线的结构剖视图；图8为沿图4中CC＇剖切线的结构剖视图；显示面板包括显示区100；显示面板还包括第一柔性基底1、第二柔性基底2和多条第一数据线3，多条第一数据线3位于叠置的第一柔性基底1和第二柔性基底2之间；多条第一数据线3分布于显示区100；显示面板还包括多个像素驱动电路4和多条第二数据线5，位于显示区100，且多个像素驱动电路4和多条第二数据线5位于第二柔性基底2的背离第一数据线3的一侧；多个像素驱动电路4呈阵列排布；多条第一数据线3与多条第二数据线5一一对应连接；其中，像素驱动电路4包括驱动晶体管，多条第一数据线3在第一柔性基底1上的正投影与驱动晶体管的沟道区在第一柔性基底1上的正投影不交叠。
本实施例中，显示面板可以为有机电致发光显示面板。显示面板包括多个发光单元，发光单元可以是OLED(Organic Light Emitting Diode，有机电致发光二极管)发光单元。在一些实施例中，OLED发光单元为顶发射型，像素驱动电路4排布于整个显示区100内。像素驱动电路4可以是7T1C(即七个晶体管和一个电容)电路、7T2C电路、6T1C电路、6T2C电路 或者9T2C电路。
通过使多条第一数据线3在第一柔性基底1上的正投影与驱动晶体管的沟道区在第一柔性基底1上的正投影不交叠，能避免第一数据线3不规则地走线于驱动晶体管的沟道区下面，从而避免驱动晶体管的沟道区出现不平整，继而避免驱动晶体管的沟道区的宽长比发生变化，以避免驱动晶体管的驱动电流发生变化，最终避免显示显示时出现mura不良，确保了显示面板的品质。
在一些实施例中，参照图4和图8，显示区100包括第一区101和第二区102，第一区101和第二区102连接；多条第一数据线3由第一区101延伸至第二区102；显示面板还包括非显示区，非显示区包括弯折区103，弯折区103位于第一区101的远离第二区102的一侧，弯折区103、第一区101和第二区102沿第二方向Y依次排布；第二方向Y为像素驱动电路阵列的列方向；第一区101包括第一子区104、第二子区105和第三子区106，第一子区104、第二子区105和第三子区106沿第一方向X依次排布且彼此连接；第一方向X为像素驱动电路阵列的行方向；弯折区103与第二子区105连接；第一柔性基底1、多条第一数据线3和第二柔性基底2由第二子区105延伸至弯折区103；第二子区105内多条第一数据线3包括第一部分31、第二部分32和第三部分33；第一部分31、第二部分32和第三部分33沿第一方向X依次排布；第一部分31由第二子区105向第一子区104延伸分布，第三部分33由第二子区105向第三子区106延伸分布，第二部分32由第二子区105向第二区102延伸分布。
本实施例中，第一部分31、第二部分32和第三部分33分别包括多条第一数据线3。图4中只示意性地画出第一部分31中的两条第一数据线3、第二部分32中的两条第一数据线3和第三部分33中的两条第一数据线3，第一部分31、第二部分32和第三部分33中的两条第一数据线3能够代表性地说明各部分中第一数据线3的走向及分布。
其中，由于弯折区103的与第一区101的连接宽度小于第一区101的与弯折区103的连接宽度，所以从弯折区103接入第一区101的多条第一数据线3走线为扇形分布(即fanout分布，也即似喇叭口一样的发散式分布)，当多条第一数据线3由第一区101走线至第二区102时，由扇形分布扩散为均匀分布。分布在第一区101的多条第一数据线3实现了扇形走线分布于显示区100内，相对于公开技术中扇形走线分布于边框区的情况，大大缩减了边框区的宽度，有利于实现极窄边框。
本实施例中，显示区100由第一区101和第二区102构成，相比于图1a中扇形走线分布于显示区的部分区域的情况，多条第一数据线3在显示区100内为整面排布，避免了扇形走线只分布于显示区的部分区域所导致的走线不均匀，提升了扇形走线在显示区100内的分布均匀性，从而提升了显示面板的显示效果。
在一些实施例中，参照图9，为本公开实施例中第二子区内第一数据线的分布俯视示意图；多个像素驱动电路中驱动晶体管的设置位置相同；分布在第二子区105内的第一部分31、第二部分32和第三部分33沿第二方向Y延伸，且任意相邻的两条第一数据线3对称分布于一个驱动晶体管沟道区41的相对两侧；在第二子区105内，任意一个像素驱动电路在第一柔性基底上的正投影区域内分布有两条第一数据线3。
在一些实施例中，像素驱动电路在第一柔性基底上的正投影区域包括由相邻的两条栅线和相邻的两条第二数据线5围成的区域，该相邻的两条第二数据线5在第一柔性基底上的正投影也可以落在像素驱动电路的正投影区域内。
在一些实施例中，对称分布指两条第一数据线3的设置位置相对称，由于制备工艺的限制，对称分布不仅包括两第一数据线3图形的物理对称设置，而且还包括两第一数据线3图形的不完全物理对称的情况。
在一些实施例中，参照图4和图5，第一子区104包括第一分区107和 第二分区108；第三子区106包括第一分区107和第二分区108；第一分区107和第二分区108沿第一方向X依次排布且相互连接；第二分区108位于第一分区107的远离第二子区105的一侧；第一部分31延伸分布至第一子区104的第一分区107；参照图10，为本公开实施例中第三部分延伸分布至第一分区的放大示意图；第三部分33延伸分布至第三子区106的第一分区107；第一部分31包括多条第一数据线3；第三部分33包括多条第一数据线3。
在一些实施例中，参照图10和图11，图11为本公开实施例中第一分区内第一数据线的分布俯视示意图；位于不同分区的第一数据线3延伸方向不同，例如：分布在第一分区107内的第一部分和第三部分沿第一方向X延伸，且第一数据线3位于相邻两行像素驱动电路4的之间；在第一分区107内，任意相邻两行像素驱动电路4之间分布有两条第一数据线3；且第一数据线3与像素驱动电路4中开关晶体管的沟道区42在第一柔性基底上的正投影不交叠。
在一些实施例中，如像素驱动电路为7T1C电路，参照图12，为一种示例性的像素驱动电路的电路图；像素驱动电路包括第一复位晶体管T1、阈值补偿晶体管T2、驱动晶体管T3、数据写入晶体管T4、第一发光控制晶体管T5、第二发光控制晶体管T6、第二复位晶体管T7和存储电容Cst。数据写入晶体管T4漏极的与驱动晶体管T3的源极电连接，数据写入晶体管T4的源极被配置为与数据线Data(即本公开实施例中的第二数据线)电连接以接收数据信号，数据写入晶体管T4的栅极被配置为与第一扫描信号线Ga1电连接以接收扫描信号；存储电容Cst的第二极板与第一电源电压线VDD电连接，存储电容Cst的第一极板与驱动晶体管T3的栅极电连接；阈值补偿晶体管T2的源极与驱动晶体管T3的栅极电连接，阈值补偿晶体管T2的漏极与驱动晶体管T3的漏极电连接，阈值补偿晶体管T2的栅极被配置为与第二扫描信号线Ga2电连接以接收补偿控制信号；第一复位晶体管T1的 源极被配置为与第一复位电源端Vinit1电连接以接收第一复位信号，第一复位晶体管T1的漏极与驱动晶体管T3的栅极电连接，第一复位晶体管T1的栅极被配置为与第一复位控制信号线Rst1电连接以接收第一复位控制信号；第二复位晶体管T7的漏极被配置为与第二复位电源端Vinit2电连接以接收第一复位信号，第二复位晶体管T7的源极与发光单元D的第一电极电连接，第二复位晶体管T7的栅极被配置为与第二复位控制信号线Rst2电连接以接收第二复位控制信号；第一发光控制晶体管T5的源极与第一电源电压线VDD电连接，第一发光控制晶体管T5的漏极与驱动晶体管T3的源极电连接，第一发光控制晶体管T5的栅极被配置为与第一发光控制信号线EM1电连接以接收第一发光控制信号；第二发光控制晶体管T6的源极与驱动晶体管T3的漏极电连接，第二发光控制晶体管T6的漏极与发光单元D的第一电极D1电连接，第二发光控制晶体管T6的栅极被配置为与第二发光控制信号线EM2电连接以接收第二发光控制信号；发光单元D的第二电极与第二电源端VSS(即本公开实施例中的参考电源走线)电连接。
其中，第一复位晶体管T1、阈值补偿晶体管T2、数据写入晶体管T4、第一发光控制晶体管T5、第二发光控制晶体管T6和第二复位晶体管T7均为开关晶体管。
在一些实施例中，如像素驱动电路4为7T1C电路时，像素驱动电路4中的开关晶体管可以指第一复位晶体管T1、阈值补偿晶体管T2、数据写入晶体管T4、第一发光控制晶体管T5、第二发光控制晶体管T6和第二复位晶体管T7。第一复位晶体管T1、阈值补偿晶体管T2、第一发光控制晶体管T5和第二发光控制晶体管T6的沟道区42位于靠近相邻两行像素驱动电路4的交界区的位置，所以尽量避免第一数据线3与像素驱动电路4中开关晶体管T5、T6、T1、T2的沟道区42在第一柔性基底上的正投影交叠。通过使第一数据线3与像素驱动电路4中开关晶体管的沟道区42在第一柔性基底上的正投影不交叠，能避免第一数据线3不规则地走线于开关晶体管的 沟道区42下面，从而避免开关晶体管的沟道区42出现不平整，继而避免开关晶体管的沟道区42的宽长比发生变化，以避免开关晶体管的开关性能发生变化，最终避免显示面板在驱动晶体管不进行阈值补偿时点灯和显示面板点灯测试时出现mura不良，确保了显示面板的品质。
在一些实施例中，参照图11，显示面板还包括多条冗余走线6，位于第一分区107内，且排布呈阵列；多条冗余走线6沿第二方向Y延伸，沿第一方向X任意相邻的两条冗余走线6对称分布于一个驱动晶体管沟道区41的相对两侧；在第一分区107内，任意一个像素驱动电路4在第一柔性基底上的正投影区域内分布有两条冗余走线6；每行冗余走线6连接一条沿第一方向X延伸的第一数据线3；每行冗余走线6与其他沿第一方向X延伸的第一数据线3在第一柔性基底上的正投影不交叠；每条冗余走线6的长度不超过像素驱动电路4在第一柔性基底上的正投影区域沿第二方向Y的长度。
在一些实施例中，第一分区107内的第一数据线3为沿第一方向X延伸的横向走线，且第一分区107内横向走线的第一数据线3与第二子区105内沿第二方向Y延伸的竖向走线第一数据线3垂直，这会导致第一区101整体感观上出现第一数据线3走线不均一现象；通过在第一分区107内设置冗余走线6，即在第一分区107内横向走线的基础上添加了竖向的冗余走线6，能够减弱第一区101整体感观上走线不均一的现象，冗余走线6与第二子区105走线相似，同样避开驱动晶体管的沟道区41，且对称分布在驱动晶体管沟道区41的相对两侧，从而能够避免出现点灯测试时的mura不良。每行冗余走线6连接一条沿第一方向X延伸的第一数据线3，防止冗余走线6悬空时对第一数据线3造成信号串扰。
在一些实施例中，参照图4，图5和图13，图13为本公开实施例中第二分区内第三部分第一数据线的分布俯视示意图；第一部分31还延伸分布至第一子区104的第二分区108；第三部分33还延伸分布至第三子区106 的第二分区108。
在一些实施例中，分布在第二分区108内的第一部分31和第三部分33沿第二方向Y延伸，且沿第一方向X任意相邻的两条第一数据线3对称分布于一个驱动晶体管沟道区41的相对两侧；在第二分区108内，任意一个像素驱动电路4在第一柔性基底上的正投影区域内分布有两条第一数据线3。
在一些实施例中，参照图4和图13，第一区101与第二区102的连接部分的宽度等于第二区102沿第一方向X的宽度；第一部分31还延伸分布至第二区102；第三部分33还延伸分布至第二区102。
在一些实施例中，分布在第二区102内的第一部分31、第二部分32和第三部分33沿第一方向X依次排布，且第一部分31、第二部分32和第三部分33分别沿第二方向Y延伸；多条第二数据线5沿第一方向X依次排布，且多条第二数据线5沿第二方向Y延伸；在第二区102内，任意一个像素驱动电路4在第一柔性基底上的正投影区域内分布有一条第一数据线3；且多条第一数据线3与多条第二数据线5在第一柔性基底上的正投影一一对应交叠。如此便于位于下层的第一数据线3与位于上层的第二数据线5进行连接。
在一些实施例中，由于第一区101内多条第一数据线3为扇形分布，所以第一区101内第一数据线3的分布密集度大于第二区102内第一数据线3的分布密集度。
在一些实施例中，参照图4和图14，图14为沿图4中DD＇剖切线的结构剖视图；非显示区还包括上边框区109，位于第二区102的远离第一区101的一侧，且上边框区109与第二区102连接；第一柔性基底1、多条第一数据线3和第二柔性基底2还由第二区102延伸至上边框区109；像素驱动电路4包括第一导电层和第二导电层，第一导电层和第二导电层依次远离第二柔性基底2设置；第一导电层和第二导电层之间设置有绝缘层7；第 一导电层包括多个第一图形8，多个第一图形8在第一柔性基底1上的正投影由上边框区109延伸至第二区102；位于上边框区109内的多条第一数据线3通过开设在第二柔性基底2中的第一过孔20分别一一对应地连接多个第一图形8；第二导电层包括多条第二数据线5；位于第二区102内的多个第一图形8通过开设在绝缘层7中的第二过孔70分别一一对应地连接多条第二数据线5。如此实现了多条第一数据线3在显示区100内的整面排布，从而提升了多条第一数据线3在显示区100内的分布均匀性，进而提升了显示面板的显示效果。
在一些实施例中，第一导电层还包括多个第二图形(图中未示出)，位于显示区，多个第二图形分别用作各像素驱动电路中存储电容的一个极板；第二图形与多条第一数据线在第一柔性基底上的正投影不交叠。
在一些实施例中，像素驱动电路包括有源层、第一栅极层、第一导电层和第二导电层，有源层、第一栅极层、第一导电层和第二导电层依次远离第二柔性基底设置，且任意相邻的两者之间通过无机绝缘层相互绝缘。有源层包括驱动晶体管的沟道区以及开关晶体管的沟道区的图形；第一栅极层包括栅线、驱动晶体管的栅极以及开关晶体管的栅极的图形；其中，驱动晶体管的栅极用作像素驱动电路中存储电容的一个极板；第一导电层包括第一图形8和第二图形，其中，第二图形用作像素驱动电路中存储电容的另一个极板，即第二图形与驱动晶体管的栅极在第一柔性基底上的正投影交叠，第二图形与驱动晶体管的栅极构成存储电容。第二导电层包括多条第二数据线5的图形以及像素驱动电路中驱动晶体管和开关晶体管的源极和漏极的图形。
在一些实施例中，参照图4和图14，显示面板还包括多个发光单元和封装层12，多个发光单元位于显示区100，且位于像素驱动电路背离第二柔性基底的一侧；多个发光单元排布呈阵列，多个发光单元与多个像素驱动电路一一对应连接；封装层12位于发光单元的背离像素驱动电路的一侧， 用于对发光单元进行封装；封装层12的上边界S位于上边框区109；第一过孔20与封装层在第一柔性基底上的正投影不交叠。即第一过孔20位于封装层的上边界S以外。
在一些实施例中，发光单元为有机电致发光单元，即OLED(Organic Light Emitting Diode)发光单元。
本公开实施例所提供的显示面板，通过使多条第一数据线的至少沿像素驱动电路阵列的列方向走线的部分在第一柔性基底上的正投影与驱动晶体管的沟道区在第一柔性基底上的正投影不交叠，能改善或避免第一数据线不规则地走线于驱动晶体管的沟道区下面，从而改善或避免驱动晶体管的沟道区出现不平整，继而改善或避免驱动晶体管的沟道区的宽长比发生变化，以改善或避免驱动晶体管的驱动电流发生变化，最终改善或避免显示面板在驱动晶体管不进行阈值补偿时点灯和显示面板点灯测试时出现mura不良，确保了显示面板的品质。
第二方面，本公开实施例还提供一种显示装置，包括上述实施例中的显示面板。
通过采用上述实施例中的显示面板，能够避免该显示装置在点灯测试时出现mura不良，确保了该显示装置的品质。
该显示装置可以为：OLED面板、OLED电视、手机、平板电脑、笔记本电脑、显示器、数码相框、导航仪等任何具有显示功能的产品或部件。
可以理解的是，以上实施方式仅仅是为了说明本公开的原理而采用的示例性实施方式，然而本公开并不局限于此。对于本领域内的普通技术人员而言，在不脱离本公开的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本公开的保护范围。

Claims (14)

  1. 一种显示面板，包括显示区；
    所述显示面板还包括第一柔性基底、第二柔性基底和多条第一数据线，
    所述多条第一数据线位于叠置的所述第一柔性基底和所述第二柔性基底之间；所述多条第一数据线分布于所述显示区；
    所述显示面板还包括多个像素驱动电路和多条第二数据线，位于所述显示区，且所述多个像素驱动电路和所述多条第二数据线位于所述第二柔性基底的背离所述第一数据线的一侧；
    所述多个像素驱动电路呈阵列排布；所述多条第一数据线与所述多条第二数据线一一对应连接；
    其中，所述多条第一数据线包括沿像素驱动电路阵列的列方向走线的部分，所述像素驱动电路包括驱动晶体管，所述多条第一数据线的至少沿像素驱动电路阵列的列方向走线的部分在所述第一柔性基底上的正投影与所述驱动晶体管的沟道区在所述第一柔性基底上的正投影不交叠。
  2. 根据权利要求1所述的显示面板，其中，所述显示区包括第一区和第二区，所述第一区和所述第二区连接；
    所述显示面板还包括非显示区，所述非显示区包括弯折区，所述弯折区位于所述第一区的远离所述第二区的一侧，所述弯折区、所述第一区和所述第二区沿第二方向依次排布；所述第二方向为像素驱动电路阵列的列方向；
    所述第一区包括第一子区、第二子区和第三子区，所述第一子区、所述第二子区和所述第三子区沿第一方向依次排布且彼此连接；所述第一方向为像素驱动电路阵列的行方向；
    所述弯折区与所述第二子区连接；
    所述第一柔性基底、所述多条第一数据线和所述第二柔性基底由所述第二子区延伸至所述弯折区；
    所述第二子区内所述多条第一数据线包括第一部分、第二部分和第三部分；所述第一部分、所述第二部分和所述第三部分沿所述第一方向依次排布；
    所述第一部分由所述第二子区向所述第一子区延伸分布，所述第三部分由所述第二子区向所述第三子区延伸分布，所述第二部分由所述第二子区向所述第二区延伸分布。
  3. 根据权利要求2所述的显示面板，其中，
    分布在所述第二子区内的所述第一部分、所述第二部分和所述第三部分沿所述第二方向延伸，且任意相邻的两条所述第一数据线对称分布于一个所述驱动晶体管沟道区的相对两侧；
    在所述第二子区内，任意一个所述像素驱动电路在所述第一柔性基底上的正投影区域内分布有两条所述第一数据线。
  4. 根据权利要求3所述的显示面板，其中，所述第一子区包括第一分区和第二分区；所述第三子区包括第一分区和第二分区；
    所述第一分区和所述第二分区沿所述第一方向依次排布且相互连接；所述第二分区位于所述第一分区的远离所述第二子区的一侧；
    所述第一部分延伸分布至所述第一子区的所述第一分区；
    所述第三部分延伸分布至所述第三子区的所述第一分区；
    所述第一部分包括多条所述第一数据线；
    所述第三部分包括多条所述第一数据线。
  5. 根据权利要求4所述的显示面板，其中，分布在所述第一分区内的 所述第一部分和所述第三部分沿所述第一方向延伸，且所述第一数据线位于相邻两行所述像素驱动电路之间；
    在所述第一分区内，任意相邻两行所述像素驱动电路之间分布有两条所述第一数据线；且所述第一数据线与所述像素驱动电路中开关晶体管的沟道区在所述第一柔性基底上的正投影不交叠。
  6. 根据权利要求5所述的显示面板，其中，还包括多条冗余走线，位于所述第一分区内，且排布呈阵列；
    所述多条冗余走线沿所述第二方向延伸，沿所述第一方向任意相邻的两条所述冗余走线对称分布于一个所述驱动晶体管沟道区的相对两侧；
    在所述第一分区内，任意一个所述像素驱动电路在所述第一柔性基底上的正投影区域内分布有两条所述冗余走线；
    每行所述冗余走线连接一条沿所述第一方向延伸的所述第一数据线；每行所述冗余走线与其他沿所述第一方向延伸的所述第一数据线在所述第一柔性基底上的正投影不交叠；
    每条所述冗余走线的长度不超过所述像素驱动电路在所述第一柔性基底上的正投影区域沿所述第二方向的长度。
  7. 根据权利要求4-6任意一项所述的显示面板，其中，所述第一部分还延伸分布至所述第一子区的所述第二分区；
    所述第三部分还延伸分布至所述第三子区的所述第二分区。
  8. 根据权利要求7所述的显示面板，其中，分布在所述第二分区内的所述第一部分和所述第三部分沿所述第二方向延伸，且沿所述第一方向任意相邻的两条所述第一数据线对称分布于一个所述驱动晶体管沟道区的相对两侧；
    在所述第二分区内，任意一个所述像素驱动电路在所述第一柔性基底上的正投影区域内分布有两条所述第一数据线。
  9. 根据权利要求7所述的显示面板，其中，所述第一区与所述第二区的连接部分的宽度等于所述第二区沿第一方向的宽度；
    所述第一部分还延伸分布至所述第二区；
    所述第三部分还延伸分布至所述第二区。
  10. 根据权利要求9所述的显示面板，其中，分布在所述第二区内的所述第一部分、所述第二部分和所述第三部分沿所述第一方向依次排布，且所述第一部分、所述第二部分和所述第三部分分别沿所述第二方向延伸；
    所述多条第二数据线沿所述第一方向依次排布，且所述多条第二数据线沿所述第二方向延伸；
    在所述第二区内，任意一个所述像素驱动电路在所述第一柔性基底上的正投影区域内分布有一条所述第一数据线；且所述多条第一数据线与所述多条第二数据线在所述第一柔性基底上的正投影一一对应交叠。
  11. 根据权利要求10所述的显示面板，其中，所述非显示区还包括上边框区，位于所述第二区的远离所述第一区的一侧，且所述上边框区与所述第二区连接；
    所述第一柔性基底、所述多条第一数据线和所述第二柔性基底还由所述第二区延伸至所述上边框区；
    所述像素驱动电路包括第一导电层和第二导电层，所述第一导电层和所述第二导电层依次远离所述第二柔性基底设置；所述第一导电层和所述第二导电层之间设置有绝缘层；
    所述第一导电层包括多个第一图形，所述多个第一图形在所述第一柔 性基底上的正投影由所述上边框区延伸至所述第二区；
    位于所述上边框区内的所述多条第一数据线通过开设在所述第二柔性基底中的第一过孔分别一一对应地连接所述多个第一图形；
    所述第二导电层包括所述多条第二数据线；
    位于所述第二区内的所述多个第一图形通过开设在所述绝缘层中的第二过孔分别一一对应地连接所述多条第二数据线。
  12. 根据权利要求11所述的显示面板，其中，还包括多个发光单元和封装层，
    所述多个发光单元位于所述显示区，且位于所述像素驱动电路背离所述第二柔性基底的一侧；
    所述多个发光单元排布呈阵列，所述多个发光单元与所述多个像素驱动电路一一对应连接；
    所述封装层位于所述发光单元的背离所述像素驱动电路的一侧，用于对所述发光单元进行封装；
    所述封装层的上边界位于所述上边框区；
    所述第一过孔与所述封装层在所述第一柔性基底上的正投影不交叠。
  13. 根据权利要求11所述的显示面板，其中，所述第一导电层还包括多个第二图形，位于所述显示区，所述多个第二图形分别用作各所述像素驱动电路中存储电容的一个极板；
    所述第二图形与所述多条第一数据线在所述第一柔性基底上的正投影不交叠。
  14. 一种显示装置，其中，包括权利要求1-13任意一项所述的显示面 板。
PCT/CN2023/110110 2022-08-09 2023-07-31 显示面板和显示装置 WO2024032403A1 (zh)

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