WO2024031544A1 - 显示装置、显示方法及终端 - Google Patents

显示装置、显示方法及终端 Download PDF

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Publication number
WO2024031544A1
WO2024031544A1 PCT/CN2022/111813 CN2022111813W WO2024031544A1 WO 2024031544 A1 WO2024031544 A1 WO 2024031544A1 CN 2022111813 W CN2022111813 W CN 2022111813W WO 2024031544 A1 WO2024031544 A1 WO 2024031544A1
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WIPO (PCT)
Prior art keywords
data
display panel
processing device
image
picture
Prior art date
Application number
PCT/CN2022/111813
Other languages
English (en)
French (fr)
Inventor
刘雨杰
龙凤
石萌
王光泉
陈秀云
赵晶
韩天洋
Original Assignee
京东方科技集团股份有限公司
北京京东方显示技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 京东方科技集团股份有限公司, 北京京东方显示技术有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2022/111813 priority Critical patent/WO2024031544A1/zh
Priority to CN202280002625.4A priority patent/CN118076994A/zh
Publication of WO2024031544A1 publication Critical patent/WO2024031544A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a display device, a display method and a terminal.
  • An e-book is an electronic tablet device.
  • the display of the e-book usually uses an electronic paper display (E-Paper Display, EPD).
  • E-paper displays have low power consumption, giving the e-book a strong battery life.
  • the driver motherboard in the e-book will provide a serial signal to the display integrated circuit according to the control instructions, and the display integrated circuit will convert the serial signal into a parallel output and provide it to the display panel.
  • e-books using e-paper displays have the following shortcomings: the time required from the touch operation to the final display screen refresh is about 28 ms, and the delay is high.
  • e-books also include a driver motherboard, a display integrated circuit and a display panel, which have many components and are larger in size.
  • Embodiments of the present disclosure provide a display device, a display method and a terminal to reduce the touch delay of the display device and reduce the number of components.
  • the technical solutions are as follows:
  • a display device in a first aspect, includes a display panel and a driving motherboard.
  • the driving motherboard includes a first processing device and a second processing device.
  • the second processing device is respectively connected to the first processing device.
  • the device is electrically connected to the display panel;
  • the first processing device is used to obtain the data of the picture change part according to the control instruction, and output the data of the picture change part to the second processing device.
  • the control instruction is used to control the display panel to display the data. Local changes in the picture;
  • the second processing device is configured to output N slave input signals to the display panel, the N slave input signals are used to carry data of the picture change part, and N is a positive integer greater than 1;
  • the display panel is used to perform partial screen refresh according to the data of the changed part of the screen.
  • the first processing device loads the image through the loading thread, and performs image processing on the image loaded by the loading thread through the algorithm thread to obtain the data of the changed part of the picture.
  • the first processing device is configured to convert the first grayscale image loaded according to the control instruction into a second grayscale image, where the number of grayscales of the first grayscale image is greater than that of the second grayscale image.
  • the gray scale number of the gray scale image, the gray scale number of the second gray scale image and the display panel compare the second gray scale image with the currently displayed image of the display panel to determine the picture of the display panel Whether it is a partial refresh, and when the picture of the display panel is partially refreshed, determine the data corresponding to the position where the display panel needs to be refreshed; add mode information and address information to the data corresponding to the position where the display panel needs to be refreshed, and obtain The data of the picture change part.
  • the first processing device is configured to call multiple transcoding threads through an algorithm thread to convert the first grayscale image in parallel, and each of the transcoding threads processes the first grayscale image. of multiple rows of data.
  • the first processing device is also used to divide each row of data in the data of the picture change part into N parts; combine the data of the same sequence in each row of data into one group to obtain N groups.
  • data, and the N sets of data respectively correspond to the N slave input signals.
  • the first processing device is also configured to combine the mode information and address information of each piece of data in each group of data and arrange them at the head of each group of data.
  • the first processing device is also configured to send the data amount of the data of the picture change part to the second processing device;
  • the second processing device is further configured to generate a clock signal according to the data amount, and the clock signal is used to control the timing of transmission of the N slave input signals.
  • the slave input signal includes image data, address information and mode information
  • the address information is the address of the display panel to which the image data is to be written
  • the mode information is used to indicate refresh of the display panel.
  • the mode is partial refresh.
  • the first processing device is a system-on-chip
  • the second processing device is a microcontrol unit.
  • the first processing device and the second processing device are electrically connected through a USB interface
  • One of the first processing device and the second processing device is integrated with a universal serial bus physical layer chip, or one of the first processing device and the second processing device is externally connected to a universal serial bus physical layer chip. chip.
  • the display panel is a display panel with a touch function
  • the control instruction is a touch instruction generated based on a touch operation of the display panel.
  • a second aspect provides a display method, which method is applied to the display device described in the first aspect, and the method includes:
  • control instructions being used to control local changes in the picture displayed by the display panel
  • N slave input signals to the display panel are used to carry data of the picture change part, and N is a positive integer greater than 1;
  • Partial picture refresh is performed according to the data of the picture change part.
  • the obtaining the data of the picture change part according to the control instruction includes:
  • the image is loaded through the loading thread, and the image loaded by the loading thread is image processed through the algorithm thread to obtain the data of the changed part of the picture.
  • the obtaining the data of the picture change part according to the control instruction includes:
  • the number of grayscales of the first grayscale image is greater than the number of grayscales of the second grayscale image.
  • the second grayscale image The grayscale number of the grayscale image is adapted to the display panel; compare the second grayscale image with the currently displayed image of the display panel, determine whether the picture of the display panel is partially refreshed, and perform a partial refresh on the display panel. When the picture is partially refreshed, the data corresponding to the position of the display panel that needs to be refreshed is determined; the mode information and the address information are added to the data corresponding to the position of the display panel that needs to be refreshed to obtain the data of the changed part of the picture.
  • converting the first grayscale image loaded according to the control instruction into a second grayscale image includes:
  • the algorithm thread calls multiple transcoding threads to convert the first grayscale image in parallel, and each transcoding thread processes multiple lines of data in the first grayscale image.
  • obtaining the data of the picture change part according to the control instruction also includes:
  • combining data in the same sequence in each row of data into a group includes:
  • the mode information and address information of each piece of data in each group of data are combined and arranged at the head of each group of data.
  • the method also includes:
  • the data amount of the data in the picture change part is converted into a clock signal, and the clock signal is used to control the timing of transmission of the N-channel slave input signals.
  • the slave input signal includes image data, address information and mode information
  • the address information is the address of the display panel to which the image data is to be written
  • the mode information is used to indicate refresh of the display panel.
  • the mode is partial refresh.
  • a terminal including a processor and a memory;
  • the memory is used to store computer programs
  • the processor is used to execute the computer program stored in the memory to implement the display method as described in the previous item.
  • a computer-readable storage medium is provided.
  • Computer instructions are stored in the computer-readable storage medium.
  • the display method as described in the previous item can be implemented.
  • a fifth aspect provides a computer program product containing instructions, which when the computer program product is run on a computer, causes the computer to perform the display method as described in the preceding item.
  • the driving motherboard can send the data of the changed part of the picture to the display panel when the control instruction is used to control the local change of the picture of the display panel, and the display panel can then send the data of the changed part of the picture to the display panel according to the data of the changed part of the picture.
  • Perform partial screen refresh since partial refresh of the display panel takes less time than refresh of the entire screen, response time and latency can be greatly reduced.
  • two processing units are used, one of which is responsible for image loading and image processing to ensure the processing speed; the other processing unit implements serial conversion and parallelization, and transmits the image output to the display panel through parallel N-channel SI signals to ensure the data transmission speed. , thereby ensuring a short response time.
  • N channels of parallel output can be realized by driving the main board, eliminating the need for a display IC arranged between the driving main board and the display panel in related technologies, saving components and reducing the size.
  • Figure 1 is a schematic structural diagram of a display device provided by at least one embodiment of the present disclosure
  • Figure 2 is a schematic structural diagram of a driving motherboard and a display panel provided by at least one embodiment of the present disclosure
  • Figure 3 is a schematic structural diagram of a display device provided by at least one embodiment of the present disclosure.
  • Figure 4 is a flow chart of image loading and processing provided by at least one embodiment of the present disclosure
  • Figure 5 is a flow chart of image conversion provided by at least one embodiment of the present disclosure.
  • Figure 6 is a schematic diagram of an SI signal provided by at least one embodiment of the present disclosure.
  • Figure 7 is an output signal waveform diagram of a second processing device provided by at least one embodiment of the present disclosure.
  • Figure 8 is a flow chart of transmission and processing provided by at least one embodiment of the present disclosure.
  • Figure 9 is a flow chart of sending data from a second processing device to a MIP display panel according to at least one embodiment of the present disclosure
  • Figure 10 is a flow chart of a display method provided by at least one embodiment of the present disclosure.
  • Figure 11 is a schematic structural diagram of a terminal provided by an embodiment of the present disclosure.
  • FIG. 1 is a schematic structural diagram of a display device provided by at least one embodiment of the present disclosure.
  • the display device includes a display panel 102 and a driving motherboard 103 .
  • the driving motherboard 103 is electrically connected to the display panel 102 .
  • the driving mainboard 103 is used to send the data of the changed part of the picture to the display panel according to the control instruction, and the control instruction is used to control the partial change of the picture displayed by the display panel;
  • the display panel 102 is used to perform partial screen refresh according to the data of the changed part of the screen.
  • the driving motherboard can send the data of the changed part of the picture to the display panel when the control instruction is used to control the local change of the picture of the display panel, and the display panel can then send the data of the changed part of the picture to the display panel according to the data of the changed part of the picture.
  • Perform partial screen refresh since partial refresh of the display panel takes less time than refresh of the entire screen, response time and latency can be greatly reduced.
  • the driving mainboard 103 includes: a first processing device 131 and a second processing device 132.
  • the second processing device 132 is electrically connected to the first processing device 131 and the display panel 102 respectively.
  • the first processing device 131 is configured to obtain the data of the picture change part according to the control instruction, and output the data of the picture change part to the second processing device;
  • the second processing device 132 is configured to output N channels of SI signals to the display panel 102 .
  • the N channels of SI signals are used to carry data of the changing part of the picture.
  • N is a positive integer greater than 1.
  • two processing units are used, one of which is responsible for image loading and image processing to ensure processing speed; the other processing unit implements serial-to-parallel conversion and transmits images to the display panel through parallel N-channel SI signals. Guaranteed data transfer speed.
  • N parallel outputs can be realized by driving the main board, eliminating the need for a display IC (Display IC) arranged between the driving main board and the display panel in related technologies, thus saving components.
  • Display IC Display IC
  • the driving motherboard outputs serial signals
  • the display IC converts the serial signals into parallel signals and outputs them to the display panel.
  • the present disclosure realizes the output of N parallel signals by driving the above structural design of the motherboard without the need for a display IC.
  • the first processing device 131 may be a system on chip (System on Chip, SOC), and the second processing device 132 may be a microcontroller unit (Mic-rocontroller Unit, MCU). ).
  • SOC System on Chip
  • MCU microcontroller Unit
  • the SOC is responsible for image loading and image processing to ensure the processing speed
  • the MCU is used to simulate N-channel SI signal transmission to ensure the data transmission speed.
  • the first processing device 131 may include a central processing unit (Central Processing Unit, CPU) and a graphics processor (Graphics Processing Unit, GPU), and the CPU and GPU are electrically connected.
  • CPU Central Processing Unit
  • GPU Graphics Processing Unit
  • the CPU After the CPU receives the signal from the driving integrated circuit, it sends the coordinate information to the GPU.
  • the GPU generates an image with the corresponding movement trajectory and stores the image in the display cache area.
  • the CPU may be a dual-core ARM Cortex-A7 or above processor with a main frequency of 1.1GHz or above, for example, a quad-core ARM Cortex-A7 CPU.
  • the GPU may be a GPU with a QDSP6v5 core.
  • the second processing device may be a programmable micro control unit with a programmable general-purpose input/output (GPIO) port of 21 pins or above, and simulates the output of N parallel SI signals through the GPIO port.
  • GPIO general-purpose input/output
  • N GPIO ports are used to simulate the output of N parallel SI signals.
  • the second processing device can be an STM32H750MCU, which includes a 21-pin or above programmable GPIO port, a Universal Serial Bus (USB) interface and a decoding module.
  • the main frequency is 480MHz to ensure that the GPIO can achieve regular flipping above 4.8Mhz.
  • the first processing device 131 and the second processing device 132 can also be implemented using other chips or processors, and the present disclosure does not limit this.
  • the display panel and the electronic paper display of the embodiments of the present disclosure are refreshed line by line. Therefore, the partial refresh method of the present disclosure takes less time than the entire picture refresh of the electronic paper display.
  • the display device may be an e-book.
  • the display device can also be other types of display devices, and there is no limitation on this.
  • the display panel 102 may be a Memory In Pixel (MIP) display panel.
  • the MIP display panel sets a Static Random Access Memory (SRAM) in each pixel of the Liquid Crystal Display (LCD) panel.
  • SRAM Static Random Access Memory
  • the SRAM is used to store the data voltage of the pixel.
  • the power consumption of the MIP display panel is similar to that of EDP, and the power consumption is lower; at the same time, it can achieve 8 to 64 color display and a full-screen refresh rate of up to 20Hz.
  • the MIP display panel adopts a glass-based decoding design, that is, the driver circuit is integrated on the screen of the MIP display panel, eliminating the need for a driver integrated circuit (IC).
  • FIG. 2 is a schematic structural diagram of a driving motherboard and a display panel provided by at least one embodiment of the present disclosure.
  • the MIP display panel has a display area (AA area) 121, and a plurality of sub-pixels 120 are provided in the display area 121.
  • a row driving circuit 122 and a column driving circuit 123 are provided in the peripheral area outside the display area 121.
  • the row driving circuit 122 is connected to the sub-pixel 120 through the gate line GATE, and the column driving circuit 123 is connected to the sub-pixel 120 through the data line DATA and the common line VCOM. .
  • the driving motherboard 103 sends the clock signal CLK and the slave input SI (Slave Input) signal to the column driving circuit 123 .
  • the slave input SI (Slave Input) here can be the slave input in the serial peripheral interface (Serial Peripheral In-terface, SPI).
  • a plurality of serial-to-parallel converters may also be provided in the peripheral area of the display panel to perform serial-to-parallel conversion of multiple SI signals.
  • the SI signal includes not only image data, but also address information and mode information
  • the address information is the address of the display panel to which the image data is to be written
  • the mode information is used to indicate that the refresh mode of the display panel is Partial refresh. Therefore, after the serial conversion is completed, the address and mode information can be decoded, so that the row driver circuit can control the level of the GATE of the corresponding row according to the address and mode information, thereby controlling whether the sub-pixels of the row refresh the data voltage in the memory. .
  • the row driver circuit only controls the GATE of row 1 and row 2 to be high level, so that the sub-pixels of this row can refresh the data in the memory. Voltage.
  • the display panel may be a display panel without a touch function.
  • the display panel can be a display panel with a touch function.
  • the control instructions can be generated by touch operations. Touch commands.
  • the following description takes a display panel with a touch function as an example.
  • the example below is also applicable to a display panel without a touch function.
  • the control instructions at this time are not generated by touch operations, but by other operations. , there is no restriction on this.
  • the touch function of the display panel can be implemented using a touch layer integrated in the display panel, that is, the display panel is an in-cell touch display panel.
  • the touch function of the display panel can also be implemented using a touch panel external to the display panel, that is, the display panel is an on-cell touch display panel.
  • the touch panel is attached to one side of the display panel.
  • the transparent touch panel is attached to the display area of the display panel, or the touch panel is arranged in the non-display area of the display panel.
  • the touch panel can be implemented using capacitive touch sensing technology, and the touch panel can be a touch pad, and the touch operation is performed through a stylus.
  • a touch event occurs when writing on the touch layer with a stylus.
  • the touch sensor in the touch layer senses a touch and processes it through the touch integrated circuit (Touch IC), and then transmits the touch information such as touch coordinates and pressure through the integrated circuit bus (Inter-Integrated Circuit, IIC)
  • the interface is passed to the driver motherboard.
  • the driver motherboard After receiving the touch information, the driver motherboard determines the subsequent operations that need to be performed, that is, determines what kind of screen to display, generates image data, and then passes the image output to the display panel.
  • the display panel After the display panel decodes the display data, it displays the picture and completes the work of the display part. Therefore, the display panel can achieve partial refresh, without the need to perform a full-screen scan of the display area and open it line by line like a traditional display panel, thus reducing the need for touch The time difference between response and display of response.
  • the touch delay time is the sum of T1, T2 and T3.
  • the picture time of one frame is (1/60)s, which is approximately equal to 16.7ms.
  • the non-scanning time (blanking) of each frame is about 1 ⁇ 2ms.
  • the touch delay time of T1+T2+T3 is about 28ms; while using MIP display panel, because it has the function of partial refresh, taking partial refresh of 100 lines as an example, the update time of 100 lines is about 3ms, that is, T3 ⁇ 3ms, the touch delay time obtained by T1+T2+T3 is about 16ms, which can greatly reduce the touch delay and improve the user experience.
  • the stylus mainly includes a pen tip, a pressure sensor, a control module, and a power module.
  • the pen tip outputs a signal, allowing the touch integrated circuit to detect the coordinate position of the pen tip; and the pen tip is in direct contact with the pressure sensor, transmitting the pressure sensed by the stylus during writing to the pressure sensor; the pressure sensor can sense the writing strength changes, so that the thickness of the handwriting can be changed according to changes in writing strength;
  • the control module performs logic editing and data processing on the signals collected by the pen tip;
  • the power module uses a DC converter boost circuit to power the stylus.
  • the pen tip emits a coding signal.
  • the pen tip signal can change the electric field at the touch point, thereby changing the electrode capacitance at the touch point.
  • the touch integrated circuit can determine the coordinates of the stylus pen by detecting changes in electrode capacitance.
  • the emitted signal of the pen tip can be a sine wave, a triangle wave, a square wave, etc., and the frequency used is tens of KHz to hundreds of KHz.
  • the stylus processes the pressure data to obtain the pressure level, and transmits the pressure information to the touch integrated circuit through the pen tip, and the touch integrated circuit then transmits it to the driving motherboard.
  • the processing and transmission of coordinates and pressure information are realized.
  • the touch integrated circuit scans the coordinates of the actual touch by charging and discharging the touch sensor, that is, sending a beacon signal (ie, coordinate signal).
  • a beacon signal ie, coordinate signal
  • the pen tip After the pen tip receives the Beacon signal, it sends the same Beacon signal to achieve synchronization.
  • the stylus After the synchronization is completed, the stylus sends information such as buttons, logos, power, and pressure to the touch integrated circuit through the pen tip. These different information are represented by electrical signals of different frequencies.
  • the touch integrated circuit detects these electrical signals and transmits them to the driving motherboard. .
  • the touch panel can also be implemented using other touch sensing technologies, such as electromagnetic touch sensing technology, which is not limited by the disclosure.
  • the driving mainboard 103 is configured to sequentially perform image loading and image processing according to the control instructions output by the touch panel, and output the data obtained by the image processing to the display panel 102 .
  • image loading may refer to generating multiple images based on the touch operation process based on the currently displayed screen according to the control instructions.
  • the images here may be higher grayscale images generated for conventional display panels, such as 256 grayscale images.
  • the driver motherboard 103 After the image is loaded, the driver motherboard 103 further processes the image so that the image can adapt to the display of the display panel, such as transcoding the image and reducing the gray scale of the image. In addition, you can also determine whether the refresh mode is static hold (no refresh), local refresh or global refresh by comparing the loaded image and the currently displayed picture, so that only the partial picture can be refreshed during local refresh. Reduce touch display delay.
  • FIG. 3 is a schematic structural diagram of a display device provided by at least one embodiment of the present disclosure.
  • the driver mainboard 103 is connected to the display panel 102 through a Flexible Printed Circuit (FPC) 104, and is connected to the touch panel 101 through a touch FPC 105.
  • the touch FPC 105 and the touch IC 106 are electrically connected.
  • the first processing device 131 and the second processing device 132 are electrically connected through a USB interface.
  • One of the first processing device and the second processing device integrates a USB physical layer (Physical Layer, PHY) chip, or one of the first processing device and the second processing device is externally connected to a USB PHY chip .
  • a USB physical layer Physical Layer, PHY
  • USB High Speed (HS) interface is implemented through a built-in or external USB PHY chip, and high-speed transmission is achieved through the USB HS interface, thereby reducing latency.
  • HS USB High Speed
  • the USB interface between the first processing device 131 and the second processing device 132 may be a USB interface that supports 85Mbp and above, such as a USB 2.0 port, which can support 12Mbp transmission in full-speed mode and 12Mbp in high-speed mode. Up to 480Mbp transmission.
  • first processing device 131 and the second processing device 132 may also be electrically connected using other interfaces, which the present disclosure does not limit.
  • the driver mainboard 103 also includes: a memory 133 , a battery management module 134 , and a communication module 135 .
  • the memory 133 is connected to the first processing device 131 and the battery management module 134 respectively, and the memory is used to store instructions and data generated by the driving motherboard.
  • the memory 133 may be 4GB and above Embedded Multi Media Card (EMMC) memory or 4GB and above Low Power Double Data Rate SDRAM (LPDDR), such as 8GB EMMC or 8GB LPDDR.
  • EMMC Embedded Multi Media Card
  • LPDDR Low Power Double Data Rate SDRAM
  • the power management module 134 is used to be electrically connected to the battery 107. At the same time, the power management module 134 is also electrically connected to the first processing device 131, the second processing device 132, and the communication module 135.
  • the power management module 134 includes a power management chip and its peripheral circuits.
  • the power management chip can be a chip that outputs a voltage of 1.8V/2.85V/2.95V/3.8V to provide the required power for driving various devices on the motherboard. Manage battery charge and discharge.
  • the power management module 134 can also be connected to a USB interface for input of external power and interaction with external signals.
  • the USB interface can be a USB interface that supports 12Mbp or more.
  • the communication module 135 can be electrically connected to the first processing device 131, and the communication module 135 is also used to communicate with the stylus 108.
  • the communication module 135 includes at least one of a Bluetooth module and a wireless fidelity (WIFI) module, communicates with the stylus 108 through Bluetooth or WIFI, and transmits the received signal to the first processing device 131 .
  • WIFI wireless fidelity
  • the first processing device 131 loads the image through a loading thread, and performs image processing on the image loaded by the loading thread through an algorithm thread to obtain the data of the changed part of the picture.
  • two threads are used to load and process images respectively, avoiding the lag that is likely to occur when using one thread for loading and processing, and further reducing latency.
  • Figure 4 is a flow chart of image loading and processing provided by at least one embodiment of the present disclosure.
  • the image loading and processing process includes: S11.
  • the algorithm thread selects the thumbnail of the first image from the cache, and then enters the waiting state; S12.
  • the loading thread loads N images from the storage and passes them to the algorithm thread. ; S13.
  • the algorithm thread processes the N images frame by frame, and after each image is processed, it determines whether to process the next image in a loop until the N images are processed and exits the process; at the same time, the loading thread executes repeatedly Step S12, exit the process until all images are loaded from the cache.
  • Using the above method can avoid lagging caused by too many images being loaded at one time and reduce latency.
  • step S12 the number of images loaded each time may be 15.
  • the first processing device 131 performs image loading and processing through a thread.
  • the first processing device 131 is used to convert the first grayscale image loaded according to the control instruction into a second grayscale image, where the number of grayscales of the first grayscale image is greater than the The gray scale number of the second gray scale image, the gray scale number of the second gray scale image and the display panel are adapted; compare the second gray scale image with the currently displayed image of the display panel, determine the Whether the picture of the display panel is partially refreshed, and when the picture of the display panel is partially refreshed, determine the data corresponding to the position of the display panel that needs to be refreshed; add mode information and data corresponding to the position of the display panel that needs to be refreshed. Address information is used to obtain the data of the changed part of the screen.
  • the first grayscale image is converted into a second grayscale image through transcoding, which is more suitable for display on the display panel; on the other hand, the data corresponding to the position that needs to be refreshed is determined through comparison, and a pattern is added
  • the information and address information enable the display panel to achieve partial refresh according to the data output by the first processing device, and the touch delay is small.
  • the number of grayscales of the first grayscale image is 256 (corresponding to the grayscale range 0-255), and the number of grayscales of the second grayscale image is 8 (corresponding to the grayscale range 0-7). Larger, the grayscale range is also larger.
  • the 256 gray-scale image is converted into an 8-gray-scale image suitable for the display panel. Compared with the 3-gray-scale image display of the electronic paper display panel, the gray scale is richer.
  • the first processing device 131 is configured to call multiple transcoding threads through an algorithm thread to convert the first grayscale image in parallel, and each of the transcoding threads processes Multiple lines of data in the first grayscale image.
  • multiple threads are used to process the first grayscale image in parallel, which can increase transcoding efficiency and reduce latency compared to using a single thread to process.
  • the first grayscale image has 1024 rows of pixels, that is, corresponding to 1024 rows of data.
  • the first processing device 131 transcodes the 1024 rows of data through 8 transcoding threads, and each transcoding thread processes 128 rows of data. .
  • the following describes the image conversion process by taking the color depth of the image generated by the first processing device 131 as 8 bits (ie, 256 gray levels) and the color depth usually supported by the MIP display panel as 1 bit (ie, 8 gray levels). It should be noted that the grayscale number of the above image is only an example and is not a limitation of the present disclosure.
  • the first processing device 131 converts the loaded image (R/G/B 8:8:8, gray scale number 0 to 255) into the image required by MIP (R/G/B 1:1:1, gray scale number for 0 and 1).
  • Figure 5 is a flow chart of image conversion provided by at least one embodiment of the present disclosure.
  • the image conversion process includes: S21, pre-processing.
  • the algorithm thread in the first processing device 131 obtains RGB888 image information; S22, RGB111 transcoding.
  • Post-processing Summarize and integrate the data output by 8 transcoding threads into one frame of RGB111 data.
  • the converted data changes from every 8 bits representing the gray level of a sub-pixel to 1 bit storing the gray level of a sub-pixel, and the number of colors also changes from 16.7M colors to 8 colors.
  • the data size before and after transcoding will be reduced from 2360KB to 295KB, as shown in Figure 9.
  • the 8 pixels before transcoding are: 0b111111110b000000000b000000000b11111110b000000000b000000000b111111110b000000000b000000000b111111110 b000000000b000000b111111110b000000000b000000b11111110b000000000b000000b111110b0000 00000b00000000.
  • the 8 pixels after transcoding are: 0b100100100b01001001001 0b00100100.
  • the first processing device 131 converts the first grayscale image through a thread.
  • the MIP display panel used in the embodiment of the present disclosure supports three working modes: global refresh, local refresh and static maintenance.
  • global refresh the MIP display panel receives the data of the entire screen and updates it; during partial refresh, the MIP display panel receives local data and updates the local screen.
  • local refresh it refreshes in row units, that is, each time a row is refreshed, a is a positive integer, and the minimum amount of data that can be refreshed alone is one row of data; when maintained statically, the screen does not need to be updated, and there is no need to transmit data.
  • the driver motherboard Before determining the working mode, the driver motherboard needs to compare the currently displayed image on the display panel with the image to be displayed in the next frame.
  • the working mode is determined based on how much the two frames of images change. For example, if the two frames of images are exactly the same, the working mode is static hold. If each line of the two frame images is different, the working mode is global refresh. If the two frames of images are only If some rows are different, the working mode is partial refresh.
  • Line address output If no row address is output, the working mode is static hold. If 1024 row addresses are output, the working mode is global refresh. If the number of output row addresses is less than 1024 and greater than 0, the working mode is partial refresh.
  • the first processing device packages the data corresponding to the output row address in the image to be displayed in the next frame and sends it to the second processing device, and the second processing device then passes the N-channel SI The signal drives the MIP display panel to realize the partial refresh function of specific rows.
  • the interface that the MIP display panel supports decoding is an N-channel SI interface, and the information of the SI is composed of mode bits + address bits + data.
  • N SIs together form one line of information, so it is necessary to add mode information and address information before the SI data, that is, add an information header.
  • FIG. 6 is a schematic diagram of an SI signal provided by at least one embodiment of the present disclosure.
  • each SI signal adds a total of 16 bits of mode information and address information, including 6 mode bits (M0 ⁇ M5) and 10 address bits (A0 ⁇ A9), followed by data bits (D0 ⁇ D7).
  • the data of the first 24 pixels in the first row is:
  • 0b means that the subsequent data is a binary number.
  • the data after adding the information header is:
  • the underlined part is the added information header
  • the first 6 bits of the information header are the mode bits, that is, 111111 (the specific mode can be set)
  • the last 10 bits of the information header are the address bits, that is, 0000000001, which can represent the first line .
  • N SI signals there are N channels of SI signals from SI0 to SI(n-1), and each SI signal adds mode information and address information.
  • N SI signals are transmitted to the MIP display panel under the control of the chip select signal CS and the clock signal CLK.
  • the first processing device 131 is also used to divide each row of data in the data of the picture change part into N parts; and combine the data of the same sequence in each row of data into a group. , N groups of data are obtained, and the N groups of data respectively correspond to the N channels of SI signals.
  • combining the data in the same sequence in each row of data into a group may mean splicing together the data in the same sequence in each row of data in ascending order of row numbers.
  • the first processing device reorders the data to generate N sets of data to prepare for the subsequent output of N SI signals by the second processing device.
  • the first processing device performs the reordering process
  • the second processing device only needs to send, thus avoiding the problem of low efficiency caused by MCU processing.
  • the first processing device groups and packages the data to facilitate the second processing device to extract the data.
  • the second processing device only needs to cyclically distribute the grouped data to the N channels of SI, that is, the N groups of packaged and grouped data are allocated to the N channels of SI in sequence.
  • each row of data is divided into 16 parts, and header information is added to each part.
  • the first data of row 1024 needs to be combined together, that is, the SI0 signal is the first data of row 1024, the SI1 signal is the second data of row 1024, and so on.
  • the first data in the first row is:
  • the first data in the second row is:
  • the first data on line 16 is:
  • the SI0 signal is:
  • the SI0 signal is:
  • the first processing device is also used to combine the mode information and address information of each piece of data in each group of data and arrange them at the head of each group of data.
  • the underlined part is the header.
  • the first processing device 131 is also configured to send the data amount of the data of the picture change part to the second processing device 132;
  • the second processing device 132 is also configured to generate a clock signal according to the data amount, and the clock signal is used to control the timing of the N-channel SI signal transmission.
  • the first processing device 131 may send pilot data to the second processing device 132, the aforementioned data amount being carried in the pilot data.
  • the pilot data may also include mode and status identification.
  • the data amount refers to the data amount of one frame of image sent by the first processing device 131 to the second processing device 132, that is, the number of rows of data to be refreshed; the mode refers to the refresh mode, including static hold (no refresh), Local refresh or global refresh; the status identifier is used to indicate the transmission status of data.
  • the status identifier changes with the data transmission situation between the first processing device 131 and the second processing device 132. When the first processing device 131 and the second processing device When the data transmission between 132 is completed, the status identifier sent by the first processing device 131 to the second processing device 132 is that the transmission is completed.
  • data transmission between the first processing device 131 and the second processing device 132 requires a higher rate.
  • the transmission rate is (768 ⁇ 3bit+( 16+16)) ⁇ 1024 ⁇ 25Hz ⁇ 59.8Mbps.
  • the first 16 indicates that the information header is 16 bits, and the second 16 is the vacant dummy bit to mark the end.
  • the rates of commonly used interfaces are as follows: IIC is 5Mbps, Serial Peripheral Interface (SPI) is 50Mbps, and USB FS (full speed) is 12Mbps, which cannot meet the requirements; Mobile Industry Processor Interface (Mobile Industry Processor Interface, Common display interface rates such as MIPI), High Definition Multimedia Interface (HDMI), Low-Voltage Differential Signaling (LVDS) interface are all above Gbps, and the rates can meet the requirements, but they all directly drive the display IC use, MCU, etc. generally do not support signal decoding of these interfaces. Therefore, as mentioned above, this disclosure uses the USB HS (High-Speed) interface with a transmission rate of 480Mbps, which can not only meet the rate requirements, but also realize the decoding of signals by the MCU.
  • USB HS High-Speed
  • the first processing device 131 transmits the image data to the second processing device 132 through the USB HS interface.
  • the second processing device 132 simulates the SI signal to carry the data through the GPIO interface, generates the corresponding CLK, and outputs it to the MIP display panel.
  • the decoding circuit of the MIP display panel is an N-channel SI decoding circuit.
  • the first processing device 131 Before sending image data, the first processing device 131 first sends pilot data to the second processing device.
  • the second processing device generates the corresponding CLK according to the data amount in the pilot data, and then transmits N sets of data to the MIP display panel through the N-channel interface with CLK.
  • the second processing device determines the length of CLK based on the amount of data in the pilot data. Each bit of data corresponds to a high level in CLK.
  • the second processing device determines the frequency of CLK based on the receiving and decoding capabilities of the display panel, for example, The CLK frequency is usually set to 4 ⁇ 6MHz based on the capabilities of the MIP display panel.
  • multiple SI signals can share one CLK, or each SI signal can have a separate CLK, but the waveforms of the multiple CLKs are the same.
  • FIG. 7 is an output signal waveform diagram of a second processing device provided by at least one embodiment of the present disclosure.
  • the output signal waveform of the second processing device includes DISP, CS, CLK and SI signals.
  • DISP Display
  • CS the control signal for communication. Only when the CS signal is at a high level, the MIP display panel will decode the SI signal.
  • CLK is the clock signal for communication, and the frequency changes according to the displayed data size.
  • SI is a data signal, including a total of 16 channels from SI_1 to SI_15.
  • the second processing device When one channel of CLK is shared, the second processing device finally outputs a total of 19 signals.
  • the second processing device When each channel of SI signal is set with a separate channel of CLK, the second processing device finally outputs a total of 34 signals.
  • the high level of each signal is 3 ⁇ 5.5V, and the low level is 0 ⁇ 1V.
  • the transmission between the first processing device and the second processing device is implemented in parallel with the processing of image data, which will be described below with reference to the accompanying drawings:
  • Figure 8 is a flow chart of transmission and processing provided by at least one embodiment of the present disclosure.
  • the first processing device jointly completes data transmission and processing through an algorithm thread, a transmission thread, and a synchronization thread.
  • the synchronization thread is triggered by a timer.
  • the transmission thread is notified that the transmission can be performed. .
  • the algorithm thread processes the A frame image data. After the processing is completed, the transmission thread is notified that the frame image can be transmitted; S32. After receiving the notification, the transmission thread transmits the A frame image data to the second processing device, and After the transmission is completed, the algorithm thread is informed through the unlock notification that the transmission thread is idle; S33. After the algorithm thread completes the processing of the A frame image data, it processes the B frame image data. After the processing is completed, the transmission thread is notified that the frame image can be transmitted. ; S34. After receiving the notification, the transmission thread transmits the B frame image data to the second processing device, and after the transmission is completed, informs the algorithm thread that the transmission thread is idle through the unlock notification. Until the synchronization thread timer ends, data processing and transmission are stopped.
  • double buffering and thread separation are used to optimize the transmission and processing process, thereby saving time and reducing latency.
  • FIG. 9 is a flow chart of sending data from a second processing device to a MIP display panel according to at least one embodiment of the present disclosure.
  • S41 when the second processing device receives the first-arrived data, it will first decode the USB data.
  • S42 Apply for the corresponding Flash cache space according to the amount of data in the pilot data, and then store all the pilot data and the reordered image data in the Flash cache.
  • S43 When the status flag is transmission completed, obtain the refresh mode in the pilot data, and read the data from the cache according to the refresh mode for transmission.
  • S44 reads N groups of data from the cache periodically. For example, each cycle reads 1 bit from the 0th to N-1 groups in sequence; S45. In each cycle, reads The data is sent to the GPIO interface registers corresponding to SI0 ⁇ SI15 on the MCU in turn. Loop steps S44 and S45, and execute step S46 after each loop to determine whether the N sets of data have been read. After reading, wait for the next transmission, otherwise continue the cycle.
  • S47 When partially refreshed, S47, read the amount of data; S48, periodically read N groups of data from the cache, for example, read 1 bit from the 0th to N-1th groups in each cycle; S49, in each cycle In each cycle, the read data is sent to the GPIO interface registers corresponding to SI0 ⁇ SI15 on the MCU in sequence. Loop steps S48 and S49, and execute step S410 after each loop to determine whether the N sets of data have been read based on the data amount. After reading, wait for the next transmission, otherwise continue the cycle.
  • the length of each group of data can be known, and then the position of the first bit of each group of data can be known, so that each group of data can be read periodically.
  • the reading is also based on the length of each group of data, and then based on the number of cycles of the current cycle. When the number of cycles reaches the length of each group of data plus 1, it is determined that the reading is complete.
  • each group of data When globally refreshed, the length of each group of data is 768*3*1024/16, and the length of each group of data is also the number of cycles to be cycled. When partially refreshed, the length of each group of data is 768*3*C/16, C is the number of rows corresponding to the data volume, and the length of each group of data is also the number of cycles to be cycled.
  • Figure 10 is a flowchart of a display method provided by at least one embodiment of the present disclosure. The method is applied to the display device shown in Figure 1, and the method includes:
  • Step S51 is executed by the first processing device driving the motherboard.
  • S52 Output N channels of slave input signals to the display panel.
  • the N channels of slave input signals are used to carry data of the changing part of the picture.
  • the N is a positive integer greater than 1.
  • Step S52 is executed by the second processing device driving the motherboard.
  • Step S53 is executed by the display panel.
  • the driving motherboard can send the data of the changed part of the picture to the display panel when the control instruction is used to control the local change of the picture of the display panel, and the display panel can then send the data of the changed part of the picture to the display panel according to the data of the changed part of the picture.
  • Perform partial screen refresh since partial refresh of the display panel takes less time than refresh of the entire screen, response time and latency can be greatly reduced.
  • two processing units are used, one of which is responsible for image loading and image processing to ensure the processing speed; the other processing unit implements serial conversion and parallelization, and transmits the image output to the display panel through parallel N-channel SI signals to ensure the data transmission speed. , thereby ensuring a short response time.
  • N channels of parallel output can be realized by driving the main board, eliminating the need for a display IC arranged between the driving main board and the display panel in related technologies, saving components and reducing the size.
  • obtaining the data of the picture changing part according to the control instruction includes:
  • the image is loaded through the loading thread, and the image loaded by the loading thread is image processed through the algorithm thread to obtain the data of the changed part of the picture.
  • two threads are used to load and process images respectively, avoiding the lag that is likely to occur when using one thread for loading and processing, and further reducing latency.
  • image loading and processing can be performed through one thread.
  • obtaining the data of the picture change part according to the control instruction includes:
  • the number of grayscales of the first grayscale image is greater than the number of grayscales of the second grayscale image.
  • the second grayscale image The grayscale number of the grayscale image is adapted to the display panel; compare the second grayscale image with the currently displayed image of the display panel, determine whether the picture of the display panel is partially refreshed, and perform a partial refresh on the display panel. When the picture is partially refreshed, the data corresponding to the position of the display panel that needs to be refreshed is determined; the mode information and the address information are added to the data corresponding to the position of the display panel that needs to be refreshed to obtain the data of the changed part of the picture.
  • the first grayscale image is converted into a second grayscale image through transcoding, which is more suitable for display on the display panel; on the other hand, the data corresponding to the position that needs to be refreshed is determined through comparison, and a pattern is added
  • the information and address information enable the display panel to achieve partial refresh according to the data output by the first processing device, and the touch delay is small.
  • the number of grayscales of the first grayscale image is 256
  • the number of grayscales of the second grayscale image is 8.
  • the 256 gray-scale image is converted into an 8-gray-scale image suitable for the display panel.
  • the gray scale is richer.
  • converting the first grayscale image loaded according to the control instruction into a second grayscale image includes:
  • the algorithm thread calls multiple transcoding threads to convert the first grayscale image in parallel, and each transcoding thread processes multiple lines of data in the first grayscale image.
  • multiple threads are used to process the first grayscale image in parallel, which can increase transcoding efficiency and reduce latency compared to using a single thread to process.
  • the first grayscale image can be converted through a thread.
  • obtaining the data of the picture change part according to the control instruction further includes:
  • N groups of data are generated by reordering the data to prepare for subsequent N-channel SI signal output.
  • the first processing device is also configured to combine the mode information and address information of each piece of data in each group of data and arrange them at the head of each group of data.
  • sending the data of the picture change part to the display panel according to the control instruction also includes:
  • a clock signal is generated according to the amount of data in the picture change part, and the clock signal is used to control the timing of transmission of the N-channel SI signals.
  • the slave input signal includes image data, address information and mode information
  • the address information is the address of the display panel to which the image data is to be written
  • the mode information is used to indicate refresh of the display panel.
  • the mode is partial refresh.
  • an embodiment of the present disclosure also provides a terminal 400, which may be a display device.
  • the terminal 400 can be used to perform the display methods provided in the above embodiments.
  • the terminal 400 includes: a memory 401, a processor 402 and a display component 403.
  • the structure of the terminal 400 shown in Figure 11 does not constitute a limitation on the terminal 400. In practical applications, More or fewer components than shown may be included, certain components may be combined, or components may be arranged differently. in:
  • the memory 401 can be used to store computer programs and modules.
  • the memory 401 can mainly include a program storage area and a data storage area, where the program storage area can store an operating system, at least one application program required for a function, etc.
  • Memory 401 may include high-speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other volatile solid-state storage device. Accordingly, the memory 401 may also include a memory controller to provide the processor 402 with access to the memory 401 .
  • the processor 402 executes various functional applications and data processing by running software programs and modules stored in the memory 401 .
  • the display component 403 is used to display images.
  • the display component 403 can include a display panel.
  • the display panel can be configured in the form of LCD (Liquid Crystal Display), OLED (Organic Light-Emitting Diode, organic light-emitting diode), etc. .
  • a computer-readable storage medium is also provided.
  • the computer-readable storage medium is a non-volatile storage medium.
  • a computer program is stored in the computer-readable storage medium. When the computer-readable storage medium When the computer-readable storage medium When the computer program in the medium is executed by the processor, it can execute the display method provided by the embodiment of the present disclosure.
  • a computer program product is also provided. Instructions are stored in the computer program product.
  • the computer program product When the computer program product is run on a computer, it enables the computer to execute the display method provided by the embodiment of the present disclosure.
  • a chip is also provided.
  • the chip includes programmable logic circuits and/or program instructions. When the chip is run, it can execute the display method provided by the embodiment of the present disclosure.

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Abstract

一种显示装置、显示方法及终端。显示装置包括显示面板（102）和驱动主板（103），驱动主板（103）包括第一处理器件（131）和第二处理器件（132），第二处理器件（132）分别与第一处理器件（131）和显示面板（102）电连接；第一处理器件（131）用于根据控制指令获取画面变化部分的数据，将画面变化部分的数据输出给第二处理器件（132），控制指令用于控制显示面板（102）显示的画面局部变化；第二处理器件（132）用于向显示面板（102）输出N路从输入信号，N路从输入信号用于携带画面变化部分的数据，N为大于1的正整数；显示面板（102），用于根据画面变化部分的数据进行局部画面刷新。

Description

显示装置、显示方法及终端 技术领域
本公开涉及显示技术领域，特别涉及一种显示装置、显示方法及终端。
背景技术
电子书是一种电子平板设备，电子书的显示器通常使用电子纸显示器(E-Paper Display，EPD)，电子纸显示器功耗低，使得电子书具有较强的续航能力。
在采用触控笔对电子书进行触控操作时，电子书中的驱动主板会根据控制指令提供串行信号给显示器集成电路，显示器集成电路将串行信号转换成并行输出提供给显示面板。
相关技术中，使用电子纸显示器的电子书存在以下缺点：从触控操作发生到最终显示画面刷新，所需的时间为28ms左右，延迟较高。另外，电子书同时包括驱动主板、显示器集成电路和显示面板，器件较多，体积较大。
发明内容
本公开实施例提供了一种显示装置、显示方法及终端，以降低显示装置的触控延迟，减少器件。所述技术方案如下：
第一方面，提供了一种显示装置，所述显示装置包括显示面板和驱动主板，所述驱动主板包括第一处理器件和第二处理器件，所述第二处理器件分别与所述第一处理器件和所述显示面板电连接；
所述第一处理器件用于根据控制指令获取所述画面变化部分的数据，将所述画面变化部分的数据输出给所述第二处理器件，所述控制指令用于控制所述显示面板显示的画面局部变化；
所述第二处理器件用于向所述显示面板输出N路从输入信号，所述N路从输入信号用于携带所述画面变化部分的数据，所述N为大于1的正整数；
所述显示面板，用于根据所述画面变化部分的数据进行局部画面刷新。
可选地，所述第一处理器件通过加载线程进行图像加载，通过算法线程对 所述加载线程加载的图像进行图像处理，得到所述画面变化部分的数据。
可选地，所述第一处理器件用于将根据所述控制指令加载的第一灰阶图像转换成第二灰阶图像，所述第一灰阶图像的灰阶数大于所述第二灰阶图像的灰阶数，所述第二灰阶图像的灰阶数和所述显示面板适配；对比所述第二灰阶图像和所述显示面板当前显示图像，确定所述显示面板的画面是否为局部刷新，并在所述显示面板的画面局部刷新时，确定所述显示面板需要刷新的位置对应的数据；给所述显示面板需要刷新的位置对应的数据添加模式信息和地址信息，得到所述画面变化部分的数据。
可选地，所述第一处理器件用于通过算法线程调用多个转码线程并行地对所述第一灰阶图像进行转换，每个所述转码线程处理所述第一灰阶图像中的多行数据。
可选地，所述第一处理器件还用于将所述画面变化部分的数据中的每行数据分为N份；将所述每行数据中相同顺序份的数据组合成一组，得到N组数据，所述N组数据分别对应所述N路从输入信号。
可选地，所述第一处理器件还用于将每组数据中的各份数据的模式信息和地址信息组合并排在每组数据的头部。
可选地，所述第一处理器件还用于向所述第二处理器件发送所述画面变化部分的数据的数据量；
所述第二处理器件还用于根据所述数据量生成时钟信号，所述时钟信号用于控制所述N路从输入信号传输的时序。
可选地，所述从输入信号包括图像数据、地址信息及模式信息，所述地址信息为所述图像数据所要写入的显示面板的地址，所述模式信息用于指示所述显示面板的刷新模式为局部刷新。
可选地，所述第一处理器件为***级芯片，所述第二处理器件为微控制单元。
可选地，所述第一处理器件和所述第二处理器件通过USB接口电连接；
所述第一处理器件和所述第二处理器件中的一个集成通用串行总线物理层芯片，或者，所述第一处理器件和所述第二处理器件中的一个外接通用串行总线物理层芯片。
可选地，所述显示面板为具有触控功能的显示面板，所述控制指令是基于 所述显示面板的触控操作生成的触控指令。
第二方面，提供了一种显示方法，所述方法应用于第一方面所述的显示装置，所述方法包括：
根据控制指令获取所述画面变化部分的数据，所述控制指令用于控制所述显示面板显示的画面局部变化；
向所述显示面板输出N路从输入信号，所述N路从输入信号用于携带所述画面变化部分的数据，所述N为大于1的正整数；
根据所述画面变化部分的数据进行局部画面刷新。
可选地，所述根据控制指令获取所述画面变化部分的数据，包括：
通过加载线程进行图像加载，通过算法线程对所述加载线程加载的图像进行图像处理，得到所述画面变化部分的数据。
可选地，所述根据控制指令获取所述画面变化部分的数据，包括：
将根据所述控制指令加载的第一灰阶图像转换成第二灰阶图像，所述第一灰阶图像的灰阶数大于所述第二灰阶图像的灰阶数，所述第二灰阶图像的灰阶数和所述显示面板适配；对比所述第二灰阶图像和所述显示面板当前显示图像，确定所述显示面板的画面是否为局部刷新，并在所述显示面板的画面局部刷新时，确定所述显示面板需要刷新的位置对应的数据；给所述显示面板需要刷新的位置对应的数据添加模式信息和地址信息，得到所述画面变化部分的数据。
可选地，所述将根据所述控制指令加载的第一灰阶图像转换成第二灰阶图像，包括：
通过算法线程调用多个转码线程并行地对所述第一灰阶图像进行转换，每个所述转码线程处理所述第一灰阶图像中的多行数据。
可选地，所述根据控制指令获取所述画面变化部分的数据，还包括：
将所述画面变化部分的数据中的每行数据分为N份；将所述每行数据中相同顺序份的数据组合成一组，得到N组数据，所述N组数据分别对应所述N路从输入信号。
可选地，所述将所述每行数据中相同顺序份的数据组合成一组，包括：
将每组数据中的各份数据的模式信息和地址信息组合并排在每组数据的头部。
可选地，所述方法还包括：
根据所述画面变化部分的数据的数据量成时钟信号，所述时钟信号用于控制所述N路从输入信号传输的时序。
可选地，所述从输入信号包括图像数据、地址信息及模式信息，所述地址信息为所述图像数据所要写入的显示面板的地址，所述模式信息用于指示所述显示面板的刷新模式为局部刷新。
第三方面，提供了一种终端，所述终端包括处理器和存储器；
其中，所述存储器，用于存储计算机程序；
所述处理器，用于执行所述存储器中存放的计算机程序，以实现如前任一项所述的显示方法。
第四方面，提供了一种计算机可读存储介质，所述计算机可读存储介质中存储有计算机指令，存储的所述计算机指令被处理器执行时能够实现如前任一项所述的显示方法。
第五方面，提供了一种包含指令的计算机程序产品，当所述计算机程序产品在计算机上运行时，使得计算机执行如前任一项所述的显示方法。
本公开实施例提供的技术方案带来的有益效果是：
在本公开实施例中，驱动主板可以在控制指令用于控制所述显示面板画面局部变化时，将画面变化部分的数据发送给所述显示面板，显示面板则可以根据所述画面变化部分的数据进行局部画面刷新；由于显示面板局部刷新相比于整幅画面刷新所需的时间更短，因此可以大大减少响应时间，降低了延迟。另外，采用两个处理单元，其中一个处理单元负责图像加载和图像处理，保证处理速度；另一个处理单元实现串转并，通过并行的N路SI信号传输图像输出给显示面板，保证数据传输速度，从而保证响应时间短。通过驱动主板即可实现N路并行输出，省去了相关技术中布置在驱动主板和显示面板之间的显示器IC，节省了器件，减小了体积。
附图说明
为了更清楚地说明本公开实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下， 还可以根据这些附图获得其他的附图。
图1是本公开至少一实施例提供的一种显示装置的结构示意图；
图2是本公开至少一实施例提供的一种驱动主板和显示面板的结构示意图；
图3是本公开至少一实施例提供的一种显示装置的结构示意图；
图4是本公开至少一实施例提供的一种图像加载和处理的流程图；
图5是本公开至少一实施例提供的一种图像转换的流程图；
图6是本公开至少一实施例提供的SI信号示意图；
图7是本公开至少一实施例提供的一种第二处理器件的输出信号波形图；
图8是本公开至少一实施例提供的一种传输和处理的流程图；
图9是本公开至少一实施例提供的一种数据从第二处理器件发送到MIP显示面板的流程图；
图10是本公开至少一实施例提供的一种显示方法的流程图；
图11是本公开实施例提供的一种终端的结构示意图。
具体实施方式
为使本公开的目的、技术方案和优点更加清楚，下面将结合附图对本公开实施方式作进一步地详细描述。
图1是本公开至少一实施例提供的一种显示装置的结构示意图。参见图1，该显示装置包括显示面板102和驱动主板103，所述驱动主板103与所述显示面板102电连接。
所述驱动主板103，用于根据控制指令，将画面变化部分的数据发送给所述显示面板，所述控制指令用于控制所述显示面板显示的画面局部变化；
所述显示面板102，用于根据所述画面变化部分的数据进行局部画面刷新。
在本公开实施例中，驱动主板可以在控制指令用于控制所述显示面板画面局部变化时，将画面变化部分的数据发送给所述显示面板，显示面板则可以根据所述画面变化部分的数据进行局部画面刷新；由于显示面板局部刷新相比于整幅画面刷新所需的时间更短，因此可以大大减少响应时间，降低了延迟。
参见图1，所述驱动主板103包括：第一处理器件131和第二处理器件132，所述第二处理器件132分别与所述第一处理器件131和所述显示面板102电连 接。
所述第一处理器件131用于根据所述控制指令获取所述画面变化部分的数据，将所述画面变化部分的数据输出给所述第二处理器件；
所述第二处理器件132用于向所述显示面板102输出N路SI信号，所述N路SI信号用于携带所述画面变化部分的数据，所述N为大于1的正整数。
在该实现方式中，采用两个处理单元，其中一个处理单元负责图像加载和图像处理，保证处理速度；另一个处理单元实现串转并，通过并行的N路SI信号传输图像输出给显示面板，保证数据传输速度。
另外，通过驱动主板即可实现N路并行输出，省去了相关技术中布置在驱动主板和显示面板之间的显示器IC(Display IC)，节省了器件。
相关技术中，驱动主板输出的是串行信号，显示器IC将串行信号转成并行信号输出给显示面板。而本公开通过驱动主板的上述结构设计，实现N路并行信号的输出，无需显示器IC。
在本公开一种可能的实现方式中，所述第一处理器件131可以为***级芯片(System on Chip，SOC)，所述第二处理器件132可以为微控制单元(Mic-rocontroller Unit，MCU)。
在该实现方式中，通过SOC负责图像加载和图像处理，保证处理速度；利用MCU模拟N路SI信号传输，保证数据传输速度。
示例性地，第一处理器件131可以包括中央处理器(Central Processing Unit，CPU)和图形处理器(Graphics Processing Unit，GPU)，CPU和GPU电连接。
CPU接收到驱动集成电路的信号后，将坐标信息发给GPU，GPU生成有相应移动轨迹的图像，并将图像存储至显示缓存区域。
示例性地，CPU可以是主频1.1GHz及以上、双核ARM Cortex-A7及以上的处理器，例如，四核ARM Cortex-A7CPU。
示例性地，GPU可以是具有QDSP6v5内核的GPU。
示例性地，第二处理器件可以是具备21pin及以上的可编程通用输入输出(General-purpose input/output，GPIO)口的可编程微控制单元，通过GPIO口模拟N路并行SI信号的输出，如通过N个GPIO口模拟N路并行SI信号的输出。例如，第二处理器件可以是STM32H750MCU，包含21pin及以上可编程GPIO口和通用串行总线(Universal Serial Bus，USB)接口及解码模块，主频 480MHz用于确保GPIO可实现4.8Mhz以上规律翻转。
在本公开其他可能的实现方式中，第一处理器件131和第二处理器件132也可以采用其他芯片或处理器实现，本公开对此不做限制。
值得说明的是，本公开实施例的显示面板和电子纸显示器在刷新时都是逐行刷新的，因而，本公开通过局部刷新的方式相比于电子纸显示器的整幅画面刷新用时更短。
示例性地，该显示装置可以为电子书。当然，该显示装置也可以为其他类型的显示装置，对此不做限制。
示例性地，该显示面板102可以为像素存储器(Memory In Pixel，MIP)显示面板。MIP显示面板是在液晶显示器(Liquid Crystal Display，LCD)面板的每个像素内设置静态随机存取存储器(Static Random Access Memory，SRAM)，SRAM用于存储像素的数据电压。对于单个像素而言，画面更新时若该像素的显示不需要变化，则该像素内的SRAM维持原状。仅有需要变化的像素内的SRAM存储的数据电压需要刷新，因而局部刷新时的画面更新延迟更小。MIP显示面板的功耗与EDP相近，功耗较低；同时，可以实现8～64色显示，以及全屏最高20Hz的刷新率。另外，MIP显示面板采用玻璃基解码设计，也即在MIP显示面板的屏上集成驱动电路，省去驱动集成电路(Integrated Circuit，IC)。
图2是本公开至少一实施例提供的一种驱动主板和显示面板的结构示意图。参见图2，MIP显示面板具有显示区(AA区)121，显示区121内设置有多个子像素120。在显示区121之外的***区域设置有行驱动电路122和列驱动电路123，行驱动电路122通过栅线GATE和子像素120连接，列驱动电路123通过数据线DATA和公共线VCOM和子像素120连接。
如图2所示，驱动主板103向列驱动电路123发送时钟信号CLK和从输入SI(Slave Input)信号。
这里的从输入SI(Slave Input)可以是串行外设接口(Serial Peripheral In-terface，SPI)中的从输入。
该显示面板的***区域还可以设置多个串转并转换器(图中未示出)，用来对多路SI信号进行串转并转换。
由于SI信号中既包括图像数据，又包括地址信息及模式信息，所述地址信息为所述图像数据所要写入的显示面板的地址，所述模式信息用于指示所述显 示面板的刷新模式为局部刷新。因此，串转并完成后可以解码出地址及模式信息，从而使得行驱动电路可以根据地址及模式信息控制对应行的GATE的电平高低，从而控制该行的子像素是否刷新存储器中的数据电压。
例如，当模式为局部刷新，地址为第1行和第2行时，行驱动电路仅控制第1行和第2行的GATE为高电平，使得该行的子像素可以刷新存储器中的数据电压。
在本公开一种可能的实现方式中，显示面板可以为不具有触控功能的显示面板。
在本公开另一种可能的实现方式中，显示面板可以为具有触控功能的显示面板，例如显示装置为电子书时，显示面板即需要显示功能，此时控制指令可以是触控操作产生的触控指令。后文以具有触控功能的显示面板为例进行说明，当然后文的示例也同样适用于不具有触控功能的显示面板，只是此时的控制指令并非触控操作产生，而是其他操作产生，对此不做限制。
示例性地，显示面板的触控功能可以采用集成在显示面板内的触控层实现，也即显示面板为内嵌式(In-Cell)触摸显示面板。
示例性地，显示面板的触控功能也可以采用外挂在显示面板外的触控面板实现，也即显示面板为外挂式(On-Cell)触摸显示面板。
这种方式下，触控面板贴合在显示面板的一侧面上。例如，透明触控面板贴合在显示面板的显示区，或者触控面板设置在显示面板的非显示区。
在本公开的一种可能的实现方式，触控面板可以采用电容式触控感应技术实现，触控面板可以为触控板，通过手写笔进行触控操作。
使用手写笔在触控层上书写时，发生触控事件。触控层中的触控传感器感应有触控发生，并通过触控集成电路(Touch IC)处理后再将触控坐标、压力等触控信息，通过集成电路总线(Inter-Integrated Circuit，IIC)接口传递给驱动主板。
驱动主板收到触控信息后，判断后续需要执行的操作，即判断显示怎样的画面，并生成图像数据，然后将图像输出传递至显示面板。
显示面板将显示数据解码后，进行画面显示，完成显示部分的工作，因此处显示面板可以实现局部刷新，无需像传统显示面板对显示区域做全屏扫描逐行开启的动作，从而减小了触控响应到显示响应的时间差。
示例性地，假设从触控动作发生到Touch IC接收到信号的时间为T1，Touch IC与驱动主板交互的时间为T2，驱动主板处理到显示面板完成画面刷新的时间为T3，触控延迟时间(move latency)即为T1、T2和T3之和。在常规方案中，以刷新率60Hz为例，一帧画面时间为(1/60)s，约等于16.7ms，每帧的非扫描时间(blanking)约为1～2ms，两者相减得到T3≈15ms，T1+T2+T3得到触控延迟时间在28ms左右；而采用MIP显示面板，因具有局部刷新的功能，以局部刷新100行为例，100行更新的时间为3ms左右，也即T3≈3ms，T1+T2+T3得到触控延迟时间在16ms左右，能够大幅提高降低触控延迟，提升用户体验。
下面结合手写笔的结构对触控感应的过程进行说明：手写笔主要包括笔尖、压力传感器、控制模块、电源模块。笔尖通过输出信号，使触控集成电路检测到笔尖坐标位置；并且，笔尖是直接和压力传感器接触的，将手写笔书写过程中感应到的压力传导给压力传感器；压力传感器能够感测到书写力度的变化，从而可以根据书写力度变化来改变笔迹的粗细；控制模块对笔尖采集到的信号进行逻辑编辑和数据处理；电源模块采用直流变换器升压电路给手写笔供电。
其中，笔尖发射打码信号，笔尖信号可以改变触控点处的电场，从而改变触控点处的电极电容，触控集成电路通过检测电极电容的变化可以确定出手写笔坐标。笔尖的发射信号可以为正弦波、三角波、方波等，使用频率为数十KHz～数百KHz。另外，手写笔对压力数据进行处理得到压力等级，通过笔尖将压力信息传给触控集成电路，触控集成电路再传给驱动主板。从而实现了坐标和压力信息的处理、传递。
其中，触控集成电路通过给触控传感器充放电，扫描实际触控的坐标，即发送信标(Beacon)信号(也即坐标信号)，笔尖接收到Beacon信号后，发送相同的Beacon信号实现同步，同步完成后，手写笔通过笔尖发送按键、标识、电量、压力等信息给触控集成电路，这些不同的信息用不同频率的电信号表示，触控集成电路检测到这些电信号传递给驱动主板。
在本公开的其他可能的实现方式，触控面板也可以采用其他触控感应技术实现，例如电磁式触控感应技术，本公开对此不做限制。
在本公开实施例中，所述驱动主板103用于根据所述触控面板输出的控制指令依次进行图像加载和图像处理，并将所述图像处理得到的数据输出给所述显示面板102。
这里，图像加载可以是指在当前显示的画面的基础上，根据控制指令生成多幅基于触控操作过程产生的图像，这里的图像可以是针对常规显示面板生成的灰阶较高的图像，例如256灰阶图像。
在图像加载完成后，驱动主板103进一步对图像进行处理，使得图像能够适配显示面板的显示，例如对图像进行转码，降低图像的灰阶。除此之外，还可以通过比对加载的图像和当前显示的画面，确定刷新模式是静态保持(不刷新)、局部刷新或全局刷新，从而能够在局部刷新时，仅对局部画面进行刷新，减小触控显示延迟。
图3是本公开至少一实施例提供的一种显示装置的结构示意图。参见图3，驱动主板103通过柔性电路板(Flexible Printed Circuit，FPC)104和显示面板102连接，通过触控FPC 105和触控面板101连接，触控FPC 105和触控IC 106电连接。
在本公开一种可能的实现方式中，所述第一处理器件131和所述第二处理器件132通过USB接口电连接。
所述第一处理器件和所述第二处理器件中的一个集成USB物理层(Physical Layer，PHY)芯片，或者，所述第一处理器件和所述第二处理器件中的一个外接USB PHY芯片。
在该实现方式中，通过内置或外接USB PHY芯片实现USB高速(High Speed，HS)接口，通过USB HS接口实现高速传输，进而降低延迟。
示例性地，所述第一处理器件131和所述第二处理器件132之间的USB接口可以是支持85Mbp及以上的USB接口，例如USB 2.0端口，可支持全速模式下12Mbp传输，高速模式下最高到480Mbp传输。
在本公开其他可能的实现方式中，第一处理器件131和第二处理器件132也可以采用其他接口电连接，本公开对此不做限制。
再次参见图3，该驱动主板103还包括：存储器133、电池管理模块134、通信模块135。
其中，存储器133分别与第一处理器件131和电池管理模块134连接，存储器用于储存驱动主板产生的指令和数据。
示例性地，存储器133可以是4GB及以上嵌入式多媒体卡(Embedded Multi Media Card，EMMC)存储器或4GB及以上低功耗双倍速率内存(Low Power  Double Data Rate SDRAM，LPDDR)，例如8GB EMMC或8GB LPDDR。
其中，电源管理模块134用于和电池107电连接，同时，电源管理模块134还与第一处理器件131、第二处理器件132、通信模块135电连接。
示例性地，电源管理模块134包含电源管理芯片及其***电路，电源管理芯片可以是输出1.8V/2.85V/2.95V/3.8V电压的芯片，为驱动主板的各器件提供所需电源，同时对电池充放电进行管理。
可选地，电源管理模块134还可以连接一USB接口，用于外部电源的输入及与外部信号的交互使，该USB接口可以是支持12Mbp以上的USB接口。
其中，通信模块135可以与第一处理器件131电连接，通信模块135还用于与手写笔108通信连接。
示例性地，通信模块135包括蓝牙模块和无线高保真(WIFI)模块中的至少一个，通过蓝牙或WIFI和手写笔108通信，并将收到的信号传输给第一处理器件131。
在本公开一种可能的实现方式中，所述第一处理器件131通过加载线程进行图像加载，通过算法线程对所述加载线程加载的图像进行图像处理，得到所述画面变化部分的数据。
该实现方式中，通过2个线程分别进行图像加载和处理，避免采用一个线程进行加载和处理时，容易出现的卡顿情况，进一步降低延迟。
图4是本公开至少一实施例提供的一种图像加载和处理的流程图。参见图4，该图像加载和处理的过程包括：S11、算法线程从缓存中选取首幅图像的缩略图，然后进入等待状态；S12、加载线程从存储中加载N幅图像，并传递给算法线程；S13、算法线程逐帧处理这N幅图像，并且在每处理完一幅图像后，判断是否循环处理下一张，直到N幅图像处理完后退出该流程；与此同时，加载线程重复执行步骤S12，直到从缓存中加载完所有图像后退出该流程。
采用上述方式，能够避免一次加载的图片数量过多造成卡顿，降低时延。
示例性地，步骤S12中，每次加载的图像数量可以为15幅。
在本公开其他可能的实现方式中，所述第一处理器件131通过一个线程进行图像加载和处理。
在本公开实施例中，所述第一处理器件131用于将根据所述控制指令加载的第一灰阶图像转换成第二灰阶图像，所述第一灰阶图像的灰阶数大于所述第 二灰阶图像的灰阶数，所述第二灰阶图像的灰阶数和所述显示面板适配；对比所述第二灰阶图像和所述显示面板当前显示图像，确定所述显示面板的画面是否为局部刷新，并在所述显示面板的画面局部刷新时，确定所述显示面板需要刷新的位置对应的数据；给所述显示面板需要刷新的位置对应的数据添加模式信息和地址信息，得到所述画面变化部分的数据。
在该实现方式中，一方面通过转码将第一灰阶图像转换成第二灰阶图像，更适合显示面板的显示；另一方面通过比对确定需要刷新的位置对应的数据，并添加模式信息和地址信息，使得显示面板能够根据第一处理器件输出的数据实现局部刷新，触控延迟小。
示例性地，第一灰阶图像的灰阶数为256(对应灰阶范围0～255)，第二灰阶图像的灰阶数为8(对应灰阶范围0～7)，灰阶数越大，灰阶范围也越大。将256灰阶图像转换适合显示面板的8灰阶图像，相比电子纸显示面板的3灰阶图像显示，灰阶更丰富。
在本公开一种可能的实现方式中，所述第一处理器件131用于通过算法线程调用多个转码线程并行地对所述第一灰阶图像进行转换，每个所述转码线程处理所述第一灰阶图像中的多行数据。
在该实现方式中，采用多个线程并行处理第一灰阶图像，相比于采用单个线程处理，能够增加转码效率，降低延迟。
示例性地，第一灰阶图像具有1024行像素点，也即对应1024行数据，第一处理器件131通过8个转码线程对1024行数据进行转码，每个转码线程处理128行数据。
下面以第一处理器件131生成的图像的色彩深度为8bit(也即256灰阶)，MIP显示面板通常支持的色彩深度为1bit(也即8灰阶)为例对图像转换的过程进行说明。需要说明的是，上述图像的灰阶数仅为举例，并不作为本公开的限制。
第一处理器件131将加载的图像(R/G/B 8:8:8，灰阶数为0～255)转换为MIP需要的图像(R/G/B 1:1:1，灰阶数为0和1)。在一种可能的实现方式中，转换的原则如下：对R、G、B的灰阶值x进行判断，x≥127则输出x＝1；x＜127则输出x＝0。下面结合附图对该过程进行说明：
图5是本公开至少一实施例提供的一种图像转换的流程图。参见图5，该图 像转换的过程包括：S21、前处理。第一处理器件131中的算法线程获取RGB888的图像信息；S22、RGB111转码。为提升转码效率降低算法延时，将图像的1024行数据分成8个转码线程同步进行灰阶的转换，每个线程处理128行数据。S23、后处理。将8个转码线程输出的数据汇总整合成一帧RGB111的数据。
转化后的数据由每8bit表示一个子像素的灰阶，变为1bit存储一个子像素的灰阶，色彩数也从16.7M色变为8色。
以分辨率768RGB*1024为例，转码前后数据大小将由2360KB降为295KB，如图9所示。
示例性地，对于一幅画面为全红色的数据，转码前的8个像素为：0b111111110b000000000b000000000b111111110b000000000b000000000b111111110b000000000b000000000b111111110b000000000b000000000b111111110b000000000b000000000b111111110b000000000b000000000b111111110b000000000b000000000b111111110b000000000b00000000。
转码后的8个像素为：0b100100100b01001001 0b00100100。
在本公开其他可能的实现方式中，所述第一处理器件131通过一个线程对所述第一灰阶图像进行转换。
在本公开实施例中，由于本公开实施例使用的MIP显示面板支持全局刷新、局部刷新以及静态保持三种工作模式。全局刷新时，MIP显示面板接收整个画面的数据并进行更新；局部刷新时，MIP显示面板接收局部的数据对局部画面进行更新，局部刷新时以行为单位刷新，也即每次刷新a行，a为正整数，最小可单独刷新的数据量为一行的数据；静态保持时，画面无需更新，无需传输数据。
在确定工作模式前，驱动主板需要对显示面板当前显示图像和下一帧要显示的图像进行对比。根据两帧图像变化的多少，决定工作模式，例如，若两帧图像完全相同，则工作模式为静态保持，若两帧图像的每一行均不同，则工作模式为全局刷新，若两帧图像仅部分行不同，则工作模式为局部刷新。
以分辨率768RGB*1024为例，首先获取当前显示图像的1024行数据，将下一帧要显示的图像的1024行数据与当前显示图像的1024行数据进行逐行对比，有数据变化的行的行地址输出。若没有输出行地址，则工作模式为静态保持，若输出1024个行地址，则工作模式为全局刷新，若输出的行地址数小于1024 且大于0，则工作模式为局部刷新。
比对完成后，若工作模式为局部刷新，则第一处理器件将下一帧要显示的图像中对应输出的行地址的数据打包发出给第二处理器件，第二处理器件再通过N路SI信号驱动MIP显示面板，实现特定行的局部刷新功能。
在本公开实施例中，MIP显示面板支持解码的接口为N路SI接口，SI的信息组成为模式位+地址位+数据。N路SI共同组成一行的信息，因此需要在SI数据前增加模式信息和地址信息，也即添加信息头。
图6是本公开至少一实施例提供的SI信号示意图。参见图6，每路SI信号增加模式信息和地址信息共16位，包括6位模式位(M0～M5)和10位地址位(A0～A9)，后续为数据位(D0～D7)。
示例性地，第一行前24个像素的数据为：
0b100100100b010010010b001001000b100100100b010010010b001001000b100100100b010010010b00100100。
其中，0b表示后续数据为二进制数。
增加信息头后的数据为：
0b111111000b000000010b100100100b100100100b010010010b001001000b100100100b010010010b001001000b100100100b01001001。其中，下划线部分为增加的信息头，信息头的前6位为模式位，也即111111(具体模式可以需要设置)，信息头的后10位为地址位，也即0000000001，可以代表第一行。
参见图6，从SI0～SI(n-1)共N路SI信号，每路SI信号都增加模式信息和地址信息。N路SI信号在片选信号CS和时钟信号CLK控制下传输到MIP显示面板。
在本公开实施例中，所述第一处理器件131还用于将所述画面变化部分的数据中的每行数据分为N份；将所述每行数据中相同顺序份的数据组合成一组，得到N组数据，所述N组数据分别对应所述N路SI信号。
这里，将所述每行数据中相同顺序份的数据组合成一组，可以是指将每行数据中相同顺序份的数据按照行序号从小到大依次拼接到一起。
在该实现方式中，通过第一处理器件对数据进行重排序，生成N组数据，为后续第二处理器件的N路SI信号输出做准备。
另外，由第一处理器件(SOC)进行重排序处理，第二处理器件(MCU) 只需要进行发送，避免MCU进行处理造成的效率低问题。
在本公开实施例中，由于第二处理器件的输出接口为N路SI输出，为提高传输效率，第一处理器件将数据进行分组打包，方便第二处理器件提取数据。第二处理器件只需将分组好的数据循环分配给N路SI即可，也即分别将打包分组好的N组数据，依次分配给N路SI。
以分辨率为768*1024、SI的路数为16为例，每一行的数据分成16份，并且每份添加完头信息。以全局刷新为例，需要把1024行的第一份数据组合到一起，即SI0信号为1024行的第一份数据，SI1信号为1024行的第二份数据，依次类推。
例如，第一行的第一份数据为：
0b111111000b000000010b100100100b100100100b010010010b001001000b100100100b01001001；
第二行的第一份数据为：
0b111111000b000000100b100100100b100100100b010010010b001001000b100100100b01001001；
……
第十六行的第一份数据为：
0b111111000b000100000b100100100b100100100b010010010b001001000b100100100b01001001。
则重排序后，SI0信号为：
0b111111000b000000010b100100100b100100100b010010010b001001000b100100100b01001001 0b111111000b000000100b100100100b100100100b010010010b001001000b100100100b01001001… 0b111111000b000100000b100100100b100100100b010010010b001001000b100100100b01001001。
为了方便后续MIP显示面板的解码，可以在重排序时，将所有信息头都放在最前面，此时SI0信号为：
0b111111000b000000010b111111000b00000010……0b111111000b000100000b100100100b100100100b010010010b001001000b100100100b010010010b100100100b100100100b010010010b001001000b100100100b01001001……0b100100100b100100100b010010010b001001000b100100100b01001001。
也即，第一处理器件还用于将每组数据中的各份数据的模式信息和地址信息组合并排在每组数据的头部。
在上述示例中，带有下划线的部分为信息头。
在本公开实施例中，所述第一处理器件131还用于向所述第二处理器件132发送画面变化部分的数据的数据量；
所述第二处理器件132还用于根据所述数据量生成时钟信号，所述时钟信号用于控制所述N路SI信号传输的时序。
示例性地，第一处理器件131可以向第二处理器件132发送先导数据，前述数据量携带在先导数据中。
可选地，先导数据除了数据量外，还可以包括模式和状态标识。
其中，数据量是指第一处理器件131向第二处理器件132发送的一帧图像的数据量，也即要刷新的数据的行数；模式是指刷新模式，包括静态保持(不刷新)、局部刷新或全局刷新；状态标识用于指示数据的传输状态，状态标识随着第一处理器件131和第二处理器件132之间的数据传输情况变化，当第一处理器件131和第二处理器件132之间的数据传输完成时，第一处理器件131向第二处理器件132发送的状态标识为传输完成。
在本公开实施例中，第一处理器件131和第二处理器件132之间的数据传输需要较高的速率，以分辨率768RGB*1024、刷新率25Hz为例，传输速率为(768×3bit+(16+16))×1024×25Hz≈59.8Mbps。
该公式中，第1个16表示信息头为16位，第2个16为空出的dummy位，用来标识结束。
而常用接口的速率如下：IIC为5Mbps、串行外设接口(Serial Peripheral Interface，SPI)为50Mbps、USB FS(full speed)为12Mbps均不能满足要求；移动产业处理器接口(Mobile Industry Processor Interface，MIPI)、高清多媒体接口(High Definition Multimedia Interface，HDMI)、低电压差分信号(Low-Voltage Differential Signaling，LVDS)接口等常用显示接口速率均在Gbps以上，速率可以满足要求，但是均为直接驱动显示IC使用，MCU等一般不支持这些接口的信号解码。因此，如前所述，本公开采用USB HS(High-Speed)接口，传输速率480Mbps，既可以满足速率要求，又能实现MCU对信号的解码。
第一处理器件131将的图像数据通过USB HS接口传输至第二处理器件 132，第二处理器件132通过GPIO接口模拟SI信号携带数据，并生成相应的CLK，输出到MIP显示面板。MIP显示面板的解码电路为N路SI解码电路。
第一处理器件131在发送图像数据前，先给第二处理器件发送先导数据。第二处理器件按照先导数据中的数据量生成相对应的CLK，然后将N组数据通过N路接口搭配CLK传输至MIP显示面板。
示例性地，第二处理器件根据先导数据中的数据量确定CLK的长度，每bit数据对应CLK中的一个高电平，同时，根据显示面板的接收和解码能力，确定CLK的频率，例如，CLK频率根据MIP显示面板的能力，通常设置为4～6MHz。
在本公开实施例中，可以多路SI信号共用一路CLK，也可以每路SI信号单独设置一路CLK，但多路CLK的波形相同。
图7是本公开至少一实施例提供的一种第二处理器件的输出信号波形图。参见图7，该第二处理器件输出信号波形包括DISP、CS、CLK和SI信号。
其中，DISP(Display)为MIP显示面板的启动控制信号，高电平有效。CS为通信的控制信号，只有当CS信号处于高电平时，MIP显示面板才会对SI信号进行解码。CLK为通信的时钟信号，频率根据显示的数据大小变动。SI为数据信号，包含SI_1～SI_15共16路。
当共用一路CLK时，第二处理器件最终共输出19路信号，当每路SI信号单独设置一路CLK时，第二处理器件最终共输出34路信号。这里，各路信号的高电平为3～5.5V，低电平为0～1V。
在本公开实施例中，第一处理器件和第二处理器件之间的传输是与图像数据的处理并行实现的，下面结合附图进行说明：
图8是本公开至少一实施例提供的一种传输和处理的流程图。参见图8，第一处理器件通过算法线程、传输线程和同步线程共同完成数据的传输和处理。
参见图8，由于传输是在第一处理器件和第二处理器件之间进行，因此，需要考虑收发双方的同步，这里同步线程通过定时器触发，当同步线程开启时，通知传输线程可以进行传输。
参见图8，S31、算法线程处理A帧图像数据，处理完成后，通知传输线程可以进行该帧图像的传输；S32、传输线程接收到通知后，传输A帧图像数据到第二处理器件，并且在传输完成后，通过解锁通知告知算法线程传输线程已空闲；S33、算法线程在完成A帧图像数据的处理后，处理B帧图像数据，处理 完成后，通知传输线程可以进行该帧图像的传输；S34、传输线程接收到通知后，传输B帧图像数据到第二处理器件，并且在传输完成后，通过解锁通知告知算法线程传输线程已空闲。直到同步线程定时器结束，停止数据处理及传送。
在该实现方式中，采用双缓冲加线程分离的方式优化传输和处理的流程，从而节省时间，降低延迟。
图9是本公开至少一实施例提供的一种数据从第二处理器件发送到MIP显示面板的流程图。参见图9，S41、当第二处理器件接收到先到数据后，会先进行USB数据解码。S42、根据先导数据中的数据量大小申请对应的Flash缓存空间，然后将先导数据和重排序后的图像数据全部存入Flash缓存中。S43、当状态标志为传输完成时，获取先导数据中刷新模式，并根据刷新模式从缓存中读取数据进行传输。
当全局刷新时，S44、周期地从缓存中读取N组数据，例如，每个周期依次读取第0至第N-1组的1个bit；S45、在每个周期中，将读取的数据依次发送至MCU上SI0～SI15对应的GPIO接口寄存器中。循环步骤S44和S45，并在每次循环后执行步骤S46、判断N组数据是否读取完，读取完则等待下一次传输，否则继续循环。
当局部刷新时，S47、读取数据量；S48、周期地从缓存中读取N组数据，例如，每个周期依次读取第0至第N-1组的1个bit；S49、在每个周期中，将读取的数据依次发送至MCU上SI0～SI15对应的GPIO接口寄存器中。循环步骤S48和S49，并在每次循环后执行步骤S410、根据数据量判断N组数据是否读取完，读取完则等待下一次传输，否则继续循环。
值得说明的是，在全局刷新时，数据量是固定的，此时可以不执行读取数据量的步骤。
根据数据量和预设的N的数值，可以知道每组数据的长度，进而知道每组数据的第1个bit的位置，从而实现周期性地读取各组数据。
在判断是否读取完时，也是根据每组数据的长度，然后根据当前循环的周期数，当周期数达到每组数据的长度加1后，确定读取完。
以分辨率为768*1024、16路SI为例。当全局刷新时，每组数据的长度为768*3*1024/16，每组数据的长度也即要循环的周期数。当局部刷新时，每组数据的长度为768*3*C/16，C为数据量对应的行数，每组数据的长度也即要循环 的周期数。
图10是本公开至少一实施例提供的一种显示方法的流程图。该方法应用于图1所示的显示装置，该方法包括：
S51、根据控制指令获取所述画面变化部分的数据，所述控制指令用于控制所述显示面板显示的画面局部变化。
步骤S51由驱动主板的第一处理器件执行。
S52、向所述显示面板输出N路从输入信号，所述N路从输入信号用于携带所述画面变化部分的数据，所述N为大于1的正整数。
步骤S52由驱动主板的第二处理器件执行。
S53、根据所述画面变化部分的数据进行局部画面刷新。
步骤S53由显示面板执行。
在本公开实施例中，驱动主板可以在控制指令用于控制所述显示面板画面局部变化时，将画面变化部分的数据发送给所述显示面板，显示面板则可以根据所述画面变化部分的数据进行局部画面刷新；由于显示面板局部刷新相比于整幅画面刷新所需的时间更短，因此可以大大减少响应时间，降低了延迟。另外，采用两个处理单元，其中一个处理单元负责图像加载和图像处理，保证处理速度；另一个处理单元实现串转并，通过并行的N路SI信号传输图像输出给显示面板，保证数据传输速度，从而保证响应时间短。通过驱动主板即可实现N路并行输出，省去了相关技术中布置在驱动主板和显示面板之间的显示器IC，节省了器件，减小了体积。
在本公开一种可能的实现方式中，所述根据控制指令获取所述画面变化部分的数据，包括：
通过加载线程进行图像加载，通过算法线程对所述加载线程加载的图像进行图像处理，得到所述画面变化部分的数据。
该实现方式中，通过2个线程分别进行图像加载和处理，避免采用一个线程进行加载和处理时，容易出现的卡顿情况，进一步降低延迟。
该图像加载和处理的过程可以参见图4及对应的描述，这里不做赘述。
在本公开其他可能的实现方式中，可以通过一个线程进行图像加载和处理。
可选地，所述根据所述控制指令获取所述画面变化部分的数据，包括：
将根据所述控制指令加载的第一灰阶图像转换成第二灰阶图像，所述第一灰阶图像的灰阶数大于所述第二灰阶图像的灰阶数，所述第二灰阶图像的灰阶数和所述显示面板适配；对比所述第二灰阶图像和所述显示面板当前显示图像，确定所述显示面板的画面是否为局部刷新，并在所述显示面板的画面局部刷新时，确定所述显示面板需要刷新的位置对应的数据；给所述显示面板需要刷新的位置对应的数据添加模式信息和地址信息，得到所述画面变化部分的数据。
在该实现方式中，一方面通过转码将第一灰阶图像转换成第二灰阶图像，更适合显示面板的显示；另一方面通过比对确定需要刷新的位置对应的数据，并添加模式信息和地址信息，使得显示面板能够根据第一处理器件输出的数据实现局部刷新，触控延迟小。
示例性地，第一灰阶图像的灰阶数为256，第二灰阶图像的灰阶数为8。将256灰阶图像转换适合显示面板的8灰阶图像，相比电子纸显示面板的3灰阶图像显示，灰阶更丰富。
在本公开一种可能的实现方式中，所述将根据所述控制指令加载的第一灰阶图像转换成第二灰阶图像，包括：
通过算法线程调用多个转码线程并行地对所述第一灰阶图像进行转换，每个所述转码线程处理所述第一灰阶图像中的多行数据。
在该实现方式中，采用多个线程并行处理第一灰阶图像，相比于采用单个线程处理，能够增加转码效率，降低延迟。
该图像转换的过程可以参见图5及对应的描述，这里不做赘述。
在本公开其他可能的实现方式中，可以通过一个线程对所述第一灰阶图像进行转换。
可选地，所述根据所述控制指令获取所述画面变化部分的数据，还包括：
将所述画面变化部分的数据中的每行数据分为N份；将所述每行数据中相同顺序份的数据组合成一组，得到N组数据，所述N组数据分别对应所述N路SI信号。
在该实现方式中，通过对数据进行重排序，生成N组数据，为后续N路SI信号输出做准备。
可选地，所述第一处理器件还用于将每组数据中的各份数据的模式信息和地址信息组合并排在每组数据的头部。
可选地，所述根据控制指令，将画面变化部分的数据发送给所述显示面板，还包括：
根据所述画面变化部分的数据的数据量成时钟信号，所述时钟信号用于控制所述N路SI信号传输的时序。
可选地，所述从输入信号包括图像数据、地址信息及模式信息，所述地址信息为所述图像数据所要写入的显示面板的地址，所述模式信息用于指示所述显示面板的刷新模式为局部刷新。
如图11所示，本公开实施例还提供了一种终端400，该终端400可以为显示装置。该终端400可以用于执行上述各个实施例中提供的显示方法。参见图11，该终端400包括：存储器401、处理器402和显示组件403，本领域技术人员可以理解，图11中示出的终端400的结构并不构成对终端400的限定，在实际应用中可以包括比图示更多或更少的组件，或者组合某些组件，或者不同的组件布置。其中：
存储器401可用于存储计算机程序以及模块，存储器401可主要包括存储程序区和存储数据区，其中，存储程序区可存储操作***、至少一个功能所需的应用程序等。存储器401可以包括高速随机存取存储器，还可以包括非易失性存储器，例如至少一个磁盘存储器件、闪存器件、或其他易失性固态存储器件。相应地，存储器401还可以包括存储器控制器，以提供处理器402对存储器401的访问。
处理器402通过运行存储在存储器401的软件程序以及模块，从而执行各种功能应用以及数据处理。
显示组件403用于显示图像，显示组件403可包括显示面板，可选的，可以采用LCD(Liquid Crystal Display，液晶显示器)、OLED(Organic Light-Emitting Diode,有机发光二极管)等形式来配置显示面板。
在示例性实施例中，还提供了一种计算机可读存储介质，该计算机可读存储介质为非易失性存储介质，该计算机可读存储介质中存储有计算机程序，当该计算机可读存储介质中的计算机程序由处理器执行时，能够执行本公开实施例提供的显示方法。
在示例性实施例中，还提供了一种计算机程序产品，该计算机程序产品中存储有指令，当其在计算机上运行时，使得计算机能够执行本公开实施例提供的显示方法。
在示例性的实施例中，还提供了一种芯片，该芯片包括可编程逻辑电路和/或程序指令，当该芯片运行时能够执行本公开实施例提供的显示方法。
本领域普通技术人员可以理解实现上述实施例的全部或部分步骤可以通过硬件来完成，也可以通过程序来指令相关的硬件完成，所述的程序可以存储于一种计算机可读存储介质中，上述提到的存储介质可以是只读存储器，磁盘或光盘等。
以上所述仅为本公开的可选实施例，并不用以限制本公开，凡在本公开的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本公开的保护范围之内。

Claims (20)

  1. 一种显示装置，其特征在于，所述显示装置包括显示面板和驱动主板，所述驱动主板包括第一处理器件和第二处理器件，所述第二处理器件分别与所述第一处理器件和所述显示面板电连接；
    所述第一处理器件用于根据控制指令获取画面变化部分的数据，将所述画面变化部分的数据输出给所述第二处理器件，所述控制指令用于控制所述显示面板显示的画面局部变化；
    所述第二处理器件用于向所述显示面板输出N路从输入信号，所述N路从输入信号用于携带所述画面变化部分的数据，所述N为大于1的正整数；
    所述显示面板，用于根据所述画面变化部分的数据进行局部画面刷新。
  2. 根据权利要求1所述的显示装置，其特征在于，所述第一处理器件通过加载线程进行图像加载，通过算法线程对所述加载线程加载的图像进行图像处理，得到所述画面变化部分的数据。
  3. 根据权利要求1所述的显示装置，其特征在于，所述第一处理器件用于将根据所述控制指令加载的第一灰阶图像转换成第二灰阶图像，所述第一灰阶图像的灰阶数大于所述第二灰阶图像的灰阶数，所述第二灰阶图像的灰阶数和所述显示面板适配；对比所述第二灰阶图像和所述显示面板当前显示图像，确定所述显示面板的画面是否为局部刷新，并在所述显示面板的画面局部刷新时，确定所述显示面板需要刷新的位置对应的数据；给所述显示面板需要刷新的位置对应的数据添加模式信息和地址信息，得到所述画面变化部分的数据。
  4. 根据权利要求3所述的显示装置，其特征在于，所述第一处理器件用于通过算法线程调用多个转码线程并行地对所述第一灰阶图像进行转换，每个所述转码线程处理所述第一灰阶图像中的多行数据。
  5. 根据权利要求3所述的显示装置，其特征在于，所述第一处理器件还用于将所述画面变化部分的数据中的每行数据分为N份；将所述每行数据中相同顺序份的数据组合成一组，得到N组数据，所述N组数据分别对应所述N路从输入信号。
  6. 根据权利要求5所述的显示装置，其特征在于，所述第一处理器件还用于将每组数据中的各份数据的模式信息和地址信息组合并排在每组数据的头部。
  7. 根据权利要求1至6任一项所述的显示装置，其特征在于，所述第一处理 器件还用于向所述第二处理器件发送所述画面变化部分的数据的数据量；
    所述第二处理器件还用于根据所述数据量生成时钟信号，所述时钟信号用于控制所述N路从输入信号传输的时序。
  8. 根据权利要求1至6任一项所述的显示装置，其特征在于，所述从输入信号包括图像数据、地址信息及模式信息，所述地址信息为所述图像数据所要写入的显示面板的地址，所述模式信息用于指示所述显示面板的刷新模式为局部刷新。
  9. 根据权利要求1至6任一项所述的显示装置，其特征在于，所述第一处理器件为***级芯片，所述第二处理器件为微控制单元。
  10. 根据权利要求1至6任一项所述的显示装置，其特征在于，所述第一处理器件和所述第二处理器件通过通用串行总线接口电连接；
    所述第一处理器件和所述第二处理器件中的一个集成通用串行总线物理层芯片，或者，所述第一处理器件和所述第二处理器件中的一个外接通用串行总线物理层芯片。
  11. 根据权利要求1至6任一项所述的显示装置，其特征在于，所述显示面板为具有触控功能的显示面板，所述控制指令是基于所述显示面板的触控操作生成的触控指令。
  12. 一种显示方法，其特征在于，所述方法应用于权利要求1所述的显示装置，所述方法包括：
    根据控制指令获取画面变化部分的数据，所述控制指令用于控制所述显示面板显示的画面局部变化；
    向所述显示面板输出N路从输入信号，所述N路从输入信号用于携带所述画面变化部分的数据，所述N为大于1的正整数；
    根据所述画面变化部分的数据进行局部画面刷新。
  13. 根据权利要求12所述的方法，其特征在于，所述根据控制指令获取所述画面变化部分的数据，包括：
    通过加载线程进行图像加载，通过算法线程对所述加载线程加载的图像进行图像处理，得到所述画面变化部分的数据。
  14. 根据权利要求12所述的方法，其特征在于，所述根据控制指令获取所述画面变化部分的数据，包括：
    将根据所述控制指令加载的第一灰阶图像转换成第二灰阶图像，所述第一灰阶图像的灰阶数大于所述第二灰阶图像的灰阶数，所述第二灰阶图像的灰阶数和所述显示面板适配；对比所述第二灰阶图像和所述显示面板当前显示图像，确定所述显示面板的画面是否为局部刷新，并在所述显示面板的画面局部刷新时，确定所述显示面板需要刷新的位置对应的数据；给所述显示面板需要刷新的位置对应的数据添加模式信息和地址信息，得到所述画面变化部分的数据。
  15. 根据权利要求14所述的方法，其特征在于，所述将根据所述控制指令加载的第一灰阶图像转换成第二灰阶图像，包括：
    通过算法线程调用多个转码线程并行地对所述第一灰阶图像进行转换，每个所述转码线程处理所述第一灰阶图像中的多行数据。
  16. 根据权利要求14所述的方法，其特征在于，所述根据控制指令获取所述画面变化部分的数据，还包括：
    将所述画面变化部分的数据中的每行数据分为N份；将所述每行数据中相同顺序份的数据组合成一组，得到N组数据，所述N组数据分别对应所述N路从输入信号。
  17. 根据权利要求16所述的方法，其特征在于，所述将所述每行数据中相同顺序份的数据组合成一组，包括：
    将每组数据中的各份数据的模式信息和地址信息组合并排在每组数据的头部。
  18. 根据权利要求12至17任一项所述的方法，其特征在于，所述方法还包括：
    根据所述画面变化部分的数据的数据量成时钟信号，所述时钟信号用于控制所述N路从输入信号传输的时序。
  19. 根据权利要求12至17任一项所述的方法，其特征在于，所述从输入信号包括图像数据、地址信息及模式信息，所述地址信息为所述图像数据所要写入的显示面板的地址，所述模式信息用于指示所述显示面板的刷新模式为局部刷新。
  20. 一种终端，其特征在于，所述终端包括处理器和存储器；
    其中，所述存储器，用于存储计算机程序；
    所述处理器，用于执行所述存储器中存放的计算机程序，以实现权利要求 12至19任一所述的显示方法。
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