WO2024026937A1 - 半导体器件、传感器器件及电子设备 - Google Patents
半导体器件、传感器器件及电子设备 Download PDFInfo
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- WO2024026937A1 WO2024026937A1 PCT/CN2022/113026 CN2022113026W WO2024026937A1 WO 2024026937 A1 WO2024026937 A1 WO 2024026937A1 CN 2022113026 W CN2022113026 W CN 2022113026W WO 2024026937 A1 WO2024026937 A1 WO 2024026937A1
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- Prior art keywords
- thin film
- film transistor
- integrated circuit
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 68
- 239000010409 thin film Substances 0.000 claims abstract description 308
- 239000000758 substrate Substances 0.000 claims abstract description 60
- 229910052751 metal Inorganic materials 0.000 claims description 41
- 239000002184 metal Substances 0.000 claims description 41
- 238000006243 chemical reaction Methods 0.000 claims description 18
- 238000002161 passivation Methods 0.000 claims description 18
- 239000000969 carrier Substances 0.000 claims description 15
- 239000013078 crystal Substances 0.000 claims description 14
- 238000009413 insulation Methods 0.000 claims description 13
- 230000002093 peripheral effect Effects 0.000 claims description 12
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 12
- 229920005591 polysilicon Polymers 0.000 claims description 12
- 239000000463 material Substances 0.000 claims description 9
- 229910044991 metal oxide Inorganic materials 0.000 claims description 9
- 150000004706 metal oxides Chemical class 0.000 claims description 9
- 238000003860 storage Methods 0.000 claims description 8
- 238000004519 manufacturing process Methods 0.000 abstract description 14
- 239000010410 layer Substances 0.000 description 270
- 238000010586 diagram Methods 0.000 description 24
- 230000037230 mobility Effects 0.000 description 24
- 239000010408 film Substances 0.000 description 20
- 239000011229 interlayer Substances 0.000 description 11
- 230000006870 function Effects 0.000 description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 9
- 229910052710 silicon Inorganic materials 0.000 description 9
- 239000010703 silicon Substances 0.000 description 9
- 238000002360 preparation method Methods 0.000 description 7
- 230000010354 integration Effects 0.000 description 6
- 239000011521 glass Substances 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000002787 reinforcement Effects 0.000 description 2
- 230000008054 signal transmission Effects 0.000 description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1251—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
- H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
Definitions
- the present invention relates to the technical field of manufacturing display panels, and in particular, to a semiconductor device, a sensor device and an electronic device.
- the semiconductor device when preparing a semiconductor device, the semiconductor device is usually prepared on a silicon-based substrate to form a silicon-based chip. Therefore, the silicon-based chip is a circuit component composed of a plurality of stacked semiconductor films, conductive films, and insulating films on a silicon substrate. It achieves the purpose of miniaturization, lightweight and integration of semiconductor devices by integrating numerous components on the silicon-based substrate.
- the preparation cost of the carrier formed by the single crystal silicon substrate is higher, the integration is high, and the production process is complicated.
- the high cost of silicon-based materials will further restrict the supply of semiconductor devices, which is not conducive to the control of manufacturing costs and the development of the semiconductor industry. There is an urgent need to find a silicon-based alternative material. As well as the device preparation process to reduce the manufacturing cost of the device and improve the overall performance of the device.
- embodiments of the present invention provide a semiconductor device, a sensor device and an electronic device to effectively improve the preparation process and production cost of the semiconductor device, and improve the overall performance of the device.
- the present invention provides a semiconductor device, including:
- a first integrated circuit disposed on an insulating substrate, the first integrated circuit including a first thin film transistor
- the second integrated circuit including a second thin film transistor
- the mobility of carriers in the active layer of the first thin film transistor is greater than the mobility of carriers in the active layer of the second thin film transistor.
- the average size of the crystal grains in the active layer of the first thin film transistor is larger than the The average size of crystal grains in the active layer of the second thin film transistor.
- the crystal grains in the active layer of the first thin film transistor include a first boundary in a first direction and a second boundary in a second direction;
- the first direction is the same as the length direction of the channel region
- the second direction is perpendicular to the length direction of the channel region
- the length of the first boundary is greater than the length of the second boundary.
- the active layer of the first thin film transistor and the active layer of the second thin film transistor are made of the same material, and the active layer of the first thin film transistor and the second thin film transistor are made of the same material.
- the active layers of the transistors are arranged on the same layer, the gate electrode of the first thin film transistor and the gate electrode of the second thin film transistor are arranged on the same layer, and the source/drain metal layer of the first thin film transistor and the second thin film transistor are arranged on the same layer.
- the source/drain metal layers of the transistor are placed on the same layer.
- the gate insulation of the first thin film transistor is provided on the active layer of the first thin film transistor, and the source/drain metal layer insulation of the first thin film transistor is provided on the gate electrode. on, and the active layer insulation of the second thin film transistor is provided on the source/drain metal layer of the first thin film transistor, and the gate insulation of the second thin film transistor is provided on the active layer of the second thin film transistor. on the source layer.
- the first thin film transistor includes a low-temperature polysilicon thin film transistor
- the second thin film transistor includes a metal oxide thin film transistor
- the active layer of the first thin film transistor is disposed on the insulating substrate
- the gate insulation of the first thin film transistor is disposed on the active layer of the first thin film transistor
- the second thin film transistor The gate electrode of the transistor is arranged in the same layer as the gate electrode of the first thin film transistor.
- it further includes a gate insulating layer disposed on the gate electrode of the first thin film transistor and the gate electrode of the second thin film transistor, and the active layer of the second thin film transistor is disposed on the gate electrode.
- the gate insulating layer On the gate insulating layer, the source/drain metal layer of the first thin film transistor and the source/drain metal layer of the second thin film transistor are arranged in the same layer on the gate insulating layer.
- the source/drain metal layer of the second thin film transistor is at least partially disposed on the surface of the active layer of the second thin film transistor and is electrically connected to the active layer of the second thin film transistor.
- the first thin film transistor and the second thin film transistor are of different types
- the second thin film transistor is provided on the first thin film transistor
- the semiconductor device further includes a device provided on the first thin film transistor. a passivation layer between the first thin film transistor and the second thin film transistor.
- the semiconductor device further includes a second gate insulating layer, a gate of the second thin film transistor is disposed on the passivation layer, and the second gate insulating layer is disposed on the passivation layer. on the passivation layer, and the active layer of the second thin film transistor is disposed on the second gate insulating layer, and the source/drain metal layer of the second thin film transistor is disposed on the second gate insulating layer superior;
- the source/drain metal layer of the second thin film transistor is at least partially disposed on the surface of the active layer of the second thin film transistor and is electrically connected to the active layer of the second thin film transistor.
- the first integrated circuit includes any one of a logic control integrated circuit, a low-pass control integrated circuit and a digital-to-analog conversion integrated circuit
- the second integrated circuit includes a storage integrated circuit and an operational amplifier integrated circuit. any type of circuit.
- a sensor device including a sensing area and a peripheral circuit area provided on one side of the sensing area, including:
- a sensing unit the sensing unit is disposed on the insulating substrate corresponding to the sensing area;
- Integrated circuit at least part of the integrated circuit is disposed on the insulating substrate corresponding to the peripheral circuit area, and the integrated circuit is used to control the sensing unit;
- the integrated circuit includes:
- a first integrated circuit including a first thin film transistor
- the second integrated circuit including a second thin film transistor
- the mobility of carriers in the active layer of the first thin film transistor is greater than the mobility of carriers in the active layer of the second thin film transistor.
- it also includes: located in the sensing area:
- a plurality of data signal lines intersect with the gate signal lines to form a plurality of intersection areas, and at least one of the sensing units is provided in each of the intersection areas, and the sensing unit includes a first sensor unit.
- Sense module
- the data signal line is electrically connected to the first sensing module, and the data signal line is electrically connected to the integrated circuit in the peripheral circuit area.
- the data signal line is electrically connected to the first integrated circuit
- the second integrated circuit is electrically connected to the first integrated circuit
- the first integrated circuit is electrically connected to the between the sensing unit and the second integrated circuit.
- the first integrated circuit includes at least one of a low-pass control integrated circuit, an analog control integrated circuit, and a digital-to-analog conversion integrated circuit
- the second integrated circuit includes a memory integrated circuit
- the first integrated circuit includes a low-pass control integrated circuit electrically connected to the data signal line, an analog control integrated circuit electrically connected to the low-pass control integrated circuit, and an analog control integrated circuit electrically connected to the analog signal line.
- a digital-to-analog conversion integrated circuit electrically connected to the control integrated circuit, the second integrated circuit including a storage integrated circuit; the low-pass control integrated circuit electrically connected between the sensing unit and the analog control integrated circuit, the digital An analog conversion integrated circuit is electrically connected between the analog control integrated circuit and the memory integrated circuit.
- the active layer of the first thin film transistor includes low-temperature polysilicon
- the active layer of the second thin film transistor includes metal oxide
- the active layer of the first sensing module includes amorphous silicon.
- the first integrated circuit and the second integrated circuit are both disposed on the same side of the insulating substrate, and the first sensing module is disposed far away from the first integrated circuit. On one side of the insulating substrate, the first sensing module is electrically connected to the first thin film transistor.
- the first integrated circuit and the second integrated circuit are both disposed on the first surface of the insulating substrate, and the first sensing module is disposed between the insulating substrate and the the second side opposite to the first side;
- the first sensing module is electrically connected to the first thin film transistor through a via hole provided on the insulating substrate.
- an electronic device including the semiconductor device or sensor device provided in the embodiment of the present application.
- Embodiments of the present invention provide a semiconductor device, a sensor device and an electronic device.
- the semiconductor device includes a first integrated circuit and a second integrated circuit.
- the first integrated circuit includes a first thin film transistor and a second thin film transistor arranged on an insulating substrate, and carriers in the active layer of the first thin film transistor The mobility is greater than the mobility of carriers in the active layer of the second thin film transistor.
- the thin film transistor device in the integrated circuit is directly placed on an insulating substrate, and the corresponding thin film transistors inside the integrated circuit are set to different mobilities, and low-cost insulating materials are used to replace high-cost semiconductor materials, thereby reducing manufacturing costs, and optimize device performance.
- Figure 1A is a simplified schematic diagram of an integrated circuit provided by an embodiment of the present application.
- Figure 1B is a schematic diagram of the film layer structure corresponding to the integrated circuit provided by the embodiment of the present application.
- Figure 2 is a schematic structural diagram of a sensor device provided by an embodiment of the present application.
- Figure 3 is a schematic diagram of the film structure of a semiconductor device provided by an embodiment of the present application.
- Figure 4 is a schematic diagram of the film structure of another semiconductor device provided in an embodiment of the present application.
- Figure 5 is a schematic plan layout diagram of an integrated circuit corresponding to the insulating substrate provided in the embodiment of the present application.
- FIGS. 6-9 are schematic diagrams of the arrangement structures of different integrated circuits provided by embodiments of the present application.
- Figures 10-13 are schematic diagrams of film layer structures corresponding to the arrangement structures of different semiconductor devices provided in embodiments of the present application.
- Figure 14 is a schematic structural diagram of the crystal grains in the active layer provided by the embodiment of the present application.
- Figure 15 is a schematic diagram of the film structure of another semiconductor device provided by an embodiment of the present application.
- Figure 16 is a film layer structure of yet another semiconductor device provided by an embodiment of the present application.
- Embodiments of the present application provide a semiconductor device to effectively improve the manufacturing process of integrated circuits and effectively reduce the production cost of integrated circuits.
- FIG. 1A is a simplified schematic diagram of an integrated circuit provided by an embodiment of the present application.
- the integrated circuit is described using a control integrated circuit in a vehicle control system as an example.
- the integrated circuit can also be used in other control devices, which will not be described again here.
- the vehicle-mounted control device may be a touch display panel device. Multiple control devices are provided in the touch display panel, and each control device is configured with an integrated circuit. At the same time, multiple control units or control modules are integrated on the integrated circuit.
- the touch display panel includes a carrier circuit board 100, and at the same time, multiple chip integration areas 101 are provided on the carrier circuit board 100. A corresponding integrated circuit is provided in each chip integration area 101 .
- multiple integrated circuits are provided in the chip integration area 101 .
- the first integrated circuit 104 and the second integrated circuit 105 are both disposed on the carrier circuit board 100, and the first integrated circuit 104 and the second integrated circuit 105 are mechanically or electrically connected.
- electrical connection is used.
- mechanical insulation connection can be used.
- the first integrated circuit 104 and the second integrated circuit 105 may be integrated circuits with the same function or integrated circuits with different functions.
- the first integrated circuit 104 is a data control integrated circuit
- the second integrated circuit 105 is a data control integrated circuit.
- the signal controls the integrated circuit, and functions such as controlling and operating the touch display panel are realized through the first integrated circuit 104 and the second integrated circuit 105 .
- the first integrated circuit 104 includes a first base layer 108
- the second integrated circuit 105 includes a second base layer 109. That is, the substrate on which the first integrated circuit 104 is prepared is the first base layer 108 , and the substrate on which the second integrated circuit 105 is prepared is the second base layer 109 .
- the first base layer 108 and the second base layer 109 are both insulating layer substrates.
- the first base layer 108 and the second base layer 109 are both glass substrates.
- a third integrated circuit 102 and a fourth integrated circuit 103 are also provided in the chip integration area 101 .
- the third integrated circuit 102 and the fourth integrated circuit 103 are disposed at different positions from the first integrated circuit 104 and the second integrated circuit 105 .
- the third integrated circuit 102 and the fourth integrated circuit 103 are arranged in different rows of the first integrated circuit 104 .
- the third integrated circuit 102 and the fourth integrated circuit 103 can be integrated circuits with different functions, and can be specifically set according to the control requirements of the actual product.
- each of the above integrated circuits may include a storage integrated circuit, a logic control integrated circuit, a digital-to-analog conversion integrated circuit, an analog control integrated circuit, a low-pass control integrated circuit, and a sensor integrated circuit.
- the corresponding thin film transistors in higher-performance integrated circuits are set to high-mobility thin film transistors, such as logic control integrated circuits, low-pass control integrated circuits, and sensing integrated circuits.
- the digital-to-analog conversion integrated circuit is configured as a high-mobility thin film transistor, while the storage integrated circuit or a lower-performance integrated circuit is configured as a low-mobility thin film transistor. This ensures the normal operation of the control device.
- Figure 1B is a schematic diagram of the film layer structure corresponding to the integrated circuit provided by the embodiment of the present application.
- the first integrated circuit 104 includes a first base layer 108, a dielectric layer 110, and a first thin film transistor 309 disposed in the dielectric layer 110.
- the first thin film transistor 309 is disposed on the first base layer 108.
- the dielectric layer 110 is disposed on the first base layer 108 and covers the corresponding thin film transistor.
- the second integrated circuit 105 includes a second base layer 109, a dielectric layer 110, and a second thin film transistor 308 disposed in the dielectric layer 110.
- each thin film transistor when preparing the thin film transistors in the dielectric layer 110, multiple thin film transistors can be provided in each integrated circuit. Wherein, each thin film transistor can be the same or different.
- the first integrated circuit includes a plurality of first thin film transistors 309
- the second integrated circuit includes a plurality of second thin film transistors 308.
- a plurality of thin film transistors can be arranged in arrays on corresponding insulating substrates.
- the mobility of carriers in the active layer of the first thin film transistor 309 is greater than the mobility of carriers in the active layer of the second thin film transistor 308 .
- the first thin film transistor and the second thin film transistor may be arranged in the same layer or stacked.
- the length of the channel region of the active layer of the first thin film transistor can be longer than the length of the channel region of the active layer of the second thin film transistor, thereby realizing different device sizes.
- the settings can be made according to the performance and specifications of the corresponding integrated circuit, which will not be described again here.
- the average size of the crystal grains in the channel region of the first thin film transistor is larger than that of the channel in the second thin film transistor.
- the average size of grains in the area is larger.
- Figure 14 is a schematic structural diagram of crystal grains in the active layer provided by an embodiment of the present application.
- a first die 450 is included within the channel region 444 of the first active layer 310 of the first thin film transistor.
- the first crystal grain 450 has a first direction X and a second direction Y.
- the first direction In the embodiment of the present application, in the first direction X, the first crystal grain 450 has a first boundary, and in the second direction Y, the first crystal grain 450 has a second boundary, where the length of the first boundary It is greater than the length of the second boundary, so that the carriers can move inside the entire grain as much as possible, thereby improving their mobility.
- the integrated circuit also includes a first wiring layer 1082 and a second wiring layer 1092 .
- the first wiring layer 1082 is provided on the first thin film transistor 309
- the second wiring layer 1092 is provided on the second thin film transistor 308 .
- Each wiring layer can be electrically connected to the corresponding thin film transistor through the corresponding metal wiring, and finally forms the integrated circuit provided in the embodiment of the present application.
- the above-mentioned first integrated circuit and the second integrated circuit can also be arranged in a stack.
- the first integrated circuit can be bound to the second integrated circuit.
- a thin film transistor is prepared on the first base layer 108 or the second base layer 109, and other circuits are continued to be prepared on the thin film transistor. line layer and encapsulate each integrated circuit.
- the first base layer 108 is disposed at a position corresponding to the first region 20
- the second base layer 109 is disposed at a position corresponding to the second region 21
- the first area 20 may be disposed on one side of the second area 21
- the first base layer 108 and the second base layer 109 provided in the first area 20 and the second area 21 may be of the same size, or may be set to different specifications according to the size of the corresponding integrated circuit, which will not be described again here.
- Figure 2 is a schematic structural diagram of a sensor device provided by an embodiment of the present application.
- a plurality of integrated circuits provided by embodiments of the present application are provided in the semiconductor device.
- the semiconductor device is described taking a sensor device as an example.
- the sensor device includes a sensing area 23 and a peripheral circuit area 24 provided on one side of the sensing area 23 .
- the sensing area 23 includes a plurality of gate signal lines 279 and a plurality of data signal lines 278.
- the gate signal lines 279 and the data signal lines 278 intersect and form multiple intersection areas, and in each intersection area At least one sensing unit is provided inside.
- the sensing unit is described taking the first sensing module 210 as an example.
- the data signal line 278 is electrically connected to the first sensing module 210
- the data signal line is electrically connected to the integrated circuit in the peripheral circuit area 24 .
- the first sensing module 210 is controlled through the integrated circuit.
- the semiconductor device may also be other devices, which will not be described again here.
- a plurality of different integrated circuits are provided in the peripheral circuit area, and the plurality of integrated circuits are provided on an insulating substrate, such as a first integrated circuit and a second integrated circuit.
- the data signal line 278 is electrically connected to the first integrated circuit
- the second integrated circuit is electrically connected to the first integrated circuit
- the first integrated circuit is electrically connected between the first sensing module 210 and the second integrated circuit.
- the first integrated circuit may include a plurality of logic control integrated circuits 206, a low-pass control integrated circuit 205, a digital-to-analog conversion integrated circuit 203, and an analog control integrated circuit 204.
- the second integrated circuit may include a memory integrated circuit. At least one of circuit 202 and an operational amplifier integrated circuit. And the second integrated circuit is configured as a low mobility thin film transistor.
- the corresponding first thin film transistor in the first integrated circuit is a low temperature polysilicon thin film transistor
- the corresponding second thin film transistor in the second integrated circuit is a metal oxide thin film transistor.
- the data signal line 278 is electrically connected to the low-pass control integrated circuit 205
- the analog control integrated circuit 204 is electrically connected to the low-pass control integrated circuit 205
- the digital-to-analog conversion integrated circuit 203 is electrically connected to the analog control integrated circuit 204.
- the low-pass control integrated circuit 205 is electrically connected between the first sensing module 210 and the analog control integrated circuit 204
- the digital-to-analog conversion integrated circuit 203 is electrically connected between the analog control integrated circuit 204 and the storage integrated circuit 202.
- the integrated circuit provided in the embodiment of the present application is directly etched and manufactured on the insulating substrate.
- Each integrated circuit includes a plurality of thin film transistors, wherein the thin film transistors in each integrated circuit are configured with the structure provided in the embodiments of the present application, thereby effectively reducing its manufacturing cost and improving its manufacturing process and working performance.
- multiple conductive traces are also provided in the sensor device, and the multiple conductive traces are arranged from the sensing area to the peripheral circuit area to realize the transmission of control signals.
- the sensor device also includes a level conversion module and a shift register, and the level conversion module and the shift register need to have high performance. Therefore, the thin film transistors in the integrated circuits corresponding to the level conversion module and the shift register can use low-temperature polysilicon thin film transistors to ensure that they have higher mobility, which will not be described again here.
- the first integrated circuit and the second integrated circuit may both be disposed on the same side of the insulating substrate.
- the first sensing module 210 is disposed on a side of the first integrated circuit away from the insulating substrate, and is electrically connected to the first thin film transistor in the first integrated circuit.
- first integrated circuit and the second integrated circuit are both disposed on the first surface of the insulating substrate, and the first sensing module is disposed on the second surface of the insulating substrate opposite to the first surface.
- Figure 3 is a schematic diagram of the film structure of a semiconductor device provided by an embodiment of the present application.
- the semiconductor device includes a first thin film transistor 309 and a second thin film transistor 308.
- the first thin film transistor 309 is provided on one side of the second thin film transistor 308 .
- the first thin film transistor 309 and the second thin film transistor 308 are stacked, thereby reducing the area of the integrated circuit.
- the first base layer 108 is a glass layer
- a light-shielding layer is also provided on the first base layer 108
- the buffer layer 302 completely covers the light-shielding layer.
- the first thin film transistor 309 is also provided with a first active layer 310, a first gate insulating layer 303, a first gate electrode 313 and a first interlayer dielectric layer 304.
- the first active layer 310 is disposed on the first buffer layer 302, the first gate insulating layer 303 is disposed on the first buffer layer 302, and the first gate insulating layer 303 completely covers the first buffer layer 302. Active layer 310.
- the first gate 313 is disposed on the first gate insulating layer 303, the first interlayer dielectric layer 304 is disposed on the first gate 313, and the first source/drain metal layer 312 is disposed on the first interlayer dielectric. on layer 304.
- the first source/drain metal layer 312 is electrically connected to the first active layer 310 through corresponding via holes.
- the second buffer layer 305 is disposed on the first thin film transistor 309
- the second active layer 306 is disposed on the second buffer layer 305
- the second gate electrode 314 is disposed on the second active layer 306.
- the second interlayer dielectric layer 307 is provided on the second active layer 306
- the second source/drain metal layer 311 is provided on the second interlayer dielectric layer 307
- the second source/drain metal layer 311 It is electrically connected to the second active layer 306 through corresponding via holes.
- the first thin film transistor 309 and the second thin film transistor can both be configured as low-temperature polysilicon thin film transistors, and the carrier mobility inside the first thin film transistor 309 is greater than the carrier mobility inside the second thin film transistor 308 migration rate.
- the average grain size of the corresponding material in the channel region of the first active layer 310 is larger than the average grain size of the corresponding material in the channel region of the second active layer 306 . This ensures that the mobility of the first thin film transistor is greater than the mobility of the second thin film transistor, and enables integrated circuits formed by different semiconductor devices to have different performances. And ensure that integrated circuits with different performances can maintain high performance under the action of high-speed or low-speed signals. Thereby improving the working performance of the integrated circuit.
- the orthographic projection of the first thin film transistor 309 in the first base layer on the substrate does not completely coincide with the orthographic projection of the second thin film transistor 308 on the substrate.
- FIG. 4 is a schematic diagram of the film structure of another semiconductor device provided in an embodiment of the present application. Combined with the schematic diagram of the film layer structure in Figure 3.
- the first thin film transistor 309 and the second thin film transistor 308 are placed on the same layer.
- the first thin film transistor 309 is disposed on one side of the second thin film transistor 308, and the first active layer 310 of the first thin film transistor 309 and the second active layer 306 of the second thin film transistor 308 can be disposed on the same side. layer.
- the first active layer 310 and the second active layer 306 are both disposed on the first buffer layer 302.
- the source/drain metal layer 312 of the first thin film transistor 309 and the source/drain metal layer 311 of the second thin film transistor 308 can be disposed on the same layer, such as both are disposed on the first interlayer dielectric layer 304, and, The first gate 313 and the second gate 314 are disposed on the same layer.
- the first gate 313 and the second gate 314 are both disposed on the first gate insulating layer 303 .
- the first thin film transistor 309 can be electrically connected to the second thin film transistor 308 to achieve signal transmission.
- the first thin film transistor 309 and the second thin film transistor 308 can be thin film transistors with different performance.
- the carrier mobility inside the first thin film transistor 309 is greater than the carrier mobility inside the second thin film transistor 308 .
- the first thin film transistor 309 and the second thin film transistor 308 are both polysilicon thin film transistors.
- Figure 15 is a schematic diagram of the film structure of another semiconductor device provided by an embodiment of the present application. Specifically, a first thin film transistor 309 and a second thin film transistor 308 are provided in the semiconductor device. The active layer 509 of the first thin film transistor 309 is disposed on the buffer layer 702 , and at the same time, the gate electrode of the first thin film transistor 309 and the gate electrode of the second thin film transistor 308 are both disposed on the gate insulating layer 703 .
- the source/drain metal layer 510 of the first thin film transistor 309 and the source/drain metal layer 610 of the second thin film transistor 308 are both disposed on the passivation layer 705 .
- the active layer 609 of the second thin film transistor 308 is disposed on the passivation layer 705, and the source/drain metal layer of the second thin film transistor 308 at least partially covers the active layer 609 and is connected with the passivation layer 705.
- the active layer 609 is electrically connected.
- the source/drain metal layer 610 of the second thin film transistor overlaps both edges of the active layer 609 . Thereby, the thickness of the second thin film transistor 308 is further reduced, and the thickness of the panel is reduced.
- FIG. 16 is a film layer structure of yet another semiconductor device provided by an embodiment of the present application.
- the first thin film transistor 309 and the second thin film transistor 308 are respectively provided on different layers.
- the source/drain metal layer 510 of the first thin film transistor 309 is disposed on the interlayer dielectric layer 704
- the passivation layer 705 is disposed on the interlayer dielectric layer 704, and the passivation layer 705 covers the source/drain.
- Metal layer 510 is disposed on the interlayer dielectric layer 704
- the passivation layer 705 covers the source/drain.
- Metal layer 510 is a film layer structure of yet another semiconductor device provided by an embodiment of the present application.
- the gate electrode 620 of the second thin film transistor 308 is disposed on the passivation layer 705, and the gate insulating layer 703 is disposed on the passivation layer 705 and completely covers the gate electrode 620.
- the active layer 609 is disposed on the gate insulating layer 703
- the source/drain metal layer 610 of the second thin film transistor 308 is disposed on the gate insulating layer 703 .
- the source/drain metal layer of the second thin film transistor 308 at least partially covers the active layer 609 and is electrically connected to the active layer 609 .
- the source/drain metal layer 610 of the second thin film transistor overlaps both edges of the active layer 609 .
- the first thin film transistor 309 and the second thin film transistor 308 form a stacked structure.
- the first thin film transistor 309 may be a low-temperature polysilicon thin film transistor
- the second thin film transistor may be a metal oxide thin film transistor.
- Figure 5 is a schematic plan layout diagram of an integrated circuit corresponding to an insulating substrate provided in an embodiment of the present application.
- a plurality of different types of thin film transistors are arranged in different areas of the base layer.
- an oxide thin film transistor is arranged in area 502.
- the oxide thin film transistor is prepared through an oxide thin film transistor preparation process.
- a low-temperature polysilicon thin film transistor is provided in area 503.
- an amorphous silicon thin film transistor is provided in the region 504 and a metal oxide thin film transistor is provided in the region 505 .
- each integrated circuit when different integrated circuits are provided, each integrated circuit can be provided on the same side of the insulating base layer, or on both sides of the insulating base layer. At the same time, when setting, the integrated circuits can also be stacked. Thereby further improving the internal structure of the device.
- the above different types of thin film transistors when arranging the above different types of thin film transistors, they can be selected according to the functions of the memory integrated circuit. If the corresponding integrated circuit requires low leakage current, metal oxide thin film transistors can be selected. If the corresponding integrated circuit requires larger thrust, low-temperature polysilicon thin film transistors can be selected and packaged. Thereby effectively improving the working performance of the prepared integrated circuit.
- Figures 6-9 are schematic diagrams of the arrangement structures of different integrated circuits provided by embodiments of the present application.
- preparation of a sensor device is taken as an example for explanation.
- the sensor device includes multiple integrated circuits with different functions.
- the sensor device can be composed of a storage integrated circuit, a digital-to-analog conversion integrated circuit, a power drive integrated circuit and a low-pass control integrated circuit, and is combined with a first sensing module.
- the second integrated circuit 604 is a storage integrated circuit
- the first integrated circuit 605 is a digital-to-analog conversion integrated circuit
- the third integrated circuit 606 is a power driving integrated circuit
- the fourth integrated circuit 607 is a low-pass control integrated circuit.
- the above-mentioned integrated circuits can also be replaced by integrated circuits with other functions, which will not be described again here.
- the sensing unit 603 is a light sensing unit as an example for description.
- the second integrated circuit 604, the first integrated circuit 605, the third integrated circuit 606, and the fourth integrated circuit 607 are all arranged using the first base layer 108 as a base and are arranged on the first insulating substrate. of the same side.
- the corresponding thin film transistors in each integrated circuit can be stacked.
- the sensing unit 603 is provided on the buffer layer 602, and the buffer layer 602 is provided on other integrated circuits.
- the sensing unit 603 and other integrated circuits form a stacked structure.
- the above-mentioned different integrated circuits are arranged on both sides of the first base layer 108. That is, the sensing unit 603 and the corresponding thin film transistors of other integrated circuits are respectively disposed on both sides of the first base layer 108 .
- the sensing unit 603 is disposed on the surface of the first base layer
- the second integrated circuit 604 the first integrated circuit 605, the third integrated circuit 606, and the fourth integrated circuit 607 are all disposed on the back side of the first base layer.
- the architecture of the integrated circuit can be further improved to improve its working performance.
- the first base layer 108 adopts a two-layer stacked structure.
- the second integrated circuit 604, the first integrated circuit 605, the third integrated circuit 606, and the fourth integrated circuit 607 are arranged on the same base layer.
- the sensing unit 603 is arranged on another base layer, and the sensing unit is arranged correspondingly. on top of other integrated circuits to form a multi-layer stack.
- the sensing unit 603 can be bonded through corresponding via holes, or connected to other integrated circuits through side bonding.
- the sensing unit is stacked with other integrated circuits. And are all disposed on the same first base layer 108 .
- Figures 10-13 are schematic diagrams of film layer structures corresponding to the arrangement structures of different semiconductor devices provided in embodiments of the present application. Among them, the film layer structures in Figures 10 to 13 correspond to the arrangement structures in Figures 6 to 9 in sequence.
- the semiconductor device includes a first base layer 108, a plurality of thin film transistors arrayed on the first base layer 108, and various dielectric layers.
- each dielectric layer includes: buffer layer 702, gate insulation layer 703, interlayer dielectric layer 704 and passivation layer 705.
- the buffer layer 702 is provided on the first base layer 108
- the gate insulating layer 703 is provided on the buffer layer 702
- the interlayer dielectric layer 704 is provided on the gate insulating layer 703
- the passivation layer 705 is provided between the layers. on the dielectric layer 704.
- the first base layer 108 is an insulating substrate.
- the multiple thin film transistors are provided in the semiconductor device, and the multiple thin film transistors can correspond to different integrated circuits.
- the first integrated circuit includes a first thin film transistor 721, and the second integrated circuit includes a second thin film transistor 722.
- a third thin film transistor 723 is included in the third integrated circuit.
- each thin film transistor is provided with an active layer, a gate electrode, and a source/drain metal layer. The specific structure is as shown in the figure, and will not be described again here.
- the semiconductor device further includes a first sensing module 706.
- the first sensing module is a sensing unit, such as a light sensing unit.
- the first sensing module 706 is disposed on the passivation layer 705 and is electrically connected to the third thin film transistor 723 .
- the first sensing module 706 includes a first sensing electrode 72 , a second sensing electrode 73 , a connection electrode layer 74 and a reinforcement layer 71 .
- the first sensing electrode 72, the second sensing electrode 73, and the connection electrode layer 74 are stacked, and the connection electrode layer 74 is provided on the passivation layer 705.
- the connection electrode layer 74 is connected to the third thin film transistor through a via hole.
- the source/drain metal layers of 723 are electrically connected.
- the reinforcement layer 71 is arranged around the first sensing electrode, the second sensing electrode and the connection electrode layer, and wraps them.
- the light enhancement layer When external light enters the inside of the film layer, the light enhancement layer further increases the amount of light it receives and improves its photosensitive effect.
- the above-mentioned thin film transistors may be of different types.
- the first thin film transistor 721 and the third thin film transistor 723 are both low-temperature polysilicon thin film transistors
- the second thin film transistor is a metal oxide thin film transistor, such as A gallium indium tin oxide thin film transistor is used as an example for illustration.
- the mobility of the active layer of the first thin film transistor 721 is greater than the mobility of the active layer of the second thin film transistor 722 .
- the performance of the integrated circuit is improved by arranging different types of thin film transistors in the TFT base.
- multiple thin film transistors are arranged in the same layer and are arranged on the same side of the insulating substrate.
- the active layer of the first thin film transistor 721 and the active layer of the third thin film transistor are arranged in the same layer, and both are arranged on the buffer layer 702.
- the gate electrode of the first thin film transistor 721 is arranged on the buffer layer 702. between the active layer and the source/drain metal layer, thereby forming a top gate structure
- the gate electrode of the second thin film transistor 722 is disposed on the corresponding film layer below the active layer, thereby forming Bottom gate structure.
- the source/drain metal layer of the first thin film transistor 721 and the source/drain metal layer of the second thin film transistor 722 are arranged on the same layer, for example, they are both arranged on the interlayer dielectric layer 704, and the first thin film transistor 722 is arranged on the same layer.
- the gate electrode of the transistor 721 and the gate electrode of the second thin film transistor 722 are arranged in the same layer, for example, they are both arranged on the gate insulating layer 703 .
- the source/drain metal layer of the second thin film transistor 722 is at least partially disposed on the surface of the active layer of the second thin film transistor.
- the integrated circuits corresponding to each of the above-mentioned thin film transistors are arranged on the same side of the insulating substrate layer.
- the first sensing module 706 is disposed on the third thin film transistor 723 and is disposed on the same side as each integrated circuit.
- the first sensing module 706 and each thin film transistor are disposed on both sides of the first base layer 108 , thereby forming a double-sided structure.
- the first thin film transistor 721 , the second thin film transistor 722 , and the third thin film transistor 723 are all disposed on the same side of the first base layer, and the first sensing module 706 is disposed on the other side of the first base layer 108 .
- the first sensing module 706 is electrically connected to the third thin film transistor 723 through the corresponding via structure. For example, it is electrically connected to the drain of the third thin film transistor 723 .
- the thin film transistors in the optical sensor integrated circuit are arranged in a stacked structure. That is, the first thin film transistor 721 and the second thin film transistor 722 are arranged on the same first base layer 108, and the third thin film transistor 723 corresponding to the first sensing module 706 is arranged on another first base layer 108.
- the two first base layers 108 The stacked arrangement can further reduce the area of the integrated circuit and improve the performance of the integrated circuit.
- a stacked structure is also used in Figure 13.
- the first thin film transistor 721 and the third thin film transistor 723 corresponding to the first sensing module 706 are located in the same layer, and the second thin film transistor 722 is located in the film layer below it.
- the active layers of the first thin film transistor 721 and the third thin film transistor 723 are both disposed on the gate insulating layer, and the gate insulating layer is disposed on the gate of the second thin film transistor and completely covers the third thin film transistor.
- the first sensing module 706 integrated circuit is also used in Figure 13.
- the corresponding signal line connections can be connected through metal lines and via holes.
- the connections can be made through the sides or bottom.
- the connection is made in a binding manner, and the connection line and the first base layer are encapsulated, and finally the integrated circuit provided in the embodiment of the present application is formed.
- embodiments of the present application also provide an electronic device, which includes the semiconductor device provided in the embodiments of the present application.
- a plurality of first integrated circuits and second integrated circuits are provided in the semiconductor device, and the mobility of the thin film transistors in the first integrated circuit is greater than the mobility of the thin film transistors in the second integrated circuit.
- the semiconductor devices and electronic devices provided in the embodiments of the present application can be used in different devices, such as different control and display devices. Specifically, it can be mobile phones, computers, drives, power supply mechanisms, vehicle-mounted devices, and any other products or components with drive control functions. There are no specific restrictions on the specific types.
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Abstract
本发明实施例提供一种半导体器件、传感器器件及电子设备。半导体器件包括设置在绝缘衬底上的第一集成电路和第二集成电路,第一集成电路包括第一薄膜晶体管,第二集成电路包括第二薄膜晶体管,第一薄膜晶体管的迁移率大于第二薄膜晶体管的迁移率。将集成电路制备在绝缘衬底上,从而降低制造成本。
Description
本发明涉及显示面板的制造技术领域,尤其涉及一种半导体器件、传感器器件及电子设备。
随着半导体制备技术的不断发展,计算机集成控制***逐渐应用到多种领域之中,如智能汽车等各式各样的机器上均搭载有用以控制此器件的半导体器件(IC)。
现有技术中,在进行制备半导体器件时,通常将半导体器件制备在硅基衬底上,形成硅基芯片。因此,该硅基芯片是一种在硅基底上设置多个叠层设置的半导体膜、导电膜以及绝缘膜而构成的电路组件。其通过将众多的零部件集成在该硅基衬底上,以实现半导体器件的小型化、轻量化以及集成化的目的。但是,相较于其他制备材料而言,该单晶硅衬底所形成的载体其制备成本较高,并且集成化高,生成工艺复杂。同时,随着半导体器件使用需求的进一步扩大,其硅基材料的高成本将会进一步制约半导体器件的供给,不利于制造成本的控制以及半导体行业的发展,亟需寻求一种硅基替代材料,以及器件的制备工艺,以降低器件的制造成本并提高器件的综合性能。
因此需要对现有技术中的问题提出解决方法。
综上所述,现有技术中,在制备半导体器件时,该半导体器件的制造成本较高,工艺复杂,不利于半导体器件的大量供给,不利于半导体行业的进一步发展。
为解决上述问题,本发明实施例提供一种半导体器件、传感器器件及电子设备,以有效的改善半导体器件的制备工艺以及生产成本,并提高器件的综合性能。
为解决上述技术问题,本发明提供一种半导体器件,包括:
设置于绝缘衬底之上的第一集成电路,所述第一集成电路包括第一薄膜晶体管;
设置于所述绝缘衬底之上的第二集成电路,所述第二集成电路包括第二薄膜晶体管;
其中,所述第一薄膜晶体管有源层内载流子的迁移率大于所述第二薄膜晶体管有源层内载流子的迁移率。
根据本发明一实施例,沿所述第一薄膜晶体管以及所述第二薄膜晶体管对应的沟道区的长度方向上,所述第一薄膜晶体管有源层中的晶粒的平均尺寸,大于所述第二薄膜晶体管有源层中的晶粒的平均尺寸。
根据本发明一实施例,所述第一薄膜晶体管有源层中的晶粒包括第一方向上的第一边界,以及第二方向上的第二边界;
其中,所述第一方向与所述沟道区的长度方向相同,所述第二方向与所述沟道区的长度方向垂直,且所述第一边界的长度大于所述第二边界的长度。
根据本发明一实施例,所述第一薄膜晶体管的有源层与所述第二薄膜晶体管的有源层为相同的材料,且所述第一薄膜晶体管的有源层与所述第二薄膜晶体管的有源层同层设置、所述第一薄膜晶体管的栅极与所述第二薄膜晶体管的栅极同层设置、所述第一薄膜晶体管的源/漏金属层与所述第二薄膜晶体管的源/漏金属层同层设置。
根据本发明一实施例,所述第一薄膜晶体管的栅极绝缘设置在所述第一薄膜晶体管的有源层上,所述第一薄膜晶体管的源/漏金属层绝缘设置在所述栅极上,且所述第二薄膜晶体管的有源层绝缘设置在所述第一薄膜晶体管的源/漏金属层上,所述第二薄膜晶体管的栅极绝缘设置在所述第二薄膜晶体管的有源层上。
根据本发明一实施例,所述第一薄膜晶体管包括低温多晶硅薄膜晶体管,所述第二薄膜晶体管包括金属氧化物薄膜晶体管;
其中,所述第一薄膜晶体管的有源层设置在所述绝缘衬底上,所述第一薄膜晶体管的栅极绝缘设置在所述第一薄膜晶体管的有源层上,所述第二薄膜晶体管的栅极与所述第一薄膜晶体管的栅极同层设置。
根据本发明一实施例,还包括设置在所述第一薄膜晶体管的栅极与所述第二薄膜晶体管的栅极上的栅极绝缘层,所述第二薄膜晶体管的有源层设置在所述栅极绝缘层上,所述第一薄膜晶体管的源/漏金属层与所述第二薄膜晶体管的源/漏金属层同层设置在所述栅极绝缘层上。
根据本发明一实施例,所述第二薄膜晶体管的源/漏金属层至少部分设置在所述第二薄膜晶体管的有源层的表面,并与所述第二薄膜晶体管的有源层电连接。
根据本发明一实施例,所述第一薄膜晶体管和所述第二薄膜晶体管的类型不同,所述第二薄膜晶体管设置在所述第一薄膜晶体管上,且所述半导体器件还包括设置在所述第一薄膜晶体管和所述第二薄膜晶体管之间的钝化层。
根据本发明一实施例,所述半导体器件还包括第二栅极绝缘层,所述第二薄膜晶体管的栅极设置在所述钝化层上,所述第二栅极绝缘层设置在所述钝化层上,且所述第二薄膜晶体管的有源层设置在所述第二栅极绝缘层上,所述第二薄膜晶体管的源/漏金属层设置在所述第二栅极绝缘层上;
其中,所述第二薄膜晶体管的源/漏金属层至少部分设置在所述第二薄膜晶体管的有源层的表面,并与所述第二薄膜晶体管的有源层电连接。
根据本发明一实施例,所述第一集成电路包括逻辑控制集成电路、低通控制集成电路以及数模转换集成电路中的任意一种,所述第二集成电路包括存储集成电路以及运放集成电路中的任意一种。
根据本发明实施例的第二方面,还提供一种传感器器件,包括感应区域以及设置在所述感应区域一侧的***电路区域,包括:
绝缘衬底;
感应单元,所述感应单元设置在所述感应区域对应的所述绝缘衬底上;以及,
集成电路,至少部分所述集成电路设置在所述***电路区域对应的所述绝缘衬底上,且所述集成电路用以控制所述感应单元;
其中,所述集成电路包括:
第一集成电路,所述第一集成电路包括第一薄膜晶体管;以及,
第二集成电路,所述第二集成电路包括第二薄膜晶体管;
其中,所述第一薄膜晶体管有源层内载流子的迁移率大于所述第二薄膜晶体管有源层内载流子的迁移率。
根据本发明一实施例,还包括位于所述感应区域的:
多条栅极信号线;
多条数据信号线,所述数据信号线与所述栅极信号线相交并形成多个交叉区域,每个所述交叉区域内设置有至少一个所述感应单元,所述感应单元包括第一传感模块;
其中,所述数据信号线与所述第一传感模块电连接,且所述数据信号线与所述***电路区域的所述集成电路电连接。
根据本发明一实施例,所述数据信号线与所述第一集成电路电连接,所述第二集成电路与所述第一集成电路电连接,且所述第一集成电路电连接于所述感应单元与所述第二集成电路之间。
根据本发明一实施例,所述第一集成电路包括低通控制集成电路、模拟控制集成电路、以及数模转换集成电路中的至少一者,所述第二集成电路包括存储集成电路。
根据本发明一实施例,所述第一集成电路包括与所述数据信号线电连接的低通控制集成电路、与所述低通控制集成电路电连接的模拟控制集成电路、以及与所述模拟控制集成电路电连接的数模转换集成电路,所述第二集成电路包括存储集成电路;所述低通控制集成电路电连接于所述感应单元与所述模拟控制集成电路之间,所述数模转换集成电路电连接于所述模拟控制集成电路与所述存储集成电路之间。
根据本发明一实施例,所述第一薄膜晶体管的有源层包括低温多晶硅,所述第二薄膜晶体管的有缘层包括金属氧化物;所述第一传感模块的有源层包括非晶硅。
根据本发明一实施例,所述第一集成电路和所述第二集成电路均设置在所述绝缘衬底的同一侧,且所述第一传感模块设置在所述第一集成电路的远离所述绝缘衬底的一侧,所述第一传感模块与所述第一薄膜晶体管电连接。
根据本发明一实施例,所述第一集成电路以及所述第二集成电路均设置在所述绝缘衬底的第一面上,所述第一传感模块设置在所述绝缘衬底与所述第一面相对的第二面上;
其中,所述第一传感模块通过设置在所述绝缘衬底上的过孔与所述第一薄膜晶体管电连接。
根据本发明实施例的第三方面,提供一种电子设备,包括本申请实施例中提供的半导体器件或者传感器器件。
综上所述,本发明实施例的有益效果为:
本发明实施例提供一种半导体器件、传感器器件及电子设备。该半导体器件包括第一集成电路以及第二集成电路,该第一集成电路包括设置在绝缘衬底上的第一薄膜晶体管和第二薄膜晶体管,且该第一薄膜晶体管有源层内载流子的迁移率大于第二薄膜晶体管有源层内载流子的迁移率。本申请实施例通过将集成电路中的薄膜晶体管器件直接设置在绝缘衬底上,且其内部对应的薄膜晶体管设置为不同的迁移率,采用低成本的绝缘材料替代高成本的半导体材料,从而降低制造成本,并优化器件性能。
图1A为本申请实施例提供的一种集成电路的简化示意图;
图1B为本申请实施例提供的该集成电路对应的膜层结构示意图;
图2为本申请实施例提供的传感器器件的结构示意图;
图3为本申请实施例提供的半导体器件的膜层结构示意图;
图4为本申请实施例中提供的另一半导体器件的膜层结构示意图;
图5为本申请实施例中提供的绝缘衬底对应的集成电路的平面布局示意图;
图6-图9为本申请实施例提供的不同的集成电路的排布结构示意图;
图10-图13为本申请实施例中提供的不同半导体器件的排布结构对应的膜层结构示意图;
图14为本申请实施例提供的有源层内晶粒的结构示意图;
图15为本申请实施例提供的另一半导体器件的膜层结构示意图;
图16为本申请实施例提供的再一半导体器件的膜层结构。
以下各实施例的说明是参考附加的图式,用以例示本揭示可用以实施的特定实施例。
随着数字化及智能化的不断深入,各半导体器件中所需要的集成电路的数量也越来越多。通过多个集成电路以实现对器件的有效控制,并提高器件性能。但是,在制备集成电路时,其通常将多个电子组件集成在硅基晶圆衬底上,而该硅基晶圆的成本较高,且制备工艺复杂,不利于集成电路技术的进一步提高。
本申请实施例提供一种半导体器件,以有效的改善集成电路的制备工艺,并有效的降低集成电路的生产成本。
如图1A所示,图1A为本申请实施例提供的一种集成电路的简化示意图。以下实施例中,该集成电路以车载控制***中的一控制集成电路为例进行说明。其中,该集成电路还可应用于其他控制器件中,这里不再赘述。具体的,该车载控制器件可为触控显示面板设备。在该触控显示面板内,设置有多个控制器件,并且每个控制器件中均配置有集成电路,同时,在该集成电路上集成有多个控制单元或控制模块。
具体的,本申请实施例中,该触控显示面板内包括承载电路板100,同时,在该承载电路板100上设置有多个芯片集成区域101。在每个芯片集成区域101内设置有对应的集成电路。
详见图1A中的局部放大示意图,本申请实施例中,在该芯片集成区域101内设置有多个集成电路。如第一集成电路104和第二集成电路105。其中,第一集成电路104和第二集成电路105均设置在该承载电路板100上,且第一集成电路104和第二集成电路105之间机械连接或者电性连接。当两者需要共同作用时,采用电性连接,当两者为单独作用时,可采用机械绝缘连接。
本申请实施例中,该第一集成电路104和第二集成电路105可为功能相同的集成电路或者功能不同的集成电路,如第一集成电路104为数据控制集成电路,第二集成电路105为信号控制集成电路,通过该第一集成电路104和第二集成电路105实现对触控显示面板的控制及操作等功能。
进一步的,在该第一集成电路104和第二集成电路105中,其第一集成电路104包括第一基层108,该第二集成电路105包括第二基层109。即制备该第一集成电路104的基板为第一基层108,制备该第二集成电路105的基板为第二基层109。
本申请实施例中,该第一基层108与第二基层109均为绝缘层衬底,优选的,该第一基层108和第二基层109均为玻璃衬底。通过将现有技术中集成电路中的硅基底设置为本申请实施例中的玻璃衬底,以有效的降低集成电路的制造成本,并改善其排布面积。
本申请实施例中,在该芯片集成区域101内,还设置有第三集成电路102以及第四集成电路103。其中,该第三集成电路102和第四集成电路103与第一集成电路104和第二集成电路105设置在不同的位置处。如第三集成电路102和第四集成电路103设置在第一集成电路104的不同行中。同时,该第三集成电路102和第四集成电路103可为不同功能的集成电路,具体的可根据实际产品的控制需求进行设置。
进一步的上述各集成电路可包括存储集成电路、逻辑控制集成电路、数模转换集成电路、模拟控制集成电路、低通控制集成电路以及传感器集成电路。根据各不同集成电路功能的不同,在进行设置时,较高性能的集成电路内对应的薄膜晶体管设置为高迁移率的薄膜晶体管,如逻辑控制集成电路、低通控制集成电路、传感集成电路以及数模转换集成电路设置为高迁移率的薄膜晶体管,而存储集成电路或者较低性能的集成电路设置为低迁移率的薄膜晶体管。从而保证控制器件的正常工作。
详见图1B所示,图1B为本申请实施例提供的该集成电路对应的膜层结构示意图。本申请实施例中,该第一集成电路104包括第一基层108、介质层110以及设置在该介质层110内的第一薄膜晶体管309,该第一薄膜晶体管309设置在该第一基层108上,该介质层110设置在该第一基层108上,并覆盖对应的薄膜晶体管。该第二集成电路105包括第二基层109、介质层110以及设置在该介质层110内的第二薄膜晶体管308。
本申请实施例中,在制备介质层110内的薄膜晶体管时,每一集成电路内可设置多个薄膜晶体管。其中,各薄膜晶体管可均相同或者不同。
以下实施例中,该第一集成电路中,包括多个第一薄膜晶体管309,在该第二集成电路中,包括多个第二薄膜晶体管308。其中,多个薄膜晶体管可分别阵列的设置在对应的绝缘衬底上。
进一步的,该第一薄膜晶体管309有源层内载流子的迁移率大于第二薄膜晶体管308有源层内载流子的迁移率。
本申请实施例中,该第一薄膜晶体管以及第二薄膜晶体管可同层设置,或者层叠设置。其中,该第一薄膜晶体管有源层的沟道区的长度,可大于第二薄膜晶体管有源层的沟道区的长度,从而实现器件不同规格的大小。在进行设置时,可根据对应的集成电路的性能以及规格来进行设定,这里不再赘述。
优选的,在设置不同薄膜晶体管的有源层内的晶粒时,如设置该有源层中沟道区内的晶粒。本申请实施例中,由于该第一薄膜晶体管的迁移率大于第二薄膜晶体管的迁移率,因此,该第一薄膜晶体管中沟道区内晶粒的平均尺寸,大于第二薄膜晶体管中沟道区内晶粒的平均尺寸。
优选的,如图14所示,图14为本申请实施例提供的有源层内晶粒的结构示意图。在第一薄膜晶体管的第一有源层310的沟道区444内包括第一晶粒450。该第一晶粒450具有第一方向X和第二方向Y。其中,该第一方向X可与沟道区444的延伸方向相同,如与第一有源层的长边平行,该第二方向Y可与沟道区相垂直,如为竖直方向。本申请实施例中,在该第一方向X上,该第一晶粒450具有第一边界,在第二方向Y上,该第一晶粒具有第二边界,其中,该第一边界的长度大于第二边界的长度,从而能使得载流子能尽可能的在整个晶粒内部移动,进而提高其迁移率。
进一步的,详见图1B,在该集成电路中还包括第一走线层1082和第二走线层1092。其中,第一走线层1082设置在该第一薄膜晶体管309上,第二走线层1092设置在第二薄膜晶体管308上。各走线层可通过对应的金属走线与对应的薄膜晶体管电性连接,并最终形成本申请实施例中提供的集成电路。
本申请实施例中,上述第一集成电路和第二集成电路还可层叠设置,层叠设置时,该第一集成电路可与第二集成电路绑定。
具体的,本申请实施例中,在制备形成第一集成电路104或第二集成电路105时,在第一基层108或第二基层109上制备薄膜晶体管,并继续在该薄膜晶体管上制备其他走线层,并对每个集成电路进行封装。
具体的,详见图1A,该第一基层108设置在第一区域20对应位置处,第二基层109设置在第二区域21对应的位置处。其中,第一区域20可设置在第二区域21的一侧。同时,该第一区域20和第二区域21内设置的第一基层108和第二基层109可为相同的大小,或者根据对应的集成电路的大小设置为不同的规格,这里不再赘述。
详见图2所示,图2为本申请实施例提供的传感器器件的结构示意图。在该半导体器件内设置有多个本申请实施例提供的集成电路。本申请实施例中,该半导体器件以传感器器件为例进行说明。
具体的,该传感器器件包括感应区域23以及设置在感应区域23一侧的***电路区域24。其中,在感应区域23内,包括多条栅极信号线279、多条数据信号线278,栅极信号线279与数据信号线278相交叉,并形成多个交叉区域,且在每个交叉区域内设置有至少一个感应单元。本申请实施例中,该感应单元以第一传感模块210为例进行说明。该数据信号线278与第一传感模块210电性连接,且数据信号线与***电路区域24中的集成电路电连接。通过集成电路以对第一传感模块210进行控制。本申请实施例中,该半导体器件还可为其他器件,这里不再赘述。
本申请实施例中,在该***电路区域内,设置有多个不同的集成电路,多个集成电路均设置在绝缘衬底上,如第一集成电路和第二集成电路。具体的,数据信号线278与第一集成电路电连接,第二集成电路与第一集成电路电连接,且第一集成电路电连接于第一传感模块210与第二集成电路之间。
各集成电路可实现不同的控制功能。本申请实施例中,该第一集成电路可包括多个逻辑控制集成电路206、低通控制集成电路205以及数模转换集成电路203、模拟控制集成电路204,该第二集成电路可包括存储集成电路202以及运放集成电路中的至少一种。且该第二集成电路设置为低迁移率的薄膜晶体管。其中,该第一集成电路内对应的第一薄膜晶体管为低温多晶硅薄膜晶体管,该第二集成电路内对应的第二薄膜晶体管为金属氧化物薄膜晶体管。
具体的,数据信号线278与低通控制集成电路205电连接、模拟控制集成电路204与低通控制集成电路205电连接、数模转换集成电路203与模拟控制集成电路204电连接。同时,该低通控制集成电路205电连接于第一传感模块210与模拟控制集成电路204之间,且数模转换集成电路203电连接于模拟控制集成电路204与存储集成电路202之间。
本申请实施例中,在设置上述各个集成电路时,直接绝缘衬底上蚀刻并制造形成本申请实施例中提供的集成电路。在每个集成电路内包括多个薄膜晶体管,其中,各集成电路内的薄膜晶体管以本申请实施例中提供的结构进行设置,从而有效的降低其制备成本,并改善其制备工艺以及工作性能。
同时,在该传感器器件内还设置有多个导电走线,多个导电走线从感应区域到***电路区域设置,从而实现控制信号的传输。
本申请实施例中,在该传感器器件内还包括电平转换模块和移位寄存器等,而该电平转换模块和移位寄存器需要具有较高的性能。因此,电平转换模块和移位寄存器对应的集成电路中的薄膜晶体管可采用低温多晶硅薄膜晶体管,从而保证其具有较高的迁移率,这里不再赘述。
本申请实施例中,第一集成电路和第二集成电路可均设置在所述绝缘衬底的同一侧。且第一传感模块210设置在第一集成电路远离所述绝缘衬底的一侧,并与第一集成电路内的第一薄膜晶体管电连接。
进一步的,第一集成电路以及第二集成电路均设置在绝缘衬底的第一面上,且第一传感模块设置在绝缘衬底与第一面相对的第二面上。
详见图3所示,图3为本申请实施例提供的半导体器件的膜层结构示意图。具体的,该半导体器件内包括第一薄膜晶体管309和第二薄膜晶体管308。第一薄膜晶体管309设置在第二薄膜晶体管308的一侧。且该第一薄膜晶体管309和第二薄膜晶体管308层叠设置,从而减小该集成电路的面积。
其中,该第一基层108为玻璃层,在该第一基层108上还设置有遮光层,同时该缓冲层302完全覆盖遮光层。进一步的,在第一薄膜晶体管309中还设置有第一有源层310、第一栅极绝缘层303、第一栅极313以及第一层间介质层304。
本申请实施例中,该第一有源层310设置在第一缓冲层302上,第一栅极绝缘层303设置在第一缓冲层302上,且第一栅极绝缘层303完全覆盖第一有源层310。同时,第一栅极313设置在第一栅极绝缘层303上,第一层间介质层304设置在第一栅极313上,且第一源/漏金属层312设置在第一层间介质层304上。且该第一源/漏金属层312通过对应的过孔与第一有源层310电性连接。
进一步的,该第二缓冲层305设置在第一薄膜晶体管309之上,且第二有源层306设置在第二缓冲层305上,第二栅极314设置在第二有源层306之上,同时,第二层间介质层307设置在第二有源层306之上,第二源/漏金属层311设置在给第二层间介质层307上,且第二源/漏金属层311通过对应的过孔与第二有源层306电性连接。
本申请实施例中,该第一薄膜晶体管309和第二薄膜晶体管可均设置为低温多晶硅薄膜晶体管,且该第一薄膜晶体管309内部的载流子迁移率大于第二薄膜晶体管308内部载流子的迁移率。
具体的,该第一有源层310的沟道区内对应的材料的晶粒平均尺寸大于第二有源层306的沟道区内对应的材料的晶粒平均尺寸。从而保证该第一薄膜晶体管的迁移率大于第二薄膜晶体管的迁移率,并使不同的半导体器件形成的集成电路具有不同的性能。并保证不同性能的集成电路能在高速或者低速的信号的作用下保持较高的性能。从而提高该集成电路的工作性能。
本申请实施例中,该第一基层内的第一薄膜晶体管309在衬底上的正投影与第二薄膜晶体管308在衬底上的正投影不完全重合。
具体的,在该半导体器件上还设置其他组件,组件可对应的与该各薄膜晶体管电连接,以实现信号的传输。封装完成后,形成具有绝缘基层的集成电路。
进一步的,如4所示,图4为本申请实施例中提供的另一半导体器件的膜层结构示意图。结合图3中的膜层结构示意图。本申请实施例中,在设置该半导体器件对应的集成电路时,该第一薄膜晶体管309和第二薄膜晶体管308同层设置。
具体的,第一薄膜晶体管309设置在第二薄膜晶体管308的一侧,且该第一薄膜晶体管309的第一有源层310和第二薄膜晶体管308的第二有源层306可设置在同一层上。具体的,第一有源层310和第二有源层306均设置在第一缓冲层302上。
同时,该第一薄膜晶体管309的源/漏金属层312可与第二薄膜晶体管308的源/漏金属层311设置在同一层上,如均设置在第一层间介质层304上,并且,将第一栅极313与第二栅极314设置在同一层上,如第一栅极313与第二栅极314均设置在第一栅极绝缘层303上。
本申请实施例中,该第一薄膜晶体管309可与第二薄膜晶体管308之间电性连接,从而实现信号的传输。同时,该第一薄膜晶体管309与第二薄膜晶体管308可为不同性能薄膜晶体管,如该第一薄膜晶体管309内部的载流子迁移率大于第二薄膜晶体管308内部载流子的迁移率。
具体的,该第一薄膜晶体管309和第二薄膜晶体管308均为多晶硅薄膜晶体管。
详见图15所示,图15为本申请实施例提供的另一半导体器件的膜层结构示意图。具体的,在该半导体器件内设置有第一薄膜晶体管309以及第二薄膜晶体管308。其中,该第一薄膜晶体管309的有源层509设置在缓冲层702上,同时,该第一薄膜晶体管309的栅极与第二薄膜晶体管308的栅极均设置在栅极绝缘层703上。
进一步的,该第一薄膜晶体管309的源/漏金属层510与第二薄膜晶体管308的源/漏金属层610均设置在钝化层705上。本申请实施例中,该第二薄膜晶体管308的有源层609设置在该钝化层705上,且该第二薄膜晶体管308的源/漏金属层至少部分覆盖该有源层609,并与该有源层609电性连接。如该第二薄膜晶体管的源/漏金属层610与有源层609的两侧边缘相搭接。从而进一步对该第二薄膜晶体管308的厚度进行减薄,并降低面板的厚度。
进一步的,如图16所示,图16为本申请实施例提供的再一半导体器件的膜层结构。结合图15中的结构,本申请实施例中,该第一薄膜晶体管309与第二薄膜晶体管308分别设置在不同层上。具体的,该第一薄膜晶体管309的源/漏金属层510设置在层间介质层704上,该钝化层705设置在层间介质层704上,同时该钝化层705覆盖该源/漏金属层510。
进一步的,该第二薄膜晶体管308的栅极620设置在钝化层705上,该栅极绝缘层703设置在该钝化层705上,并完全覆盖该栅极620。同时,该有源层609设置在该栅极绝缘层703上,该第二薄膜晶体管308的源/漏金属层610设置在栅极绝缘层703上。本申请实施例中,该第二薄膜晶体管308的源/漏金属层至少部分覆盖该有源层609,并与该有源层609电性连接。如该第二薄膜晶体管的源/漏金属层610与有源层609的两侧边缘相搭接。从而该第一薄膜晶体管309与第二薄膜晶体管308形成层叠结构。在图15及图16中,第一薄膜晶体管309可为低温多晶硅薄膜晶体管,第二薄膜晶体管可为金属氧化物薄膜晶体管。
详见图5所示,图5为本申请实施例中提供的绝缘衬底对应的集成电路的平面布局示意图。在该集成电路中,多个不同类型的薄膜晶体管设置在基层的不同区域内,具体的,在区域502中设置氧化物薄膜晶体管,该氧化物薄膜晶体管通过氧化物薄膜晶体管制备工艺制备得到,在区域503中设置低温多晶硅薄膜晶体管。或者在区域504中设置非晶硅薄膜晶体管,同时,在区域505内设置金属氧化物薄膜晶体管。
结合图2中的器件结构示意图,本申请实施例中,在设置不同的集成电路时,各集成电路可设置在绝缘基层的同一侧,或者该绝缘基层的两侧位置上。同时,在进行设置时,各集成电路之间还可层叠设置。从而对器件的内部结构进一步改善。
其中,在设置上述不同类型的薄膜晶体管时,可根据存储集成电路的功能进行选取。如对应的集成电路需要低漏电流,可选取为金属氧化物薄膜晶体管,对应的集成电路需要较大的推力,可选取为低温多晶硅薄膜晶体管,并进行封装。从而有效的提高制备得到的集成电路的工作性能。
进一步的,如图6-图9所示,图6-图9为本申请实施例提供的不同的集成电路的排布结构示意图。结合图2的结构示意图,本申请实施例中,以制备传感器器件为例进行说明。在该传感器器件中包括多个功能不同的集成电路。如该传感器器件可由存储集成电路、数模转换集成电路、电力驱动集成电路以及低通控制集成电路,并搭配第一传感模块所构成。
详见图6,在该第一基层108的不同区域内对应设置有不同的集成电路,如第一集成电路605、第二集成电路604、第三集成电路606、第四集成电路607以及感应单元603。具体的,该第二集成电路604为存储集成电路,第一集成电路605为数模转换集成电路,第三集成电路606为电力驱动集成电路,第四集成电路607为低通控制集成电路。优选的,上述各集成电路还可为替换为其他功能的集成电路,这里不再赘述。同时,该感应单元603为光感应单元为例进行说明。
本申请实施例中,第二集成电路604、第一集成电路605、第三集成电路606、第四集成电路607均以该第一基层108为基底进行设置,并设置在该第一绝缘衬底的同一侧。
本申请实施例中,各集成电路内对应的薄膜晶体管可叠层设置,具体的,感应单元603设置在缓冲层602上,且缓冲层602设置在其他集成电路上。从而使该感应单元603与其他集成电路形成层叠结构。
详见图7,结合图6中的结构,本申请实施例中,将上述不同的集成电路设置在该第一基层108的两侧。即感应单元603和其他集成电路对应的薄膜晶体管分别设置在第一基层108的两侧。如该感应单元603设置在第一基层的表面,而第二集成电路604、第一集成电路605、第三集成电路606、第四集成电路607均设置在第一基层的背面上。这样,相当于将不同的集成电路分别设置在第一基层的第一面上,以及与第一面相对的第二面上。从而进一步对集成电路的架构进行改善,以提高其工作性能。
详见图8所示,本申请实施例中,该第一基层108采用两层的叠构。如第二集成电路604、第一集成电路605、第三集成电路606、第四集成电路607设置在同一基层上,同时,感应单元603设置在另一基层上,并将该感应单元对应的设置在其他集成电路之上,从而形成多层叠构。此时,该感应单元603可通过对应过孔进行绑定,或者通过侧面绑定的方式,与其他集成电路进行连接。
以及图9,本申请实施例中,将该感应单元与其他集成电路进行层叠设置。并均设置在同一第一基层108之上。
进一步的,如图10-图13所示,图10-图13为本申请实施例中提供的不同半导体器件的排布结构对应的膜层结构示意图。其中,该图10-图13中的膜层结构依次对应图6-图9中的排布结构。
具体的,详见图10所示,该半导体器件包括第一基层108、阵列设置在第一基层108上的多个薄膜晶体管以及各介质层。具体的,各介质层包括:缓冲层702、栅极绝缘层703、层间介质层704以及钝化层705。
其中,该缓冲层702设置在第一基层108上,栅极绝缘层703设置在缓冲层702上,同时,层间介质层704设置在栅极绝缘层703上,钝化层705设置在层间介质层704上。本申请实施例中,该第一基层108为绝缘衬底。
同时,在该半导体器件内设置有多个薄膜晶体管,多个薄膜晶体管可对应不同的集成电路,如第一集成电路内包括第一薄膜晶体管721、第二集成电路内包括第二薄膜晶体管722,第三集成电路内包括第三薄膜晶体管723。其中,每个薄膜晶体管均对应设置有有源层、栅极以及源/漏金属层,具体结构如图所示,这里不在赘述。
本申请实施例中,该半导体器件还包括第一传感模块706。该第一传感模块为感应单元,如光感应单元。其中,该第一传感模块706设置在钝化层705上,并与第三薄膜晶体管723电性连接。
本申请实施例中,该第一传感模块706包括第一感应电极72、第二感应电极73、连接电极层74以及增强层71。具体的,该第一感应电极72、第二感应电极73、连接电极层74层叠设置,且该连接电极层74设置在钝化层705上,该连接电极层74通过过孔与第三薄膜晶体管723的源/漏金属层电性连接。
进一步的,该增强层71围绕第一感应电极、第二感应电极以及连接电极层设置,并将其包裹。当外界的光线进入膜层内部时,通过该光增强层进一步提高其接收的光量,并提高其感光效果。
进一步的,上述薄膜晶体管可为不同类型的,以下实施例中,该第一薄膜晶体管721和第三薄膜晶体管723均以低温多晶硅薄膜晶体管为例,第二薄膜晶体管以金属氧化物薄膜晶体管,如氧化镓铟锡薄膜晶体管为例进行说明。
详见如图10中,第一薄膜晶体管721的有源层的迁移率大于第二薄膜晶体管722的有源层的迁移率。从而通过在该TFT基内设置不同类型的薄膜晶体管以提高该集成电路的性能。
图10中,多个薄膜晶体管同层设置,并均设置在绝缘衬底的同一侧。具体的,该第一薄膜晶体管721的有源层与该第三薄膜晶体管的有源层同层设置,且均设置在缓冲层702上,同时,该第一薄膜晶体管721的栅极设置在其有源层与源/漏金属层之间,从而形成顶栅结构,而在第二薄膜晶体管722内,该第二薄膜晶体管722的栅极设置在其有源层下方对应膜层上,从而形成底栅结构。
本申请实施例中,该第一薄膜晶体管721的源/漏金属层与该第二薄膜晶体管722的源/漏金属层同层设置,如均设置层间介质层704上,且该第一薄膜晶体管721的栅极与该第二薄膜晶体管722的栅极同层设置,如均设置栅极绝缘层703上。且该第二薄膜晶体管722的源/漏金属层至少部分设置在该第二薄膜晶体管的有源层的表面。这样,上述各薄膜晶体管对应的集成电路均设置在绝缘衬底层的同一侧。同时,该第一传感模块706设置在该第三薄膜晶体管723上,并与各集成电路同侧设置。
而在图11中,该第一传感模块706与各薄膜晶体管设置在第一基层108的两侧,从而形成双面结构。
具体的,该第一薄膜晶体管721、第二薄膜晶体管722、第三薄膜晶体管723均设置在第一基层的同一侧,而该第一传感模块706设置在第一基层108的另一侧。同时,该第一传感模块706通过对应的过孔结构与该第三薄膜晶体管723电性连接。如与该第三薄膜晶体管723的漏极电性连接。
详见图12,本申请实施例中,该光学传感器集成电路内的薄膜晶体管设置为叠层结构。即第一薄膜晶体管721和第二薄膜晶体管722设置在同一第一基层108上,而第一传感模块706对应的第三薄膜晶体管723设置在另一第一基层108上,两第一基层108层叠设置,从而可进一步将该集成电路的面积减小,并提高集成电路的性能。
进一步的,如图13所示,图13中也采用叠层结构设置。具体的,第一薄膜晶体管721与第一传感模块706对应的第三薄膜晶体管723位于同一层中,而第二薄膜晶体管722位于其下方的膜层中。具体的,该第一薄膜晶体管721和第三薄膜晶体管723的有源层均设置在栅极绝缘层上,该栅极绝缘层设置在该第二薄膜晶体管的栅极上,并完全覆盖该第二薄膜晶体管的栅极。并最终形成搭配有第一传感模块
706的集成电路。
本申请实施例中,在该第一基层上设置上述叠层或者平铺结构时,对应的信号线连接可通过金属线以及过孔进行连接,同时,在进行连接时,可通过侧边或者底部绑定的方式进行连接,并对该连接线以及该第一基层进行封装,并最终形成本申请实施例中提供的集成电路。
其中,本申请实施例还提供一种电子设备,该电子设备包括本申请实施例中提供的半导体器件。且该半导体器件内设置有多个第一集成电路和第二集成电路,且该第一集成电路内薄膜晶体管的迁移率大于第二集成电路内的薄膜晶体管的迁移率。本申请实施例中提供的半导体器件以及电子设备可应用于不同的设备中,如不同的控制及显示设备中。具体的,可为手机、电脑、驱动器、电源机构、车载器件、等任何具有驱动控制功能的产品或部件,其具体类型不做具体限制。
综上所述,以上对本发明实施例所提供的一种半导体器件、传感器器件以及电子设备进行了详细介绍,本文中应用了具体个例对本发明的原理及实施方式进行了阐述,以上实施例的说明只是用于帮助理解本发明的技术方案及其核心思想;虽然本发明以优选实施例揭露如上,但上述优选实施例并非用以限制本发明,本领域的普通技术人员,在不脱离本发明的精神和范围内,均可作各种更动与润饰,因此本发明的保护范围以权利要求界定的范围为基准。
Claims (20)
- 一种半导体器件,包括:绝缘衬底;设置于所述绝缘衬底上的第一集成电路,所述第一集成电路包括第一薄膜晶体管;设置于所述绝缘衬底上的第二集成电路,所述第二集成电路包括第二薄膜晶体管;其中,所述第一薄膜晶体管有源层内载流子的迁移率大于所述第二薄膜晶体管有源层内载流子的迁移率。
- 根据权利要求1所述的半导体器件,其中沿所述第一薄膜晶体管以及所述第二薄膜晶体管对应的沟道区的长度方向上,所述第一薄膜晶体管有源层中的晶粒的平均尺寸,大于所述第二薄膜晶体管有源层中的晶粒的平均尺寸。
- 根据权利要求2所述的半导体器件,其中所述第一薄膜晶体管有源层中的晶粒包括第一方向上的第一边界,以及第二方向上的第二边界;其中,所述第一方向与所述沟道区的长度方向相同,所述第二方向与所述沟道区的长度方向垂直,且所述第一边界的长度大于所述第二边界的长度。
- 根据权利要求2所述的半导体器件,其中所述第一薄膜晶体管的有源层与所述第二薄膜晶体管的有源层为相同的材料,且所述第一薄膜晶体管的有源层与所述第二薄膜晶体管的有源层同层设置、所述第一薄膜晶体管的栅极与所述第二薄膜晶体管的栅极同层设置、所述第一薄膜晶体管的源/漏金属层与所述第二薄膜晶体管的源/漏金属层同层设置。
- 根据权利要求2所述的半导体器件,其中所述第一薄膜晶体管的栅极绝缘设置在所述第一薄膜晶体管的有源层上,所述第一薄膜晶体管的源/漏金属层绝缘设置在所述栅极上,且所述第二薄膜晶体管的有源层绝缘设置在所述第一薄膜晶体管的源/漏金属层上,所述第二薄膜晶体管的栅极绝缘设置在所述第二薄膜晶体管的有源层上。
- 根据权利要求1所述的半导体器件,其中所述第一薄膜晶体管包括低温多晶硅薄膜晶体管,所述第二薄膜晶体管包括金属氧化物薄膜晶体管;其中,所述第一薄膜晶体管的有源层设置在所述绝缘衬底上,所述第一薄膜晶体管的栅极绝缘设置在所述第一薄膜晶体管的有源层上,所述第二薄膜晶体管的栅极与所述第一薄膜晶体管的栅极同层设置。
- 根据权利要求6所述的半导体器件,还包括设置在所述第一薄膜晶体管的栅极与所述第二薄膜晶体管的栅极上的栅极绝缘层,所述第二薄膜晶体管的有源层设置在所述栅极绝缘层上,所述第一薄膜晶体管的源/漏金属层与所述第二薄膜晶体管的源/漏金属层同层设置在所述栅极绝缘层上。
- 根据权利要求6所述的半导体器件,其中所述第二薄膜晶体管的源/漏金属层至少部分设置在所述第二薄膜晶体管的有源层的表面,并与所述第二薄膜晶体管的有源层电连接。
- 根据权利要求2所述的半导体器件,其中所述第一薄膜晶体管和所述第二薄膜晶体管的类型不同,所述第二薄膜晶体管设置在所述第一薄膜晶体管上,且所述半导体器件还包括设置在所述第一薄膜晶体管和所述第二薄膜晶体管之间的钝化层。
- 根据权利要求9所述的半导体器件,其中所述半导体器件还包括第二栅极绝缘层,所述第二薄膜晶体管的栅极设置在所述钝化层上,所述第二栅极绝缘层设置在所述钝化层上,且所述第二薄膜晶体管的有源层设置在所述第二栅极绝缘层上,所述第二薄膜晶体管的源/漏金属层设置在所述第二栅极绝缘层上;其中,所述第二薄膜晶体管的源/漏金属层至少部分设置在所述第二薄膜晶体管的有源层的表面,并与所述第二薄膜晶体管的有源层电连接。
- 根据权利要求1所述的半导体器件,其中所述第一集成电路包括栅极驱动集成电路、逻辑控制集成电路、低通控制集成电路以及数模转换集成电路中的任意一种,所述第二集成电路包括存储集成电路以及运放集成电路中的任意一种。
- 一种传感器器件,包括感应区域以及设置在所述感应区域一侧的***电路区域,包括:绝缘衬底;感应单元,所述感应单元设置在所述感应区域对应的所述绝缘衬底上;以及,集成电路,至少部分所述集成电路设置在所述***电路区域对应的所述绝缘衬底上,且所述集成电路用以控制所述感应单元;其中,所述集成电路包括:第一集成电路,所述第一集成电路包括第一薄膜晶体管;以及,第二集成电路,所述第二集成电路包括第二薄膜晶体管;其中,所述第一薄膜晶体管有源层内载流子的迁移率大于所述第二薄膜晶体管有源层内载流子的迁移率。
- 根据权利要求12所述的传感器器件,其中还包括位于所述感应区域的:多条栅极信号线;多条数据信号线,所述数据信号线与所述栅极信号线相交并形成多个交叉区域,每个所述交叉区域内设置有至少一个所述感应单元,所述感应单元包括第一传感模块;其中,所述数据信号线与所述第一传感模块电连接,且所述数据信号线与所述***电路区域的所述集成电路电连接。
- 根据权利要求13所述的传感器器件,其中所述数据信号线与所述第一集成电路电连接,所述第二集成电路与所述第一集成电路电连接,且所述第一集成电路电连接于所述感应单元与所述第二集成电路之间。
- 根据权利要求14所述的传感器器件,其中所述第一集成电路包括低通控制集成电路、模拟控制集成电路、以及数模转换集成电路中的至少一者,所述第二集成电路包括存储集成电路。
- 根据权利要求14所述的传感器器件,其中所述第一集成电路包括与所述数据信号线电连接的低通控制集成电路、与所述低通控制集成电路电连接的模拟控制集成电路、以及与所述模拟控制集成电路电连接的数模转换集成电路,所述第二集成电路包括存储集成电路;所述低通控制集成电路电连接于所述感应单元与所述模拟控制集成电路之间,所述数模转换集成电路电连接于所述模拟控制集成电路与所述存储集成电路之间。
- 根据权利要求15或16所述的传感器器件,其中所述第一薄膜晶体管的有源层包括低温多晶硅,所述第二薄膜晶体管的有缘层包括金属氧化物。
- 根据权利要求14所述的传感器器件,其中所述第一集成电路和所述第二集成电路均设置在所述绝缘衬底的同一侧,且所述第一传感模块设置在所述第一集成电路远离所述绝缘衬底的一侧,所述第一传感模块与所述第一薄膜晶体管电连接。
- 根据权利要求14所述的传感器器件,其中所述第一集成电路以及所述第二集成电路均设置在所述绝缘衬底的第一面上,所述第一传感模块设置在所述绝缘衬底与所述第一面相对的第二面上;其中,所述第一传感模块通过设置在所述绝缘衬底上的过孔与所述第一薄膜晶体管电连接。
- 一种电子设备,其特征在于,包括半导体器件,所述半导体器件包括:绝缘衬底;设置于所述绝缘衬底上的第一集成电路,所述第一集成电路包括第一薄膜晶体管;设置于所述绝缘衬底上的第二集成电路,所述第二集成电路包括第二薄膜晶体管;或者,包括一种传感器器件,所述传感器器件包括感应区域以及设置在所述感应区域一侧的***电路区域,包括:绝缘衬底;感应单元,所述感应单元设置在所述感应区域对应的所述绝缘衬底上;以及,集成电路,至少部分所述集成电路设置在所述***电路区域对应的所述绝缘衬底上,且所述集成电路用以控制所述感应单元;其中,所述集成电路包括:第一集成电路,所述第一集成电路包括第一薄膜晶体管;以及,第二集成电路,所述第二集成电路包括第二薄膜晶体管;其中,所述第一薄膜晶体管有源层内载流子的迁移率大于所述第二薄膜晶体管有源层内载流子的迁移率。
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Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009224620A (ja) * | 2008-03-17 | 2009-10-01 | Ricoh Co Ltd | ポリジアセチレンを半導体層とする有機薄膜トランジスタの製造方法 |
CN105408813A (zh) * | 2013-08-26 | 2016-03-16 | 苹果公司 | 具有硅薄膜晶体管和半导体氧化物薄膜晶体管的显示器 |
CN107731858A (zh) * | 2017-10-27 | 2018-02-23 | 京东方科技集团股份有限公司 | 一种阵列基板、其制作方法及显示面板 |
CN110137203A (zh) * | 2019-05-06 | 2019-08-16 | 上海交通大学 | 像素传感结构、传感装置及像素传感结构的形成方法 |
CN110752219A (zh) * | 2019-10-29 | 2020-02-04 | 昆山国显光电有限公司 | 一种薄膜晶体管和显示面板 |
CN112216705A (zh) * | 2019-07-11 | 2021-01-12 | 天马日本株式会社 | 薄膜晶体管衬底 |
-
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Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009224620A (ja) * | 2008-03-17 | 2009-10-01 | Ricoh Co Ltd | ポリジアセチレンを半導体層とする有機薄膜トランジスタの製造方法 |
CN105408813A (zh) * | 2013-08-26 | 2016-03-16 | 苹果公司 | 具有硅薄膜晶体管和半导体氧化物薄膜晶体管的显示器 |
CN107731858A (zh) * | 2017-10-27 | 2018-02-23 | 京东方科技集团股份有限公司 | 一种阵列基板、其制作方法及显示面板 |
CN110137203A (zh) * | 2019-05-06 | 2019-08-16 | 上海交通大学 | 像素传感结构、传感装置及像素传感结构的形成方法 |
CN112216705A (zh) * | 2019-07-11 | 2021-01-12 | 天马日本株式会社 | 薄膜晶体管衬底 |
CN110752219A (zh) * | 2019-10-29 | 2020-02-04 | 昆山国显光电有限公司 | 一种薄膜晶体管和显示面板 |
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