WO2024021693A1 - Structure semi-conductrice et son procédé de fabrication - Google Patents

Structure semi-conductrice et son procédé de fabrication Download PDF

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Publication number
WO2024021693A1
WO2024021693A1 PCT/CN2023/089000 CN2023089000W WO2024021693A1 WO 2024021693 A1 WO2024021693 A1 WO 2024021693A1 CN 2023089000 W CN2023089000 W CN 2023089000W WO 2024021693 A1 WO2024021693 A1 WO 2024021693A1
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substrate
layer
isolation ring
material layer
dielectric constant
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PCT/CN2023/089000
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English (en)
Chinese (zh)
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毛宇
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长鑫存储技术有限公司
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Publication of WO2024021693A1 publication Critical patent/WO2024021693A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors

Definitions

  • the present disclosure relates to the field of integrated circuit technology, and in particular to a semiconductor structure and a preparation method thereof.
  • TSV Through Silicon Via
  • TSV technology is an emerging three-dimensional integrated circuit manufacturing process that stacks chips to achieve interconnection. It achieves electrical interconnection between different chips by producing several vertical interconnection TSV structures on the wafer. even.
  • TSV technology has enabled the layout of integrated circuits to evolve from traditional two-dimensional side-by-side arrangement to more advanced three-dimensional stacking. It can maximize the density of chip stacking in the three-dimensional direction, the shortest interconnection lines between chips, and the smallest overall size, thus greatly improving the efficiency of the circuit. Frequency characteristics and power characteristics are very important technologies in current electronic packaging technology.
  • one aspect of the present disclosure provides a semiconductor structure, including a substrate, a metal pad, a through silicon via structure and an isolation ring structure; the substrate has an opposite first surface and a second surface; a metal The pad is located on a side of the second surface facing away from the substrate; the through-silicon via structure penetrates the substrate along the thickness direction through the first surface and is in contact with the metal pad; the orthographic projection of the metal pad on the second surface covers the bottom surface of the through-silicon via structure;
  • the isolation ring structure is formed in the substrate and surrounds the through silicon via structure, wherein the inner side wall and the outer side wall of the isolation ring structure have a preset distance.
  • the isolation ring structure penetrates the substrate along the thickness direction through the first surface and extends to the second surface.
  • an isolation protective layer is included between the inner side wall of the isolation ring structure and the outer side wall of the through silicon via structure.
  • the isolation protective layer includes an insulating material.
  • the semiconductor structure further includes an annular barrier layer; the annular barrier layer surrounds the through silicon via structure and is located between the isolation protection layer and the through silicon via structure.
  • the annular barrier layer extends through the substrate through the first surface in the thickness direction and to the metal pad.
  • the minimum distance between the inner side wall of the isolation ring structure and the outer side wall of the through silicon via structure is greater than or equal to 1 ⁇ m.
  • the minimum distance between the outer side walls of adjacent isolation ring structures is greater than or equal to 1 ⁇ m.
  • the preset distance is 2 ⁇ m-10 ⁇ m.
  • the material of the isolation ring structure includes a first low-k material layer, a metal barrier layer, and a second low-k material layer, wherein the first low-k material layer surrounds the through silicon via.
  • the metal barrier layer surrounds the first low dielectric constant material layer
  • the second low dielectric constant material layer surrounds the metal barrier layer.
  • the thickness of the metal barrier layer is less than the sum of the thicknesses of the first low-k material layer and the second low-k material layer.
  • the thickness of the metal barrier layer is 1/3-2/3 of the sum of the thicknesses of the first low dielectric constant material layer and the second low dielectric constant material layer.
  • the material of the first low dielectric constant material layer is selected from the group consisting of fluorine-doped silicon dioxide, carbon-doped silicon dioxide, fluorocarbons, and combinations thereof.
  • the material of the metal barrier layer is selected from tantalum, tantalum nitride, titanium nitride, and combinations thereof.
  • the material of the second low-k material layer is selected from the group consisting of fluorine-doped silicon dioxide, carbon-doped silicon dioxide, fluorocarbons, and combinations thereof.
  • the material of the annular barrier layer includes at least one of tantalum, tantalum nitride, and titanium nitride.
  • Another aspect of the present disclosure provides a method for preparing a semiconductor structure, including the following steps: providing a substrate with opposing first and second surfaces, and forming a metal pad on a side of the second surface facing away from the substrate; An isolation ring structure is formed in the substrate, and there is a preset distance between the inner wall and the outer wall of the isolation ring structure; a through silicon via structure is formed in the substrate within the isolation ring structure, and the through silicon via structure passes through the first surface along the thickness direction It penetrates the substrate and is in contact with the metal pad; the orthographic projection of the metal pad on the second surface covers the bottom surface of the through silicon via structure.
  • a first dielectric layer is formed between the metal pad and the second surface;
  • the isolation ring structure includes a first low dielectric constant material layer, a metal barrier layer and a second low dielectric constant material layer.
  • a low dielectric constant material layer surrounds the through silicon via structure, a metal barrier layer surrounds the first low dielectric constant material layer, and a second low dielectric constant material layer surrounds the metal barrier layer;
  • an isolation ring structure is formed in the substrate The steps include: forming a second dielectric layer on the first surface of the substrate; etching the second dielectric layer and the substrate to obtain an isolation ring gap, which exposes part of the first dielectric layer; forming a first dielectric layer in the isolation ring gap.
  • a low dielectric constant material layer, a metal barrier layer and a second low dielectric constant material layer to obtain an isolation ring structure.
  • the step of forming a through silicon via structure in the substrate in the isolation ring structure includes: etching the second dielectric layer and the substrate in the isolation ring structure to obtain a through hole, and the through hole exposes part of the metal pad; form an isolation protective layer on the side wall of the through hole; deposit an annular barrier layer on the side wall of the isolation protective layer; fill the through hole with a conductive material layer and perform planarization to obtain a through silicon hole structure.
  • the minimum distance between the inner side wall of the isolation ring structure and the outer side wall of the through silicon via structure is greater than or equal to 1 ⁇ m.
  • the minimum distance between the outer side walls of adjacent isolation ring structures is greater than or equal to 1 ⁇ m.
  • the preset distance is 2 ⁇ m-10 ⁇ m.
  • 1-2 are schematic cross-sectional views of a semiconductor structure in the process of etching TSVs in traditional technology according to an embodiment of the present disclosure
  • Figure 3 shows a schematic cross-sectional view of a semiconductor structure provided in an embodiment of the present disclosure
  • Figure 4 shows a schematic cross-sectional view of the semiconductor structure along the direction AA' in Figure 3 provided in an embodiment of the present disclosure
  • Figure 5 shows a schematic flowchart of a method for manufacturing a semiconductor structure provided in an embodiment of the present disclosure
  • Figure 6 shows a schematic flow chart of a method for manufacturing a semiconductor structure provided in another embodiment of the present disclosure
  • Figure 7 shows a schematic flow chart of a semiconductor structure preparation method provided in yet another embodiment of the present disclosure.
  • FIG. 8 is a schematic cross-sectional view of a semiconductor structure provided in another embodiment of the present disclosure.
  • CMOS Complementary Metal-Oxide-Semiconductor
  • 3D packaging technology refers to a packaging technology that stacks two or more chips in the same package in the vertical direction without changing the size of the package. technique. 3D packaging has two methods: package stacking (Package-on-Package, POP) and chip stacking packaging.
  • Package stacking technology usually uses stacked thin small outline packaging (Thin Sma11 Outline Package, TSOP) or chip size packaging based on traditional packaging technology ( Chip Scale Package (CSP), however, there are long interconnect lines between chips, which limits the high-frequency and high-speed performance of the package stack.
  • TSOP Thin Sma11 Outline Package
  • CSP Chip Scale Package
  • TSV technology based on wafer manufacturing technology has attracted more and more attention from the semiconductor manufacturing industry. TSV technology achieves electrical interconnection between upper and lower chips by creating vertical interconnection vias on the wafer. Compared with wire bonds, Hehe flip-chip welding and other processes.
  • TSV technology can reduce the interconnection length between two nodes, so it has the following advantages compared to two-dimensional integrated circuits: shorter signal delay, higher operating frequency, smaller parasitic capacitance and lower energy consumption , can effectively realize 3D chip stacking and create packages with more complex structures, more powerful performance, and cost-efficiency.
  • TSV has been used to form stacked arrangements in devices such as MEMS (Micro-Electro-Mechanical System) and semiconductor devices. Or the electrical connection between layers in a 3D layout.
  • MEMS Micro-Electro-Mechanical System
  • TSV needs to etch the thinned wafer and other dielectric layers, and finally connect them to the metal pads. Due to the thinned wafer, Circles are also typically micron thick, so advanced etching processes are required to create holes or trenches in the substrate with extremely large aspect ratios.
  • the energy of the etched material is usually enhanced.
  • the present disclosure provides a semiconductor structure and a preparation method thereof, which can prevent the etching appendages 111 from diffusing into the interior of the substrate, that is, preventing the material in the metal pad from diffusing into the sidewalls and opposing each other.
  • the interference caused by adjacent TSVs can effectively improve the degradation of TSV isolation performance caused by deep hole etching and improve the yield.
  • An embodiment of the present disclosure provides a semiconductor structure, including a substrate 10, a metal pad 11, a through silicon via structure 12 and an isolation ring structure 13; the substrate 10 has an opposite first surface 10a and the second surface 10b; the metal pad 11 is located on the side of the second surface 10b away from the substrate 10; the through silicon via structure 12 penetrates the substrate 10 along the thickness direction through the first surface 10a and is in contact with the metal pad 11; the metal pad 11
  • the orthographic projection on the second surface 10b covers the bottom surface of the through silicon via structure 12; the isolation ring structure 13 is formed in the substrate 10 and surrounds the through silicon via structure 12, wherein the inner and outer walls of the isolation ring structure 13 have predetermined Set distance.
  • the metal pad 11 is located on the second surface 10b of the substrate 10 and on the side away from the substrate 10, and an isolation ring structure 13 is provided in the area surrounding the through silicon via structure 12, which is formed during the TSV etching process.
  • the through-silicon via structure 12 with a high aspect ratio will be etched using an etching material with high energy.
  • the etching process proceeds to the substrate 10
  • the high-energy etching material will bombard the metal pad 11, and the metal material in the metal pad 11 will splash to the side wall of the etching hole. Then, the material in the metal pad 11 will hit the metal pad 11.
  • the material in the metal pad 11 will not appear on the side of the isolation ring structure 13 away from the through silicon via structure 12 , that is, it will not diffuse to the substrate 10 deep, thereby avoiding the situation that adjacent through silicon holes are connected due to the gradual diffusion of metal inside the substrate 10 during or even after the etching of the through silicon via structure 12, thereby improving the through silicon via structure 12 isolation performance.
  • deep hole etching with high aspect ratio usually intensifies the energy of the etching material, which inevitably bombards the underlying metal pad 11, thereby sputtering to the side walls of the hole and gradually diffusing the adjacent silicon.
  • the semiconductor structure provided by the present disclosure prevents the metal pad 11 from sputtering out during the etching of the through-silicon via structure 12 through the arrangement of the isolation ring structure 13
  • the metal material diffuses into the interior of the substrate 10, thereby improving the isolation performance of the through silicon via structure 12, reducing the risk of interconnection between adjacent through silicon via structures 12, and improving the yield of semiconductor products.
  • the substrate may be constructed of semiconductor materials, insulating materials, conductive materials, or any combination thereof.
  • the substrate 10 may have a single-layer structure or a multi-layer structure.
  • the substrate 10 may be a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an arsenic Indium oxide (InAs) substrate, indium phosphide (InP) substrate or other III/V semiconductor substrate or II/VI semiconductor substrate.
  • the substrate 10 may be a layered substrate including, for example, Si/SiGe, Si/SiC, silicon on insulator (SOI), or silicon germanium on insulator.
  • SOI silicon on insulator
  • the substrate type can select the substrate type according to the type of transistors formed on the substrate 10, and therefore the type of the substrate 10 should not limit the scope of the present disclosure.
  • the isolation ring structure 13 penetrates the substrate 10 along the thickness direction through the first surface 10 a and extends to the second surface 10 b to prevent the metal material in the metal pad 11 from appearing in the isolation ring structure 13 away from the silicon.
  • the metal material on one side of the through-hole structure 12 that is, the metal pad 11 will not diffuse deep into the substrate 10 , thereby avoiding the connection between adjacent through silicon holes due to the gradual diffusion of metal inside the substrate 10 .
  • An isolation protective layer 14 is included between the inner side wall of the isolation ring structure 13 and the outer side wall of the through silicon via structure 12 .
  • the isolation protective layer 14 includes an insulating material.
  • the material of the isolation protective layer 14 may be silicon dioxide (SiO 2 ).
  • the semiconductor structure further includes an annular barrier layer 15; the annular barrier layer 15 surrounds the through silicon via structure 12 and is located between the isolation protection layer 14 and the through silicon via structure 12.
  • the annular barrier layer 15 penetrates the substrate 10 in the thickness direction through the first surface 10 a and extends to the metal pad 11 .
  • the minimum distance between the inner side wall of the isolation ring structure 13 and the outer side wall of the through silicon via structure 12 is greater than or equal to 1 ⁇ m.
  • the minimum distance between the inner side wall of the isolation ring structure 13 and the outer side wall of the through silicon via structure 12 may be 1 ⁇ m, 1.5 ⁇ m, 2 ⁇ m, or 3 ⁇ m, etc.
  • the minimum distance between the outer side walls of adjacent isolation ring structures 13 is greater than or equal to 1 ⁇ m.
  • the minimum distance between the outer side walls of adjacent isolation ring structures 13 may be 1 ⁇ m, 1.5 ⁇ m, 2 ⁇ m or 2.5 ⁇ m, etc.
  • the preset distance is 2 ⁇ m-10 ⁇ m.
  • the preset distance may be 2 ⁇ m, 3 ⁇ m, 6 ⁇ m, or 10 ⁇ m, etc.
  • the material of the isolation ring structure 13 includes a first low dielectric constant material layer 131 , a metal barrier layer 132 and a second low dielectric constant material layer 133 , where the first The low dielectric constant material layer 131 is located in the substrate 10 and surrounds the through silicon via structure 12.
  • the metal barrier layer 132 surrounds the first low dielectric constant material layer 131, and the second low dielectric constant material layer 133 surrounds the metal barrier layer. 132.
  • the first low dielectric constant material layer 131 may include fluorine-doped silicon dioxide (SiOF), carbon-doped silicon dioxide (SiOC), fluorocarbon (a-C:F), etc.
  • the metal barrier layer 132 may include tantalum ( Ta), tantalum nitride (TaN) and titanium nitride (Ti)
  • the second low dielectric constant material layer 133 may include fluorine-doped silicon dioxide (SiOF), carbon-doped silicon dioxide (SiOC) And fluorocarbons (a-C:F), etc.
  • the material of the first low dielectric constant material layer 131 and the second low dielectric constant material layer 133 may be carbon-doped silicon dioxide, and the material of the metal barrier layer 132 may be tantalum nitride.
  • parasitic capacitance inevitably exists between the filling material in the through silicon via structure 12 and the metal barrier layer 132.
  • the parasitic capacitance not only affects the speed of the chip, but also poses a serious threat to the working reliability, and due to Reducing the dielectric constant value of the dielectric can reduce the capacitance of the capacitor. Therefore, when the metal barrier layer 132 is used as the isolation ring structure 13, a first low dielectric constant material layer 131 is formed on the inner and outer walls of the isolation ring structure 13. With the second low dielectric constant material layer 133, the parasitic capacitance between the through silicon via structure 12 and the isolation ring structure 13 can be effectively reduced, thereby improving the overall performance of the semiconductor product.
  • the thickness of the metal barrier layer 132 may be less than the sum of the thicknesses of the first low-dielectric constant material layer 131 and the second low-dielectric constant material layer 133 to ensure the isolation ring structure 13 at the same time. Insulating properties and metal barrier properties.
  • the thickness of the metal barrier layer 132 may be 1/3-2/3 of the sum of the thicknesses of the first low dielectric constant material layer 131 and the second low dielectric constant material layer 133 .
  • the thickness of the metal barrier layer 132 may be 1/3, 0.5, 0.55 or 2/3 of the sum of the thicknesses of the first low dielectric constant material layer 131 and the second low dielectric constant material layer 133, and so on.
  • the thickness of the metal barrier layer 132 cannot be too thin to prevent the sputtering and diffusion of etching appendages during the preparation of the through-silicon via structure from interfering with adjacent semiconductor structures or electronic components; the thickness of the metal barrier layer 132 should not be too thin. No It can be too thick to avoid the problem of increasing parasitic capacitance caused by relatively reducing the thickness of the first low dielectric constant material layer 131 or the second low dielectric constant material layer 133 .
  • the material of the annular barrier layer 15 includes at least one of tantalum, tantalum nitride, and titanium nitride; the material of the isolation protective layer 14 includes an insulating material and/or a low dielectric constant. Material, specifically, the material of the isolation protective layer 14 may be silicon dioxide.
  • FIG. 4 is a top view of the semiconductor structure in the above embodiment, that is, a cross-sectional view along the direction AA' in FIG. 3.
  • the annular barrier layer 15, the isolation protection layer 14 and the isolation ring structure 13 are concentric. ring, and has the same center as the through silicon via structure 12.
  • the annular barrier layer 15, the isolation protection layer 14, the isolation ring structure 13 and the through silicon via structure 12 all penetrate the substrate 10 along the thickness direction, where the preset distance is 2 ⁇ m-10 ⁇ m, and the minimum distance between the inner wall of the isolation ring structure 13 and the outer wall of the through silicon via structure 12 is greater than or equal to 1 ⁇ m.
  • the above structure can avoid metal sputtering caused by etching the metal pad 11 from diffusing into the depth of the substrate 10 during the etching of the through silicon via structure 12, thereby causing the connection between the adjacent through silicon via structures 12 and improving the The isolation performance of the through silicon via structure 12.
  • An embodiment of the present disclosure also provides a method for preparing a semiconductor structure, including the following steps:
  • Step S10 Provide a substrate with opposing first and second surfaces, and form a metal pad on the side of the second surface facing away from the substrate;
  • Step S20 Form an isolation ring structure in the substrate, with a preset distance between the inner wall and the outer wall of the isolation ring structure;
  • Step S30 Form a through silicon via structure in the substrate within the isolation ring structure.
  • the through silicon via structure penetrates the substrate along the thickness direction through the first surface and is in contact with the metal pad; the orthographic projection of the metal pad on the second surface covers the silicon The bottom surface of the through-hole structure.
  • step S10 please refer to step S10 in FIG. 3 and FIG. 5 , a substrate 10 having opposite first surfaces 10 a and second surfaces 10 b is provided, and a metal pad 11 is formed on the second surface 10 b.
  • step S10 may also include the following steps: thinning the substrate 10 to a preset thickness.
  • the thinning method may include grinding, and the grinding may include different processing procedures such as rough grinding, fine grinding, and polishing.
  • the thickness of the substrate 10 after thinning is less than 100 ⁇ m.
  • a rapid wet etching is performed on the surface of the substrate 10. The isotropy of the wet etching allows the stress on the substrate 10 to be eliminated; because the thinned substrate 10 There is a surface damage layer on the back, and its residual stress will cause the thinned epitaxial wafer to bend and easily break in subsequent processes, thus affecting the yield. Therefore, the back side of the substrate 10 can be polished after thinning.
  • the polishing process technology can use chemical mechanical polishing (CMP) technology.
  • step S20 please refer to step S20 in FIG. 3 and FIG. 5 , an isolation ring structure 13 is formed in the substrate 10 , and there is a preset distance between the inner side wall and the outer side wall of the isolation ring structure 13 . Since the material of the isolation ring structure 13 is selected to be a material that can block the metal in the metal pad, when the etching causes the etching accessory, that is, the metal material in the metal pad to splash when the through-silicon via structure 12 is subsequently formed, splashing can be avoided.
  • the etching appendages diffuse into the side of the isolation ring structure 13 away from the through-silicon via structure 12 along the width direction, thereby preventing the adjacent through-silicon via structures 12 from being interconnected; and preventing the etching appendages from being sputtered and diffusing to the adjacent through-silicon via structures 12 Interference occurs in semiconductor structures or electronic components and improves the performance and reliability of semiconductor products.
  • a through silicon via structure 12 is formed in the substrate 10 in the isolation ring structure 13 , and the through silicon via structure 12 penetrates the substrate along the thickness direction through the first surface 10 a.
  • the bottom 10 is in contact with the metal pad 11; the orthographic projection of the metal pad 11 on the second surface 10b covers the bottom surface of the through silicon via structure 12. Since the isolation ring structure 13 is formed before the through-silicon via structure 12, during the process of forming the through-silicon via structure 12, when the etching of the through-silicon via structure by the high-energy etching material is about to end, the through-silicon via structure 12 is formed.
  • the metal pad 11 in contact with the hole structure 12 is bombarded until the metal is sputtered. At this time, the metal is sputtered to the side wall and diffuses to the isolation ring structure 13 to stop. It will not diffuse into the interior of the substrate 10, that is, no adjacent silicon will appear. The phenomenon that the through-hole structure 12 is connected.
  • the metal pad 11 is formed on the side of the second surface 10b of the substrate 10 away from the substrate 10, and Before the through silicon via structure 12 is formed, the isolation ring structure 13 is formed first.
  • the isolation ring structure 13 surrounds the through silicon via structure 12 that will be formed later.
  • the substrate 10 needs to be High-energy etching is performed.
  • the metal pad 11 will inevitably be etched, causing the metal material in the metal pad 11 to be sputtered onto the side walls of the etching holes and gradually diffuse.
  • the metal material sputtered on the side wall stops the diffusion movement when it diffuses and contacts the isolation ring structure 13, and will not appear when the isolation ring structure 13 moves away in the width direction.
  • One side of the through-silicon via structure 12 prevents the sputtered metal material from diffusing deep into the substrate 10 and connecting with the adjacent through-silicon via structure 12 , thus avoiding the possibility of electrical connection between different through-silicon via structures 12 risk, improving the isolation performance of the through silicon via structure 12 and improving the yield of semiconductor products.
  • a first dielectric layer is formed between the metal pad and the second surface; the steps of forming the isolation ring structure in the substrate include:
  • Step S21 Form a second dielectric layer on the first surface of the substrate
  • Step S22 Etch the second dielectric layer and the substrate to obtain an isolation ring gap, which exposes part of the first dielectric layer;
  • Step S23 Form a first low dielectric constant material layer, a metal barrier layer and a second low dielectric constant material layer in the isolation ring gap to obtain an isolation ring structure.
  • a second dielectric layer 17 is formed on the first surface 10 a of the substrate 10 .
  • the second dielectric layer 17 can be formed using a rapid thermal oxidation process (Rapid Thermal Oxidation, RTO).
  • a dry etching process may be used to etch the second dielectric layer 17 and the substrate 10 to obtain an isolation ring gap.
  • the isolation ring gap exposes part of the first medium. layer.
  • the etching process may include, but is not limited to, dry etching process and/or wet etching process.
  • the dry etching process may include, but is not limited to, one or more of reactive ion etching (RIE), inductively coupled plasma etching (ICP), high concentration plasma etching (HDP), and the like.
  • RIE reactive ion etching
  • ICP inductively coupled plasma etching
  • HDP high concentration plasma etching
  • step S23 please refer to step S23 of Figure 8 and Figure 6 to deposit an initial low dielectric constant material layer on the inner wall and bottom of the isolation ring gap.
  • the deposition process may include physical vapor deposition (Physical Vapor Deposition, PVD), chemical vapor phase Any one or more of deposition (Chemical Vapor Deposition, CVD) and Atomic Layer Deposition (ALD) processes, etching and removing the portion of the initial low dielectric constant material layer located at the bottom of the isolation ring gap and exposing it
  • the first dielectric layer 16 forms a first low dielectric constant material layer 131 surrounding the through silicon via structure 12 and a second low dielectric constant material layer 133 surrounding the first low dielectric constant material layer 131; and then the first low dielectric constant material layer 133 is formed around the first low dielectric constant material layer 131.
  • a metal barrier layer 132 is formed in the gap between the dielectric constant material layer 131 and the second low dielectric constant material layer 133 .
  • the isolation ring structure 13 includes a first low-k material layer 131 , a metal barrier layer 132 and a second low-k material layer 133 , where the first low-k material layer 131 is located in the substrate 10 and surrounds the through silicon via structure 12 , the metal barrier layer 132 surrounds the first low dielectric constant material layer 131 , and the second low dielectric constant material layer 133 surrounds the metal barrier layer 132 .
  • the metal barrier layer 132 is used as the isolation ring structure 13
  • forming the first low dielectric constant material layer 131 and the second low dielectric constant material layer 133 on the inner and outer walls of the isolation ring structure 13 can effectively reduce through silicon vias.
  • the parasitic capacitance between the structure 12 and the isolation ring structure 13 can improve the overall performance of the semiconductor device.
  • the steps of forming a through silicon via structure in the substrate within the isolation ring structure include:
  • Step S31 Etch the second dielectric layer and the substrate in the isolation ring structure to obtain a through hole, which exposes part of the metal pad;
  • Step S32 Form an isolation protective layer on the side wall of the through hole
  • Step S33 Deposit an annular barrier layer on the sidewall of the isolation protective layer; Step S34: Fill the through hole with a conductive material layer and perform planarization to obtain a through silicon hole structure.
  • step S31 please refer to step S31 in FIG. 8 and FIG. 7 to etch the second dielectric layer 17 and the isolation ring structure.
  • the substrate 10 in 13 obtains a through hole, which exposes part of the metal pad 11.
  • the etching process to obtain the through hole may use plasma etching technology.
  • step S31 and after step S23 the following steps may also be included: spin-coating photoresist on the first surface 10b of the substrate 10, and forming pattern openings through a photolithography process; and removing the photoresist after step S31. glue.
  • step S32 please refer to step S32 in FIG. 8 and FIG. 7 to form an isolation protective layer 14 on the side wall of the through hole.
  • the isolation protective layer 14 can be formed using a rapid thermal oxidation process (Rapid Thermal Oxidation, RTO), a low pressure chemical vapor deposition method (Low Pressure Chemical Vapor Deposition, LPCVD) or a sub-atmospheric pressure chemical vapor deposition method (Selected Area Chemical Vapor Deposition, SACVD).
  • RTO Rapid Thermal Oxidation
  • LPCVD Low Pressure Chemical Vapor Deposition
  • SACVD Select Area Chemical Vapor Deposition
  • an annular barrier layer 15 is deposited on the sidewall of the isolation protection layer 14 .
  • the annular barrier layer 15 may be formed using a physical vapor deposition process (Physical Vapor Deposition, PVD).
  • PVD Physical Vapor Deposition
  • the electroplating process is used to fill the through holes in the TSV process.
  • the electroplating copper process is used to fill the through holes.
  • the diffusion speed of copper in the isolation protective layer is very fast, which can easily cause severe degradation of its dielectric properties.
  • copper has a strong trapping effect on semiconductor carriers.
  • depositing an annular barrier layer 15 between the through silicon via structure 12 and the isolation protection layer 14 can prevent the diffusion of the conductive material layer filled in the subsequently formed through silicon via structure 12 and improve the performance of the semiconductor device. .
  • step S34 please refer to step S34 in FIG. 8 and FIG. 7 , a conductive material layer is filled in the through hole and is planarized to obtain the through silicon via structure 12 .
  • the method of filling the conductive material layer can use electroplating.
  • the step of filling the conductive layer material in the through hole and planarizing it can include: first, physically exhausting the air in the cavity, for example, using ultrasonic waves. , spraying, vacuuming, etc. to allow the electroplating liquid to enter the cavity smoothly; secondly, the electroplating copper process is used to fill the conductive material layer.
  • the process of the electroplating copper process includes oil removal, micro-etching, pickling and plating conductive materials, among which, Degreasing includes removing oil stains and fingerprints on the board surface, micro-etching includes cleaning and roughening the copper surface, and removing oxides and debris from the board surface, and pickling includes removing the oxide film on the surface of the metal pad 11 and activating the surface of the metal pad 11 , and can reduce impurities. Copper plating includes using a DC electroplating method to deposit a conductive material layer on the surface of the metal pad 11 and in the hole; after electroplating, due to excessive internal stress accumulated in the electroplated conductive material layer, many problems will occur.
  • a low-temperature annealing process can be used to suppress the occurrence of protrusion defects; in addition, after the low-temperature annealing process, the through silicon via structure 12 can be planarized.
  • the planarization process can use CMP process, dry etching process and planarization process. Any one or more of the push processes.
  • the minimum distance between the inner side wall of the isolation ring structure 13 and the outer side wall of the through silicon via structure 12 is greater than or equal to 1 ⁇ m, for example, the distance between the inner side wall of the isolation ring structure 13 and the outer side wall of the through silicon via structure 12
  • the minimum distance can be 1 ⁇ m, 1.5 ⁇ m, 2 ⁇ m or 3 ⁇ m etc.
  • the minimum distance between the outer side walls of adjacent isolation ring structures 13 is greater than or equal to 1 ⁇ m.
  • the minimum distance between the outer side walls of adjacent isolation ring structures 13 may be 1 ⁇ m, 1.5 ⁇ m, 2 ⁇ m, or 2.5 ⁇ m, etc. wait.
  • the preset distance is 2 ⁇ m-10 ⁇ m.
  • the preset distance may be 2 ⁇ m, 3 ⁇ m, 6 ⁇ m, or 10 ⁇ m, etc.
  • a semiconductor element (not shown) can be formed on the substrate 10 first, such as a metal oxide semiconductor transistor (MOS transistor). ) or dynamic random access memory (Dynamic Random Access Memory After accessing Memory (DRAM), the isolation ring structure 13 and the through silicon via structure 12 are formed using the steps of the present disclosure.
  • MOS transistor metal oxide semiconductor transistor
  • DRAM Dynamic Random Access Memory After accessing Memory
  • a substrate is provided, and a metal pad is formed on the side of the second surface of the substrate facing away from the substrate; then, an isolation ring structure is formed in the substrate , there is a preset distance between the inner wall and the outer wall of the isolation ring structure; then, a through silicon via structure is formed in the substrate within the isolation ring structure, and the through silicon via structure penetrates the substrate along the thickness direction through the first surface and is connected with Metal pad contact connection.
  • the metal pad covers the bottom surface of the through-silicon via structure in the orthographic projection of the second surface, when the etching process proceeds to a position close to the metal pad, the metal pad will be etched, and then the metal pad will be etched.
  • the metal material in the metal pad is sputtered into the sidewall of the through-silicon via structure. Since the isolation ring structure is formed in the semiconductor structure of the present disclosure before the through-silicon via structure is formed, the metal material sputtered into the sidewall is isolated.
  • the ring structure blocks the side of the isolation ring structure that is close to the through-silicon via structure along the width direction, and does not diffuse into the depth of the substrate, thereby preventing adjacent through-silicon via structures from being connected to improve through-silicon vias.
  • the isolation performance of the structure and improve the reliability of semiconductor products.

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Abstract

L'invention concerne une structure semi-conductrice et un procédé de fabrication correspondant. La structure semi-conductrice comprend : un substrat (10), des pastilles métalliques (11), des structures de trou d'interconnexion traversant le silicium (12), et des structures de bague d'isolation (13). Le substrat (10) possède une première surface (10a) et une seconde surface (130b) opposées l'une à l'autre. Les pastilles métalliques (11) sont situés sur le côté de la seconde surface (10b) tourné à l'opposé au substrat (10). Les structures de trou d'interconnexion traversant le silicium (12) pénètrent à travers le substrat (10) à travers la première surface (10a) dans la direction de l'épaisseur et sont en connexion de contact avec les pastilles métalliques (11) ; les projections orthogonales des pastilles métalliques (11) sur la seconde surface (10b) recouvrent les surfaces inférieures des structures de trou d'interconnexion traversant le silicium (12). Les structures de bague d'isolation (13) sont formées dans le substrat (10) et entourent les structures de trou d'interconnexion traversant le silicium (12), la paroi latérale interne et la paroi latérale externe de chaque structure de bague d'isolation (13) ayant une distance prédéfinie.
PCT/CN2023/089000 2022-07-28 2023-04-18 Structure semi-conductrice et son procédé de fabrication WO2024021693A1 (fr)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101789390A (zh) * 2009-01-23 2010-07-28 财团法人工业技术研究院 硅导通孔的制造方法与硅导通孔结构
CN102623437A (zh) * 2012-04-06 2012-08-01 上海集成电路研发中心有限公司 硅通孔结构及其制造方法
CN108538811A (zh) * 2018-03-20 2018-09-14 杭州电子科技大学 运用硅通孔的低阻止区差分传输结构及其层间互连结构
CN111769097A (zh) * 2020-06-18 2020-10-13 复旦大学 一种用于三维互连的硅通孔结构及其制造方法
US20210202315A1 (en) * 2018-09-14 2021-07-01 Changxin Memory Technologies, Inc. Semiconductor device and methods for manufacturing thereof

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101789390A (zh) * 2009-01-23 2010-07-28 财团法人工业技术研究院 硅导通孔的制造方法与硅导通孔结构
CN102623437A (zh) * 2012-04-06 2012-08-01 上海集成电路研发中心有限公司 硅通孔结构及其制造方法
CN108538811A (zh) * 2018-03-20 2018-09-14 杭州电子科技大学 运用硅通孔的低阻止区差分传输结构及其层间互连结构
US20210202315A1 (en) * 2018-09-14 2021-07-01 Changxin Memory Technologies, Inc. Semiconductor device and methods for manufacturing thereof
CN111769097A (zh) * 2020-06-18 2020-10-13 复旦大学 一种用于三维互连的硅通孔结构及其制造方法

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